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Mon, 1 Jul 2024 11:13:04 -0700 From: Shani Peretz To: CC: , , , , Viacheslav Ovsiienko , "Bing Zhao" , Ori Kam , Suanming Mou , Matan Azrad Subject: [PATCH 1/2] net/mlx5: add global hairpin out of buffer counter Date: Mon, 1 Jul 2024 21:12:44 +0300 Message-ID: <20240701181245.128810-2-shperetz@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240701181245.128810-1-shperetz@nvidia.com> References: <20240701181245.128810-1-shperetz@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E9:EE_|MW4PR12MB7359:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ff5dee2-44c7-4adb-4956-08dc99f97c3a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: Rws6LSzCkH2YZ/2GQYqItKOcn2RSPq8e86eTpIvDTr1gub9WFucntGZSiwRewF99E2bebomJVp7H58gyhOkj3aRiVv7pcsn+Y4lVJcina+6uiblnzc7UddrDo1fU6V46H0CGtC2cKqsvDEpwNhUf+DroKVUKGJNOGLfCbdYwl+ljK5oyXFWdK0+iUzKkf7l623HgMv+loacxqcnea98Hd2Wuvj9TvF8/k42fK3YCKzI5MuOHIMR6+DvFDsy3+szMRYi0oLMwAJhL26bo/lFGZQu1g1oZ7u8n0C8hh3EJZFRyRwpAuyee63YYi2oMmJ5zRdwFksfocbs+QmhFhlakeXaAlXduuPhgeM2r/SZTieH7a/+nxHEdBcaoQOdLGkXQzLJoAYpKkNygEztmEd39Szjte60VbN6MSggaOwYKhRhIoipXpqWul7rMM3i4sk+xIdnNppRM168e2DyDowvFXo8WF2YmBO6r3824bXfilhCZZxr2FnqmGZG8Ds+fjkxFcaFUV7jt3xmE6esj55LADjXKieyVN8nkLm3RMxlRs5iVHphv1czHCBUHGIiahRaASM4qPXf6+EQlNQ0ZqSan/y0UQb2fa3Oio+3cGPULQkNQQWe+Jq9IjaMhQZ7hn5dvvsnR16Iy/lVJaBzR94J/LgiaUWvR0p8EKGJkKoqzdNU7Vk2DYwB4XPkpyXsDtklCa/a0NLEocIilYUURFMgoqreeI3+C2AwpisPXN7/AEqKHVtnkigMfy0RkxiS4RfJCxkEro9lKAzsQAKlFIpa3WRHyDvXpRfSDtAAoJ5DL9clv2J/0J1P7+P/gNG42uQcCew8Fx78rt6joTGyUtVMDDcqwYl4AWqWuOjSIn0o06H5X49CdU6FHR32SSFicMJ5ESQbtvur/Bzx9SfBDpl8X0BUZDASpGfLtmR613W59lDjz2T92cXlvdJB5Ix1eChP8a6d2URcYLGd/QadIQZt0ec+87/xuWDwsPgHQ9j3sHuf4pcui9HuFwRVFPZuNBaNuFlLqws6K1EKZaHe9AiCP/XfAYjkLijm7GnB+Q/spgLvDCBK8yMU2ffhgcE+P4XGUyBE/jSezD4znyxTFpq9vydQDEb5ms31G49hAoxjba+oeMM6fVey5AFWqWq0+j/rS9EGu7vkNnQuhkGmwi+NBlqOGMeiDasr1FmMtD9H2WctkuqIuXc+2wcizbzsmES4EU7n9n01MZEAMDunbXKBpFQVNghRliAxJqe6oPoqW0kV7O+xmAc2r9Y09YmYp67vky5JcHiOJ6UmQkCBFLN56dq2zCFPKTzwFdSOVeWVLhqwMnVNy15IkYdmoBRrFAEn+ec5WJZ8HkEnclIlHJBFf35Xann3RN96pFOQ/fpITO2AJ3uM/WearpwC02C054sVBnfzddqJqKt7MPn14QkYSyJl+5q6CAAVtOeLkR69RSU2ovvVs1KfYY90+BVbPSJZ7 X-Forefront-Antispam-Report: CIP:216.228.118.232; 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Signed-off-by: Shani Peretz Acked-by: Dariusz Sosnowski --- doc/guides/rel_notes/release_24_07.rst | 1 + drivers/net/mlx5/linux/mlx5_ethdev_os.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst index d4efb5be84..c3e4fa5038 100644 --- a/doc/guides/rel_notes/release_24_07.rst +++ b/doc/guides/rel_notes/release_24_07.rst @@ -98,6 +98,7 @@ New Features * Added match with external Tx queue. * Added match with E-Switch manager. * Added flow item and actions validation to async flow API. + * Added global out of buffer counter for hairpin queues. * **Updated TAP driver.** diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 70bba6c8e0..7995ac6bbc 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -1420,6 +1420,10 @@ static const struct mlx5_counter_ctrl mlx5_counters_init[] = { .ctr_name = "out_of_buffer", .dev = 1, }, + { + .dpdk_name = "dev_internal_queue_oob", + .ctr_name = "dev_internal_queue_oob", + }, { .dpdk_name = "tx_phy_packets", .ctr_name = "tx_packets_phy", From patchwork Mon Jul 1 18:12:45 2024 Content-Type: text/plain; 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Mon, 1 Jul 2024 11:13:08 -0700 From: Shani Peretz To: CC: , , , , Viacheslav Ovsiienko , "Bing Zhao" , Ori Kam , Suanming Mou , Matan Azrad , Anatoly Burakov Subject: [PATCH 2/2] net/mlx5: add hairpin out of buffer counter Date: Mon, 1 Jul 2024 21:12:45 +0300 Message-ID: <20240701181245.128810-3-shperetz@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240701181245.128810-1-shperetz@nvidia.com> References: <20240701181245.128810-1-shperetz@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E0:EE_|CH3PR12MB7569:EE_ X-MS-Office365-Filtering-Correlation-Id: 239509fd-f50b-413b-145a-08dc99f980c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: SHdy/U9VQnB02XFHnNXDRNAVeNysvXOGP42Dc50qWBrNQSsks85FJ1l2Ml4vYIt/GAKY9/1da83xAscl3KMALoRRHCohNtfpRDgDcG6AlB7YWwZx6NtOsGXCZMi963gysvMB1rTP0zwtCXBkRk4tpj+xykJH4Jy6qoFbrzBtjDkamPK2UaQLDw1kUvzW/usIPqBvf90ay3WLz9gwMyOewZu/Q+BKKiXkALCqz01d9NjqPM1Ud+79JEF8STQydwQxcxGtYyE1OeefApT8Ur+gXeSI6SdmVe6HaFcxRLLravD7S0ZoxwaONCiX6icNUZ0tUfA5xDgwF2PnzbCWcCJeWGy4EGVbs12uAWPlqfpg1VFzo9SFQaWfCjtivakko7Qi7FCTuc+z7LS9DWaNmWw3r4nWSR68pF1pzT2X2OgNdNP6jB2WCt57ZzPmhRHGxBfQjlKpeus7AR9TiBcEwSbE11lCn6UYXLYT3ivozxl6LSsQx4QwiiJOBY80mv19pUcs2LZmG/+vBHTB5m1+WbBnX1b/sqDQYBh/4OjMMp4icBjgx65TLtsNdYUVo3tmwoKXqNV/btlM//7Zj370jjjEyNHUUg5AH5iKTvj0RhOgHJ5ltBkL3NW562aVzS3aMTC/IV75iGMgwvsvgaAdSr6dqmR64Ne9xhpVo5Ced2ELXwSPa6vhoifvzTDdiJ32nZxFE3ZvElKOCNkH17MpdNNoANc9/hHjYrNLUQlytiA+pwuGoW5fpP/d6d/iTyUDCsz8pN95u+5z+ltqIP75Z2XMBaNMeVCtN3UP/8fNFfrxs5U1J1xEDh7QDUkV9ja/aksQFDqjNDu9oPfOvt5lyjQwmQIx40UTi7BMrLysO08Nfjum8LSnRp3bBKqmS1oA0B6nX8/VYUBSdUaZLvcVYJHu59XtyKEpXzBYgPOtmsuT8dvjnywdfZBpeUMWw8IEQJ8iL6W+14dOPalsi7Dl7qOgSfG4FlefFKEF5eJKXhdNPoO9mAXbduLWsnSihJ81HcutGXLUKyGbDvMv08x0QKHLObtzzGu8+g4RVUPA2QO6BnpHoI/NyVuzxdMMsdGu1r6VJo8vQfsEholJVj3QO9/ixkMqqs7FcPWYLAXJQrmN7vGvydfif8/GmwY5qQYUURn81beP7oXLa+jS7lfQuAzRL0ZpooEnDTemuXj1C+0nmdhp+1vmsCv4nkoHZBFEg9Rxg2TCppiIjWOQ1JFIHcchghIiGcwm5N98LArszGkuF2f+b7XyAFoc51HZfy5bXf+b1ppfAXCduuTVtZZhZcIfaJgd+b0t5UAr3Yw1cYJchEvtWqwmIQNxXMajmtkliNjU9SfBbhpeLQX+ne5tP2JE/y6aYmfxEn1udkMjHyEuh7aPaJ1+4VD2tBo9WU83UeQF643SMq7AhyCt2o7Laz87/AARLXBEWp6eY0AGaoKa9a9jsUv66RwEyqLybUyMeWdB X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jul 2024 18:13:26.4405 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 239509fd-f50b-413b-145a-08dc99f980c1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7569 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Currently mlx5 PMD exposes rx_out_of_buffer counter that tracks packets dropped when Rx queue was full. To provide more granular statistics, this patch splits the `rx_out_of_buffer` counter into two separate counters: 1. hairpin_out_of_buffer - This counter specifically tracks packets dropped by the device's hairpin Rx queues. 2. rx_out_of_buffer - This counter tracks packets dropped by the device's Rx queues, excluding the hairpin Rx queues. Two hardware counter objects will be created per device, and all the Rx queues will be assigned to these counters during the configuration phase. The `hairpin_out_of_buffer` counter will be created only if there is at least one hairpin Rx queue present on the device. Signed-off-by: Shani Peretz Acked-by: Dariusz Sosnowski --- doc/guides/nics/mlx5.rst | 3 ++ doc/guides/rel_notes/release_24_07.rst | 1 + drivers/net/mlx5/linux/mlx5_ethdev_os.c | 5 +++ drivers/net/mlx5/linux/mlx5_os.c | 14 ++++++- drivers/net/mlx5/mlx5.c | 4 ++ drivers/net/mlx5/mlx5.h | 4 ++ drivers/net/mlx5/mlx5_devx.c | 54 ++++++++++++++++++++++++- drivers/net/mlx5/windows/mlx5_os.c | 1 + 8 files changed, 84 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 304c6770af..caacc9f62d 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -750,6 +750,9 @@ Limitations - Hairpin between two ports could only manual binding and explicit Tx flow mode. For single port hairpin, all the combinations of auto/manual binding and explicit/implicit Tx flow mode could be supported. - Hairpin in switchdev SR-IOV mode is not supported till now. + - "out_of_buffer" statistics are not available on: + - NICs older than ConnectX-7. + - DPUs older than BlueField-3. - Quota: diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst index c3e4fa5038..b9aec2d999 100644 --- a/doc/guides/rel_notes/release_24_07.rst +++ b/doc/guides/rel_notes/release_24_07.rst @@ -99,6 +99,7 @@ New Features * Added match with E-Switch manager. * Added flow item and actions validation to async flow API. * Added global out of buffer counter for hairpin queues. + * Added port out of buffer counter for hairpin queues. * **Updated TAP driver.** diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 7995ac6bbc..82f651f2f3 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -1420,6 +1420,11 @@ static const struct mlx5_counter_ctrl mlx5_counters_init[] = { .ctr_name = "out_of_buffer", .dev = 1, }, + { + .dpdk_name = "hairpin_out_of_buffer", + .ctr_name = "hairpin_out_of_buffer", + .dev = 1, + }, { .dpdk_name = "dev_internal_queue_oob", .ctr_name = "dev_internal_queue_oob", diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 50f4810bff..5e950e9be1 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -964,6 +964,8 @@ mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " "by DevX - fall-back to use the kernel driver global " "queue counter.", dev->data->port_id); + priv->q_counters_allocation_failure = 1; + /* Create WQ by kernel and query its queue counter ID. */ if (cq) { wq = mlx5_glue->create_wq(ctx, @@ -3037,13 +3039,23 @@ mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, if (priv->q_counters != NULL && strcmp(ctr_name, "out_of_buffer") == 0) { if (rte_eal_process_type() == RTE_PROC_SECONDARY) { - DRV_LOG(WARNING, "Devx out_of_buffer counter is not supported in the secondary process"); + DRV_LOG(WARNING, "DevX out_of_buffer counter is not supported in the secondary process"); rte_errno = ENOTSUP; return 1; } return mlx5_devx_cmd_queue_counter_query (priv->q_counters, 0, (uint32_t *)stat); } + if (priv->q_counters_hairpin != NULL && + strcmp(ctr_name, "hairpin_out_of_buffer") == 0) { + if (rte_eal_process_type() == RTE_PROC_SECONDARY) { + DRV_LOG(WARNING, "DevX out_of_buffer counter is not supported in the secondary process"); + rte_errno = ENOTSUP; + return 1; + } + return mlx5_devx_cmd_queue_counter_query + (priv->q_counters_hairpin, 0, (uint32_t *)stat); + } MKSTR(path, "%s/ports/%d/hw_counters/%s", priv->sh->ibdev_path, priv->dev_port, diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index e482f7f0e5..8d266b0e64 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -2394,6 +2394,10 @@ mlx5_dev_close(struct rte_eth_dev *dev) mlx5_devx_cmd_destroy(priv->q_counters); priv->q_counters = NULL; } + if (priv->q_counters_hairpin) { + mlx5_devx_cmd_destroy(priv->q_counters_hairpin); + priv->q_counters_hairpin = NULL; + } mlx5_mprq_free_mp(dev); mlx5_os_free_shared_dr(priv); #ifdef HAVE_MLX5_HWS_SUPPORT diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index bd149b43e5..75a1e170af 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1986,8 +1986,12 @@ struct mlx5_priv { LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ uint32_t rss_shared_actions; /* RSS shared actions. */ + /* If true, indicates that we failed to allocate a q counter in the past. */ + bool q_counters_allocation_failure; struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */ uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */ + /* DevX queue counter object for all hairpin queues of the port. */ + struct mlx5_devx_obj *q_counters_hairpin; uint32_t lag_affinity_idx; /* LAG mode queue 0 affinity starting. */ rte_spinlock_t flex_item_sl; /* Flex item list spinlock. */ struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM]; diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index f23eb1def6..7db271acb4 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -496,6 +496,56 @@ mlx5_rxq_create_devx_cq_resources(struct mlx5_rxq_priv *rxq) return 0; } +/** + * Create a global queue counter for all the port hairpin queues. + * + * @param priv + * Device private data. + * + * @return + * The counter_set_id of the queue counter object, 0 otherwise. + */ +static uint32_t +mlx5_set_hairpin_queue_counter_obj(struct mlx5_priv *priv) +{ + if (priv->q_counters_hairpin != NULL) + return priv->q_counters_hairpin->id; + + /* Queue counter allocation failed in the past - don't try again. */ + if (priv->q_counters_allocation_failure != 0) + return 0; + + if (priv->pci_dev == NULL) { + DRV_LOG(DEBUG, "Hairpin out of buffer counter is " + "only supported on PCI device."); + priv->q_counters_allocation_failure = 1; + return 0; + } + + switch (priv->pci_dev->id.device_id) { + /* Counting out of buffer drops on hairpin queues is supported only on CX7 and up. */ + case PCI_DEVICE_ID_MELLANOX_CONNECTX7: + case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: + case PCI_DEVICE_ID_MELLANOX_BLUEFIELD3: + case PCI_DEVICE_ID_MELLANOX_BLUEFIELDVF: + + priv->q_counters_hairpin = mlx5_devx_cmd_queue_counter_alloc(priv->sh->cdev->ctx); + if (priv->q_counters_hairpin == NULL) { + /* Failed to allocate */ + DRV_LOG(DEBUG, "Some of the statistics of port %d " + "will not be available.", priv->dev_data->port_id); + priv->q_counters_allocation_failure = 1; + return 0; + } + return priv->q_counters_hairpin->id; + default: + DRV_LOG(DEBUG, "Hairpin out of buffer counter " + "is not available on this NIC."); + priv->q_counters_allocation_failure = 1; + return 0; + } +} + /** * Create the Rx hairpin queue object. * @@ -541,7 +591,9 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq) unlocked_attr.wq_attr.log_hairpin_num_packets = unlocked_attr.wq_attr.log_hairpin_data_sz - MLX5_HAIRPIN_QUEUE_STRIDE; - unlocked_attr.counter_set_id = priv->counter_set_id; + + unlocked_attr.counter_set_id = mlx5_set_hairpin_queue_counter_obj(priv); + rxq_ctrl->rxq.delay_drop = priv->config.hp_delay_drop; unlocked_attr.delay_drop_en = priv->config.hp_delay_drop; unlocked_attr.hairpin_data_buffer_type = diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 98022ed3c7..0ebd233595 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -83,6 +83,7 @@ mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) DRV_LOG(ERR, "Port %d queue counter object cannot be created " "by DevX - imissed counter will be unavailable", dev->data->port_id); + priv->q_counters_allocation_failure = 1; return; } priv->counter_set_id = priv->q_counters->id;