From patchwork Wed Oct 9 21:12:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145555 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CFDB245AF8; Wed, 9 Oct 2024 23:17:50 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A0A15402F1; Wed, 9 Oct 2024 23:17:45 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id 4A8284014F; Wed, 9 Oct 2024 23:17:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728508662; x=1760044662; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tcTgVEc5Ws4J65v/8CSsIePc4+KoMtPuwDvYek3mMe0=; b=d5CDbaFmAu3Tb8R9IMb887M2wSK6TdROJWu4aIKLdwMmGk5j8nZEcByx myK41jzW0xpi98wltK0LvFNfbB9cuAAPuyc0eI8tDH8yN0iQvyZxbRdT6 rhxfHyXhoY1Ib5aLRHJXKaXPT5rxtrrnR4lwTEtqCzmj+I3tHlQpVqoJY CoS8Vj/DfPlmSiOxBbkJwtUXHFdvXeQBkzyzVd1ZcnRmg8w0KHtunPa5G LSQdDJMtwWUO5k2Ch7uRE3sTilHnpJxGS4sPDQVT6pqqq/AzQvalxJlLr +U5lHnMV26EKVVlB89wVI2FWvnGGZifmgipOZrYJ/thRJvBPtJs6Gdxb7 A==; X-CSE-ConnectionGUID: EgmI2mc5R3Kiaxcpj++Baw== X-CSE-MsgGUID: GUjF47lHTUGzb/WMInQlEA== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="39202220" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202220" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:41 -0700 X-CSE-ConnectionGUID: cGd+UsoKRdun+oTS3Pl+Og== X-CSE-MsgGUID: /iuZdMXjR1O3CpkbuICk3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480581" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:41 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v3 01/12] baseband/acc: fix access to deallocated mem Date: Wed, 9 Oct 2024 14:12:51 -0700 Message-Id: <20241009211302.177471-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Prevent op_addr access during queue_stop operation, as this memory may have been deallocated. Fixes: e640f6cdfa84 ("baseband/acc200: add LDPC processing") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 36 ---------------------- drivers/baseband/acc/rte_vrb_pmd.c | 44 +-------------------------- 2 files changed, 1 insertion(+), 79 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 5e6ee85e1321..c690d1492ba3 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -838,51 +838,15 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, return ret; } -static inline void -acc100_print_op(struct rte_bbdev_dec_op *op, enum rte_bbdev_op_type op_type, - uint16_t index) -{ - if (op == NULL) - return; - if (op_type == RTE_BBDEV_OP_LDPC_DEC) - rte_bbdev_log(DEBUG, - " Op 5GUL %d %d %d %d %d %d %d %d %d %d %d %d", - index, - op->ldpc_dec.basegraph, op->ldpc_dec.z_c, - op->ldpc_dec.n_cb, op->ldpc_dec.q_m, - op->ldpc_dec.n_filler, op->ldpc_dec.cb_params.e, - op->ldpc_dec.op_flags, op->ldpc_dec.rv_index, - op->ldpc_dec.iter_max, op->ldpc_dec.iter_count, - op->ldpc_dec.harq_combined_input.length - ); - else if (op_type == RTE_BBDEV_OP_LDPC_ENC) { - struct rte_bbdev_enc_op *op_dl = (struct rte_bbdev_enc_op *) op; - rte_bbdev_log(DEBUG, - " Op 5GDL %d %d %d %d %d %d %d %d %d", - index, - op_dl->ldpc_enc.basegraph, op_dl->ldpc_enc.z_c, - op_dl->ldpc_enc.n_cb, op_dl->ldpc_enc.q_m, - op_dl->ldpc_enc.n_filler, op_dl->ldpc_enc.cb_params.e, - op_dl->ldpc_enc.op_flags, op_dl->ldpc_enc.rv_index - ); - } -} - static int acc100_queue_stop(struct rte_bbdev *dev, uint16_t queue_id) { struct acc_queue *q; - struct rte_bbdev_dec_op *op; - uint16_t i; q = dev->data->queues[queue_id].queue_private; rte_bbdev_log(INFO, "Queue Stop %d H/T/D %d %d %x OpType %d", queue_id, q->sw_ring_head, q->sw_ring_tail, q->sw_ring_depth, q->op_type); - for (i = 0; i < q->sw_ring_depth; ++i) { - op = (q->ring_addr + i)->req.op_addr; - acc100_print_op(op, q->op_type, i); - } /* ignore all operations in flight and clear counters */ q->sw_ring_tail = q->sw_ring_head; q->aq_enqueued = 0; diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 646c12ad5cac..e3f98d6e421c 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -1048,58 +1048,16 @@ vrb_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, return ret; } -static inline void -vrb_print_op(struct rte_bbdev_dec_op *op, enum rte_bbdev_op_type op_type, - uint16_t index) -{ - if (op == NULL) - return; - if (op_type == RTE_BBDEV_OP_LDPC_DEC) - rte_bbdev_log(INFO, - " Op 5GUL %d %d %d %d %d %d %d %d %d %d %d %d", - index, - op->ldpc_dec.basegraph, op->ldpc_dec.z_c, - op->ldpc_dec.n_cb, op->ldpc_dec.q_m, - op->ldpc_dec.n_filler, op->ldpc_dec.cb_params.e, - op->ldpc_dec.op_flags, op->ldpc_dec.rv_index, - op->ldpc_dec.iter_max, op->ldpc_dec.iter_count, - op->ldpc_dec.harq_combined_input.length - ); - else if (op_type == RTE_BBDEV_OP_LDPC_ENC) { - struct rte_bbdev_enc_op *op_dl = (struct rte_bbdev_enc_op *) op; - rte_bbdev_log(INFO, - " Op 5GDL %d %d %d %d %d %d %d %d %d", - index, - op_dl->ldpc_enc.basegraph, op_dl->ldpc_enc.z_c, - op_dl->ldpc_enc.n_cb, op_dl->ldpc_enc.q_m, - op_dl->ldpc_enc.n_filler, op_dl->ldpc_enc.cb_params.e, - op_dl->ldpc_enc.op_flags, op_dl->ldpc_enc.rv_index - ); - } else if (op_type == RTE_BBDEV_OP_MLDTS) { - struct rte_bbdev_mldts_op *op_mldts = (struct rte_bbdev_mldts_op *) op; - rte_bbdev_log(INFO, " Op MLD %d RBs %d NL %d Rp %d %d %x", - index, - op_mldts->mldts.num_rbs, op_mldts->mldts.num_layers, - op_mldts->mldts.r_rep, - op_mldts->mldts.c_rep, op_mldts->mldts.op_flags); - } -} - /* Stop queue and clear counters. */ static int vrb_queue_stop(struct rte_bbdev *dev, uint16_t queue_id) { struct acc_queue *q; - struct rte_bbdev_dec_op *op; - uint16_t i; + q = dev->data->queues[queue_id].queue_private; rte_bbdev_log(INFO, "Queue Stop %d H/T/D %d %d %x OpType %d", queue_id, q->sw_ring_head, q->sw_ring_tail, q->sw_ring_depth, q->op_type); - for (i = 0; i < q->sw_ring_depth; ++i) { - op = (q->ring_addr + i)->req.op_addr; - vrb_print_op(op, q->op_type, i); - } /* ignore all operations in flight and clear counters */ q->sw_ring_tail = q->sw_ring_head; q->aq_enqueued = 0; From patchwork Wed Oct 9 21:12:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145556 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 52F6E45AF8; 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a="39202224" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202224" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:41 -0700 X-CSE-ConnectionGUID: yT74MpYqTGyvgssk2wfY7A== X-CSE-MsgGUID: rNqGoPz4T3KG8FxMz3pMhg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480586" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:41 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v3 02/12] baseband/acc: fix soft output bypass RM Date: Wed, 9 Oct 2024 14:12:52 -0700 Message-Id: <20241009211302.177471-3-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Removing soft output bypass RM capability due to VRB2 device limitations. Fixes: b49fe052f9cd ("baseband/acc: add FEC capabilities for VRB2 variant") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_vrb_pmd.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index e3f98d6e421c..52a683e4e49b 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -1272,7 +1272,6 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info) RTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION | RTE_BBDEV_LDPC_LLR_COMPRESSION | RTE_BBDEV_LDPC_SOFT_OUT_ENABLE | - RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS | RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS | RTE_BBDEV_LDPC_DEC_INTERRUPTS, .llr_size = 8, @@ -1643,18 +1642,18 @@ vrb_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, fcw->so_en = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_SOFT_OUT_ENABLE); fcw->so_bypass_intlv = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS); - fcw->so_bypass_rm = check_bit(op->ldpc_dec.op_flags, - RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS); + fcw->so_bypass_rm = 0; fcw->minsum_offset = 1; fcw->dec_llrclip = 2; } /* - * These are all implicitly set + * These are all implicitly set: * fcw->synd_post = 0; * fcw->dec_convllr = 0; * fcw->hcout_convllr = 0; * fcw->hcout_size1 = 0; + * fcw->so_it = 0; * fcw->hcout_offset = 0; * fcw->negstop_th = 0; * fcw->negstop_it = 0; From patchwork Wed Oct 9 21:12:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145557 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7481E45AF8; Wed, 9 Oct 2024 23:18:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8CF6E40612; Wed, 9 Oct 2024 23:17:48 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id 20C8E402B7 for ; Wed, 9 Oct 2024 23:17:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728508663; x=1760044663; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nhXPQWxI1iJ2X21oNR+lqXa29FPpc8UFmpf86PCso8c=; b=BM+WYPGhAFsTcYZ2m/Z9BHgNaN4zPxR0pkBDf8i4N4YWfW5IhCw9Gr5Q aFEHYdLHBZlvM81OmqFAzfj0g/2gVt5cnNzkAjVDVJlPSMRCGZVWGzYlE w2yVE2t5gUn2hB1tx+vch+YTiuWHj9VnN55EcboPLPRB1XgelVB0YT8Vn RqPOwvdy1vTLcelN31MdFDyyARcXgyeU5Eb4JVaekFG9/mS8rGD5oeEL4 V4fcbfMVLLmnM+LlqUzVsunKLfoa/9QO1Jnq1YWMuxyoN3cTlGWIy/kNd IDxyU3vpW1qYr/SE4qazf+EJHi71J6tzMNs8B0O3nvLAg4JLXdX7egfN+ g==; X-CSE-ConnectionGUID: I39LzQEuSvyb6K80W9zeVg== X-CSE-MsgGUID: H7hx/LI7RFqBX5AzdDuQYg== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="39202228" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202228" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:42 -0700 X-CSE-ConnectionGUID: Idrhv1DaTq2ePUE+nkjFuQ== X-CSE-MsgGUID: 30BJkduoQJSISaRQJx3tXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480590" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:41 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 03/12] baseband/acc: queue allocation refactor Date: Wed, 9 Oct 2024 14:12:53 -0700 Message-Id: <20241009211302.177471-4-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor to manage queue memory per operation more flexibly for VRB devices. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/acc_common.h | 5 + drivers/baseband/acc/rte_vrb_pmd.c | 214 ++++++++++++++++++++--------- 2 files changed, 157 insertions(+), 62 deletions(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 38870c6458c4..70028fb5d235 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -149,6 +149,8 @@ #define VRB2_VF_ID_SHIFT 6 #define ACC_MAX_FFT_WIN 16 +#define ACC_MAX_RING_BUFFER 64 +#define VRB2_MAX_Q_PER_OP 256 extern int acc_common_logtype; #define RTE_LOGTYPE_ACC_COMMON acc_common_logtype @@ -581,6 +583,9 @@ struct acc_device { void *sw_rings_base; /* Base addr of un-aligned memory for sw rings */ void *sw_rings; /* 64MBs of 64MB aligned memory for sw rings */ rte_iova_t sw_rings_iova; /* IOVA address of sw_rings */ + void *sw_rings_array[ACC_MAX_RING_BUFFER]; /* Array of aligned memory for sw rings. */ + rte_iova_t sw_rings_iova_array[ACC_MAX_RING_BUFFER]; /* Array of sw_rings IOVA. */ + uint32_t queue_index[ACC_MAX_RING_BUFFER]; /* Tracking queue index per ring buffer. */ /* Virtual address of the info memory routed to the this function under * operation, whether it is PF or VF. * HW may DMA information data at this location asynchronously diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 52a683e4e49b..7e967ba97ac2 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -282,7 +282,7 @@ fetch_acc_config(struct rte_bbdev *dev) /* Check the depth of the AQs. */ reg_len0 = acc_reg_read(d, d->reg_addr->depth_log0_offset); reg_len1 = acc_reg_read(d, d->reg_addr->depth_log1_offset); - for (acc = 0; acc < NUM_ACC; acc++) { + for (acc = 0; acc < VRB1_NUM_ACCS; acc++) { qtopFromAcc(&q_top, acc, acc_conf); if (q_top->first_qgroup_index < ACC_NUM_QGRPS_PER_WORD) q_top->aq_depth_log2 = @@ -291,7 +291,7 @@ fetch_acc_config(struct rte_bbdev *dev) q_top->aq_depth_log2 = (reg_len1 >> ((q_top->first_qgroup_index - ACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF; } - } else { + } else if (d->device_variant == VRB2_VARIANT) { reg0 = acc_reg_read(d, d->reg_addr->qman_group_func); reg1 = acc_reg_read(d, d->reg_addr->qman_group_func + 4); reg2 = acc_reg_read(d, d->reg_addr->qman_group_func + 8); @@ -309,7 +309,7 @@ fetch_acc_config(struct rte_bbdev *dev) idx = (reg2 >> ((qg % ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7; else idx = (reg3 >> ((qg % ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7; - if (idx < VRB_NUM_ACCS) { + if (idx < VRB2_NUM_ACCS) { acc = qman_func_id[idx]; updateQtop(acc, qg, acc_conf, d); } @@ -322,7 +322,7 @@ fetch_acc_config(struct rte_bbdev *dev) reg_len2 = acc_reg_read(d, d->reg_addr->depth_log0_offset + 8); reg_len3 = acc_reg_read(d, d->reg_addr->depth_log0_offset + 12); - for (acc = 0; acc < NUM_ACC; acc++) { + for (acc = 0; acc < VRB2_NUM_ACCS; acc++) { qtopFromAcc(&q_top, acc, acc_conf); if (q_top->first_qgroup_index / ACC_NUM_QGRPS_PER_WORD == 0) q_top->aq_depth_log2 = (reg_len0 >> ((q_top->first_qgroup_index % @@ -544,6 +544,7 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) { uint32_t phys_low, phys_high, value; struct acc_device *d = dev->data->dev_private; + uint16_t queues_per_op, i; int ret; if (d->pf_device && !d->acc_conf.pf_mode_en) { @@ -565,27 +566,37 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) return -ENODEV; } - alloc_sw_rings_min_mem(dev, d, num_queues, socket_id); + if (d->device_variant == VRB1_VARIANT) { + alloc_sw_rings_min_mem(dev, d, num_queues, socket_id); - /* If minimal memory space approach failed, then allocate - * the 2 * 64MB block for the sw rings. - */ - if (d->sw_rings == NULL) - alloc_2x64mb_sw_rings_mem(dev, d, socket_id); + /* If minimal memory space approach failed, then allocate + * the 2 * 64MB block for the sw rings. + */ + if (d->sw_rings == NULL) + alloc_2x64mb_sw_rings_mem(dev, d, socket_id); - if (d->sw_rings == NULL) { - rte_bbdev_log(NOTICE, - "Failure allocating sw_rings memory"); - return -ENOMEM; + if (d->sw_rings == NULL) { + rte_bbdev_log(NOTICE, "Failure allocating sw_rings memory"); + return -ENOMEM; + } + } else if (d->device_variant == VRB2_VARIANT) { + queues_per_op = RTE_MIN(VRB2_MAX_Q_PER_OP, num_queues); + for (i = 0; i <= RTE_BBDEV_OP_MLDTS; i++) { + alloc_sw_rings_min_mem(dev, d, queues_per_op, socket_id); + if (d->sw_rings == NULL) { + rte_bbdev_log(NOTICE, "Failure allocating sw_rings memory %d", i); + return -ENOMEM; + } + /* Moves the pointer to the relevant array. */ + d->sw_rings_array[i] = d->sw_rings; + d->sw_rings_iova_array[i] = d->sw_rings_iova; + d->sw_rings = NULL; + d->sw_rings_base = NULL; + d->sw_rings_iova = 0; + d->queue_index[i] = 0; + } } - /* Configure device with the base address for DMA descriptor rings. - * Same descriptor rings used for UL and DL DMA Engines. - * Note : Assuming only VF0 bundle is used for PF mode. - */ - phys_high = (uint32_t)(d->sw_rings_iova >> 32); - phys_low = (uint32_t)(d->sw_rings_iova & ~(ACC_SIZE_64MBYTE-1)); - /* Read the populated cfg from device registers. */ fetch_acc_config(dev); @@ -600,20 +611,60 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) if (d->pf_device) acc_reg_write(d, VRB1_PfDmaAxiControl, 1); - acc_reg_write(d, d->reg_addr->dma_ring_ul5g_hi, phys_high); - acc_reg_write(d, d->reg_addr->dma_ring_ul5g_lo, phys_low); - acc_reg_write(d, d->reg_addr->dma_ring_dl5g_hi, phys_high); - acc_reg_write(d, d->reg_addr->dma_ring_dl5g_lo, phys_low); - acc_reg_write(d, d->reg_addr->dma_ring_ul4g_hi, phys_high); - acc_reg_write(d, d->reg_addr->dma_ring_ul4g_lo, phys_low); - acc_reg_write(d, d->reg_addr->dma_ring_dl4g_hi, phys_high); - acc_reg_write(d, d->reg_addr->dma_ring_dl4g_lo, phys_low); - acc_reg_write(d, d->reg_addr->dma_ring_fft_hi, phys_high); - acc_reg_write(d, d->reg_addr->dma_ring_fft_lo, phys_low); - if (d->device_variant == VRB2_VARIANT) { - acc_reg_write(d, d->reg_addr->dma_ring_mld_hi, phys_high); - acc_reg_write(d, d->reg_addr->dma_ring_mld_lo, phys_low); + if (d->device_variant == VRB1_VARIANT) { + /* Configure device with the base address for DMA descriptor rings. + * Same descriptor rings used for UL and DL DMA Engines. + * Note : Assuming only VF0 bundle is used for PF mode. + */ + phys_high = (uint32_t)(d->sw_rings_iova >> 32); + phys_low = (uint32_t)(d->sw_rings_iova & ~(ACC_SIZE_64MBYTE-1)); + acc_reg_write(d, d->reg_addr->dma_ring_ul5g_hi, phys_high); + acc_reg_write(d, d->reg_addr->dma_ring_ul5g_lo, phys_low); + acc_reg_write(d, d->reg_addr->dma_ring_dl5g_hi, phys_high); + acc_reg_write(d, d->reg_addr->dma_ring_dl5g_lo, phys_low); + acc_reg_write(d, d->reg_addr->dma_ring_ul4g_hi, phys_high); + acc_reg_write(d, d->reg_addr->dma_ring_ul4g_lo, phys_low); + acc_reg_write(d, d->reg_addr->dma_ring_dl4g_hi, phys_high); + acc_reg_write(d, d->reg_addr->dma_ring_dl4g_lo, phys_low); + acc_reg_write(d, d->reg_addr->dma_ring_fft_hi, phys_high); + acc_reg_write(d, d->reg_addr->dma_ring_fft_lo, phys_low); + } else if (d->device_variant == VRB2_VARIANT) { + /* Configure device with the base address for DMA descriptor rings. + * Different ring buffer used for each operation type. + * Note : Assuming only VF0 bundle is used for PF mode. + */ + acc_reg_write(d, d->reg_addr->dma_ring_ul5g_hi, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_LDPC_DEC] >> 32)); + acc_reg_write(d, d->reg_addr->dma_ring_ul5g_lo, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_LDPC_DEC] + & ~(ACC_SIZE_64MBYTE - 1))); + acc_reg_write(d, d->reg_addr->dma_ring_dl5g_hi, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_LDPC_ENC] >> 32)); + acc_reg_write(d, d->reg_addr->dma_ring_dl5g_lo, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_LDPC_ENC] + & ~(ACC_SIZE_64MBYTE - 1))); + acc_reg_write(d, d->reg_addr->dma_ring_ul4g_hi, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_TURBO_DEC] >> 32)); + acc_reg_write(d, d->reg_addr->dma_ring_ul4g_lo, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_TURBO_DEC] + & ~(ACC_SIZE_64MBYTE - 1))); + acc_reg_write(d, d->reg_addr->dma_ring_dl4g_hi, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_TURBO_ENC] >> 32)); + acc_reg_write(d, d->reg_addr->dma_ring_dl4g_lo, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_TURBO_ENC] + & ~(ACC_SIZE_64MBYTE - 1))); + acc_reg_write(d, d->reg_addr->dma_ring_fft_hi, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_FFT] >> 32)); + acc_reg_write(d, d->reg_addr->dma_ring_fft_lo, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_FFT] + & ~(ACC_SIZE_64MBYTE - 1))); + acc_reg_write(d, d->reg_addr->dma_ring_mld_hi, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_MLDTS] >> 32)); + acc_reg_write(d, d->reg_addr->dma_ring_mld_lo, + (uint32_t)(d->sw_rings_iova_array[RTE_BBDEV_OP_MLDTS] + & ~(ACC_SIZE_64MBYTE - 1))); } + /* * Configure Ring Size to the max queue ring size * (used for wrapping purpose). @@ -637,19 +688,21 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) phys_high = (uint32_t)(d->tail_ptr_iova >> 32); phys_low = (uint32_t)(d->tail_ptr_iova); - acc_reg_write(d, d->reg_addr->tail_ptrs_ul5g_hi, phys_high); - acc_reg_write(d, d->reg_addr->tail_ptrs_ul5g_lo, phys_low); - acc_reg_write(d, d->reg_addr->tail_ptrs_dl5g_hi, phys_high); - acc_reg_write(d, d->reg_addr->tail_ptrs_dl5g_lo, phys_low); - acc_reg_write(d, d->reg_addr->tail_ptrs_ul4g_hi, phys_high); - acc_reg_write(d, d->reg_addr->tail_ptrs_ul4g_lo, phys_low); - acc_reg_write(d, d->reg_addr->tail_ptrs_dl4g_hi, phys_high); - acc_reg_write(d, d->reg_addr->tail_ptrs_dl4g_lo, phys_low); - acc_reg_write(d, d->reg_addr->tail_ptrs_fft_hi, phys_high); - acc_reg_write(d, d->reg_addr->tail_ptrs_fft_lo, phys_low); - if (d->device_variant == VRB2_VARIANT) { - acc_reg_write(d, d->reg_addr->tail_ptrs_mld_hi, phys_high); - acc_reg_write(d, d->reg_addr->tail_ptrs_mld_lo, phys_low); + { + acc_reg_write(d, d->reg_addr->tail_ptrs_ul5g_hi, phys_high); + acc_reg_write(d, d->reg_addr->tail_ptrs_ul5g_lo, phys_low); + acc_reg_write(d, d->reg_addr->tail_ptrs_dl5g_hi, phys_high); + acc_reg_write(d, d->reg_addr->tail_ptrs_dl5g_lo, phys_low); + acc_reg_write(d, d->reg_addr->tail_ptrs_ul4g_hi, phys_high); + acc_reg_write(d, d->reg_addr->tail_ptrs_ul4g_lo, phys_low); + acc_reg_write(d, d->reg_addr->tail_ptrs_dl4g_hi, phys_high); + acc_reg_write(d, d->reg_addr->tail_ptrs_dl4g_lo, phys_low); + acc_reg_write(d, d->reg_addr->tail_ptrs_fft_hi, phys_high); + acc_reg_write(d, d->reg_addr->tail_ptrs_fft_lo, phys_low); + if (d->device_variant == VRB2_VARIANT) { + acc_reg_write(d, d->reg_addr->tail_ptrs_mld_hi, phys_high); + acc_reg_write(d, d->reg_addr->tail_ptrs_mld_lo, phys_low); + } } ret = allocate_info_ring(dev); @@ -685,8 +738,13 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) rte_free(d->tail_ptrs); d->tail_ptrs = NULL; free_sw_rings: - rte_free(d->sw_rings_base); - d->sw_rings = NULL; + if (d->device_variant == VRB1_VARIANT) { + rte_free(d->sw_rings_base); + d->sw_rings = NULL; + } else if (d->device_variant == VRB2_VARIANT) { + for (i = 0; i <= RTE_BBDEV_OP_MLDTS; i++) + rte_free(d->sw_rings_array[i]); + } return ret; } @@ -810,17 +868,34 @@ vrb_intr_enable(struct rte_bbdev *dev) static int vrb_dev_close(struct rte_bbdev *dev) { + int i; struct acc_device *d = dev->data->dev_private; + vrb_check_ir(d); - if (d->sw_rings_base != NULL) { - rte_free(d->tail_ptrs); - rte_free(d->info_ring); - rte_free(d->sw_rings_base); - rte_free(d->harq_layout); - d->tail_ptrs = NULL; - d->info_ring = NULL; - d->sw_rings_base = NULL; - d->harq_layout = NULL; + if (d->device_variant == VRB1_VARIANT) { + if (d->sw_rings_base != NULL) { + rte_free(d->tail_ptrs); + rte_free(d->info_ring); + rte_free(d->sw_rings_base); + rte_free(d->harq_layout); + d->tail_ptrs = NULL; + d->info_ring = NULL; + d->sw_rings_base = NULL; + d->harq_layout = NULL; + } + } else if (d->device_variant == VRB2_VARIANT) { + if (d->sw_rings_array[1] != NULL) { + rte_free(d->tail_ptrs); + rte_free(d->info_ring); + rte_free(d->harq_layout); + d->tail_ptrs = NULL; + d->info_ring = NULL; + d->harq_layout = NULL; + for (i = 0; i <= RTE_BBDEV_OP_MLDTS; i++) { + rte_free(d->sw_rings_array[i]); + d->sw_rings_array[i] = NULL; + } + } } /* Ensure all in flight HW transactions are completed. */ usleep(ACC_LONG_WAIT); @@ -891,8 +966,16 @@ vrb_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, } q->d = d; - q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id)); - q->ring_addr_iova = d->sw_rings_iova + (d->sw_ring_size * queue_id); + if (d->device_variant == VRB1_VARIANT) { + q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id)); + q->ring_addr_iova = d->sw_rings_iova + (d->sw_ring_size * queue_id); + } else if (d->device_variant == VRB2_VARIANT) { + q->ring_addr = RTE_PTR_ADD(d->sw_rings_array[conf->op_type], + (d->sw_ring_size * d->queue_index[conf->op_type])); + q->ring_addr_iova = d->sw_rings_iova_array[conf->op_type] + + (d->sw_ring_size * d->queue_index[conf->op_type]); + d->queue_index[conf->op_type]++; + } /* Prepare the Ring with default descriptor format. */ union acc_dma_desc *desc = NULL; @@ -1347,8 +1430,14 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info) dev_info->queue_priority[RTE_BBDEV_OP_FFT] = d->acc_conf.q_fft.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_MLDTS] = d->acc_conf.q_mld.num_qgroups; dev_info->max_num_queues = 0; - for (i = RTE_BBDEV_OP_NONE; i <= RTE_BBDEV_OP_MLDTS; i++) + for (i = RTE_BBDEV_OP_NONE; i <= RTE_BBDEV_OP_MLDTS; i++) { + if (unlikely(dev_info->num_queues[i] > VRB2_MAX_Q_PER_OP)) { + rte_bbdev_log(ERR, "Unexpected number of queues %d exposed for op %d", + dev_info->num_queues[i], i); + dev_info->num_queues[i] = VRB2_MAX_Q_PER_OP; + } dev_info->max_num_queues += dev_info->num_queues[i]; + } dev_info->queue_size_lim = ACC_MAX_QUEUE_DEPTH; dev_info->hardware_accelerated = true; dev_info->max_dl_queue_priority = @@ -4239,7 +4328,8 @@ vrb_bbdev_init(struct rte_bbdev *dev, struct rte_pci_driver *drv) d->reg_addr = &vrb1_pf_reg_addr; else d->reg_addr = &vrb1_vf_reg_addr; - } else { + } else if ((pci_dev->id.device_id == RTE_VRB2_PF_DEVICE_ID) || + (pci_dev->id.device_id == RTE_VRB2_VF_DEVICE_ID)) { d->device_variant = VRB2_VARIANT; d->queue_offset = vrb2_queue_offset; d->num_qgroups = VRB2_NUM_QGRPS; From patchwork Wed Oct 9 21:12:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145558 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3FA9045AF8; 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a="39202231" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202231" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:42 -0700 X-CSE-ConnectionGUID: vozKzjGcSnesn/UTOvr+pw== X-CSE-MsgGUID: JattH0FHSbiTyxhwwbgbMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480597" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:42 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 04/12] baseband/acc: configure max queues per device Date: Wed, 9 Oct 2024 14:12:54 -0700 Message-Id: <20241009211302.177471-5-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Configure max_queues based on the number of queue groups and numbers of AQS per device variant. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_vrb_pmd.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 7e967ba97ac2..519385e82ed3 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -545,7 +545,7 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) uint32_t phys_low, phys_high, value; struct acc_device *d = dev->data->dev_private; uint16_t queues_per_op, i; - int ret; + int ret, max_queues = 0; if (d->pf_device && !d->acc_conf.pf_mode_en) { rte_bbdev_log(NOTICE, @@ -672,10 +672,15 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) value = log2_basic(d->sw_ring_size / ACC_RING_SIZE_GRANULARITY); acc_reg_write(d, d->reg_addr->ring_size, value); + if (d->device_variant == VRB1_VARIANT) + max_queues = VRB1_NUM_QGRPS * VRB1_NUM_AQS; + else if (d->device_variant == VRB2_VARIANT) + max_queues = VRB2_NUM_QGRPS * VRB2_NUM_AQS; + /* Configure tail pointer for use when SDONE enabled. */ if (d->tail_ptrs == NULL) d->tail_ptrs = rte_zmalloc_socket(dev->device->driver->name, - VRB_MAX_QGRPS * VRB_MAX_AQS * sizeof(uint32_t), + max_queues * sizeof(uint32_t), RTE_CACHE_LINE_SIZE, socket_id); if (d->tail_ptrs == NULL) { rte_bbdev_log(ERR, "Failed to allocate tail ptr for %s:%u", From patchwork Wed Oct 9 21:12:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145559 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 40D3145AF8; Wed, 9 Oct 2024 23:18:15 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CB9BA40651; Wed, 9 Oct 2024 23:17:51 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id E576340156 for ; Wed, 9 Oct 2024 23:17:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728508664; x=1760044664; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yWcNL74hinYiUVbN/pjZoHy7msPPhDRU1Hxh98rhOUs=; b=ChewKB2SrylNVUtrkW/Ib1YZ57cgmKOUkZfF6N9dxbUj+QhUxLsDMqlc iR9WUkQszNwSWGY91ZTlwVzJss0FypEqhlhlBljJrbnLLvctfv0dzey3S 4RdTvxeJRIKG9qnArDUp0ZkPZe7yLpn1b2xfn8vj5CnTa7ZKRo8rYw5CX 434aV8y4L/S/fM9oA+1dZyp8ccJm7r+RJZd+t4vUgoIB5pVtZUgC9VV8S nrN++AWodkJdmuDDZe1OCGUufcQ1KBhm82yeAj/+mhNIdABUcMIts4cVs 7Sb6SeyApzf9aeWzd1Th+2YHPyDpitDhv8sehnPHAAPV4d4Z5nyFk+7s0 A==; X-CSE-ConnectionGUID: lrIKjtS/TZeu1M3qjghk7A== X-CSE-MsgGUID: 8fv2O+5eTRyXQHm1m/idNQ== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="39202234" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202234" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:42 -0700 X-CSE-ConnectionGUID: 1IEwqolVSoSatSEVWkLYew== X-CSE-MsgGUID: oU9AFSnWTNe3t6nFtrK3nQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480600" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:42 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 05/12] baseband/acc: future proof structure comparison Date: Wed, 9 Oct 2024 14:12:55 -0700 Message-Id: <20241009211302.177471-6-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some implementation in the PMD is based on some size assumption from the bbdev structure, which should use sizeof instead to be more future proof in case these structures change. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/acc_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 70028fb5d235..1d8fd24ba008 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -95,8 +95,8 @@ #define ACC_COMPANION_PTRS 8 #define ACC_FCW_VER 2 #define ACC_MUX_5GDL_DESC 6 -#define ACC_CMP_ENC_SIZE 20 -#define ACC_CMP_DEC_SIZE 24 +#define ACC_CMP_ENC_SIZE (sizeof(struct rte_bbdev_op_ldpc_enc) - ACC_ENC_OFFSET) +#define ACC_CMP_DEC_SIZE (sizeof(struct rte_bbdev_op_ldpc_dec) - ACC_DEC_OFFSET) #define ACC_ENC_OFFSET (32) #define ACC_DEC_OFFSET (80) #define ACC_LIMIT_DL_MUX_BITS 534 From patchwork Wed Oct 9 21:12:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145560 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41F2645AF8; Wed, 9 Oct 2024 23:18:21 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 16B9B40658; Wed, 9 Oct 2024 23:17:53 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id 18487402E4 for ; Wed, 9 Oct 2024 23:17:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728508664; x=1760044664; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ei+7U2Rl6KGe01jHZKAvbhyLFjxJFXcwJC03zQSnyMs=; b=EcRfOFFKjkxJCaU+sc9imKp9Nra85UmIClkIZbny28caBPtZCNdliRPK EbsMIYYYadGZ0eIQS2mL5JjiGp/0VOBMLx88QILhXrCynnunhZ724qDE2 mpohVoUbUtGDWivIoXiqta6kcxvAyaZIBFeU+DfIzCBq810RN0R2cCJQ4 Jt2rrfOmZ+7e5M7oFrI2aiakX97NqVLGiZ/ApwW+7ADAf3T407BgHAFU3 dzOBg1t0nqb8R/9JQqrvhOU6x6aOnVXSTmf5hVT63fe7dgNybAVF6s2SC K3rfdtYBnl1sPG5ymcPrW1to5E0gGHTTCyK2wlFfptFOivEUDz147o32w w==; X-CSE-ConnectionGUID: TF8wUBRXQWq9qQa0Qf/R0g== X-CSE-MsgGUID: nFg1zlwbR/ic+CboUbF+ZQ== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="39202237" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202237" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:43 -0700 X-CSE-ConnectionGUID: SdmNJLGNQgGi/68CPIvkmw== X-CSE-MsgGUID: e6VMZ+2pRf6+6bRgNKzHoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480605" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:42 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 06/12] baseband/acc: enhance SW ring alignment Date: Wed, 9 Oct 2024 14:12:56 -0700 Message-Id: <20241009211302.177471-7-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Calculate the aligned total size required for queue rings, ensuring that the size is a power of two for proper memory allocation. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/acc_common.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 1d8fd24ba008..0c249d5b93fd 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -767,6 +767,7 @@ alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc_device *d, int i = 0; uint32_t q_sw_ring_size = ACC_MAX_QUEUE_DEPTH * get_desc_len(); uint32_t dev_sw_ring_size = q_sw_ring_size * num_queues; + uint32_t alignment = q_sw_ring_size * rte_align32pow2(num_queues); /* Free first in case this is a reconfiguration */ rte_free(d->sw_rings_base); @@ -774,12 +775,12 @@ alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc_device *d, while (i < ACC_SW_RING_MEM_ALLOC_ATTEMPTS) { /* * sw_ring allocated memory is guaranteed to be aligned to - * q_sw_ring_size at the condition that the requested size is - * less than the page size + * the variable 'alignment' at the condition that the requested + * size is less than the page size */ sw_rings_base = rte_zmalloc_socket( dev->device->driver->name, - dev_sw_ring_size, q_sw_ring_size, socket); + dev_sw_ring_size, alignment, socket); if (sw_rings_base == NULL) { rte_acc_log(ERR, From patchwork Wed Oct 9 21:12:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145561 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E576445AF8; Wed, 9 Oct 2024 23:18:26 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7973E40654; Wed, 9 Oct 2024 23:17:54 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id 4202A402E9 for ; Wed, 9 Oct 2024 23:17:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728508664; x=1760044664; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rwZK1NfPhSPAOL1l4HzN+LRRdck6w+HXuEdlfyHfbdQ=; b=m8ak3FasZShFkzSnRJSNJZyy2OAFCppeRbA3dp9UgFp72gTZv2G/T6zq s0bKCZprQV6WJpQ+d2cDmstnGMWjBgR1S7/xAJ49aPAMRXdYDF1X9Vdr2 iF+S7jaKTvNjfWm4xFYOqXw3UfAaUtBbt3oNGSmxOipg6zKTMvstSoKdT C8lQd6nc7GtUZUgnzIxwRY1/WiNUOtsLCftND1QUeYD8UKch085LeqWTe e+o/0MLaLXHyjkb+wyIYrOnBS+wMjBk1TjRznh/v5PwV0R6L/pl/XXBcU FEy/MYqJQBfZ4xYmjefNqkbCNuZA7d9SqUaos/7lt5ZNoeLgsusAMmXEz g==; X-CSE-ConnectionGUID: jy69cXp4TKiea2D616DKrA== X-CSE-MsgGUID: zCqPpvSLSP6H50sjqSgFcg== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="39202240" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202240" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:43 -0700 X-CSE-ConnectionGUID: ftOXI+WwQHmtbd7sggWv6g== X-CSE-MsgGUID: PJ+T3tcQTsKneLnTFOBOcg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480608" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:43 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 07/12] baseband/acc: algorithm tuning for LDPC decoder Date: Wed, 9 Oct 2024 14:12:57 -0700 Message-Id: <20241009211302.177471-8-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Reverting to MS1 version of the algorithm to improve MU1 fading conditions. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_vrb_pmd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 519385e82ed3..4d7535e9d99f 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -1363,7 +1363,7 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info) RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS | RTE_BBDEV_LDPC_DEC_INTERRUPTS, .llr_size = 8, - .llr_decimals = 2, + .llr_decimals = 1, .num_buffers_src = RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, .num_buffers_hard_out = @@ -1737,8 +1737,8 @@ vrb_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, fcw->so_bypass_intlv = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS); fcw->so_bypass_rm = 0; - fcw->minsum_offset = 1; - fcw->dec_llrclip = 2; + fcw->minsum_offset = 0; + fcw->dec_llrclip = 0; } /* From patchwork Wed Oct 9 21:12:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145562 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1BDD945AF8; Wed, 9 Oct 2024 23:18:33 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E65A040663; Wed, 9 Oct 2024 23:17:55 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id 8E6BA402EF for ; Wed, 9 Oct 2024 23:17:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728508665; x=1760044665; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TuekPoS61AcO04BjNONiOdCr8+PJ3XEau0afBOdLtvU=; b=l/ncLC+M4eG+wJyhPk+C9KXTwMlDijKdz3T/iv0CJl0Ci2XcB14Q1LvH JMaGeY/VNSXZCzOyuPwE53PL6isRljoXbT0rr+HVqWLextcYoicb79KWg bn9u7Ha2Mq4vRhJJ6pFXm0gRePAS6MlA2T6o+6Z7s8szfE8TqaNnbhKNQ Vr7A7awU25nIem7IO0R0Kc1/XjOp2QhZc2WA8FGHetAOLiOp7AhF0SP8H 3+Wt8+rbrr9v8/hW45xSBCJSv3yh61HpKWkQHw10gQvn/OkgGAE979rGH wCJLZEb7v5argJCHGzQJgYB5JaAVJJZmcrH/MH/Xsc/8YNWXAG3+kEF0x A==; X-CSE-ConnectionGUID: pq84RCCETDSA48cUmNb9hQ== X-CSE-MsgGUID: 06nT/AO4QDGNwMnobOUMQg== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="39202243" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202243" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:44 -0700 X-CSE-ConnectionGUID: RsRd3SdEQ1aCa+GYXn4xtg== X-CSE-MsgGUID: 0ub6r4T5Rv2s6TzhRjDZAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480614" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:43 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 08/12] baseband/acc: remove check on HARQ memory Date: Wed, 9 Oct 2024 14:12:58 -0700 Message-Id: <20241009211302.177471-9-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Automatically reset HARQ memory to prevent errors and simplify usage. In a way we can assume that the HARQ output operation will always overwrite the buffer, so we can reset this from the driver to prevent an error being reported when application fails to do this explicitly. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_vrb_pmd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 4d7535e9d99f..f7a120688f5a 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -2596,8 +2596,9 @@ vrb_enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, /* Hard output. */ mbuf_append(h_output_head, h_output, h_out_length); if (op->ldpc_dec.harq_combined_output.length > 0) { - /* Push the HARQ output into host memory. */ + /* Push the HARQ output into host memory overwriting existing data. */ struct rte_mbuf *hq_output_head, *hq_output; + op->ldpc_dec.harq_combined_output.data->data_len = 0; hq_output_head = op->ldpc_dec.harq_combined_output.data; hq_output = op->ldpc_dec.harq_combined_output.data; hq_len = op->ldpc_dec.harq_combined_output.length; From patchwork Wed Oct 9 21:12:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145563 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 48EB245AF8; Wed, 9 Oct 2024 23:18:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4E1D040667; Wed, 9 Oct 2024 23:17:57 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id B3D89402E4 for ; Wed, 9 Oct 2024 23:17:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728508665; x=1760044665; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0POG4epq08vSoMfAUr/DvUVhpH6cmfPlOfQtMLcFkhI=; b=WCI2QuBAF74AgEf37htVWEf0GA52oxom1xm0owKaQuTPr8oRdfxZoluv R6+JC7bt4vGYcxEjhSEapj08LKdcQLvWrx7XlJRjFsoNPP27YkZTfh844 VYhn0BKULmrLX9FTKnNnMBqmuOgCziHWG5Zug5rWzyWr1gHKV4etR3Qs8 gxxeyriYK8GG7tOX5YHNLKBHzeM7IrWRYy30mokBD7Vue0AVfBiIE2fc3 7mTtDcrv3LoK7ND+k0op9QRNNtjJgv7zRQTB7q2G1FNDutZ3Qr+apOzQp dk0aKDnCwJiTT7mMav6Ve9Y0SACB+g+nDPJ6eE7gLm2c8cFmBeXC7AgtU w==; X-CSE-ConnectionGUID: aReyx0PVTRSUSBrmcT/ggg== X-CSE-MsgGUID: TqaZIurTSZe82DctqxMS+w== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="39202246" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202246" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:44 -0700 X-CSE-ConnectionGUID: JjmEELhATruEhCbaczijYQ== X-CSE-MsgGUID: SK8STIP7QnKLUakd8mmPMw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480617" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:44 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 09/12] baseband/acc: reset ring data valid bit Date: Wed, 9 Oct 2024 14:12:59 -0700 Message-Id: <20241009211302.177471-10-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Reset only the valid bit to keep info ring data notably for dumping. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_vrb_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index f7a120688f5a..42414823541e 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -412,7 +412,7 @@ vrb_check_ir(struct acc_device *acc_dev) rte_bbdev_log(WARNING, "InfoRing: ITR:%d Info:0x%x", int_nb, ring_data->detailed_info); /* Initialize Info Ring entry and move forward. */ - ring_data->val = 0; + ring_data->valid = 0; } info_ring_head++; ring_data = acc_dev->info_ring + (info_ring_head & ACC_INFO_RING_MASK); From patchwork Wed Oct 9 21:13:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145564 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4B83245AF8; Wed, 9 Oct 2024 23:18:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A4EDE4066C; Wed, 9 Oct 2024 23:17:58 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id DBEA1402E9 for ; Wed, 9 Oct 2024 23:17:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728508665; x=1760044665; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=emkjUEUFuLVmmdsQWxAHu3g4Y0GlO/GNxiLsZmpFUfk=; b=Wxf/vnsLbENjcUBuHfPcoW1rb+ELxBsSTnRE8VmKTTHL1zsVK2LjkKhM OpKH+GIkyoTSQYkUPcCb+a6PbW3sxYsVk4woAMefJme5zSXHFQkCzApmo 5te+WiB489dmAHTKSNPQ+bs8N8HnlENVCpl+8YidSzgC6lsggcAZVmzZR 787rmTJnJ/5Nf56t9qlrqLz80nRUQUSNR0ekgeIYfc6USe2rwWl2Y7/5T 4RsV0AjD5RkKGxq/YyM55l1sSCTIeCpvhz8qQPOzfBNR7GGahwbUrIglW YKdc/0wY8Kj1F7irjjd4J4j1HWpoLB08K1UphhNwmHmE7/38fVlHaNkrI g==; X-CSE-ConnectionGUID: iNppSchyQe23MJibYQgWXQ== X-CSE-MsgGUID: Opc1gyKbSqG8TgxvvA46cQ== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="39202249" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202249" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:44 -0700 X-CSE-ConnectionGUID: BqwD9XDBSfWUjqodP+kv7A== X-CSE-MsgGUID: G3MfG7tXTbi7qdUAv+m/mQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480622" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:44 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 10/12] baseband/acc: cosmetic changes Date: Wed, 9 Oct 2024 14:13:00 -0700 Message-Id: <20241009211302.177471-11-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Cosmetic code changes. No functional impact. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 2 +- drivers/baseband/acc/rte_vrb_pmd.c | 54 +++++++++++++++++---------- 2 files changed, 36 insertions(+), 20 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index c690d1492ba3..c82a0b6cc174 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -4200,7 +4200,7 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d, acc_reg_write(d, HWPfQmgrIngressAq + 0x100, enq_req.val); usleep(ACC_LONG_WAIT * 100); if (desc->req.word0 != 2) - rte_bbdev_log(WARNING, "DMA Response %#"PRIx32, desc->req.word0); + rte_bbdev_log(WARNING, "DMA Response %#"PRIx32"", desc->req.word0); } /* Reset LDPC Cores */ diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 42414823541e..c0464d20c641 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -957,6 +957,9 @@ vrb_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, struct acc_queue *q; int32_t q_idx; int ret; + union acc_dma_desc *desc = NULL; + unsigned int desc_idx, b_idx; + int fcw_len; if (d == NULL) { rte_bbdev_log(ERR, "Undefined device"); @@ -983,16 +986,33 @@ vrb_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, } /* Prepare the Ring with default descriptor format. */ - union acc_dma_desc *desc = NULL; - unsigned int desc_idx, b_idx; - int fcw_len = (conf->op_type == RTE_BBDEV_OP_LDPC_ENC ? - ACC_FCW_LE_BLEN : (conf->op_type == RTE_BBDEV_OP_TURBO_DEC ? - ACC_FCW_TD_BLEN : (conf->op_type == RTE_BBDEV_OP_LDPC_DEC ? - ACC_FCW_LD_BLEN : (conf->op_type == RTE_BBDEV_OP_FFT ? - ACC_FCW_FFT_BLEN : ACC_FCW_MLDTS_BLEN)))); - - if ((q->d->device_variant == VRB2_VARIANT) && (conf->op_type == RTE_BBDEV_OP_FFT)) - fcw_len = ACC_FCW_FFT_BLEN_3; + switch (conf->op_type) { + case RTE_BBDEV_OP_LDPC_ENC: + fcw_len = ACC_FCW_LE_BLEN; + break; + case RTE_BBDEV_OP_LDPC_DEC: + fcw_len = ACC_FCW_LD_BLEN; + break; + case RTE_BBDEV_OP_TURBO_DEC: + fcw_len = ACC_FCW_TD_BLEN; + break; + case RTE_BBDEV_OP_TURBO_ENC: + fcw_len = ACC_FCW_TE_BLEN; + break; + case RTE_BBDEV_OP_FFT: + fcw_len = ACC_FCW_FFT_BLEN; + if (q->d->device_variant == VRB2_VARIANT) + fcw_len = ACC_FCW_FFT_BLEN_3; + break; + case RTE_BBDEV_OP_MLDTS: + fcw_len = ACC_FCW_MLDTS_BLEN; + break; + default: + /* NOT REACHED. */ + fcw_len = 0; + rte_bbdev_log(ERR, "Unexpected error in %s using type %d", __func__, conf->op_type); + break; + } for (desc_idx = 0; desc_idx < d->sw_ring_max_depth; desc_idx++) { desc = q->ring_addr + desc_idx; @@ -1758,8 +1778,7 @@ vrb_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, if (fcw->hcout_en > 0) { parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8) * op->ldpc_dec.z_c - op->ldpc_dec.n_filler; - k0_p = (fcw->k0 > parity_offset) ? - fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; + k0_p = (fcw->k0 > parity_offset) ? fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; ncb_p = fcw->ncb - op->ldpc_dec.n_filler; l = k0_p + fcw->rm_e; harq_out_length = (uint16_t) fcw->hcin_size0; @@ -2001,16 +2020,15 @@ vrb_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, next_triplet++; } - if (check_bit(op->ldpc_dec.op_flags, - RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { if (op->ldpc_dec.harq_combined_output.data == 0) { rte_bbdev_log(ERR, "HARQ output is not defined"); return -1; } - /* Pruned size of the HARQ */ + /* Pruned size of the HARQ. */ h_p_size = fcw->hcout_size0 + fcw->hcout_size1; - /* Non-Pruned size of the HARQ */ + /* Non-Pruned size of the HARQ. */ h_np_size = fcw->hcout_offset > 0 ? fcw->hcout_offset + fcw->hcout_size1 : h_p_size; @@ -2584,7 +2602,6 @@ vrb_enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, seg_total_left = rte_pktmbuf_data_len(input) - in_offset; else seg_total_left = fcw->rm_e; - ret = vrb_dma_desc_ld_fill(op, &desc->req, &input, h_output, &in_offset, &h_out_offset, &h_out_length, &mbuf_total_left, @@ -2646,7 +2663,6 @@ vrb_enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, desc_first = desc; fcw_offset = (desc_idx << 8) + ACC_DESC_FCW_OFFSET; harq_layout = q->d->harq_layout; - vrb_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout, q->d->device_variant); input = op->ldpc_dec.input.data; @@ -3274,7 +3290,7 @@ vrb2_dequeue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **r return 1; } -/* Dequeue one LDPC encode operations from device in TB mode. +/* Dequeue one encode operations from device in TB mode. * That operation may cover multiple descriptors. */ static inline int From patchwork Wed Oct 9 21:13:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145565 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B5B4745AF8; Wed, 9 Oct 2024 23:18:51 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3D1CC40671; Wed, 9 Oct 2024 23:18:00 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id 33DCB402EF for ; Wed, 9 Oct 2024 23:17:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728508665; x=1760044665; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+JNNn4KFmZ9TUszcnvRICTpCSDSLNPJFLpvtDmFFw1M=; b=kra+tpV9Dhg6iJeRSk1DJO/zXSYUjJaE/dnjtmRRMgTqkBgWrefJR8o8 Rlnj6PUMUSs32a83pUkZ5tHbSfsZPldTX5Ha3tnX0CMhfOTVrnxm3Q1M9 oI0W+qPmxz8czrOazfKi1d1O2C3m9/T5Pm0EGrtjogwomN6ysry7jPLSJ PZ8/tL/2zeR0HvxgyhvWS3CA6xSezJhSejMcLDZkOsAQ+hxeXFbeEn9AX 5HduPkLuuJWx0mhSQlZVIeDTk36+febaM1UEEDlob8BOb3A/hcfvUQ+JU Mv1wYsmdPB6NgBqBy2r0hkof3aggqkCDqMY4ULe+D1wohGbruvNNEz3Lw w==; X-CSE-ConnectionGUID: jVpGYAE7RUWEDXzH5g1EAQ== X-CSE-MsgGUID: zVcrf0TOTt6lGA3tuz8A4Q== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="39202252" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202252" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:45 -0700 X-CSE-ConnectionGUID: MIxnPjEISxWNByo65DXDnw== X-CSE-MsgGUID: 3CUIh2LOTBCHeBTmTJbfpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480627" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:44 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 11/12] baseband/acc: rte free refactor Date: Wed, 9 Oct 2024 14:13:01 -0700 Message-Id: <20241009211302.177471-12-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor to explicitly set pointer to NULL after free to avoid double free. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 23 +++++++------ drivers/baseband/acc/rte_vrb_pmd.c | 48 +++++++++++++++------------ 2 files changed, 39 insertions(+), 32 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index c82a0b6cc174..d33e42c8070b 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -564,6 +564,7 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) d->tail_ptrs = NULL; free_sw_rings: rte_free(d->sw_rings_base); + d->sw_rings_base = NULL; d->sw_rings = NULL; return ret; @@ -593,6 +594,7 @@ acc100_intr_enable(struct rte_bbdev *dev) "Couldn't enable interrupts for device: %s", dev->data->name); rte_free(d->info_ring); + d->info_ring = NULL; return ret; } ret = rte_intr_callback_register(dev->intr_handle, @@ -602,6 +604,7 @@ acc100_intr_enable(struct rte_bbdev *dev) "Couldn't register interrupt callback for device: %s", dev->data->name); rte_free(d->info_ring); + d->info_ring = NULL; return ret; } @@ -619,16 +622,15 @@ acc100_dev_close(struct rte_bbdev *dev) { struct acc_device *d = dev->data->dev_private; acc100_check_ir(d); - if (d->sw_rings_base != NULL) { - rte_free(d->tail_ptrs); - rte_free(d->info_ring); - rte_free(d->sw_rings_base); - rte_free(d->harq_layout); - d->sw_rings_base = NULL; - d->tail_ptrs = NULL; - d->info_ring = NULL; - d->harq_layout = NULL; - } + rte_free(d->tail_ptrs); + rte_free(d->info_ring); + rte_free(d->sw_rings_base); + rte_free(d->harq_layout); + d->tail_ptrs = NULL; + d->info_ring = NULL; + d->sw_rings_base = NULL; + d->sw_rings = NULL; + d->harq_layout = NULL; /* Ensure all in flight HW transactions are completed */ usleep(ACC_LONG_WAIT); return 0; @@ -4235,6 +4237,7 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d, rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines); rte_free(d->sw_rings_base); + d->sw_rings_base = NULL; usleep(ACC_LONG_WAIT); } diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index c0464d20c641..03df270af1cf 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -745,10 +745,13 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) free_sw_rings: if (d->device_variant == VRB1_VARIANT) { rte_free(d->sw_rings_base); + d->sw_rings_base = NULL; d->sw_rings = NULL; } else if (d->device_variant == VRB2_VARIANT) { - for (i = 0; i <= RTE_BBDEV_OP_MLDTS; i++) + for (i = 0; i <= RTE_BBDEV_OP_MLDTS; i++) { rte_free(d->sw_rings_array[i]); + d->sw_rings_array[i] = 0; + } } return ret; @@ -786,6 +789,7 @@ vrb_intr_enable(struct rte_bbdev *dev) "Couldn't enable interrupts for device: %s", dev->data->name); rte_free(d->info_ring); + d->info_ring = NULL; return ret; } ret = rte_intr_callback_register(dev->intr_handle, @@ -795,6 +799,7 @@ vrb_intr_enable(struct rte_bbdev *dev) "Couldn't register interrupt callback for device: %s", dev->data->name); rte_free(d->info_ring); + d->info_ring = NULL; return ret; } @@ -849,6 +854,7 @@ vrb_intr_enable(struct rte_bbdev *dev) "Couldn't enable interrupts for device: %s", dev->data->name); rte_free(d->info_ring); + d->info_ring = NULL; return ret; } ret = rte_intr_callback_register(dev->intr_handle, @@ -858,6 +864,7 @@ vrb_intr_enable(struct rte_bbdev *dev) "Couldn't register interrupt callback for device: %s", dev->data->name); rte_free(d->info_ring); + d->info_ring = NULL; return ret; } @@ -878,28 +885,25 @@ vrb_dev_close(struct rte_bbdev *dev) vrb_check_ir(d); if (d->device_variant == VRB1_VARIANT) { - if (d->sw_rings_base != NULL) { - rte_free(d->tail_ptrs); - rte_free(d->info_ring); - rte_free(d->sw_rings_base); - rte_free(d->harq_layout); - d->tail_ptrs = NULL; - d->info_ring = NULL; - d->sw_rings_base = NULL; - d->harq_layout = NULL; - } + rte_free(d->tail_ptrs); + rte_free(d->info_ring); + rte_free(d->sw_rings_base); + rte_free(d->harq_layout); + d->tail_ptrs = NULL; + d->info_ring = NULL; + d->sw_rings_base = NULL; + d->sw_rings = NULL; + d->harq_layout = NULL; } else if (d->device_variant == VRB2_VARIANT) { - if (d->sw_rings_array[1] != NULL) { - rte_free(d->tail_ptrs); - rte_free(d->info_ring); - rte_free(d->harq_layout); - d->tail_ptrs = NULL; - d->info_ring = NULL; - d->harq_layout = NULL; - for (i = 0; i <= RTE_BBDEV_OP_MLDTS; i++) { - rte_free(d->sw_rings_array[i]); - d->sw_rings_array[i] = NULL; - } + rte_free(d->tail_ptrs); + rte_free(d->info_ring); + rte_free(d->harq_layout); + d->tail_ptrs = NULL; + d->info_ring = NULL; + d->harq_layout = NULL; + for (i = 0; i <= RTE_BBDEV_OP_MLDTS; i++) { + rte_free(d->sw_rings_array[i]); + d->sw_rings_array[i] = NULL; } } /* Ensure all in flight HW transactions are completed. */ From patchwork Wed Oct 9 21:13:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 145566 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 086A345AF8; Wed, 9 Oct 2024 23:18:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4804440676; Wed, 9 Oct 2024 23:18:03 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id 7A3B8402E4 for ; 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09 Oct 2024 14:17:45 -0700 X-CSE-ConnectionGUID: n1hq+QAMT/yc1IaSM1WseA== X-CSE-MsgGUID: PpSFswaJQ0+jWW0ppQe78Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480631" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:45 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 12/12] baseband/acc: clean up of VRB1 capabilities Date: Wed, 9 Oct 2024 14:13:02 -0700 Message-Id: <20241009211302.177471-13-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The interrupt support was defeatured on the VRB1 device. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- doc/guides/bbdevs/vrb1.rst | 3 --- drivers/baseband/acc/rte_vrb_pmd.c | 8 ++------ 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/doc/guides/bbdevs/vrb1.rst b/doc/guides/bbdevs/vrb1.rst index 36c1ac04b6d3..e450e0061fcb 100644 --- a/doc/guides/bbdevs/vrb1.rst +++ b/doc/guides/bbdevs/vrb1.rst @@ -33,7 +33,6 @@ These hardware blocks provide the following features exposed by the PMD: - FFT processing - Single Root I/O Virtualization (SR-IOV) with 16 Virtual Functions (VFs) per Physical Function (PF) - Maximum of 256 queues per VF -- Message Signaled Interrupts (MSIs) The Intel vRAN Boost v1.0 PMD supports the following bbdev capabilities: @@ -57,14 +56,12 @@ The Intel vRAN Boost v1.0 PMD supports the following bbdev capabilities: * For the turbo encode operation: - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH``: set to attach CRC24B to CB(s). - ``RTE_BBDEV_TURBO_RATE_MATCH``: if set then do not do Rate Match bypass. - - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS``: set for encoder dequeue interrupts. - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS``: set to bypass RV index. - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER``: supports scatter-gather for input/output data. * For the turbo decode operation: - ``RTE_BBDEV_TURBO_CRC_TYPE_24B``: check CRC24B from CB(s). - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE``: perform subblock de-interleave. - - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS``: set for decoder dequeue interrupts. - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN``: set if negative LLR input is supported. - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP``: keep CRC24B bits appended while decoding. - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP``: option to drop the code block CRC after decoding. diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 03df270af1cf..0455320c2a50 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -1222,7 +1222,6 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info) RTE_BBDEV_TURBO_HALF_ITERATION_EVEN | RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH | RTE_BBDEV_TURBO_EARLY_TERMINATION | - RTE_BBDEV_TURBO_DEC_INTERRUPTS | RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN | RTE_BBDEV_TURBO_MAP_DEC | RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP | @@ -1243,7 +1242,6 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info) RTE_BBDEV_TURBO_CRC_24B_ATTACH | RTE_BBDEV_TURBO_RV_INDEX_BYPASS | RTE_BBDEV_TURBO_RATE_MATCH | - RTE_BBDEV_TURBO_ENC_INTERRUPTS | RTE_BBDEV_TURBO_ENC_SCATTER_GATHER, .num_buffers_src = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS, @@ -1257,8 +1255,7 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info) .capability_flags = RTE_BBDEV_LDPC_RATE_MATCH | RTE_BBDEV_LDPC_CRC_24B_ATTACH | - RTE_BBDEV_LDPC_INTERLEAVER_BYPASS | - RTE_BBDEV_LDPC_ENC_INTERRUPTS, + RTE_BBDEV_LDPC_INTERLEAVER_BYPASS, .num_buffers_src = RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, .num_buffers_dst = @@ -1279,8 +1276,7 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info) RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS | RTE_BBDEV_LDPC_DEC_SCATTER_GATHER | RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION | - RTE_BBDEV_LDPC_LLR_COMPRESSION | - RTE_BBDEV_LDPC_DEC_INTERRUPTS, + RTE_BBDEV_LDPC_LLR_COMPRESSION, .llr_size = 8, .llr_decimals = 1, .num_buffers_src =