From patchwork Tue Oct 15 03:09:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145931 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9517C45B3C; Tue, 15 Oct 2024 05:09:57 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 688C0402D3; Tue, 15 Oct 2024 05:09:57 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id E097940156 for ; Tue, 15 Oct 2024 05:09:54 +0200 (CEST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 49F39qAzA819480, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realsil.com.cn; s=dkim; t=1728961792; bh=cFjtUcjLn46Kg9UqXPnvMNSBchuGzxF848iY0CGbWOA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=qsqI3BO33ol9LzEHJiEgQyd7opLjmsEkiZwgr5sSnhJZ4vOnQ1sX0qJb3YAItJlLY Apbkwul2bsu4QQ95vNrZLfwmSsu9IvC1bWP/HoOaxlWsclMMhVorETTqjY3vXM7lZa B+rV2zT8q7ATrML4Z8cqPPONwyduI3MfKnOSQwb3yQ3bGUrTxBKNr5oRrcrRu+wMBs fB8tbYvXpMJEM9l8+ZeG8zRPAeZ5UnV58glVxENYLUtOSyjVZSlBu9vnPiTLKnEgDX fAdND3NECCz9j9we5+A6RM2rp/vGywG4iByfNDmqYRhZINlCS9soAPt0HJjajlwQHV s89KuTxd9QduA== Received: from RSEXMBS03.realsil.com.cn ([172.29.17.197]) by rtits2.realtek.com.tw (8.15.2/3.06/5.92) with ESMTPS id 49F39qAzA819480 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL) for ; Tue, 15 Oct 2024 11:09:52 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXMBS03.realsil.com.cn (172.29.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:09:52 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:09:52 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 01/18] net/r8169: add PMD driver skeleton Date: Tue, 15 Oct 2024 11:09:11 +0800 Message-ID: <20241015030928.70642-2-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Meson build infrastructure, r8169_ethdev minimal skeleton, header with Realtek NIC device and vendor IDs. Signed-off-by: Howard Wang --- MAINTAINERS | 7 ++ drivers/net/meson.build | 1 + drivers/net/r8169/meson.build | 7 ++ drivers/net/r8169/r8169_base.h | 16 +++ drivers/net/r8169/r8169_ethdev.c | 179 +++++++++++++++++++++++++++++++ drivers/net/r8169/r8169_ethdev.h | 41 +++++++ 6 files changed, 251 insertions(+) create mode 100644 drivers/net/r8169/meson.build create mode 100644 drivers/net/r8169/r8169_base.h create mode 100644 drivers/net/r8169/r8169_ethdev.c create mode 100644 drivers/net/r8169/r8169_ethdev.h diff --git a/MAINTAINERS b/MAINTAINERS index c5a703b5c0..5f9eccc43f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1076,6 +1076,13 @@ F: drivers/net/memif/ F: doc/guides/nics/memif.rst F: doc/guides/nics/features/memif.ini +Realtek r8169 +M: Howard Wang +M: ChunHao Lin +M: Xing Wang +M: Realtek NIC SW +F: drivers/net/r8169 + Crypto Drivers -------------- diff --git a/drivers/net/meson.build b/drivers/net/meson.build index fb6d34b782..fddcf39655 100644 --- a/drivers/net/meson.build +++ b/drivers/net/meson.build @@ -53,6 +53,7 @@ drivers = [ 'pfe', 'qede', 'ring', + 'r8169', 'sfc', 'softnic', 'tap', diff --git a/drivers/net/r8169/meson.build b/drivers/net/r8169/meson.build new file mode 100644 index 0000000000..e37b4fb237 --- /dev/null +++ b/drivers/net/r8169/meson.build @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2024 Realtek Corporation. All rights reserved + +sources = files( + 'r8169_ethdev.c', +) + diff --git a/drivers/net/r8169/r8169_base.h b/drivers/net/r8169/r8169_base.h new file mode 100644 index 0000000000..c3b0186daa --- /dev/null +++ b/drivers/net/r8169/r8169_base.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _R8169_BASE_H_ +#define _R8169_BASE_H_ + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +#define PCI_VENDOR_ID_REALTEK 0x10EC + +#endif + diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c new file mode 100644 index 0000000000..e5f8857304 --- /dev/null +++ b/drivers/net/r8169/r8169_ethdev.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "r8169_ethdev.h" +#include "r8169_base.h" + +static int rtl_dev_configure(struct rte_eth_dev *dev __rte_unused); +static int rtl_dev_start(struct rte_eth_dev *dev); +static int rtl_dev_stop(struct rte_eth_dev *dev); +static int rtl_dev_reset(struct rte_eth_dev *dev); +static int rtl_dev_close(struct rte_eth_dev *dev); + +/* + * The set of PCI devices this driver supports + */ +static const struct rte_pci_id pci_id_r8169_map[] = { + { RTE_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8162) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8126) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x5000) }, + {.vendor_id = 0, /* sentinel */ }, +}; + +static const struct eth_dev_ops rtl_eth_dev_ops = { + .dev_configure = rtl_dev_configure, + .dev_start = rtl_dev_start, + .dev_stop = rtl_dev_stop, + .dev_close = rtl_dev_close, + .dev_reset = rtl_dev_reset, +}; + +static int +rtl_dev_configure(struct rte_eth_dev *dev __rte_unused) +{ + return 0; +} + +/* + * Configure device link speed and setup link. + * It returns 0 on success. + */ +static int +rtl_dev_start(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + hw->adapter_stopped = 0; + + return 0; +} + +/* + * Stop device: disable RX and TX functions to allow for reconfiguring. + */ +static int +rtl_dev_stop(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + if (hw->adapter_stopped) + return 0; + + hw->adapter_stopped = 1; + dev->data->dev_started = 0; + + return 0; +} + +/* + * Reset and stop device. + */ +static int +rtl_dev_close(struct rte_eth_dev *dev) +{ + int ret_stp; + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + ret_stp = rtl_dev_stop(dev); + + return ret_stp; +} + +static int +rtl_dev_init(struct rte_eth_dev *dev) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + dev->dev_ops = &rtl_eth_dev_ops; + + /* For secondary processes, the primary process has done all the work */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rte_eth_copy_pci_info(dev, pci_dev); + + return 0; +} + +static int +rtl_dev_uninit(struct rte_eth_dev *dev) +{ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return -EPERM; + + rtl_dev_close(dev); + + return 0; +} + +static int +rtl_dev_reset(struct rte_eth_dev *dev) +{ + int ret; + + ret = rtl_dev_uninit(dev); + if (ret) + return ret; + + ret = rtl_dev_init(dev); + + return ret; +} + +static int +rtl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct rtl_adapter), + rtl_dev_init); +} + +static int +rtl_pci_remove(struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_remove(pci_dev, rtl_dev_uninit); +} + +static struct rte_pci_driver rte_r8169_pmd = { + .id_table = pci_id_r8169_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, + .probe = rtl_pci_probe, + .remove = rtl_pci_remove, +}; + +RTE_PMD_REGISTER_PCI(net_r8169, rte_r8169_pmd); +RTE_PMD_REGISTER_PCI_TABLE(net_r8169, pci_id_r8169_map); +RTE_PMD_REGISTER_KMOD_DEP(net_r8169, "* igb_uio | uio_pci_generic | vfio-pci"); + diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h new file mode 100644 index 0000000000..5453832e04 --- /dev/null +++ b/drivers/net/r8169/r8169_ethdev.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _R8169_ETHDEV_H_ +#define _R8169_ETHDEV_H_ + +#include +#include + +#include +#include + +#include "r8169_base.h" + +struct rtl_hw { + u8 adapter_stopped; +}; + +struct rtl_sw_stats { + u64 tx_packets; + u64 tx_bytes; + u64 tx_errors; + u64 rx_packets; + u64 rx_bytes; + u64 rx_errors; +}; + +struct rtl_adapter { + struct rtl_hw hw; + struct rtl_sw_stats sw_stats; +}; + +#define RTL_DEV_PRIVATE(eth_dev) \ + ((struct rtl_adapter *)((eth_dev)->data->dev_private)) + +uint16_t rtl_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); +uint16_t rtl_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); + +#endif + From patchwork Tue Oct 15 03:09:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145932 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DEC1A45B3C; Tue, 15 Oct 2024 05:10:04 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D4C4E40662; Tue, 15 Oct 2024 05:10:04 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id 02BE540662 for ; Tue, 15 Oct 2024 05:10:02 +0200 (CEST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 49F3A0xB4819494, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realsil.com.cn; s=dkim; t=1728961800; bh=cmOLMd39VlcyGHmXDf3lcj0pNOETl2sXvk7IzxUz2ks=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=aEouOf8qYNuBw1fzRV0xB9jPvsZaR7Q9HuAP1qHnJHtJmVjyhqYlYlHE0YJjS7iKL Vu2EuikTyB21Pi2WxXMpaRM+TmfSdHOJDo0w6z7lxp6Ib0ADdKqfX/OjHX7oLgZYxA t2nk+4plDTxtb291O6e6KMOTZbo3NMSp25vX2SDSQ2QNmdo7ArFwOAc+Pv67V2JkUM rIBkwwUxgpMcELOl5k87AdHHHw6K+6kJuiU5bVUt9WcTEPCkG221UxhIRhkdQEfd8N wNSGGcUD7GdaFwegcKiu4KLBlRxeTpke0H7GcZf+mLGJqV7R2mmLkiiruhzrMWOIVR MowKGBp4upYSQ== Received: from RSEXMBS03.realsil.com.cn ([172.29.17.197]) by rtits2.realtek.com.tw (8.15.2/3.06/5.92) with ESMTPS id 49F3A0xB4819494 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL) for ; Tue, 15 Oct 2024 11:10:00 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXMBS03.realsil.com.cn (172.29.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:10:00 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:10:00 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 02/18] net/r8169: add logging structure Date: Tue, 15 Oct 2024 11:09:12 +0800 Message-ID: <20241015030928.70642-3-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement logging macros for debug purposes. Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_ethdev.c | 40 ++++++++++++++++++++++++ drivers/net/r8169/r8169_logs.h | 53 ++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+) create mode 100644 drivers/net/r8169/r8169_logs.h diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index e5f8857304..09e12fb56d 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -177,3 +177,43 @@ RTE_PMD_REGISTER_PCI(net_r8169, rte_r8169_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_r8169, pci_id_r8169_map); RTE_PMD_REGISTER_KMOD_DEP(net_r8169, "* igb_uio | uio_pci_generic | vfio-pci"); +int r8169_logtype_init; +int r8169_logtype_driver; + +#ifdef RTE_LIBRTE_R8169_DEBUG_RX +int r8169_logtype_rx; +#endif +#ifdef RTE_LIBRTE_R8169_DEBUG_TX +int r8169_logtype_tx; +#endif +#ifdef RTE_LIBRTE_R8169_DEBUG_TX_FREE +int r8169_logtype_tx_free; +#endif + +RTE_INIT(r8169_init_log) +{ + r8169_logtype_init = rte_log_register("pmd.net.r8169.init"); + if (r8169_logtype_init >= 0) + rte_log_set_level(r8169_logtype_init, RTE_LOG_NOTICE); + r8169_logtype_driver = rte_log_register("pmd.net.r8169.driver"); + if (r8169_logtype_driver >= 0) + rte_log_set_level(r8169_logtype_driver, RTE_LOG_NOTICE); +#ifdef RTE_LIBRTE_R8169_DEBUG_RX + r8169_logtype_rx = rte_log_register("pmd.net.r8169.rx"); + if (r8169_logtype_rx >= 0) + rte_log_set_level(r8169_logtype_rx, RTE_LOG_DEBUG); +#endif + +#ifdef RTE_LIBRTE_R8169_DEBUG_TX + r8169_logtype_tx = rte_log_register("pmd.net.r8169.tx"); + if (r8169_logtype_tx >= 0) + rte_log_set_level(r8169_logtype_tx, RTE_LOG_DEBUG); +#endif + +#ifdef RTE_LIBRTE_R8169_DEBUG_TX_FREE + r8169_logtype_tx_free = rte_log_register("pmd.net.r8169.tx_free"); + if (r8169_logtype_tx_free >= 0) + rte_log_set_level(r8169_logtype_tx_free, RTE_LOG_DEBUG); +#endif +} + diff --git a/drivers/net/r8169/r8169_logs.h b/drivers/net/r8169/r8169_logs.h new file mode 100644 index 0000000000..6ce5b4b5ac --- /dev/null +++ b/drivers/net/r8169/r8169_logs.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _R8169_LOGS_H_ +#define _R8169_LOGS_H_ + +#include + +extern int r8169_logtype_init; +#define PMD_INIT_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, r8169_logtype_init, \ + "%s(): " fmt "\n", __func__, ##args) + +#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, " >>") + +#ifdef RTE_LIBRTE_R8169_DEBUG_RX +extern int r8169_logtype_rx; +#define PMD_RX_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, r8169_logtype_rx, \ + "%s(): " fmt "\n", __func__, ## args) +#else +#define PMD_RX_LOG(level, fmt, args...) do { } while (0) +#endif + +#ifdef RTE_LIBRTE_R8169_DEBUG_TX +extern int r8169_logtype_tx; +#define PMD_TX_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, r8169_logtype_tx, \ + "%s(): " fmt "\n", __func__, ## args) +#else +#define PMD_TX_LOG(level, fmt, args...) do { } while (0) +#endif + +#ifdef RTE_LIBRTE_R8169_DEBUG_TX_FREE +extern int r8169_logtype_tx_free; +#define PMD_TX_FREE_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, r8169_logtype_tx_free, \ + "%s(): " fmt "\n", __func__, ## args) +#else +#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while (0) +#endif + +extern int r8169_logtype_driver; +#define PMD_DRV_LOG_RAW(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, r8169_logtype_driver, "%s(): " fmt, \ + __func__, ## args) + +#define PMD_DRV_LOG(level, fmt, args...) \ + PMD_DRV_LOG_RAW(level, fmt "\n", ## args) + +#endif /* _R8169_LOGS_H_ */ + From patchwork Tue Oct 15 03:09:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145933 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5E1EB45B3C; Tue, 15 Oct 2024 05:10:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 57B8240664; Tue, 15 Oct 2024 05:10:12 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id F00EF4064E for ; Tue, 15 Oct 2024 05:10:09 +0200 (CEST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 49F3A75g8819516, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realsil.com.cn; s=dkim; t=1728961808; bh=aUdPNR8xwXwMOVSRBB+oqJgfzZN9ZAKCGe/wpLPSpk4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=L3kMPS/+081McZMjDNVRx41f6FvG9ZHPU/vBcK3yn5Rjr0hXl0CddrGqCWO8BKdlf 5orGk19ETLdq/hYv0NdyMzCIl89msvZ5BpU0i+oo9FzLv1VNVaStJgcwBI4eCstd7Q pS5hRpQCPFG83e41QN25GA3I+xKXRWJBAaVRAXE7PStga8tMm1xIs+2UF0XBXJihl9 /YLteX0kfFeoO5M4p9q01eBscBok7ryOgpc/BwxoWSLABmW1UMBYTb7cRH9q7kHv10 qeaSzaDKJYRzxq+re9EcvAyCXo3bJge1FpbLz3d7nnfM7cignzTeHTiTJB7EO3h7/E 2IkmDlf8u5oXA== Received: from RSEXMBS03.realsil.com.cn ([172.29.17.197]) by rtits2.realtek.com.tw (8.15.2/3.06/5.92) with ESMTPS id 49F3A75g8819516 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL) for ; Tue, 15 Oct 2024 11:10:08 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXMBS03.realsil.com.cn (172.29.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:10:06 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:10:06 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 03/18] net/r8169: add hardware registers access routines Date: Tue, 15 Oct 2024 11:09:13 +0800 Message-ID: <20241015030928.70642-4-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add implementation for hardware registers access routines. Signed-off-by: Howard Wang --- drivers/net/r8169/meson.build | 1 + drivers/net/r8169/r8169_base.h | 389 +++++++++++++++++++++++++++++++ drivers/net/r8169/r8169_ethdev.h | 1 + drivers/net/r8169/r8169_hw.c | 94 ++++++++ drivers/net/r8169/r8169_hw.h | 29 +++ 5 files changed, 514 insertions(+) create mode 100644 drivers/net/r8169/r8169_hw.c create mode 100644 drivers/net/r8169/r8169_hw.h diff --git a/drivers/net/r8169/meson.build b/drivers/net/r8169/meson.build index e37b4fb237..f659e56192 100644 --- a/drivers/net/r8169/meson.build +++ b/drivers/net/r8169/meson.build @@ -3,5 +3,6 @@ sources = files( 'r8169_ethdev.c', + 'r8169_hw.c', ) diff --git a/drivers/net/r8169/r8169_base.h b/drivers/net/r8169/r8169_base.h index c3b0186daa..0e79d8d22a 100644 --- a/drivers/net/r8169/r8169_base.h +++ b/drivers/net/r8169/r8169_base.h @@ -5,12 +5,401 @@ #ifndef _R8169_BASE_H_ #define _R8169_BASE_H_ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + typedef uint8_t u8; typedef uint16_t u16; typedef uint32_t u32; typedef uint64_t u64; +enum RTL_registers { + MAC0 = 0x00, /* Ethernet hardware address */ + MAC4 = 0x04, + MAR0 = 0x08, /* Multicast filter */ + CounterAddrLow = 0x10, + CounterAddrHigh = 0x14, + CustomLED = 0x18, + TxDescStartAddrLow = 0x20, + TxDescStartAddrHigh = 0x24, + TxHDescStartAddrLow = 0x28, + TxHDescStartAddrHigh = 0x2C, + FLASH = 0x30, + INT_CFG0_8125 = 0x34, + ERSR = 0x36, + ChipCmd = 0x37, + TxPoll = 0x38, + IntrMask = 0x3C, + IntrStatus = 0x3E, + TxConfig = 0x40, + RxConfig = 0x44, + TCTR = 0x48, + Cfg9346 = 0x50, + Config0 = 0x51, + Config1 = 0x52, + Config2 = 0x53, + Config3 = 0x54, + Config4 = 0x55, + Config5 = 0x56, + TDFNR = 0x57, + TimeInt0 = 0x58, + TimeInt1 = 0x5C, + PHYAR = 0x60, + CSIDR = 0x64, + CSIAR = 0x68, + PHYstatus = 0x6C, + MACDBG = 0x6D, + GPIO = 0x6E, + PMCH = 0x6F, + ERIDR = 0x70, + ERIAR = 0x74, + INT_CFG1_8125 = 0x7A, + EPHY_RXER_NUM = 0x7C, + EPHYAR = 0x80, + TimeInt2 = 0x8C, + OCPDR = 0xB0, + MACOCP = 0xB0, + OCPAR = 0xB4, + SecMAC0 = 0xB4, + SecMAC4 = 0xB8, + PHYOCP = 0xB8, + DBG_reg = 0xD1, + TwiCmdReg = 0xD2, + MCUCmd_reg = 0xD3, + RxMaxSize = 0xDA, + EFUSEAR = 0xDC, + CPlusCmd = 0xE0, + IntrMitigate = 0xE2, + RxDescAddrLow = 0xE4, + RxDescAddrHigh = 0xE8, + MTPS = 0xEC, + FuncEvent = 0xF0, + PPSW = 0xF2, + FuncEventMask = 0xF4, + TimeInt3 = 0xF4, + FuncPresetState = 0xF8, + CMAC_IBCR0 = 0xF8, + CMAC_IBCR2 = 0xF9, + CMAC_IBIMR0 = 0xFA, + CMAC_IBISR0 = 0xFB, + FuncForceEvent = 0xFC, + + /* 8125 */ + IMR0_8125 = 0x38, + ISR0_8125 = 0x3C, + TPPOLL_8125 = 0x90, + IMR1_8125 = 0x800, + ISR1_8125 = 0x802, + IMR2_8125 = 0x804, + ISR2_8125 = 0x806, + IMR3_8125 = 0x808, + ISR3_8125 = 0x80A, + BACKUP_ADDR0_8125 = 0x19E0, + BACKUP_ADDR1_8125 = 0X19E4, + TCTR0_8125 = 0x0048, + TCTR1_8125 = 0x004C, + TCTR2_8125 = 0x0088, + TCTR3_8125 = 0x001C, + TIMER_INT0_8125 = 0x0058, + TIMER_INT1_8125 = 0x005C, + TIMER_INT2_8125 = 0x008C, + TIMER_INT3_8125 = 0x00F4, + INT_MITI_V2_0_RX = 0x0A00, + INT_MITI_V2_0_TX = 0x0A02, + INT_MITI_V2_1_RX = 0x0A08, + INT_MITI_V2_1_TX = 0x0A0A, + IMR_V2_CLEAR_REG_8125 = 0x0D00, + ISR_V2_8125 = 0x0D04, + IMR_V2_SET_REG_8125 = 0x0D0C, + TDU_STA_8125 = 0x0D08, + RDU_STA_8125 = 0x0D0A, + IMR_V4_L2_CLEAR_REG_8125 = 0x0D10, + IMR_V4_L2_SET_REG_8125 = 0x0D18, + ISR_V4_L2_8125 = 0x0D14, + DOUBLE_VLAN_CONFIG = 0x1000, + TX_NEW_CTRL = 0x203E, + TNPDS_Q1_LOW_8125 = 0x2100, + PLA_TXQ0_IDLE_CREDIT = 0x2500, + PLA_TXQ1_IDLE_CREDIT = 0x2504, + SW_TAIL_PTR0_8125 = 0x2800, + HW_CLO_PTR0_8125 = 0x2802, + SW_TAIL_PTR0_8126 = 0x2800, + HW_CLO_PTR0_8126 = 0x2800, + RDSAR_Q1_LOW_8125 = 0x4000, + RSS_CTRL_8125 = 0x4500, + Q_NUM_CTRL_8125 = 0x4800, + RSS_KEY_8125 = 0x4600, + RSS_INDIRECTION_TBL_8125_V2 = 0x4700, + EEE_TXIDLE_TIMER_8125 = 0x6048, +}; + +enum RTL_register_content { + /* Interrupt status bits */ + SYSErr = 0x8000, + PCSTimeout = 0x4000, + SWInt = 0x0100, + TxDescUnavail = 0x0080, + RxFIFOOver = 0x0040, + LinkChg = 0x0020, + RxDescUnavail = 0x0010, + TxErr = 0x0008, + TxOK = 0x0004, + RxErr = 0x0002, + RxOK = 0x0001, + + /* RX status desc */ + RxRWT = (1UL << 22), + RxRES = (1UL << 21), + RxRUNT = (1UL << 20), + RxCRC = (1UL << 19), + + /* ChipCmd bits */ + StopReq = 0x80, + CmdReset = 0x10, + CmdRxEnb = 0x08, + CmdTxEnb = 0x04, + RxBufEmpty = 0x01, + + /* Cfg9346 bits */ + Cfg9346_Lock = 0x00, + Cfg9346_Unlock = 0xC0, + Cfg9346_EEDO = (1UL << 0), + Cfg9346_EEDI = (1UL << 1), + Cfg9346_EESK = (1UL << 2), + Cfg9346_EECS = (1UL << 3), + Cfg9346_EEM0 = (1UL << 6), + Cfg9346_EEM1 = (1UL << 7), + + /* RX mode bits */ + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0x08, + AcceptMulticast = 0x04, + AcceptMyPhys = 0x02, + AcceptAllPhys = 0x01, + + /* Transmit priority polling */ + HPQ = 0x80, + NPQ = 0x40, + FSWInt = 0x01, + + /* RX config bits */ + Reserved2_shift = 13, + RxCfgDMAShift = 8, + EnableRxDescV3 = (1 << 24), + EnableOuterVlan = (1 << 23), + EnableInnerVlan = (1 << 22), + RxCfg_128_int_en = (1 << 15), + RxCfg_fet_multi_en = (1 << 14), + RxCfg_half_refetch = (1 << 13), + RxCfg_pause_slot_en = (1 << 11), + RxCfg_9356SEL = (1 << 6), + EnableRxDescV4_0 = (1 << 1), /* Not in rcr */ + + /* TX config bits */ + TxInterFrameGapShift = 24, + TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits. */ + TxMACLoopBack = (1UL << 17), /* MAC loopback */ + + /* Config1 register */ + LEDS1 = (1UL << 7), + LEDS0 = (1UL << 6), + Speed_down = (1UL << 4), + MEMMAP = (1UL << 3), + IOMAP = (1UL << 2), + VPD = (1UL << 1), + PMEnable = (1UL << 0), /* Power management enable */ + + /* Config2 register */ + PMSTS_En = (1UL << 5), + + /* Config3 register */ + Isolate_en = (1UL << 12), /* Isolate enable */ + MagicPacket = (1UL << 5), /* Wake up when receives a magic packet */ + LinkUp = (1UL << 4), /* This bit is reserved in RTL8125B. */ + + /* Wake up when the cable connection is re-established */ + ECRCEN = (1UL << 3), /* This bit is reserved in RTL8125B. */ + Jumbo_En0 = (1UL << 2), /* This bit is reserved in RTL8125B. */ + RDY_TO_L23 = (1UL << 1), /* This bit is reserved in RTL8125B. */ + Beacon_en = (1UL << 0), /* This bit is reserved in RTL8125B. */ + + /* Config4 register */ + Jumbo_En1 = (1UL << 1), /* This bit is reserved in RTL8125B. */ + + /* Config5 register */ + BWF = (1UL << 6), /* Accept broadcast wakeup frame */ + MWF = (1UL << 5), /* Accept multicast wakeup frame */ + UWF = (1UL << 4), /* Accept unicast wakeup frame */ + LanWake = (1UL << 1), /* LanWake enable/disable */ + PMEStatus = (1UL << 0), /* PME status can be reset by PCI RST#. */ + + /* CPlusCmd */ + EnableBist = (1UL << 15), + Macdbgo_oe = (1UL << 14), + Normal_mode = (1UL << 13), + Force_halfdup = (1UL << 12), + Force_rxflow_en = (1UL << 11), + Force_txflow_en = (1UL << 10), + Cxpl_dbg_sel = (1UL << 9), /* This bit is reserved in RTL8125B. */ + ASF = (1UL << 8), /* This bit is reserved in RTL8125C. */ + PktCntrDisable = (1UL << 7), + RxVlan = (1UL << 6), + RxChkSum = (1UL << 5), + Macdbgo_sel = 0x001C, + INTT_0 = 0x0000, + INTT_1 = 0x0001, + INTT_2 = 0x0002, + INTT_3 = 0x0003, + + /* PHY status */ + PowerSaveStatus = 0x80, + _2500bpsF = 0x400, + TxFlowCtrl = 0x40, + RxFlowCtrl = 0x20, + _1000bpsF = 0x10, + _100bps = 0x08, + _10bps = 0x04, + LinkStatus = 0x02, + FullDup = 0x01, + + /* DBG reg */ + Fix_Nak_1 = (1UL << 4), + Fix_Nak_2 = (1UL << 3), + DBGPIN_E2 = (1UL << 0), + + /* Reset counter command */ + CounterReset = 0x1, + /* Dump counter command */ + CounterDump = 0x8, + + /* PHY access */ + PHYAR_Flag = 0x80000000, + PHYAR_Write = 0x80000000, + PHYAR_Read = 0x00000000, + PHYAR_Reg_Mask = 0x1f, + PHYAR_Reg_shift = 16, + PHYAR_Data_Mask = 0xffff, + + /* EPHY access */ + EPHYAR_Flag = 0x80000000, + EPHYAR_Write = 0x80000000, + EPHYAR_Read = 0x00000000, + EPHYAR_Reg_Mask = 0x3f, + EPHYAR_Reg_Mask_v2 = 0x7f, + EPHYAR_Reg_shift = 16, + EPHYAR_Data_Mask = 0xffff, + + /* CSI access */ + CSIAR_Flag = 0x80000000, + CSIAR_Write = 0x80000000, + CSIAR_Read = 0x00000000, + CSIAR_ByteEn = 0x0f, + CSIAR_ByteEn_shift = 12, + CSIAR_Addr_Mask = 0x0fff, + + /* ERI access */ + ERIAR_Flag = 0x80000000, + ERIAR_Write = 0x80000000, + ERIAR_Read = 0x00000000, + ERIAR_Addr_Align = 4, /* ERI access register address must be 4 byte alignment. */ + ERIAR_ExGMAC = 0, + ERIAR_MSIX = 1, + ERIAR_ASF = 2, + ERIAR_OOB = 2, + ERIAR_Type_shift = 16, + ERIAR_ByteEn = 0x0f, + ERIAR_ByteEn_shift = 12, + + /* OCP GPHY access */ + OCPDR_Write = 0x80000000, + OCPDR_Read = 0x00000000, + OCPDR_Reg_Mask = 0xFF, + OCPDR_Data_Mask = 0xFFFF, + OCPDR_GPHY_Reg_shift = 16, + OCPAR_Flag = 0x80000000, + OCPAR_GPHY_Write = 0x8000F060, + OCPAR_GPHY_Read = 0x0000F060, + OCPR_Write = 0x80000000, + OCPR_Read = 0x00000000, + OCPR_Addr_Reg_shift = 16, + OCPR_Flag = 0x80000000, + OCP_STD_PHY_BASE_PAGE = 0x0A40, + + /* MCU command */ + Now_is_oob = (1UL << 7), + Txfifo_empty = (1UL << 5), + Rxfifo_empty = (1UL << 4), + + /* E-FUSE access */ + EFUSE_WRITE = 0x80000000, + EFUSE_WRITE_OK = 0x00000000, + EFUSE_READ = 0x00000000, + EFUSE_READ_OK = 0x80000000, + EFUSE_WRITE_V3 = 0x40000000, + EFUSE_WRITE_OK_V3 = 0x00000000, + EFUSE_READ_V3 = 0x80000000, + EFUSE_READ_OK_V3 = 0x00000000, + EFUSE_Reg_Mask = 0x03FF, + EFUSE_Reg_Shift = 8, + EFUSE_Check_Cnt = 300, + EFUSE_READ_FAIL = 0xFF, + EFUSE_Data_Mask = 0x000000FF, + + /* GPIO */ + GPIO_en = (1UL << 0), + + /* New interrupt bits */ + INT_CFG0_ENABLE_8125 = (1 << 0), + INT_CFG0_TIMEOUT0_BYPASS_8125 = (1 << 1), + INT_CFG0_MITIGATION_BYPASS_8125 = (1 << 2), + ISRIMR_V2_ROK_Q0 = (1 << 0), + ISRIMR_TOK_Q0 = (1 << 16), + ISRIMR_TOK_Q1 = (1 << 18), + ISRIMR_V2_LINKCHG = (1 << 21), +}; + #define PCI_VENDOR_ID_REALTEK 0x10EC +#define RTL_PCI_REG_ADDR(hw, reg) ((u8 *)(hw)->mmio_addr + (reg)) + +#define RTL_R8(hw, reg) rte_read8(RTL_PCI_REG_ADDR(hw, reg)) +#define RTL_R16(hw, reg) rtl_read16(RTL_PCI_REG_ADDR(hw, reg)) +#define RTL_R32(hw, reg) rtl_read32(RTL_PCI_REG_ADDR(hw, reg)) + +#define RTL_W8(hw, reg, val) \ + rte_write8((val), RTL_PCI_REG_ADDR(hw, reg)) +#define RTL_W16(hw, reg, val) \ + rte_write16((rte_cpu_to_le_16(val)), RTL_PCI_REG_ADDR(hw, reg)) +#define RTL_W32(hw, reg, val) \ + rte_write32((rte_cpu_to_le_32(val)), RTL_PCI_REG_ADDR(hw, reg)) + +#define mdelay rte_delay_ms +#define udelay rte_delay_us +#define msleep rte_delay_ms +#define usleep rte_delay_us + +static inline u32 +rtl_read32(volatile void *addr) +{ + return rte_le_to_cpu_32(rte_read32(addr)); +} + +static inline u32 +rtl_read16(volatile void *addr) +{ + return rte_le_to_cpu_16(rte_read16(addr)); +} + #endif diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index 5453832e04..04458dc497 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -15,6 +15,7 @@ struct rtl_hw { u8 adapter_stopped; + u8 *mmio_addr; }; struct rtl_sw_stats { diff --git a/drivers/net/r8169/r8169_hw.c b/drivers/net/r8169/r8169_hw.c new file mode 100644 index 0000000000..b3c0c23ecf --- /dev/null +++ b/drivers/net/r8169/r8169_hw.c @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include "r8169_hw.h" +#include "r8169_logs.h" + +void +rtl_mac_ocp_write(struct rtl_hw *hw, u16 addr, u16 value) +{ + u32 data32; + + data32 = addr / 2; + data32 <<= OCPR_Addr_Reg_shift; + data32 += value; + data32 |= OCPR_Write; + + RTL_W32(hw, MACOCP, data32); +} + +u16 +rtl_mac_ocp_read(struct rtl_hw *hw, u16 addr) +{ + u32 data32; + u16 data16 = 0; + + data32 = addr / 2; + data32 <<= OCPR_Addr_Reg_shift; + + RTL_W32(hw, MACOCP, data32); + data16 = (u16)RTL_R32(hw, MACOCP); + + return data16; +} + +u32 +rtl_csi_read(struct rtl_hw *hw, u32 addr) +{ + u32 cmd; + int i; + u32 value = 0; + + cmd = CSIAR_Read | CSIAR_ByteEn << CSIAR_ByteEn_shift | + (addr & CSIAR_Addr_Mask); + + RTL_W32(hw, CSIAR, cmd); + + for (i = 0; i < 10; i++) { + udelay(100); + + /* Check if the NIC has completed CSI read */ + if (RTL_R32(hw, CSIAR) & CSIAR_Flag) { + value = RTL_R32(hw, CSIDR); + break; + } + } + + udelay(20); + + return value; +} + +void +rtl_csi_write(struct rtl_hw *hw, u32 addr, u32 value) +{ + u32 cmd; + int i; + + RTL_W32(hw, CSIDR, value); + cmd = CSIAR_Write | CSIAR_ByteEn << CSIAR_ByteEn_shift | + (addr & CSIAR_Addr_Mask); + + RTL_W32(hw, CSIAR, cmd); + + for (i = 0; i < RTL_CHANNEL_WAIT_COUNT; i++) { + udelay(RTL_CHANNEL_WAIT_TIME); + + /* Check if the NIC has completed CSI write */ + if (!(RTL_R32(hw, CSIAR) & CSIAR_Flag)) + break; + } + + udelay(RTL_CHANNEL_EXIT_DELAY_TIME); +} + diff --git a/drivers/net/r8169/r8169_hw.h b/drivers/net/r8169/r8169_hw.h new file mode 100644 index 0000000000..e62b99a068 --- /dev/null +++ b/drivers/net/r8169/r8169_hw.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _R8169_HW_H_ +#define _R8169_HW_H_ + +#include + +#include +#include +#include + +#include "r8169_base.h" +#include "r8169_ethdev.h" + +u16 rtl_mac_ocp_read(struct rtl_hw *hw, u16 addr); +void rtl_mac_ocp_write(struct rtl_hw *hw, u16 addr, u16 value); + +u32 rtl_csi_read(struct rtl_hw *hw, u32 addr); +void rtl_csi_write(struct rtl_hw *hw, u32 addr, u32 value); + +/* Channel wait count */ +#define RTL_CHANNEL_WAIT_COUNT 20000 +#define RTL_CHANNEL_WAIT_TIME 1 /* 1 us */ +#define RTL_CHANNEL_EXIT_DELAY_TIME 20 /* 20 us */ + +#endif + From patchwork Tue Oct 15 03:09:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145934 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4653645B3C; Tue, 15 Oct 2024 05:10:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 293EC4065C; Tue, 15 Oct 2024 05:10:19 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id 4FB4E40661 for ; Tue, 15 Oct 2024 05:10:17 +0200 (CEST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 49F3AFTa8819604, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realsil.com.cn; s=dkim; t=1728961815; bh=BtDTj+RFDwpzSe2QC4Vx5NSu2Y96j29BLdZ72/P9IOc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=oZxtEgC8EBgP7Qcryo9usuRHMZfPYFCgbajbRoL1patblXvFG6Keu69iW9Aqaegfw sviYBxNV5sLBhYFF3Lwb5om0DSpHO0OwQDm3c35E4sM3MfSSGf/WZi7knVRaLNnI3Q fk9UgR4+fK3qjncUYgWhcYijBfrSYWv2Ct2sJ5a780k1TGqGeRVpp19BMVz806mp2+ nlbNxcy79t8ZrSjbMzsLeiZpE0UEdSbTrtNztKCVhptEYGLOp/3W/vuV2eqDYTkR2C D/RFQ8keRA4dhl9zIh0dcqY3UhpvzhzwMwlGeisLlCGEBVogqFmi8N/wRLyhVzWVSi Nn1eqgtjEUl/g== Received: from RSEXMBS03.realsil.com.cn ([172.29.17.197]) by rtits2.realtek.com.tw (8.15.2/3.06/5.92) with ESMTPS id 49F3AFTa8819604 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL) for ; Tue, 15 Oct 2024 11:10:15 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXMBS03.realsil.com.cn (172.29.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:10:15 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:10:15 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 04/18] net/r8169: implement core logic for Tx/Rx Date: Tue, 15 Oct 2024 11:09:14 +0800 Message-ID: <20241015030928.70642-5-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add RX/TX function prototypes for further datapath development. Signed-off-by: Howard Wang --- drivers/net/r8169/meson.build | 1 + drivers/net/r8169/r8169_ethdev.c | 17 ++++++++++ drivers/net/r8169/r8169_ethdev.h | 3 ++ drivers/net/r8169/r8169_rxtx.c | 57 ++++++++++++++++++++++++++++++++ 4 files changed, 78 insertions(+) create mode 100644 drivers/net/r8169/r8169_rxtx.c diff --git a/drivers/net/r8169/meson.build b/drivers/net/r8169/meson.build index f659e56192..ff7d6ca4b8 100644 --- a/drivers/net/r8169/meson.build +++ b/drivers/net/r8169/meson.build @@ -4,5 +4,6 @@ sources = files( 'r8169_ethdev.c', 'r8169_hw.c', + 'r8169_rxtx.c', ) diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index 09e12fb56d..92121ad3fb 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -27,6 +27,8 @@ #include "r8169_ethdev.h" #include "r8169_base.h" +#include "r8169_logs.h" +#include "r8169_hw.h" static int rtl_dev_configure(struct rte_eth_dev *dev __rte_unused); static int rtl_dev_start(struct rte_eth_dev *dev); @@ -68,10 +70,23 @@ rtl_dev_start(struct rte_eth_dev *dev) { struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); struct rtl_hw *hw = &adapter->hw; + int err; + + /* Initialize transmission unit */ + rtl_tx_init(dev); + + /* This can fail when allocating mbufs for descriptor rings */ + err = rtl_rx_init(dev); + if (err) { + PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); + goto error; + } hw->adapter_stopped = 0; return 0; +error: + return -EIO; } /* @@ -117,6 +132,8 @@ rtl_dev_init(struct rte_eth_dev *dev) struct rtl_hw *hw = &adapter->hw; dev->dev_ops = &rtl_eth_dev_ops; + dev->tx_pkt_burst = &rtl_xmit_pkts; + dev->rx_pkt_burst = &rtl_recv_pkts; /* For secondary processes, the primary process has done all the work */ if (rte_eal_process_type() != RTE_PROC_PRIMARY) diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index 04458dc497..7c6e110e7f 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -35,6 +35,9 @@ struct rtl_adapter { #define RTL_DEV_PRIVATE(eth_dev) \ ((struct rtl_adapter *)((eth_dev)->data->dev_private)) +int rtl_rx_init(struct rte_eth_dev *dev); +int rtl_tx_init(struct rte_eth_dev *dev); + uint16_t rtl_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); uint16_t rtl_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); diff --git a/drivers/net/r8169/r8169_rxtx.c b/drivers/net/r8169/r8169_rxtx.c new file mode 100644 index 0000000000..cce78d4e60 --- /dev/null +++ b/drivers/net/r8169/r8169_rxtx.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "r8169_ethdev.h" +#include "r8169_hw.h" +#include "r8169_logs.h" + +/* ---------------------------------RX---------------------------------- */ +int +rtl_rx_init(struct rte_eth_dev *dev) +{ + return 0; +} + +uint16_t +rtl_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) +{ + return 0; +} + +/* ---------------------------------TX---------------------------------- */ +int +rtl_tx_init(struct rte_eth_dev *dev) +{ + return 0; +} + +uint16_t +rtl_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) +{ + return 0; +} + From patchwork Tue Oct 15 03:09:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145935 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5959C45B3C; Tue, 15 Oct 2024 05:10:27 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3B24F4065D; Tue, 15 Oct 2024 05:10:27 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id 7A9AB4065E for ; Tue, 15 Oct 2024 05:10:24 +0200 (CEST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 49F3ALOO0819636, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realsil.com.cn; s=dkim; t=1728961822; bh=KR2t32CYRFik2ZQAfRSREyV3u0fJTFllzdZrPAtVlUw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=M62TrZM5ihDzZ3COXQyDqWkSNXe60QKlBJPQ7sYXsJtVAufg2BJCFctAWxkWLaDZQ vYLD4IMbPFbbZAszXd76scz4e/vizIGVBq+kg/kgW9RFD9vBd9Ne7w1Bm001Bd8/aA ZkWVcuFCXaCGarFaIOGDRd/iUbF3CB1xttRnvZsZOPNT2AfAXjR/ChvEHO+jxZNXM3 7z0FSrB6ht2hhIrJTiZf15UixLrGHz4t0UIQLoEjq1U823E+O3KOxCoxp0laRjuIoy TevZ2BdlXMwWY7h+y8eFjFB5p1qU5J9F8Ui1wDCF7SzigDW5be/ZZMI+23mFSAzuJu qtBcALLlw142Q== Received: from RSEXMBS03.realsil.com.cn ([172.29.17.197]) by rtits2.realtek.com.tw (8.15.2/3.06/5.92) with ESMTPS id 49F3ALOO0819636 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL) for ; Tue, 15 Oct 2024 11:10:22 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXMBS03.realsil.com.cn (172.29.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:10:22 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:10:22 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 05/18] net/r8169: add support for hw config Date: Tue, 15 Oct 2024 11:09:15 +0800 Message-ID: <20241015030928.70642-6-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement the rtl_hw_config function to configure the hardware. Signed-off-by: Howard Wang --- drivers/net/r8169/meson.build | 1 + drivers/net/r8169/r8169_base.h | 125 ++++++ drivers/net/r8169/r8169_ethdev.c | 2 + drivers/net/r8169/r8169_ethdev.h | 15 +- drivers/net/r8169/r8169_hw.c | 710 +++++++++++++++++++++++++++++++ drivers/net/r8169/r8169_hw.h | 17 + drivers/net/r8169/r8169_phy.c | 41 ++ drivers/net/r8169/r8169_phy.h | 21 + 8 files changed, 930 insertions(+), 2 deletions(-) create mode 100644 drivers/net/r8169/r8169_phy.c create mode 100644 drivers/net/r8169/r8169_phy.h diff --git a/drivers/net/r8169/meson.build b/drivers/net/r8169/meson.build index ff7d6ca4b8..56f857ac8c 100644 --- a/drivers/net/r8169/meson.build +++ b/drivers/net/r8169/meson.build @@ -5,5 +5,6 @@ sources = files( 'r8169_ethdev.c', 'r8169_hw.c', 'r8169_rxtx.c', + 'r8169_phy.c', ) diff --git a/drivers/net/r8169/r8169_base.h b/drivers/net/r8169/r8169_base.h index 0e79d8d22a..2e72faeb2c 100644 --- a/drivers/net/r8169/r8169_base.h +++ b/drivers/net/r8169/r8169_base.h @@ -23,6 +23,117 @@ typedef uint16_t u16; typedef uint32_t u32; typedef uint64_t u64; +enum mcfg { + CFG_METHOD_1 = 1, + CFG_METHOD_2, + CFG_METHOD_3, + CFG_METHOD_4, + CFG_METHOD_5, + CFG_METHOD_6, + CFG_METHOD_7, + CFG_METHOD_8, + CFG_METHOD_9, + CFG_METHOD_10, + CFG_METHOD_11, + CFG_METHOD_12, + CFG_METHOD_13, + CFG_METHOD_14, + CFG_METHOD_15, + CFG_METHOD_16, + CFG_METHOD_17, + CFG_METHOD_18, + CFG_METHOD_19, + CFG_METHOD_20, + CFG_METHOD_21, + CFG_METHOD_22, + CFG_METHOD_23, + CFG_METHOD_24, + CFG_METHOD_25, + CFG_METHOD_26, + CFG_METHOD_27, + CFG_METHOD_28, + CFG_METHOD_29, + CFG_METHOD_30, + CFG_METHOD_31, + CFG_METHOD_32, + CFG_METHOD_33, + CFG_METHOD_34, + CFG_METHOD_35, + CFG_METHOD_36, + CFG_METHOD_37, + CFG_METHOD_38, + CFG_METHOD_39, + CFG_METHOD_40, + CFG_METHOD_41, + CFG_METHOD_42, + CFG_METHOD_43, + CFG_METHOD_44, + CFG_METHOD_45, + CFG_METHOD_46, + CFG_METHOD_47, + CFG_METHOD_48, + CFG_METHOD_49, + CFG_METHOD_50, + CFG_METHOD_51, + CFG_METHOD_52, + CFG_METHOD_53, + CFG_METHOD_54, + CFG_METHOD_55, + CFG_METHOD_56, + CFG_METHOD_57, + CFG_METHOD_58, + CFG_METHOD_59, + CFG_METHOD_60, + CFG_METHOD_61, + CFG_METHOD_62, + CFG_METHOD_63, + CFG_METHOD_64, + CFG_METHOD_65, + CFG_METHOD_66, + CFG_METHOD_67, + CFG_METHOD_68, + CFG_METHOD_69, + CFG_METHOD_70, + CFG_METHOD_71, + CFG_METHOD_MAX, + CFG_METHOD_DEFAULT = 0xFF +}; + +enum bits { + BIT_0 = (1UL << 0), + BIT_1 = (1UL << 1), + BIT_2 = (1UL << 2), + BIT_3 = (1UL << 3), + BIT_4 = (1UL << 4), + BIT_5 = (1UL << 5), + BIT_6 = (1UL << 6), + BIT_7 = (1UL << 7), + BIT_8 = (1UL << 8), + BIT_9 = (1UL << 9), + BIT_10 = (1UL << 10), + BIT_11 = (1UL << 11), + BIT_12 = (1UL << 12), + BIT_13 = (1UL << 13), + BIT_14 = (1UL << 14), + BIT_15 = (1UL << 15), + BIT_16 = (1UL << 16), + BIT_17 = (1UL << 17), + BIT_18 = (1UL << 18), + BIT_19 = (1UL << 19), + BIT_20 = (1UL << 20), + BIT_21 = (1UL << 21), + BIT_22 = (1UL << 22), + BIT_23 = (1UL << 23), + BIT_24 = (1UL << 24), + BIT_25 = (1UL << 25), + BIT_26 = (1UL << 26), + BIT_27 = (1UL << 27), + BIT_28 = (1UL << 28), + BIT_29 = (1UL << 29), + BIT_30 = (1UL << 30), + BIT_31 = (1UL << 31) +}; + enum RTL_registers { MAC0 = 0x00, /* Ethernet hardware address */ MAC4 = 0x04, @@ -363,6 +474,8 @@ enum RTL_register_content { INT_CFG0_ENABLE_8125 = (1 << 0), INT_CFG0_TIMEOUT0_BYPASS_8125 = (1 << 1), INT_CFG0_MITIGATION_BYPASS_8125 = (1 << 2), + INT_CFG0_RDU_BYPASS_8126 = (1 << 4), + INT_CFG0_MSIX_ENTRY_NUM_MODE = (1 << 5), ISRIMR_V2_ROK_Q0 = (1 << 0), ISRIMR_TOK_Q0 = (1 << 16), ISRIMR_TOK_Q1 = (1 << 18), @@ -389,6 +502,18 @@ enum RTL_register_content { #define msleep rte_delay_ms #define usleep rte_delay_us +#define RX_DMA_BURST_unlimited 7 /* Maximum PCI burst, '7' is unlimited */ +#define RX_DMA_BURST_512 5 +#define TX_DMA_BURST_unlimited 7 +#define TX_DMA_BURST_1024 6 +#define TX_DMA_BURST_512 5 +#define TX_DMA_BURST_256 4 +#define TX_DMA_BURST_128 3 +#define TX_DMA_BURST_64 2 +#define TX_DMA_BURST_32 1 +#define TX_DMA_BURST_16 0 +#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ + static inline u32 rtl_read32(volatile void *addr) { diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index 92121ad3fb..a23370c6a1 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -72,6 +72,8 @@ rtl_dev_start(struct rte_eth_dev *dev) struct rtl_hw *hw = &adapter->hw; int err; + rtl_hw_config(hw); + /* Initialize transmission unit */ rtl_tx_init(dev); diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index 7c6e110e7f..20dbf06c9b 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -14,8 +14,19 @@ #include "r8169_base.h" struct rtl_hw { - u8 adapter_stopped; - u8 *mmio_addr; + u8 adapter_stopped; + u8 *mmio_addr; + u32 mcfg; + u8 HwSuppIntMitiVer; + + /* Enable Tx No Close */ + u8 EnableTxNoClose; + + /* Dash */ + u8 HwSuppDashVer; + u8 DASH; + u8 HwSuppOcpChannelVer; + u8 AllowAccessDashOcp; }; struct rtl_sw_stats { diff --git a/drivers/net/r8169/r8169_hw.c b/drivers/net/r8169/r8169_hw.c index b3c0c23ecf..06d2ca27d9 100644 --- a/drivers/net/r8169/r8169_hw.c +++ b/drivers/net/r8169/r8169_hw.c @@ -14,6 +14,257 @@ #include "r8169_hw.h" #include "r8169_logs.h" +static u32 +rtl_eri_read_with_oob_base_address(struct rtl_hw *hw, int addr, int len, + int type, const u32 base_address) +{ + int i, val_shift, shift = 0; + u32 value1 = 0; + u32 value2 = 0; + u32 eri_cmd, tmp, mask; + const u32 transformed_base_address = ((base_address & 0x00FFF000) << 6) | + (base_address & 0x000FFF); + + if (len > 4 || len <= 0) + return -1; + + while (len > 0) { + val_shift = addr % ERIAR_Addr_Align; + addr = addr & ~0x3; + + eri_cmd = ERIAR_Read | transformed_base_address | + type << ERIAR_Type_shift | + ERIAR_ByteEn << ERIAR_ByteEn_shift | + (addr & 0x0FFF); + if (addr & 0xF000) { + tmp = addr & 0xF000; + tmp >>= 12; + eri_cmd |= (tmp << 20) & 0x00F00000; + } + + RTL_W32(hw, ERIAR, eri_cmd); + + for (i = 0; i < RTL_CHANNEL_WAIT_COUNT; i++) { + udelay(RTL_CHANNEL_WAIT_TIME); + + /* Check if the NIC has completed ERI read */ + if (RTL_R32(hw, ERIAR) & ERIAR_Flag) + break; + } + + if (len == 1) + mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF; + else if (len == 2) + mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF; + else if (len == 3) + mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; + else + mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; + + value1 = RTL_R32(hw, ERIDR) & mask; + value2 |= (value1 >> val_shift * 8) << shift * 8; + + if (len <= 4 - val_shift) + len = 0; + else { + len -= (4 - val_shift); + shift = 4 - val_shift; + addr += 4; + } + } + + udelay(RTL_CHANNEL_EXIT_DELAY_TIME); + + return value2; +} + +static int +rtl_eri_write_with_oob_base_address(struct rtl_hw *hw, int addr, + int len, u32 value, int type, const u32 base_address) +{ + int i, val_shift, shift = 0; + u32 value1 = 0; + u32 eri_cmd, mask, tmp; + const u32 transformed_base_address = ((base_address & 0x00FFF000) << 6) | + (base_address & 0x000FFF); + + if (len > 4 || len <= 0) + return -1; + + while (len > 0) { + val_shift = addr % ERIAR_Addr_Align; + addr = addr & ~0x3; + + if (len == 1) + mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF; + else if (len == 2) + mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF; + else if (len == 3) + mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; + else + mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; + + value1 = rtl_eri_read_with_oob_base_address(hw, addr, 4, type, + base_address) & ~mask; + value1 |= ((value << val_shift * 8) >> shift * 8); + + RTL_W32(hw, ERIDR, value1); + + eri_cmd = ERIAR_Write | transformed_base_address | + type << ERIAR_Type_shift | + ERIAR_ByteEn << ERIAR_ByteEn_shift | + (addr & 0x0FFF); + if (addr & 0xF000) { + tmp = addr & 0xF000; + tmp >>= 12; + eri_cmd |= (tmp << 20) & 0x00F00000; + } + + RTL_W32(hw, ERIAR, eri_cmd); + + for (i = 0; i < RTL_CHANNEL_WAIT_COUNT; i++) { + udelay(RTL_CHANNEL_WAIT_TIME); + + /* Check if the NIC has completed ERI write */ + if (!(RTL_R32(hw, ERIAR) & ERIAR_Flag)) + break; + } + + if (len <= 4 - val_shift) + len = 0; + else { + len -= (4 - val_shift); + shift = 4 - val_shift; + addr += 4; + } + } + + udelay(RTL_CHANNEL_EXIT_DELAY_TIME); + + return 0; +} + +static u32 +rtl_ocp_read_with_oob_base_address(struct rtl_hw *hw, u16 addr, u8 len, + const u32 base_address) +{ + return rtl_eri_read_with_oob_base_address(hw, addr, len, ERIAR_OOB, + base_address); +} + +u32 +rtl_ocp_read(struct rtl_hw *hw, u16 addr, u8 len) +{ + u32 value = 0; + + if (!hw->AllowAccessDashOcp) + return 0xffffffff; + + if (hw->HwSuppOcpChannelVer == 2) + value = rtl_ocp_read_with_oob_base_address(hw, addr, len, NO_BASE_ADDRESS); + + return value; +} + +static u32 +rtl_ocp_write_with_oob_base_address(struct rtl_hw *hw, u16 addr, u8 len, + u32 value, const u32 base_address) +{ + return rtl_eri_write_with_oob_base_address(hw, addr, len, value, ERIAR_OOB, + base_address); +} + +void +rtl_ocp_write(struct rtl_hw *hw, u16 addr, u8 len, u32 value) +{ + if (!hw->AllowAccessDashOcp) + return; + + if (hw->HwSuppOcpChannelVer == 2) + rtl_ocp_write_with_oob_base_address(hw, addr, len, value, NO_BASE_ADDRESS); +} + +void +rtl8125_oob_mutex_lock(struct rtl_hw *hw) +{ + u8 reg_16, reg_a0; + u16 ocp_reg_mutex_ib; + u16 ocp_reg_mutex_oob; + u16 ocp_reg_mutex_prio; + u32 wait_cnt_0, wait_cnt_1; + + if (!hw->DASH) + return; + + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + case CFG_METHOD_52: + case CFG_METHOD_54: + case CFG_METHOD_55: + ocp_reg_mutex_oob = 0x110; + ocp_reg_mutex_ib = 0x114; + ocp_reg_mutex_prio = 0x11C; + break; + default: + return; + } + + rtl_ocp_write(hw, ocp_reg_mutex_ib, 1, BIT_0); + reg_16 = rtl_ocp_read(hw, ocp_reg_mutex_oob, 1); + wait_cnt_0 = 0; + while (reg_16) { + reg_a0 = rtl_ocp_read(hw, ocp_reg_mutex_prio, 1); + if (reg_a0) { + rtl_ocp_write(hw, ocp_reg_mutex_ib, 1, 0x00); + reg_a0 = rtl_ocp_read(hw, ocp_reg_mutex_prio, 1); + wait_cnt_1 = 0; + while (reg_a0) { + reg_a0 = rtl_ocp_read(hw, ocp_reg_mutex_prio, 1); + + wait_cnt_1++; + + if (wait_cnt_1 > 2000) + break; + }; + rtl_ocp_write(hw, ocp_reg_mutex_ib, 1, BIT_0); + + } + reg_16 = rtl_ocp_read(hw, ocp_reg_mutex_oob, 1); + + wait_cnt_0++; + + if (wait_cnt_0 > 2000) + break; + }; +} + +void +rtl8125_oob_mutex_unlock(struct rtl_hw *hw) +{ + u16 ocp_reg_mutex_ib; + u16 ocp_reg_mutex_prio; + + if (!hw->DASH) + return; + + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + case CFG_METHOD_52: + case CFG_METHOD_54: + case CFG_METHOD_55: + ocp_reg_mutex_ib = 0x114; + ocp_reg_mutex_prio = 0x11C; + break; + default: + return; + } + + rtl_ocp_write(hw, ocp_reg_mutex_prio, 1, BIT_0); + rtl_ocp_write(hw, ocp_reg_mutex_ib, 1, 0x00); +} + void rtl_mac_ocp_write(struct rtl_hw *hw, u16 addr, u16 value) { @@ -92,3 +343,462 @@ rtl_csi_write(struct rtl_hw *hw, u32 addr, u32 value) udelay(RTL_CHANNEL_EXIT_DELAY_TIME); } +static void +rtl_enable_rxdvgate(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + RTL_W8(hw, 0xF2, RTL_R8(hw, 0xF2) | BIT_3); + mdelay(2); + } +} + +void +rtl_disable_rxdvgate(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_1 ... CFG_METHOD_3: + RTL_W8(hw, 0xF2, RTL_R8(hw, 0xF2) & ~BIT_3); + mdelay(2); + } +} + +static void +rtl_stop_all_request(struct rtl_hw *hw) +{ + int i; + + RTL_W8(hw, ChipCmd, RTL_R8(hw, ChipCmd) | StopReq); + + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + case CFG_METHOD_52: + for (i = 0; i < 20; i++) { + udelay(10); + if (!(RTL_R8(hw, ChipCmd) & StopReq)) + break; + } + + break; + default: + udelay(200); + break; + } + + RTL_W8(hw, ChipCmd, RTL_R8(hw, ChipCmd) & (CmdTxEnb | CmdRxEnb)); +} + +static void +rtl_wait_txrx_fifo_empty(struct rtl_hw *hw) +{ + int i; + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + for (i = 0; i < 3000; i++) { + udelay(50); + if ((RTL_R8(hw, MCUCmd_reg) & (Txfifo_empty | Rxfifo_empty)) == + (Txfifo_empty | Rxfifo_empty)) + break; + } + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_50: + case CFG_METHOD_51: + case CFG_METHOD_53 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + for (i = 0; i < 3000; i++) { + udelay(50); + if ((RTL_R16(hw, IntrMitigate) & (BIT_0 | BIT_1 | BIT_8)) == + (BIT_0 | BIT_1 | BIT_8)) + break; + } + break; + } +} + +static void +rtl_disable_rx_packet_filter(struct rtl_hw *hw) +{ + RTL_W32(hw, RxConfig, RTL_R32(hw, RxConfig) & + ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | + AcceptMyPhys | AcceptAllPhys)); +} + +void +rtl_nic_reset(struct rtl_hw *hw) +{ + int i; + + rtl_disable_rx_packet_filter(hw); + + rtl_enable_rxdvgate(hw); + + rtl_stop_all_request(hw); + + rtl_wait_txrx_fifo_empty(hw); + + mdelay(2); + + /* Soft reset the chip. */ + RTL_W8(hw, ChipCmd, CmdReset); + + /* Check that the chip has finished the reset. */ + for (i = 100; i > 0; i--) { + udelay(100); + if ((RTL_R8(hw, ChipCmd) & CmdReset) == 0) + break; + } +} + +void +rtl_enable_cfg9346_write(struct rtl_hw *hw) +{ + RTL_W8(hw, Cfg9346, RTL_R8(hw, Cfg9346) | Cfg9346_Unlock); +} + +void +rtl_disable_cfg9346_write(struct rtl_hw *hw) +{ + RTL_W8(hw, Cfg9346, RTL_R8(hw, Cfg9346) & ~Cfg9346_Unlock); +} + +static void +rtl_enable_force_clkreq(struct rtl_hw *hw, bool enable) +{ + if (enable) + RTL_W8(hw, 0xF1, RTL_R8(hw, 0xF1) | BIT_7); + else + RTL_W8(hw, 0xF1, RTL_R8(hw, 0xF1) & ~BIT_7); +} + +static void +rtl_enable_aspm_clkreq_lock(struct rtl_hw *hw, bool enable) +{ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69: + rtl_enable_cfg9346_write(hw); + if (enable) { + RTL_W8(hw, Config2, RTL_R8(hw, Config2) | BIT_7); + RTL_W8(hw, Config5, RTL_R8(hw, Config5) | BIT_0); + } else { + RTL_W8(hw, Config2, RTL_R8(hw, Config2) & ~BIT_7); + RTL_W8(hw, Config5, RTL_R8(hw, Config5) & ~BIT_0); + } + rtl_disable_cfg9346_write(hw); + break; + case CFG_METHOD_70: + case CFG_METHOD_71: + rtl_enable_cfg9346_write(hw); + if (enable) { + RTL_W8(hw, INT_CFG0_8125, RTL_R8(hw, INT_CFG0_8125) | BIT_3); + RTL_W8(hw, Config5, RTL_R8(hw, Config5) | BIT_0); + } else { + RTL_W8(hw, INT_CFG0_8125, RTL_R8(hw, INT_CFG0_8125) & ~BIT_3); + RTL_W8(hw, Config5, RTL_R8(hw, Config5) & ~BIT_0); + } + rtl_disable_cfg9346_write(hw); + break; + } +} + +static void +rtl_disable_l1_timeout(struct rtl_hw *hw) +{ + rtl_csi_write(hw, 0x890, rtl_csi_read(hw, 0x890) & ~BIT_0); +} + +static void +rtl_disable_eee_plus(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_mac_ocp_write(hw, 0xE080, rtl_mac_ocp_read(hw, 0xE080) & ~BIT_1); + break; + + default: + /* Not support EEEPlus */ + break; + } +} + +static void +rtl_hw_clear_timer_int(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + RTL_W32(hw, TIMER_INT0_8125, 0x0000); + RTL_W32(hw, TIMER_INT1_8125, 0x0000); + RTL_W32(hw, TIMER_INT2_8125, 0x0000); + RTL_W32(hw, TIMER_INT3_8125, 0x0000); + break; + } +} + +static void +rtl_hw_clear_int_miti(struct rtl_hw *hw) +{ + int i; + switch (hw->HwSuppIntMitiVer) { + case 3: + case 6: + /* IntMITI_0-IntMITI_31 */ + for (i = 0xA00; i < 0xB00; i += 4) + RTL_W32(hw, i, 0x0000); + break; + case 4: + case 5: + /* IntMITI_0-IntMITI_15 */ + for (i = 0xA00; i < 0xA80; i += 4) + RTL_W32(hw, i, 0x0000); + + if (hw->HwSuppIntMitiVer == 5) + RTL_W8(hw, INT_CFG0_8125, RTL_R8(hw, INT_CFG0_8125) & + ~(INT_CFG0_TIMEOUT0_BYPASS_8125 | + INT_CFG0_MITIGATION_BYPASS_8125 | + INT_CFG0_RDU_BYPASS_8126)); + else + RTL_W8(hw, INT_CFG0_8125, RTL_R8(hw, INT_CFG0_8125) & + ~(INT_CFG0_TIMEOUT0_BYPASS_8125 | INT_CFG0_MITIGATION_BYPASS_8125)); + + RTL_W16(hw, INT_CFG1_8125, 0x0000); + break; + } +} + +void +rtl_hw_config(struct rtl_hw *hw) +{ + u32 mac_ocp_data; + + /* Set RxConfig to default */ + RTL_W32(hw, RxConfig, (RX_DMA_BURST_unlimited << RxCfgDMAShift)); + + rtl_nic_reset(hw); + + rtl_enable_cfg9346_write(hw); + + /* Disable aspm clkreq internal */ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_enable_force_clkreq(hw, 0); + rtl_enable_aspm_clkreq_lock(hw, 0); + break; + } + + /* Disable magic packet */ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + mac_ocp_data = 0; + rtl_mac_ocp_write(hw, 0xC0B6, mac_ocp_data); + break; + } + + /* Set DMA burst size and interframe gap time */ + RTL_W32(hw, TxConfig, (TX_DMA_BURST_unlimited << TxDMAShift) | + (InterFrameGap << TxInterFrameGapShift)); + + if (hw->EnableTxNoClose) + RTL_W32(hw, TxConfig, (RTL_R32(hw, TxConfig) | BIT_6)); + + /* TCAM */ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_53: + RTL_W16(hw, 0x382, 0x221B); + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_disable_l1_timeout(hw); + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + + /* RSS_control_0 */ + RTL_W32(hw, RSS_CTRL_8125, 0x00); + + /* VMQ_control */ + RTL_W16(hw, Q_NUM_CTRL_8125, 0x0000); + + /* Disable speed down */ + RTL_W8(hw, Config1, RTL_R8(hw, Config1) & ~0x10); + + /* CRC disable set */ + rtl_mac_ocp_write(hw, 0xC140, 0xFFFF); + rtl_mac_ocp_write(hw, 0xC142, 0xFFFF); + + /* New TX desc format */ + mac_ocp_data = rtl_mac_ocp_read(hw, 0xEB58); + if (hw->mcfg == CFG_METHOD_70 || hw->mcfg == CFG_METHOD_71) + mac_ocp_data &= ~(BIT_0 | BIT_1); + mac_ocp_data |= BIT_0; + rtl_mac_ocp_write(hw, 0xEB58, mac_ocp_data); + + if (hw->mcfg == CFG_METHOD_70 || hw->mcfg == CFG_METHOD_71) + RTL_W8(hw, 0xD8, RTL_R8(hw, 0xD8) & ~BIT_1); + + /* + * MTPS + * 15-8 maximum tx use credit number + * 7-0 reserved for pcie product line + */ + mac_ocp_data = rtl_mac_ocp_read(hw, 0xE614); + mac_ocp_data &= ~(BIT_10 | BIT_9 | BIT_8); + if (hw->mcfg == CFG_METHOD_50 || hw->mcfg == CFG_METHOD_51 || + hw->mcfg == CFG_METHOD_53) + mac_ocp_data |= ((2 & 0x07) << 8); + else if (hw->mcfg == CFG_METHOD_69 || hw->mcfg == CFG_METHOD_70 || + hw->mcfg == CFG_METHOD_71) + mac_ocp_data |= ((4 & 0x07) << 8); + else + mac_ocp_data |= ((3 & 0x07) << 8); + rtl_mac_ocp_write(hw, 0xE614, mac_ocp_data); + + mac_ocp_data = rtl_mac_ocp_read(hw, 0xE63E); + mac_ocp_data &= ~(BIT_5 | BIT_4); + if (hw->mcfg == CFG_METHOD_48 || hw->mcfg == CFG_METHOD_49 || + hw->mcfg == CFG_METHOD_52 || hw->mcfg == CFG_METHOD_69 || + hw->mcfg == CFG_METHOD_70 || hw->mcfg == CFG_METHOD_71) + mac_ocp_data |= ((0x02 & 0x03) << 4); + rtl_mac_ocp_write(hw, 0xE63E, mac_ocp_data); + + /* + * FTR_MCU_CTRL + * 3-2 txpla packet valid start + */ + mac_ocp_data = rtl_mac_ocp_read(hw, 0xC0B4); + mac_ocp_data &= ~BIT_0; + rtl_mac_ocp_write(hw, 0xC0B4, mac_ocp_data); + mac_ocp_data |= BIT_0; + rtl_mac_ocp_write(hw, 0xC0B4, mac_ocp_data); + + mac_ocp_data = rtl_mac_ocp_read(hw, 0xC0B4); + mac_ocp_data |= (BIT_3 | BIT_2); + rtl_mac_ocp_write(hw, 0xC0B4, mac_ocp_data); + + mac_ocp_data = rtl_mac_ocp_read(hw, 0xEB6A); + mac_ocp_data &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | + BIT_0); + mac_ocp_data |= (BIT_5 | BIT_4 | BIT_1 | BIT_0); + rtl_mac_ocp_write(hw, 0xEB6A, mac_ocp_data); + + mac_ocp_data = rtl_mac_ocp_read(hw, 0xEB50); + mac_ocp_data &= ~(BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5); + mac_ocp_data |= BIT_6; + rtl_mac_ocp_write(hw, 0xEB50, mac_ocp_data); + + mac_ocp_data = rtl_mac_ocp_read(hw, 0xE056); + mac_ocp_data &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4); + rtl_mac_ocp_write(hw, 0xE056, mac_ocp_data); + + /* EEE_CR */ + mac_ocp_data = rtl_mac_ocp_read(hw, 0xE040); + mac_ocp_data &= ~BIT_12; + rtl_mac_ocp_write(hw, 0xE040, mac_ocp_data); + + mac_ocp_data = rtl_mac_ocp_read(hw, 0xEA1C); + mac_ocp_data &= ~(BIT_1 | BIT_0); + mac_ocp_data |= BIT_0; + rtl_mac_ocp_write(hw, 0xEA1C, mac_ocp_data); + + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + case CFG_METHOD_52: + case CFG_METHOD_54: + case CFG_METHOD_55: + rtl8125_oob_mutex_lock(hw); + break; + } + + /* MAC_PWRDWN_CR0 */ + rtl_mac_ocp_write(hw, 0xE0C0, 0x4000); + + rtl_set_mac_ocp_bit(hw, 0xE052, (BIT_6 | BIT_5)); + rtl_clear_mac_ocp_bit(hw, 0xE052, (BIT_3 | BIT_7)); + + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + case CFG_METHOD_52: + case CFG_METHOD_54: + case CFG_METHOD_55: + rtl8125_oob_mutex_unlock(hw); + break; + } + + /* + * DMY_PWR_REG_0 + * (1)ERI(0xD4)(OCP 0xC0AC).bit[7:12]=6'b111111, L1 Mask + */ + rtl_set_mac_ocp_bit(hw, 0xC0AC, + (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12)); + + mac_ocp_data = rtl_mac_ocp_read(hw, 0xD430); + mac_ocp_data &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | + BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); + mac_ocp_data |= 0x45F; + rtl_mac_ocp_write(hw, 0xD430, mac_ocp_data); + + if (!hw->DASH) + RTL_W8(hw, 0xD0, RTL_R8(hw, 0xD0) | BIT_6 | BIT_7); + else + RTL_W8(hw, 0xD0, RTL_R8(hw, 0xD0) & ~(BIT_6 | BIT_7)); + + if (hw->mcfg == CFG_METHOD_48 || hw->mcfg == CFG_METHOD_49 || + hw->mcfg == CFG_METHOD_52) + RTL_W8(hw, MCUCmd_reg, RTL_R8(hw, MCUCmd_reg) | BIT_0); + + rtl_disable_eee_plus(hw); + + mac_ocp_data = rtl_mac_ocp_read(hw, 0xEA1C); + mac_ocp_data &= ~BIT_2; + if (hw->mcfg == CFG_METHOD_70 || hw->mcfg == CFG_METHOD_71) + mac_ocp_data &= ~(BIT_9 | BIT_8); + rtl_mac_ocp_write(hw, 0xEA1C, mac_ocp_data); + + /* Clear TCAM entries */ + rtl_set_mac_ocp_bit(hw, 0xEB54, BIT_0); + udelay(1); + rtl_clear_mac_ocp_bit(hw, 0xEB54, BIT_0); + + RTL_W16(hw, 0x1880, RTL_R16(hw, 0x1880) & ~(BIT_4 | BIT_5)); + + switch (hw->mcfg) { + case CFG_METHOD_54 ... CFG_METHOD_57: + RTL_W8(hw, 0xd8, RTL_R8(hw, 0xd8) & ~EnableRxDescV4_0); + break; + } + } + + /* Other hw parameters */ + rtl_hw_clear_timer_int(hw); + + rtl_hw_clear_int_miti(hw); + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_mac_ocp_write(hw, 0xE098, 0xC302); + break; + } + + rtl_disable_cfg9346_write(hw); + + udelay(10); +} + diff --git a/drivers/net/r8169/r8169_hw.h b/drivers/net/r8169/r8169_hw.h index e62b99a068..4effe2c6c7 100644 --- a/drivers/net/r8169/r8169_hw.h +++ b/drivers/net/r8169/r8169_hw.h @@ -13,13 +13,30 @@ #include "r8169_base.h" #include "r8169_ethdev.h" +#include "r8169_phy.h" u16 rtl_mac_ocp_read(struct rtl_hw *hw, u16 addr); void rtl_mac_ocp_write(struct rtl_hw *hw, u16 addr, u16 value); +u32 rtl_ocp_read(struct rtl_hw *hw, u16 addr, u8 len); +void rtl_ocp_write(struct rtl_hw *hw, u16 addr, u8 len, u32 value); + u32 rtl_csi_read(struct rtl_hw *hw, u32 addr); void rtl_csi_write(struct rtl_hw *hw, u32 addr, u32 value); +void rtl_hw_config(struct rtl_hw *hw); +void rtl_nic_reset(struct rtl_hw *hw); + +void rtl_enable_cfg9346_write(struct rtl_hw *hw); +void rtl_disable_cfg9346_write(struct rtl_hw *hw); + +void rtl8125_oob_mutex_lock(struct rtl_hw *hw); +void rtl8125_oob_mutex_unlock(struct rtl_hw *hw); + +void rtl_disable_rxdvgate(struct rtl_hw *hw); + +#define NO_BASE_ADDRESS 0x00000000 + /* Channel wait count */ #define RTL_CHANNEL_WAIT_COUNT 20000 #define RTL_CHANNEL_WAIT_TIME 1 /* 1 us */ diff --git a/drivers/net/r8169/r8169_phy.c b/drivers/net/r8169/r8169_phy.c new file mode 100644 index 0000000000..f0a880eeca --- /dev/null +++ b/drivers/net/r8169/r8169_phy.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved */ + +#include +#include +#include +#include +#include + +#include +#include + +#include "r8169_ethdev.h" +#include "r8169_hw.h" +#include "r8169_phy.h" +#include "r8169_logs.h" + +static void +rtl_clear_set_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 clearmask, + u16 setmask) +{ + u16 phy_reg_value; + + phy_reg_value = rtl_mac_ocp_read(hw, addr); + phy_reg_value &= ~clearmask; + phy_reg_value |= setmask; + rtl_mac_ocp_write(hw, addr, phy_reg_value); +} + +void +rtl_clear_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask) +{ + rtl_clear_set_mac_ocp_bit(hw, addr, mask, 0); +} + +void +rtl_set_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask) +{ + rtl_clear_set_mac_ocp_bit(hw, addr, 0, mask); +} + diff --git a/drivers/net/r8169/r8169_phy.h b/drivers/net/r8169/r8169_phy.h new file mode 100644 index 0000000000..f31eb163d8 --- /dev/null +++ b/drivers/net/r8169/r8169_phy.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _R8169_PHY_H_ +#define _R8169_PHY_H_ + +#include +#include + +#include +#include + +#include "r8169_base.h" +#include "r8169_ethdev.h" + +void rtl_clear_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); +void rtl_set_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); + +#endif + From patchwork Tue Oct 15 03:09:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145936 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 021DD45B3C; Tue, 15 Oct 2024 05:10:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EB4C240674; Tue, 15 Oct 2024 05:10:31 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id 7D34540156 for ; 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Tue, 15 Oct 2024 11:10:28 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:10:28 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 06/18] net/r8169: add phy registers access routines Date: Tue, 15 Oct 2024 11:09:16 +0800 Message-ID: <20241015030928.70642-7-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_ethdev.h | 1 + drivers/net/r8169/r8169_phy.c | 219 +++++++++++++++++++++++++++++++ drivers/net/r8169/r8169_phy.h | 18 +++ 3 files changed, 238 insertions(+) diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index 20dbf06c9b..9656a26eb0 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -18,6 +18,7 @@ struct rtl_hw { u8 *mmio_addr; u32 mcfg; u8 HwSuppIntMitiVer; + u16 cur_page; /* Enable Tx No Close */ u8 EnableTxNoClose; diff --git a/drivers/net/r8169/r8169_phy.c b/drivers/net/r8169/r8169_phy.c index f0a880eeca..cfec426ee1 100644 --- a/drivers/net/r8169/r8169_phy.c +++ b/drivers/net/r8169/r8169_phy.c @@ -39,3 +39,222 @@ rtl_set_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask) rtl_clear_set_mac_ocp_bit(hw, addr, 0, mask); } +static u16 +rtl_map_phy_ocp_addr(u16 PageNum, u8 RegNum) +{ + u8 ocp_reg_num = 0; + u16 ocp_page_num = 0; + u16 ocp_phy_address = 0; + + if (PageNum == 0) { + ocp_page_num = OCP_STD_PHY_BASE_PAGE + (RegNum / 8); + ocp_reg_num = 0x10 + (RegNum % 8); + } else { + ocp_page_num = PageNum; + ocp_reg_num = RegNum; + } + + ocp_page_num <<= 4; + + if (ocp_reg_num < 16) + ocp_phy_address = 0; + else { + ocp_reg_num -= 16; + ocp_reg_num <<= 1; + + ocp_phy_address = ocp_page_num + ocp_reg_num; + } + + return ocp_phy_address; +} + +static u32 +rtl_mdio_real_read_phy_ocp(struct rtl_hw *hw, u32 RegAddr) +{ + u32 data32; + int i, value = 0; + + data32 = RegAddr / 2; + data32 <<= OCPR_Addr_Reg_shift; + + RTL_W32(hw, PHYOCP, data32); + for (i = 0; i < 100; i++) { + udelay(1); + + if (RTL_R32(hw, PHYOCP) & OCPR_Flag) + break; + } + value = RTL_R32(hw, PHYOCP) & OCPDR_Data_Mask; + + return value; +} + +u32 +rtl_mdio_direct_read_phy_ocp(struct rtl_hw *hw, u32 RegAddr) +{ + return rtl_mdio_real_read_phy_ocp(hw, RegAddr); +} + +static u32 +rtl_mdio_read_phy_ocp(struct rtl_hw *hw, u16 PageNum, u32 RegAddr) +{ + u16 ocp_addr; + + ocp_addr = rtl_map_phy_ocp_addr(PageNum, RegAddr); + + return rtl_mdio_direct_read_phy_ocp(hw, ocp_addr); +} + +static u32 +rtl_mdio_real_read(struct rtl_hw *hw, u32 RegAddr) +{ + return rtl_mdio_read_phy_ocp(hw, hw->cur_page, RegAddr); +} + +static void +rtl_mdio_real_write_phy_ocp(struct rtl_hw *hw, u32 RegAddr, u32 value) +{ + u32 data32; + int i; + + data32 = RegAddr / 2; + data32 <<= OCPR_Addr_Reg_shift; + data32 |= OCPR_Write | value; + + RTL_W32(hw, PHYOCP, data32); + for (i = 0; i < 100; i++) { + udelay(1); + + if (!(RTL_R32(hw, PHYOCP) & OCPR_Flag)) + break; + } +} + +void +rtl_mdio_direct_write_phy_ocp(struct rtl_hw *hw, u32 RegAddr, u32 value) +{ + rtl_mdio_real_write_phy_ocp(hw, RegAddr, value); +} + +static void +rtl_mdio_write_phy_ocp(struct rtl_hw *hw, u16 PageNum, u32 RegAddr, u32 value) +{ + u16 ocp_addr; + + ocp_addr = rtl_map_phy_ocp_addr(PageNum, RegAddr); + + rtl_mdio_direct_write_phy_ocp(hw, ocp_addr, value); +} + +static void +rtl_mdio_real_write(struct rtl_hw *hw, u32 RegAddr, u32 value) +{ + if (RegAddr == 0x1F) + hw->cur_page = value; + rtl_mdio_write_phy_ocp(hw, hw->cur_page, RegAddr, value); +} + +u32 +rtl_mdio_read(struct rtl_hw *hw, u32 RegAddr) +{ + return rtl_mdio_real_read(hw, RegAddr); +} + +void +rtl_mdio_write(struct rtl_hw *hw, u32 RegAddr, u32 value) +{ + rtl_mdio_real_write(hw, RegAddr, value); +} + +void +rtl_clear_and_set_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 clearmask, + u16 setmask) +{ + u16 phy_reg_value; + + phy_reg_value = rtl_mdio_direct_read_phy_ocp(hw, addr); + phy_reg_value &= ~clearmask; + phy_reg_value |= setmask; + rtl_mdio_direct_write_phy_ocp(hw, addr, phy_reg_value); +} + +void +rtl_clear_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask) +{ + rtl_clear_and_set_eth_phy_ocp_bit(hw, addr, mask, 0); +} + +void +rtl_set_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask) +{ + rtl_clear_and_set_eth_phy_ocp_bit(hw, addr, 0, mask); +} + +void +rtl_ephy_write(struct rtl_hw *hw, int addr, int value) +{ + int i; + + RTL_W32(hw, EPHYAR, EPHYAR_Write | + (addr & EPHYAR_Reg_Mask_v2) << EPHYAR_Reg_shift | + (value & EPHYAR_Data_Mask)); + + for (i = 0; i < 10; i++) { + udelay(100); + + /* Check if the NIC has completed EPHY write */ + if (!(RTL_R32(hw, EPHYAR) & EPHYAR_Flag)) + break; + } + + udelay(20); +} + +static u16 +rtl_ephy_read(struct rtl_hw *hw, int addr) +{ + int i; + u16 value = 0xffff; + + RTL_W32(hw, EPHYAR, EPHYAR_Read | (addr & EPHYAR_Reg_Mask_v2) << + EPHYAR_Reg_shift); + + for (i = 0; i < 10; i++) { + udelay(100); + + /* Check if the NIC has completed EPHY read */ + if (RTL_R32(hw, EPHYAR) & EPHYAR_Flag) { + value = (u16)(RTL_R32(hw, EPHYAR) & EPHYAR_Data_Mask); + break; + } + } + + udelay(20); + + return value; +} + +void +rtl_clear_and_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 clearmask, + u16 setmask) +{ + u16 ephy_value; + + ephy_value = rtl_ephy_read(hw, addr); + ephy_value &= ~clearmask; + ephy_value |= setmask; + rtl_ephy_write(hw, addr, ephy_value); +} + +void +rtl_clear_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask) +{ + rtl_clear_and_set_pcie_phy_bit(hw, addr, mask, 0); +} + +void +rtl_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask) +{ + rtl_clear_and_set_pcie_phy_bit(hw, addr, 0, mask); +} + diff --git a/drivers/net/r8169/r8169_phy.h b/drivers/net/r8169/r8169_phy.h index f31eb163d8..da5a6575d4 100644 --- a/drivers/net/r8169/r8169_phy.h +++ b/drivers/net/r8169/r8169_phy.h @@ -17,5 +17,23 @@ void rtl_clear_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); void rtl_set_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); +u32 rtl_mdio_direct_read_phy_ocp(struct rtl_hw *hw, u32 RegAddr); +void rtl_mdio_direct_write_phy_ocp(struct rtl_hw *hw, u32 RegAddr, u32 value); + +u32 rtl_mdio_read(struct rtl_hw *hw, u32 RegAddr); +void rtl_mdio_write(struct rtl_hw *hw, u32 RegAddr, u32 value); + +void rtl_clear_and_set_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, + u16 clearmask, u16 setmask); +void rtl_clear_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); +void rtl_set_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); + +void rtl_ephy_write(struct rtl_hw *hw, int addr, int value); + +void rtl_clear_and_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 clearmask, + u16 setmask); +void rtl_clear_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask); +void rtl_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask); + #endif From patchwork Tue Oct 15 03:09:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145937 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E18E45B3C; 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Tue, 15 Oct 2024 11:10:36 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXMBS03.realsil.com.cn (172.29.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:10:35 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:10:35 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 07/18] net/r8169: add support for hardware operations Date: Tue, 15 Oct 2024 11:09:17 +0800 Message-ID: <20241015030928.70642-8-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org rtl_hw_ops contains multiple function pointers, each pointing to a specific hardware operation function. Signed-off-by: Howard Wang --- drivers/net/r8169/base/rtl8125a.c | 413 ++++ drivers/net/r8169/base/rtl8125a_mcu.c | 1586 +++++++++++++ drivers/net/r8169/base/rtl8125a_mcu.h | 15 + drivers/net/r8169/base/rtl8125b.c | 391 ++++ drivers/net/r8169/base/rtl8125b_mcu.c | 1068 +++++++++ drivers/net/r8169/base/rtl8125b_mcu.h | 15 + drivers/net/r8169/base/rtl8125bp.c | 116 + drivers/net/r8169/base/rtl8125bp_mcu.c | 289 +++ drivers/net/r8169/base/rtl8125bp_mcu.h | 14 + drivers/net/r8169/base/rtl8125d.c | 245 ++ drivers/net/r8169/base/rtl8125d_mcu.c | 618 +++++ drivers/net/r8169/base/rtl8125d_mcu.h | 14 + drivers/net/r8169/base/rtl8126a.c | 534 +++++ drivers/net/r8169/base/rtl8126a_mcu.c | 2994 ++++++++++++++++++++++++ drivers/net/r8169/base/rtl8126a_mcu.h | 16 + drivers/net/r8169/meson.build | 10 + drivers/net/r8169/r8169_base.h | 8 + drivers/net/r8169/r8169_ethdev.c | 3 + drivers/net/r8169/r8169_ethdev.h | 20 + drivers/net/r8169/r8169_hw.c | 120 +- drivers/net/r8169/r8169_hw.h | 18 + drivers/net/r8169/r8169_phy.c | 72 + drivers/net/r8169/r8169_phy.h | 6 + 23 files changed, 8584 insertions(+), 1 deletion(-) create mode 100644 drivers/net/r8169/base/rtl8125a.c create mode 100644 drivers/net/r8169/base/rtl8125a_mcu.c create mode 100644 drivers/net/r8169/base/rtl8125a_mcu.h create mode 100644 drivers/net/r8169/base/rtl8125b.c create mode 100644 drivers/net/r8169/base/rtl8125b_mcu.c create mode 100644 drivers/net/r8169/base/rtl8125b_mcu.h create mode 100644 drivers/net/r8169/base/rtl8125bp.c create mode 100644 drivers/net/r8169/base/rtl8125bp_mcu.c create mode 100644 drivers/net/r8169/base/rtl8125bp_mcu.h create mode 100644 drivers/net/r8169/base/rtl8125d.c create mode 100644 drivers/net/r8169/base/rtl8125d_mcu.c create mode 100644 drivers/net/r8169/base/rtl8125d_mcu.h create mode 100644 drivers/net/r8169/base/rtl8126a.c create mode 100644 drivers/net/r8169/base/rtl8126a_mcu.c create mode 100644 drivers/net/r8169/base/rtl8126a_mcu.h diff --git a/drivers/net/r8169/base/rtl8125a.c b/drivers/net/r8169/base/rtl8125a.c new file mode 100644 index 0000000000..aad63059d9 --- /dev/null +++ b/drivers/net/r8169/base/rtl8125a.c @@ -0,0 +1,413 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include "../r8169_ethdev.h" +#include "../r8169_hw.h" +#include "../r8169_phy.h" +#include "rtl8125a_mcu.h" + +/* For RTL8125A, CFG_METHOD_48,49 */ + +static void +hw_init_rxcfg_8125a(struct rtl_hw *hw) +{ + RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | (RX_DMA_BURST_256 << RxCfgDMAShift)); +} + +static void +hw_ephy_config_8125a(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48: + rtl_ephy_write(hw, 0x01, 0xA812); + rtl_ephy_write(hw, 0x09, 0x520C); + rtl_ephy_write(hw, 0x04, 0xD000); + rtl_ephy_write(hw, 0x0D, 0xF702); + rtl_ephy_write(hw, 0x0A, 0x8653); + rtl_ephy_write(hw, 0x06, 0x001E); + rtl_ephy_write(hw, 0x08, 0x3595); + rtl_ephy_write(hw, 0x20, 0x9455); + rtl_ephy_write(hw, 0x21, 0x99FF); + rtl_ephy_write(hw, 0x02, 0x6046); + rtl_ephy_write(hw, 0x29, 0xFE00); + rtl_ephy_write(hw, 0x23, 0xAB62); + + rtl_ephy_write(hw, 0x41, 0xA80C); + rtl_ephy_write(hw, 0x49, 0x520C); + rtl_ephy_write(hw, 0x44, 0xD000); + rtl_ephy_write(hw, 0x4D, 0xF702); + rtl_ephy_write(hw, 0x4A, 0x8653); + rtl_ephy_write(hw, 0x46, 0x001E); + rtl_ephy_write(hw, 0x48, 0x3595); + rtl_ephy_write(hw, 0x60, 0x9455); + rtl_ephy_write(hw, 0x61, 0x99FF); + rtl_ephy_write(hw, 0x42, 0x6046); + rtl_ephy_write(hw, 0x69, 0xFE00); + rtl_ephy_write(hw, 0x63, 0xAB62); + break; + case CFG_METHOD_49: + rtl_ephy_write(hw, 0x04, 0xD000); + rtl_ephy_write(hw, 0x0A, 0x8653); + rtl_ephy_write(hw, 0x23, 0xAB66); + rtl_ephy_write(hw, 0x20, 0x9455); + rtl_ephy_write(hw, 0x21, 0x99FF); + rtl_ephy_write(hw, 0x29, 0xFE04); + + rtl_ephy_write(hw, 0x44, 0xD000); + rtl_ephy_write(hw, 0x4A, 0x8653); + rtl_ephy_write(hw, 0x63, 0xAB66); + rtl_ephy_write(hw, 0x60, 0x9455); + rtl_ephy_write(hw, 0x61, 0x99FF); + rtl_ephy_write(hw, 0x69, 0xFE04); + + rtl_clear_and_set_pcie_phy_bit(hw, 0x2A, (BIT_14 | BIT_13 | BIT_12), + (BIT_13 | BIT_12)); + rtl_clear_pcie_phy_bit(hw, 0x19, BIT_6); + rtl_set_pcie_phy_bit(hw, 0x1B, (BIT_11 | BIT_10 | BIT_9)); + rtl_clear_pcie_phy_bit(hw, 0x1B, (BIT_14 | BIT_13 | BIT_12)); + rtl_ephy_write(hw, 0x02, 0x6042); + rtl_ephy_write(hw, 0x06, 0x0014); + + rtl_clear_and_set_pcie_phy_bit(hw, 0x6A, (BIT_14 | BIT_13 | BIT_12), + (BIT_13 | BIT_12)); + rtl_clear_pcie_phy_bit(hw, 0x59, BIT_6); + rtl_set_pcie_phy_bit(hw, 0x5B, (BIT_11 | BIT_10 | BIT_9)); + rtl_clear_pcie_phy_bit(hw, 0x5B, (BIT_14 | BIT_13 | BIT_12)); + rtl_ephy_write(hw, 0x42, 0x6042); + rtl_ephy_write(hw, 0x46, 0x0014); + break; + } +} + +static void +rtl_hw_phy_config_8125a_1(struct rtl_hw *hw) +{ + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD40, 0x03FF, 0x84); + + rtl_set_eth_phy_ocp_bit(hw, 0xAD4E, BIT_4); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD16, 0x03FF, 0x0006); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD32, 0x003F, 0x0006); + rtl_clear_eth_phy_ocp_bit(hw, 0xAC08, BIT_12); + rtl_clear_eth_phy_ocp_bit(hw, 0xAC08, BIT_8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC8A, + (BIT_15 | BIT_14 | BIT_13 | BIT_12), + (BIT_14 | BIT_13 | BIT_12)); + rtl_set_eth_phy_ocp_bit(hw, 0xAD18, BIT_10); + rtl_set_eth_phy_ocp_bit(hw, 0xAD1A, 0x3FF); + rtl_set_eth_phy_ocp_bit(hw, 0xAD1C, 0x3FF); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80EA); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC400); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80EB); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x0700, 0x0300); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80F8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1C00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80F1); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x3000); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80FE); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xA500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8102); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8105); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x3300); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8100); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x7000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8104); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xF000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8106); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x6500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DC); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xED00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DF); + rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E1); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_8); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF06, 0x003F, 0x38); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x819F); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xD0B6); + + rtl_mdio_direct_write_phy_ocp(hw, 0xBC34, 0x5555); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF0A, (BIT_11 | BIT_10 | BIT_9), + (BIT_11 | BIT_9)); + + rtl_clear_eth_phy_ocp_bit(hw, 0xA5C0, BIT_10); + + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); +} + +static void +rtl_hw_phy_config_8125a_2(struct rtl_hw *hw) +{ + u16 adccal_offset_p0; + u16 adccal_offset_p1; + u16 adccal_offset_p2; + u16 adccal_offset_p3; + u16 rg_lpf_cap_xg_p0; + u16 rg_lpf_cap_xg_p1; + u16 rg_lpf_cap_xg_p2; + u16 rg_lpf_cap_xg_p3; + u16 rg_lpf_cap_p0; + u16 rg_lpf_cap_p1; + u16 rg_lpf_cap_p2; + u16 rg_lpf_cap_p3; + + rtl_set_eth_phy_ocp_bit(hw, 0xAD4E, BIT_4); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD16, 0x03FF, 0x03FF); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD32, 0x003F, 0x0006); + rtl_clear_eth_phy_ocp_bit(hw, 0xAC08, BIT_12); + rtl_clear_eth_phy_ocp_bit(hw, 0xAC08, BIT_8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xACC0, (BIT_1 | BIT_0), BIT_1); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD40, (BIT_7 | BIT_6 | BIT_5), + BIT_6); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD40, (BIT_2 | BIT_1 | BIT_0), + BIT_2); + rtl_clear_eth_phy_ocp_bit(hw, 0xAC14, BIT_7); + rtl_clear_eth_phy_ocp_bit(hw, 0xAC80, BIT_9 | BIT_8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC5E, (BIT_2 | BIT_1 | BIT_0), + BIT_1); + rtl_mdio_direct_write_phy_ocp(hw, 0xAD4C, 0x00A8); + rtl_mdio_direct_write_phy_ocp(hw, 0xAC5C, 0x01FF); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC8A, (BIT_7 | BIT_6 | BIT_5 | BIT_4), + (BIT_5 | BIT_4)); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8157); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8159); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80A2); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0153); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x809C); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0153); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81B3); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0043); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00A7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00D6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00EC); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00F6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FB); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FD); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FF); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00BB); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0058); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0029); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0013); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0009); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0004); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8257); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x020F); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80EA); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7843); + + rtl_set_phy_mcu_patch_request(hw); + + rtl_clear_eth_phy_ocp_bit(hw, 0xB896, BIT_0); + rtl_clear_eth_phy_ocp_bit(hw, 0xB892, 0xFF00); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC091); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x6E12); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC092); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1214); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC094); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1516); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC096); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x171B); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC098); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1B1C); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC09A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1F1F); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC09C); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x2021); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC09E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x2224); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC0A0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x2424); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC0A2); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x2424); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC0A4); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x2424); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC018); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0AF2); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC01A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0D4A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC01C); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0F26); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC01E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x118D); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC020); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x14F3); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC022); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x175A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC024); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x19C0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC026); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1C26); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC089); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x6050); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC08A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x5F6E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC08C); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x6E6E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC08E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x6E6E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC090); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x6E12); + + rtl_set_eth_phy_ocp_bit(hw, 0xB896, BIT_0); + + rtl_clear_phy_mcu_patch_request(hw); + + rtl_set_eth_phy_ocp_bit(hw, 0xD068, BIT_13); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81A2); + rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB54C, 0xFF00, 0xDB00); + + rtl_clear_eth_phy_ocp_bit(hw, 0xA454, BIT_0); + + rtl_set_eth_phy_ocp_bit(hw, 0xA5D4, BIT_5); + rtl_clear_eth_phy_ocp_bit(hw, 0xAD4E, BIT_4); + rtl_clear_eth_phy_ocp_bit(hw, 0xA86A, BIT_0); + + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); + + if (hw->RequirePhyMdiSwapPatch) { + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0007, 0x0001); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0000); + adccal_offset_p0 = rtl_mdio_direct_read_phy_ocp(hw, 0xD06A); + adccal_offset_p0 &= 0x07FF; + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0008); + adccal_offset_p1 = rtl_mdio_direct_read_phy_ocp(hw, 0xD06A); + adccal_offset_p1 &= 0x07FF; + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0010); + adccal_offset_p2 = rtl_mdio_direct_read_phy_ocp(hw, 0xD06A); + adccal_offset_p2 &= 0x07FF; + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0018); + adccal_offset_p3 = rtl_mdio_direct_read_phy_ocp(hw, 0xD06A); + adccal_offset_p3 &= 0x07FF; + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0000); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD06A, 0x07FF, adccal_offset_p3); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0008); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD06A, 0x07FF, adccal_offset_p2); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0010); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD06A, 0x07FF, adccal_offset_p1); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0018); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD06A, 0x07FF, adccal_offset_p0); + + rg_lpf_cap_xg_p0 = rtl_mdio_direct_read_phy_ocp(hw, 0xBD5A); + rg_lpf_cap_xg_p0 &= 0x001F; + rg_lpf_cap_xg_p1 = rtl_mdio_direct_read_phy_ocp(hw, 0xBD5A); + rg_lpf_cap_xg_p1 &= 0x1F00; + rg_lpf_cap_xg_p2 = rtl_mdio_direct_read_phy_ocp(hw, 0xBD5C); + rg_lpf_cap_xg_p2 &= 0x001F; + rg_lpf_cap_xg_p3 = rtl_mdio_direct_read_phy_ocp(hw, 0xBD5C); + rg_lpf_cap_xg_p3 &= 0x1F00; + rg_lpf_cap_p0 = rtl_mdio_direct_read_phy_ocp(hw, 0xBC18); + rg_lpf_cap_p0 &= 0x001F; + rg_lpf_cap_p1 = rtl_mdio_direct_read_phy_ocp(hw, 0xBC18); + rg_lpf_cap_p1 &= 0x1F00; + rg_lpf_cap_p2 = rtl_mdio_direct_read_phy_ocp(hw, 0xBC1A); + rg_lpf_cap_p2 &= 0x001F; + rg_lpf_cap_p3 = rtl_mdio_direct_read_phy_ocp(hw, 0xBC1A); + rg_lpf_cap_p3 &= 0x1F00; + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD5A, 0x001F, + rg_lpf_cap_xg_p3 >> 8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD5A, 0x1F00, + rg_lpf_cap_xg_p2 << 8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD5C, 0x001F, + rg_lpf_cap_xg_p1 >> 8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD5C, 0x1F00, + rg_lpf_cap_xg_p0 << 8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC18, 0x001F, rg_lpf_cap_p3 >> 8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC18, 0x1F00, rg_lpf_cap_p2 << 8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC1A, 0x001F, rg_lpf_cap_p1 >> 8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC1A, 0x1F00, rg_lpf_cap_p0 << 8); + } + + rtl_set_eth_phy_ocp_bit(hw, 0xA424, BIT_3); +} + +static void +hw_phy_config_8125a(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48: + rtl_hw_phy_config_8125a_1(hw); + break; + case CFG_METHOD_49: + rtl_hw_phy_config_8125a_2(hw); + break; + } +} + +static void +hw_mac_mcu_config_8125a(struct rtl_hw *hw) +{ + if (hw->NotWrMcuPatchCode == TRUE) + return; + + switch (hw->mcfg) { + case CFG_METHOD_48: + rtl_set_mac_mcu_8125a_1(hw); + break; + case CFG_METHOD_49: + rtl_set_mac_mcu_8125a_2(hw); + break; + } +} + +static void +hw_phy_mcu_config_8125a(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48: + rtl_set_phy_mcu_8125a_1(hw); + break; + case CFG_METHOD_49: + rtl_set_phy_mcu_8125a_2(hw); + break; + } +} + +const struct rtl_hw_ops rtl8125a_ops = { + .hw_init_rxcfg = hw_init_rxcfg_8125a, + .hw_ephy_config = hw_ephy_config_8125a, + .hw_phy_config = hw_phy_config_8125a, + .hw_mac_mcu_config = hw_mac_mcu_config_8125a, + .hw_phy_mcu_config = hw_phy_mcu_config_8125a, +}; + diff --git a/drivers/net/r8169/base/rtl8125a_mcu.c b/drivers/net/r8169/base/rtl8125a_mcu.c new file mode 100644 index 0000000000..0316a3d5ef --- /dev/null +++ b/drivers/net/r8169/base/rtl8125a_mcu.c @@ -0,0 +1,1586 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include "../r8169_ethdev.h" +#include "../r8169_hw.h" +#include "../r8169_phy.h" +#include "rtl8125a_mcu.h" + +/* For RTL8125A, CFG_METHOD_48,49 */ + +/* ------------------------------------MAC 8125A------------------------------------- */ + +void +rtl_set_mac_mcu_8125a_1(struct rtl_hw *hw) +{ + rtl_hw_disable_mac_mcu_bps(hw); +} + +void +rtl_set_mac_mcu_8125a_2(struct rtl_hw *hw) +{ + static const u16 mcu_patch_code_8125a_2[] = { + 0xE010, 0xE012, 0xE022, 0xE024, 0xE029, 0xE02B, 0xE094, 0xE09D, 0xE09F, + 0xE0AA, 0xE0B5, 0xE0C6, 0xE0CC, 0xE0D1, 0xE0D6, 0xE0D8, 0xC602, 0xBE00, + 0x0000, 0xC60F, 0x73C4, 0x49B3, 0xF106, 0x73C2, 0xC608, 0xB406, 0xC609, + 0xFF80, 0xC605, 0xB406, 0xC605, 0xFF80, 0x0544, 0x0568, 0xE906, 0xCDE8, + 0xC602, 0xBE00, 0x0000, 0x48C1, 0x48C2, 0x9C46, 0xC402, 0xBC00, 0x0A12, + 0xC602, 0xBE00, 0x0EBA, 0x1501, 0xF02A, 0x1500, 0xF15D, 0xC661, 0x75C8, + 0x49D5, 0xF00A, 0x49D6, 0xF008, 0x49D7, 0xF006, 0x49D8, 0xF004, 0x75D2, + 0x49D9, 0xF150, 0xC553, 0x77A0, 0x75C8, 0x4855, 0x4856, 0x4857, 0x4858, + 0x48DA, 0x48DB, 0x49FE, 0xF002, 0x485A, 0x49FF, 0xF002, 0x485B, 0x9DC8, + 0x75D2, 0x4859, 0x9DD2, 0xC643, 0x75C0, 0x49D4, 0xF033, 0x49D0, 0xF137, + 0xE030, 0xC63A, 0x75C8, 0x49D5, 0xF00E, 0x49D6, 0xF00C, 0x49D7, 0xF00A, + 0x49D8, 0xF008, 0x75D2, 0x49D9, 0xF005, 0xC62E, 0x75C0, 0x49D7, 0xF125, + 0xC528, 0x77A0, 0xC627, 0x75C8, 0x4855, 0x4856, 0x4857, 0x4858, 0x48DA, + 0x48DB, 0x49FE, 0xF002, 0x485A, 0x49FF, 0xF002, 0x485B, 0x9DC8, 0x75D2, + 0x4859, 0x9DD2, 0xC616, 0x75C0, 0x4857, 0x9DC0, 0xC613, 0x75C0, 0x49DA, + 0xF003, 0x49D0, 0xF107, 0xC60B, 0xC50E, 0x48D9, 0x9DC0, 0x4859, 0x9DC0, + 0xC608, 0xC702, 0xBF00, 0x3AE0, 0xE860, 0xB400, 0xB5D4, 0xE908, 0xE86C, + 0x1200, 0xC409, 0x6780, 0x48F1, 0x8F80, 0xC404, 0xC602, 0xBE00, 0x10AA, + 0xC010, 0xEA7C, 0xC602, 0xBE00, 0x0000, 0x740A, 0x4846, 0x4847, 0x9C0A, + 0xC607, 0x74C0, 0x48C6, 0x9CC0, 0xC602, 0xBE00, 0x13FE, 0xE054, 0x72CA, + 0x4826, 0x4827, 0x9ACA, 0xC607, 0x72C0, 0x48A6, 0x9AC0, 0xC602, 0xBE00, + 0x07DC, 0xE054, 0xC60F, 0x74C4, 0x49CC, 0xF109, 0xC60C, 0x74CA, 0x48C7, + 0x9CCA, 0xC609, 0x74C0, 0x4846, 0x9CC0, 0xC602, 0xBE00, 0x2480, 0xE092, + 0xE0C0, 0xE054, 0x7420, 0x48C0, 0x9C20, 0x7444, 0xC602, 0xBE00, 0x12F8, + 0x1BFF, 0x46EB, 0x1BFF, 0xC102, 0xB900, 0x0D5A, 0x1BFF, 0x46EB, 0x1BFF, + 0xC102, 0xB900, 0x0E2A, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6486, + 0x0B15, 0x090E, 0x1139 + }; + + rtl_hw_disable_mac_mcu_bps(hw); + + rtl_write_mac_mcu_ram_code(hw, mcu_patch_code_8125a_2, + ARRAY_SIZE(mcu_patch_code_8125a_2)); + + rtl_mac_ocp_write(hw, 0xFC26, 0x8000); + + rtl_mac_ocp_write(hw, 0xFC2A, 0x0540); + rtl_mac_ocp_write(hw, 0xFC2E, 0x0A06); + rtl_mac_ocp_write(hw, 0xFC30, 0x0EB8); + rtl_mac_ocp_write(hw, 0xFC32, 0x3A5C); + rtl_mac_ocp_write(hw, 0xFC34, 0x10A8); + rtl_mac_ocp_write(hw, 0xFC40, 0x0D54); + rtl_mac_ocp_write(hw, 0xFC42, 0x0E24); + + rtl_mac_ocp_write(hw, 0xFC48, 0x307A); +} + +/* ------------------------------------PHY 8125A--------------------------------------- */ + +static void +rtl_acquire_phy_mcu_patch_key_lock(struct rtl_hw *hw) +{ + u16 patch_key; + + switch (hw->mcfg) { + case CFG_METHOD_48: + patch_key = 0x8600; + break; + case CFG_METHOD_49: + case CFG_METHOD_52: + patch_key = 0x8601; + break; + case CFG_METHOD_50: + patch_key = 0x3700; + break; + case CFG_METHOD_51: + case CFG_METHOD_53: + patch_key = 0x3701; + break; + default: + return; + } + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8024); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, patch_key); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xB82E); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0001); +} + +static void +rtl_release_phy_mcu_patch_key_lock(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_53: + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_clear_eth_phy_ocp_bit(hw, 0xB82E, BIT_0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8024); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + break; + default: + break; + } +} + +static void +rtl_real_set_phy_mcu_8125a_1(struct rtl_hw *hw) +{ + rtl_acquire_phy_mcu_patch_key_lock(hw); + + rtl_set_eth_phy_ocp_bit(hw, 0xB820, BIT_7); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA016); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA012); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA014); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8013); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8021); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x802f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x803d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8042); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8051); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8051); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa088); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a50); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8008); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd014); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd1a3); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x401a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd707); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x40c2); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60a6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5f8b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a86); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a6c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8080); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd019); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd1a2); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x401a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd707); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x40c4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60a6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5f8b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a86); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a84); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd503); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8970); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c07); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0901); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xcf09); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd705); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xceff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaf0a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1213); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8401); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8580); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1253); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd064); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd181); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4018); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xc50f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd706); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2c59); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x804d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xc60f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xc605); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xae02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x10fd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA026); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA024); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA022); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x10f4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA020); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1252); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA006); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1206); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA004); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a78); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a60); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a4f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA008); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3f00); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA016); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA012); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA014); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8066); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x807c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8089); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x808e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x80a0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x80b2); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x80c2); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x62db); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x655c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd73e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60e9); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x614a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x61ab); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0503); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0505); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0509); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x653c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd73e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60e9); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x614a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x61ab); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0503); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0502); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0506); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x050a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd73e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60e9); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x614a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x61ab); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0505); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0506); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x050c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd73e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60e9); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x614a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x61ab); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0509); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x050a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x050c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0508); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0304); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd73e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60e9); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x614a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x61ab); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0321); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0502); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0321); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0321); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0508); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0321); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0346); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8208); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x609d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa50f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x001a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0503); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x001a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x607d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ab); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ab); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60fd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa50f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaa0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x017b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0503); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a05); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x017b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60fd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa50f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaa0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x01e0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0503); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a05); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x01e0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60fd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa50f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaa0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0231); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0503); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a05); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0231); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA08E); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA08C); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0221); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA08A); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x01ce); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA088); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0169); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA086); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00a6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA084); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x000d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA082); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0308); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA080); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x029f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA090); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x007f); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA016); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0020); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA012); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA014); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8017); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x801b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8029); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8054); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x805a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8064); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x80a7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x9430); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x9480); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb408); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd120); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd057); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x064b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xcb80); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x9906); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0567); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xcb94); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8190); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x82a0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x800a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8406); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8dff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07e4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa840); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0773); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xcb91); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4063); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd139); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd140); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd040); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07dc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa610); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa110); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa2a0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4045); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa180); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x405d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa720); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0742); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07ec); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5f74); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0742); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd702); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7fb6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8190); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x82a0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8610); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07dc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x064b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07c0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5fa7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0481); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x94bc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x870c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa190); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa00a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa280); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8220); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x078e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xcb92); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa840); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4063); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd140); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd150); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd040); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd703); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60a0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6121); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x61a2); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6223); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf02f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d10); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf00f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d20); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf00a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d30); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf005); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d40); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07e4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa610); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa008); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4046); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x405d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa720); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0742); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07f7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5f74); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0742); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd702); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7fb5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x800a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07e4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3ad4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0537); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8610); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8840); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x064b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8301); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x800a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8190); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x82a0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa70c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x9402); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x890c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8840); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x064b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA10E); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0642); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA10C); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0686); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA10A); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0788); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA108); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x047b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA106); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x065c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA104); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0769); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA102); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0565); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA100); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x06f9); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA110); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ff); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb87c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8530); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb87e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaf85); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3caf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8593); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaf85); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x9caf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x85a5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf86); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd702); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5afb); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xe083); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfb0c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x020d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x021b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x10bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86d7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86da); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfbe0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x83fc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1b10); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf86); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xda02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf86); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xdd02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5afb); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xe083); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfd0c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x020d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x021b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x10bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86dd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86e0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfbe0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x83fe); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1b10); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf86); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xe002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaf2f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbd02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2cac); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0286); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x65af); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x212b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x022c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86b6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaf21); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cd1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x03bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8710); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x870d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8719); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8716); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x871f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x871c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8728); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8725); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8707); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfbad); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x281c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd100); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1302); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2202); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2b02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xae1a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd101); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1302); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2202); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2b02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd101); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3402); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3102); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3d02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3a02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4302); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4c02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4902); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd100); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2e02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3702); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4602); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf87); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4f02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ab7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaf35); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7ff8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfaef); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x69bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86e3); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfbbf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86fb); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86e6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfbbf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86fe); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86e9); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfbbf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86ec); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfbbf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x025a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7bf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86ef); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0262); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7cbf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86f2); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0262); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7cbf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86f5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0262); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7cbf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86f8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0262); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7cef); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x96fe); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfc04); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf8fa); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xef69); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf86); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xef02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6273); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf86); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf202); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6273); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf86); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf502); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6273); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbf86); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf802); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6273); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xef96); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfefc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0420); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb540); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x53b5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4086); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb540); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb9b5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x40c8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb03a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xc8b0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbac8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb13a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xc8b1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xba77); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbd26); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffbd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2677); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbd28); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffbd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2840); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbd26); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xc8bd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2640); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbd28); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xc8bd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x28bb); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa430); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x98b0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1eba); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb01e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xdcb0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1e98); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb09e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbab0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x9edc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb09e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x98b1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1eba); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb11e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xdcb1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1e98); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb19e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbab1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x9edc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb19e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x11b0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1e22); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb01e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x33b0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1e11); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb09e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x22b0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x9e33); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb09e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x11b1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1e22); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb11e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x33b1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1e11); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb19e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x22b1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x9e33); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb19e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb85e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2f71); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb860); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x20d9); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb862); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2109); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb864); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x34e7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb878); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x000f); + + rtl_clear_eth_phy_ocp_bit(hw, 0xB820, BIT_7); + + rtl_release_phy_mcu_patch_key_lock(hw); +} + +static void +rtl_real_set_phy_mcu_8125a_2(struct rtl_hw *hw) +{ + rtl_acquire_phy_mcu_patch_key_lock(hw); + + rtl_set_eth_phy_ocp_bit(hw, 0xB820, BIT_7); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA016); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA012); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA014); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x808b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x808f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8093); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8097); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x809d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x80a1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x80aa); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd718); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x607b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x40da); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf00e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x42da); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf01e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd718); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x615b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1456); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x14a4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x14bc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd718); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5f2e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf01c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1456); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x14a4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x14bc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd718); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5f2e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf024); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1456); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x14a4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x14bc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd718); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5f2e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf02c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1456); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x14a4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x14bc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd718); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5f2e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf034); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd719); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4118); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xac11); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa410); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4779); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xac0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xae01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1444); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf034); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd719); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4118); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xac22); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa420); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4559); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xac0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xae01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1444); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf023); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd719); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4118); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xac44); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa440); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4339); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xac0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xae01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1444); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf012); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd719); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4118); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xac88); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa480); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xce00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4119); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xac0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xae01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1444); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf001); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1456); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd718); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5fac); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xc48f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x141b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd504); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x121a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd0b4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd1bb); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0898); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd0b4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd1bb); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a0e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd064); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd18a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0b7e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x401c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd501); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa804); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8804); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x053b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa301); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0648); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xc520); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa201); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x252d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1646); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd708); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4006); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1646); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0308); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA026); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0307); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA024); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1645); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA022); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0647); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA020); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x053a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA006); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0b7c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA004); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0a0c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0896); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x11a1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA008); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xff00); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA016); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA012); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA014); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8015); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x801a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x801a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x801a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x801a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x801a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x801a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xad02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x02d7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ed); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0509); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xc100); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x008f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA08E); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA08C); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA08A); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA088); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA086); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA084); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA082); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x008d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA080); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00eb); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA090); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0103); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA016); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0020); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA012); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA014); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8014); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8018); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8024); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8051); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8055); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8072); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x80dc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfffd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfffd); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8301); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x800a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8190); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x82a0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa70c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x9402); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x890c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8840); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa380); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x066e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xcb91); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4063); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd139); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd140); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd040); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07e0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa610); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa110); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa2a0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4085); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa180); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8280); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x405d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa720); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0743); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07f0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5f74); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0743); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd702); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7fb6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8190); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x82a0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8610); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0c0f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07e0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x066e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd158); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd04d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x03d4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x94bc); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x870c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8380); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd10d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd040); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07c4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5fb4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa190); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa00a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa280); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa404); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa220); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd130); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd040); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07c4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5fb4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xbb80); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd1c4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd074); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa301); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x604b); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa90c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0556); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xcb92); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4063); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd116); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd119); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd040); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd703); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x60a0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6241); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x63e2); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6583); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf054); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x611e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x40da); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d10); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf02f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d50); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf02a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x611e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x40da); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d20); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf021); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d60); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf01c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x611e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x40da); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d30); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf013); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d70); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf00e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x611e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x40da); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d40); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf005); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d80); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07e8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa610); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x405d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa720); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5ff4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa008); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd704); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4046); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0743); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07fb); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd703); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7f6f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7f4e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7f2d); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7f0c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x800a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0cf0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0d00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07e8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8010); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa740); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0743); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd702); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7fb5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd701); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3ad4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0556); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8610); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x066e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd1f5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xd049); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x01ec); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA10E); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x01ea); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA10C); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x06a9); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA10A); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x078a); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA108); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x03d2); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA106); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x067f); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA104); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0665); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA102); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA100); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xA110); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00fc); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb87c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8530); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb87e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaf85); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3caf); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8545); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaf85); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x45af); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8545); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xee82); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf900); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0103); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xaf03); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb7f8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xe0a6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00e1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa601); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xef01); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x58f0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa080); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x37a1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8402); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xae16); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa185); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x02ae); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x11a1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8702); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xae0c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xa188); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x02ae); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x07a1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8902); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xae02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xae1c); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xe0b4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x62e1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb463); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6901); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xe4b4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x62e5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb463); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xe0b4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x62e1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb463); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6901); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xe4b4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x62e5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xb463); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xfc04); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb85e); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x03b3); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb860); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb862); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb864); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xffff); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0xb878); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0001); + + rtl_clear_eth_phy_ocp_bit(hw, 0xB820, BIT_7); + + rtl_release_phy_mcu_patch_key_lock(hw); +} + +void +rtl_set_phy_mcu_8125a_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8125a_1(hw); + + rtl_clear_phy_mcu_patch_request(hw); +} + +void +rtl_set_phy_mcu_8125a_2(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8125a_2(hw); + + rtl_clear_phy_mcu_patch_request(hw); +} + diff --git a/drivers/net/r8169/base/rtl8125a_mcu.h b/drivers/net/r8169/base/rtl8125a_mcu.h new file mode 100644 index 0000000000..a820583489 --- /dev/null +++ b/drivers/net/r8169/base/rtl8125a_mcu.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _RTL8125A_MCU_H_ +#define _RTL8125A_MCU_H_ + +void rtl_set_mac_mcu_8125a_1(struct rtl_hw *hw); +void rtl_set_mac_mcu_8125a_2(struct rtl_hw *hw); + +void rtl_set_phy_mcu_8125a_1(struct rtl_hw *hw); +void rtl_set_phy_mcu_8125a_2(struct rtl_hw *hw); + +#endif + diff --git a/drivers/net/r8169/base/rtl8125b.c b/drivers/net/r8169/base/rtl8125b.c new file mode 100644 index 0000000000..c049cc3939 --- /dev/null +++ b/drivers/net/r8169/base/rtl8125b.c @@ -0,0 +1,391 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include "../r8169_ethdev.h" +#include "../r8169_hw.h" +#include "../r8169_phy.h" +#include "rtl8125b_mcu.h" + +/* For RTL8125B, CFG_METHOD_50,51 */ + +static void +hw_init_rxcfg_8125b(struct rtl_hw *hw) +{ + RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | RxCfg_pause_slot_en | + (RX_DMA_BURST_256 << RxCfgDMAShift)); +} + +static void +hw_ephy_config_8125b(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_50: + rtl_ephy_write(hw, 0x06, 0x001F); + rtl_ephy_write(hw, 0x0A, 0xB66B); + rtl_ephy_write(hw, 0x01, 0xA852); + rtl_ephy_write(hw, 0x24, 0x0008); + rtl_ephy_write(hw, 0x2F, 0x6052); + rtl_ephy_write(hw, 0x0D, 0xF716); + rtl_ephy_write(hw, 0x20, 0xD477); + rtl_ephy_write(hw, 0x21, 0x4477); + rtl_ephy_write(hw, 0x22, 0x0013); + rtl_ephy_write(hw, 0x23, 0xBB66); + rtl_ephy_write(hw, 0x0B, 0xA909); + rtl_ephy_write(hw, 0x29, 0xFF04); + rtl_ephy_write(hw, 0x1B, 0x1EA0); + + rtl_ephy_write(hw, 0x46, 0x001F); + rtl_ephy_write(hw, 0x4A, 0xB66B); + rtl_ephy_write(hw, 0x41, 0xA84A); + rtl_ephy_write(hw, 0x64, 0x000C); + rtl_ephy_write(hw, 0x6F, 0x604A); + rtl_ephy_write(hw, 0x4D, 0xF716); + rtl_ephy_write(hw, 0x60, 0xD477); + rtl_ephy_write(hw, 0x61, 0x4477); + rtl_ephy_write(hw, 0x62, 0x0013); + rtl_ephy_write(hw, 0x63, 0xBB66); + rtl_ephy_write(hw, 0x4B, 0xA909); + rtl_ephy_write(hw, 0x69, 0xFF04); + rtl_ephy_write(hw, 0x5B, 0x1EA0); + break; + case CFG_METHOD_51: + rtl_ephy_write(hw, 0x0B, 0xA908); + rtl_ephy_write(hw, 0x1E, 0x20EB); + rtl_ephy_write(hw, 0x22, 0x0023); + rtl_ephy_write(hw, 0x02, 0x60C2); + rtl_ephy_write(hw, 0x29, 0xFF00); + + rtl_ephy_write(hw, 0x4B, 0xA908); + rtl_ephy_write(hw, 0x5E, 0x28EB); + rtl_ephy_write(hw, 0x62, 0x0023); + rtl_ephy_write(hw, 0x42, 0x60C2); + rtl_ephy_write(hw, 0x69, 0xFF00); + break; + } +} + +static void +rtl_hw_phy_config_8125b_1(struct rtl_hw *hw) +{ + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); + + rtl_set_eth_phy_ocp_bit(hw, 0xBC08, (BIT_3 | BIT_2)); + + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) { + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FFF); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0400); + } + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8560); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x19CC); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8562); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x19CC); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8564); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x19CC); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8566); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x147D); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8568); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x147D); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x856A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x147D); + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) { + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFE); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0907); + } + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xACDA, 0xFF00, 0xFF00); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xACDE, 0xF000, 0xF000); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80D6); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x2801); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80F2); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x2801); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80F4); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6077); + rtl_mdio_direct_write_phy_ocp(hw, 0xB506, 0x01E7); + rtl_mdio_direct_write_phy_ocp(hw, 0xAC8C, 0x0FFC); + rtl_mdio_direct_write_phy_ocp(hw, 0xAC46, 0xB7B4); + rtl_mdio_direct_write_phy_ocp(hw, 0xAC50, 0x0FBC); + rtl_mdio_direct_write_phy_ocp(hw, 0xAC3C, 0x9240); + rtl_mdio_direct_write_phy_ocp(hw, 0xAC4E, 0x0DB4); + rtl_mdio_direct_write_phy_ocp(hw, 0xACC6, 0x0707); + rtl_mdio_direct_write_phy_ocp(hw, 0xACC8, 0xA0D3); + rtl_mdio_direct_write_phy_ocp(hw, 0xAD08, 0x0007); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8013); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0700); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FB9); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x2801); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FBA); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FBC); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x1900); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FBE); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xE100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FC0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0800); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FC2); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xE500); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FC4); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FC6); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xF100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FC8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0400); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FCa); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xF300); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FCc); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFD00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FCe); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFF00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FD0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFB00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FD2); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FD4); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xF400); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FD6); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFF00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FD8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xF600); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x813D); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x390E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814F); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x790E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80B0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F31); + rtl_set_eth_phy_ocp_bit(hw, 0xBF4C, BIT_1); + rtl_set_eth_phy_ocp_bit(hw, 0xBCCA, (BIT_9 | BIT_8)); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8141); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x320E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8153); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x720E); + rtl_clear_eth_phy_ocp_bit(hw, 0xA432, BIT_6); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8529); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x050E); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x816C); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xC4A0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8170); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xC4A0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8174); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x04A0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8178); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x04A0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x817C); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0719); + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) { + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF4); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0400); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0404); + } + rtl_mdio_direct_write_phy_ocp(hw, 0xBF4A, 0x001B); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8033); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C13); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8037); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C13); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x803B); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFC32); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x803F); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C13); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8043); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C13); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8047); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C13); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8145); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x370E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8157); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x770E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8169); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0D0A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x817B); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x1D0A); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8217); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x821A); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5000); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DA); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0403); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DC); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B3); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0384); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2007); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BA); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x6C00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xF009); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BD); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x9F00); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80C7); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf083); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DD); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x03f0); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DF); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CB); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2007); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CE); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x6C00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80C9); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8009); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D1); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x8000); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A3); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x200A); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xF0AD); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x809F); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6073); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x000B); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A9); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC000); + + rtl_set_phy_mcu_patch_request(hw); + + rtl_clear_eth_phy_ocp_bit(hw, 0xB896, BIT_0); + rtl_clear_eth_phy_ocp_bit(hw, 0xB892, 0xFF00); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC23E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC240); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0103); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC242); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0507); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC244); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x090B); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC246); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0C0E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC248); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1012); + rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC24A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1416); + + rtl_set_eth_phy_ocp_bit(hw, 0xB896, BIT_0); + + rtl_clear_phy_mcu_patch_request(hw); + + rtl_set_eth_phy_ocp_bit(hw, 0xA86A, BIT_0); + rtl_set_eth_phy_ocp_bit(hw, 0xA6F0, BIT_0); + + rtl_mdio_direct_write_phy_ocp(hw, 0xBFA0, 0xD70D); + rtl_mdio_direct_write_phy_ocp(hw, 0xBFA2, 0x4100); + rtl_mdio_direct_write_phy_ocp(hw, 0xBFA4, 0xE868); + rtl_mdio_direct_write_phy_ocp(hw, 0xBFA6, 0xDC59); + rtl_mdio_direct_write_phy_ocp(hw, 0xB54C, 0x3C18); + rtl_clear_eth_phy_ocp_bit(hw, 0xBFA4, BIT_5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x817D); + rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_12); +} + +static void +rtl_hw_phy_config_8125b_2(struct rtl_hw *hw) +{ + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC46, 0x00F0, 0x0090); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD30, 0x0003, 0x0001); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80F5); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x760E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8107); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x360E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8551); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, + (BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 | + BIT_9 | BIT_8), + BIT_11); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xbf00, 0xE000, 0xA000); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xbf46, 0x0F00, 0x0300); + rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8044); + rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417); + rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x804A); + rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417); + rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8050); + rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417); + rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8056); + rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417); + rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x805C); + rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417); + rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8062); + rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417); + rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8068); + rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417); + rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x806E); + rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417); + rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8074); + rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417); + rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x807A); + rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417); + + rtl_set_eth_phy_ocp_bit(hw, 0xA4CA, BIT_6); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF84, (BIT_15 | BIT_14 | BIT_13), + (BIT_15 | BIT_13)); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8170); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, + (BIT_13 | BIT_10 | BIT_9 | BIT_8), + (BIT_15 | BIT_14 | BIT_12 | BIT_11)); + + rtl_set_eth_phy_ocp_bit(hw, 0xA424, BIT_3); +} + +static void +hw_phy_config_8125b(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_50: + rtl_hw_phy_config_8125b_1(hw); + break; + case CFG_METHOD_51: + rtl_hw_phy_config_8125b_2(hw); + break; + } +} + +static void +hw_mac_mcu_config_8125b(struct rtl_hw *hw) +{ + if (hw->NotWrMcuPatchCode == TRUE) + return; + + switch (hw->mcfg) { + case CFG_METHOD_50: + rtl_set_mac_mcu_8125b_1(hw); + break; + case CFG_METHOD_51: + rtl_set_mac_mcu_8125b_2(hw); + break; + } +} + +static void +hw_phy_mcu_config_8125b(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_50: + rtl_set_phy_mcu_8125b_1(hw); + break; + case CFG_METHOD_51: + rtl_set_phy_mcu_8125b_2(hw); + break; + } +} + +const struct rtl_hw_ops rtl8125b_ops = { + .hw_init_rxcfg = hw_init_rxcfg_8125b, + .hw_ephy_config = hw_ephy_config_8125b, + .hw_phy_config = hw_phy_config_8125b, + .hw_mac_mcu_config = hw_mac_mcu_config_8125b, + .hw_phy_mcu_config = hw_phy_mcu_config_8125b, +}; + diff --git a/drivers/net/r8169/base/rtl8125b_mcu.c b/drivers/net/r8169/base/rtl8125b_mcu.c new file mode 100644 index 0000000000..590420b7dc --- /dev/null +++ b/drivers/net/r8169/base/rtl8125b_mcu.c @@ -0,0 +1,1068 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include "../r8169_ethdev.h" +#include "../r8169_hw.h" +#include "../r8169_phy.h" +#include "rtl8125b_mcu.h" + +/* For RTL8125B, CFG_METHOD_50,51 */ + +/* ------------------------------------MAC 8125B------------------------------------- */ + +void +rtl_set_mac_mcu_8125b_1(struct rtl_hw *hw) +{ + rtl_hw_disable_mac_mcu_bps(hw); +} + +void +rtl_set_mac_mcu_8125b_2(struct rtl_hw *hw) +{ + static const u16 mcu_patch_code_8125b_2[] = { + 0xE010, 0xE01B, 0xE026, 0xE037, 0xE03D, 0xE057, 0xE05B, 0xE060, 0xE062, + 0xE064, 0xE066, 0xE068, 0xE06A, 0xE06C, 0xE06E, 0xE070, 0x740A, 0x4846, + 0x4847, 0x9C0A, 0xC607, 0x74C0, 0x48C6, 0x9CC0, 0xC602, 0xBE00, 0x13F0, + 0xE054, 0x72CA, 0x4826, 0x4827, 0x9ACA, 0xC607, 0x72C0, 0x48A6, 0x9AC0, + 0xC602, 0xBE00, 0x081C, 0xE054, 0xC60F, 0x74C4, 0x49CC, 0xF109, 0xC60C, + 0x74CA, 0x48C7, 0x9CCA, 0xC609, 0x74C0, 0x4846, 0x9CC0, 0xC602, 0xBE00, + 0x2494, 0xE092, 0xE0C0, 0xE054, 0x7420, 0x48C0, 0x9C20, 0x7444, 0xC602, + 0xBE00, 0x12DC, 0x733A, 0x21B5, 0x25BC, 0x1304, 0xF111, 0x1B12, 0x1D2A, + 0x3168, 0x3ADA, 0x31AB, 0x1A00, 0x9AC0, 0x1300, 0xF1FB, 0x7620, 0x236E, + 0x276F, 0x1A3C, 0x22A1, 0x41B5, 0x9EE2, 0x76E4, 0x486F, 0x9EE4, 0xC602, + 0xBE00, 0x4A26, 0x733A, 0x49BB, 0xC602, 0xBE00, 0x47A2, 0x48C1, 0x48C2, + 0x9C46, 0xC402, 0xBC00, 0x0A52, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, + 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, + 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, + 0x0000, 0xC602, 0xBE00, 0x0000 + }; + + rtl_hw_disable_mac_mcu_bps(hw); + + rtl_write_mac_mcu_ram_code(hw, mcu_patch_code_8125b_2, + ARRAY_SIZE(mcu_patch_code_8125b_2)); + + rtl_mac_ocp_write(hw, 0xFC26, 0x8000); + + rtl_mac_ocp_write(hw, 0xFC28, 0x13E6); + rtl_mac_ocp_write(hw, 0xFC2A, 0x0812); + rtl_mac_ocp_write(hw, 0xFC2C, 0x248C); + rtl_mac_ocp_write(hw, 0xFC2E, 0x12DA); + rtl_mac_ocp_write(hw, 0xFC30, 0x4A20); + rtl_mac_ocp_write(hw, 0xFC32, 0x47A0); + + rtl_mac_ocp_write(hw, 0xFC48, 0x003F); +} + +/* ------------------------------------PHY 8125B--------------------------------------- */ + +static const u16 phy_mcu_ram_code_8125b_1[] = { + 0xa436, 0x8024, 0xa438, 0x3700, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x8025, 0xa438, 0x1800, 0xa438, 0x803a, + 0xa438, 0x1800, 0xa438, 0x8044, 0xa438, 0x1800, 0xa438, 0x8083, + 0xa438, 0x1800, 0xa438, 0x808d, 0xa438, 0x1800, 0xa438, 0x808d, + 0xa438, 0x1800, 0xa438, 0x808d, 0xa438, 0xd712, 0xa438, 0x4077, + 0xa438, 0xd71e, 0xa438, 0x4159, 0xa438, 0xd71e, 0xa438, 0x6099, + 0xa438, 0x7f44, 0xa438, 0x1800, 0xa438, 0x1a14, 0xa438, 0x9040, + 0xa438, 0x9201, 0xa438, 0x1800, 0xa438, 0x1b1a, 0xa438, 0xd71e, + 0xa438, 0x2425, 0xa438, 0x1a14, 0xa438, 0xd71f, 0xa438, 0x3ce5, + 0xa438, 0x1afb, 0xa438, 0x1800, 0xa438, 0x1b00, 0xa438, 0xd712, + 0xa438, 0x4077, 0xa438, 0xd71e, 0xa438, 0x4159, 0xa438, 0xd71e, + 0xa438, 0x60b9, 0xa438, 0x2421, 0xa438, 0x1c17, 0xa438, 0x1800, + 0xa438, 0x1a14, 0xa438, 0x9040, 0xa438, 0x1800, 0xa438, 0x1c2c, + 0xa438, 0xd71e, 0xa438, 0x2425, 0xa438, 0x1a14, 0xa438, 0xd71f, + 0xa438, 0x3ce5, 0xa438, 0x1c0f, 0xa438, 0x1800, 0xa438, 0x1c13, + 0xa438, 0xd702, 0xa438, 0xd501, 0xa438, 0x6072, 0xa438, 0x8401, + 0xa438, 0xf002, 0xa438, 0xa401, 0xa438, 0x1000, 0xa438, 0x146e, + 0xa438, 0x1800, 0xa438, 0x0b77, 0xa438, 0xd703, 0xa438, 0x665d, + 0xa438, 0x653e, 0xa438, 0x641f, 0xa438, 0xd700, 0xa438, 0x62c4, + 0xa438, 0x6185, 0xa438, 0x6066, 0xa438, 0x1800, 0xa438, 0x165a, + 0xa438, 0xc101, 0xa438, 0xcb00, 0xa438, 0x1000, 0xa438, 0x1945, + 0xa438, 0xd700, 0xa438, 0x7fa6, 0xa438, 0x1800, 0xa438, 0x807d, + 0xa438, 0xc102, 0xa438, 0xcb00, 0xa438, 0x1000, 0xa438, 0x1945, + 0xa438, 0xd700, 0xa438, 0x2569, 0xa438, 0x8058, 0xa438, 0x1800, + 0xa438, 0x807d, 0xa438, 0xc104, 0xa438, 0xcb00, 0xa438, 0x1000, + 0xa438, 0x1945, 0xa438, 0xd700, 0xa438, 0x7fa4, 0xa438, 0x1800, + 0xa438, 0x807d, 0xa438, 0xc120, 0xa438, 0xcb00, 0xa438, 0x1000, + 0xa438, 0x1945, 0xa438, 0xd703, 0xa438, 0x7fbf, 0xa438, 0x1800, + 0xa438, 0x807d, 0xa438, 0xc140, 0xa438, 0xcb00, 0xa438, 0x1000, + 0xa438, 0x1945, 0xa438, 0xd703, 0xa438, 0x7fbe, 0xa438, 0x1800, + 0xa438, 0x807d, 0xa438, 0xc180, 0xa438, 0xcb00, 0xa438, 0x1000, + 0xa438, 0x1945, 0xa438, 0xd703, 0xa438, 0x7fbd, 0xa438, 0xc100, + 0xa438, 0xcb00, 0xa438, 0xd708, 0xa438, 0x6018, 0xa438, 0x1800, + 0xa438, 0x165a, 0xa438, 0x1000, 0xa438, 0x14f6, 0xa438, 0xd014, + 0xa438, 0xd1e3, 0xa438, 0x1000, 0xa438, 0x1356, 0xa438, 0xd705, + 0xa438, 0x5fbe, 0xa438, 0x1800, 0xa438, 0x1559, 0xa436, 0xA026, + 0xa438, 0xffff, 0xa436, 0xA024, 0xa438, 0xffff, 0xa436, 0xA022, + 0xa438, 0xffff, 0xa436, 0xA020, 0xa438, 0x1557, 0xa436, 0xA006, + 0xa438, 0x1677, 0xa436, 0xA004, 0xa438, 0x0b75, 0xa436, 0xA002, + 0xa438, 0x1c17, 0xa436, 0xA000, 0xa438, 0x1b04, 0xa436, 0xA008, + 0xa438, 0x1f00, 0xa436, 0xA016, 0xa438, 0x0020, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x817f, 0xa438, 0x1800, 0xa438, 0x82ab, + 0xa438, 0x1800, 0xa438, 0x83f8, 0xa438, 0x1800, 0xa438, 0x8444, + 0xa438, 0x1800, 0xa438, 0x8454, 0xa438, 0x1800, 0xa438, 0x8459, + 0xa438, 0x1800, 0xa438, 0x8465, 0xa438, 0xcb11, 0xa438, 0xa50c, + 0xa438, 0x8310, 0xa438, 0xd701, 0xa438, 0x4076, 0xa438, 0x0c03, + 0xa438, 0x0903, 0xa438, 0xd700, 0xa438, 0x6083, 0xa438, 0x0c1f, + 0xa438, 0x0d00, 0xa438, 0xf003, 0xa438, 0x0c1f, 0xa438, 0x0d00, + 0xa438, 0x1000, 0xa438, 0x0a7d, 0xa438, 0x1000, 0xa438, 0x0a4d, + 0xa438, 0xcb12, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, + 0xa438, 0x5f84, 0xa438, 0xd102, 0xa438, 0xd040, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xd701, + 0xa438, 0x60f3, 0xa438, 0xd413, 0xa438, 0x1000, 0xa438, 0x0a37, + 0xa438, 0xd410, 0xa438, 0x1000, 0xa438, 0x0a37, 0xa438, 0xcb13, + 0xa438, 0xa108, 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8108, + 0xa438, 0xa00a, 0xa438, 0xa910, 0xa438, 0xa780, 0xa438, 0xd14a, + 0xa438, 0xd048, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd701, + 0xa438, 0x6255, 0xa438, 0xd700, 0xa438, 0x5f74, 0xa438, 0x6326, + 0xa438, 0xd702, 0xa438, 0x5f07, 0xa438, 0x800a, 0xa438, 0xa004, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8004, 0xa438, 0xa001, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8001, 0xa438, 0x0c03, + 0xa438, 0x0902, 0xa438, 0xffe2, 0xa438, 0x1000, 0xa438, 0x0a5e, + 0xa438, 0xd71f, 0xa438, 0x5fab, 0xa438, 0xba08, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd71f, 0xa438, 0x7f8b, 0xa438, 0x9a08, + 0xa438, 0x800a, 0xa438, 0xd702, 0xa438, 0x6535, 0xa438, 0xd40d, + 0xa438, 0x1000, 0xa438, 0x0a37, 0xa438, 0xcb14, 0xa438, 0xa004, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8004, 0xa438, 0xa001, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8001, 0xa438, 0xa00a, + 0xa438, 0xa780, 0xa438, 0xd14a, 0xa438, 0xd048, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0x6206, + 0xa438, 0xd702, 0xa438, 0x5f47, 0xa438, 0x800a, 0xa438, 0xa004, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8004, 0xa438, 0xa001, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8001, 0xa438, 0x0c03, + 0xa438, 0x0902, 0xa438, 0x1800, 0xa438, 0x8064, 0xa438, 0x800a, + 0xa438, 0xd40e, 0xa438, 0x1000, 0xa438, 0x0a37, 0xa438, 0xb920, + 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, 0xa438, 0x5fac, + 0xa438, 0x9920, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, + 0xa438, 0x7f8c, 0xa438, 0xd701, 0xa438, 0x6073, 0xa438, 0xd701, + 0xa438, 0x4216, 0xa438, 0xa004, 0xa438, 0x1000, 0xa438, 0x0a42, + 0xa438, 0x8004, 0xa438, 0xa001, 0xa438, 0x1000, 0xa438, 0x0a42, + 0xa438, 0x8001, 0xa438, 0xd120, 0xa438, 0xd040, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0x8504, + 0xa438, 0xcb21, 0xa438, 0xa301, 0xa438, 0x1000, 0xa438, 0x0a5e, + 0xa438, 0xd700, 0xa438, 0x5f9f, 0xa438, 0x8301, 0xa438, 0xd704, + 0xa438, 0x40e0, 0xa438, 0xd196, 0xa438, 0xd04d, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xcb22, + 0xa438, 0x1000, 0xa438, 0x0a6d, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xa640, 0xa438, 0x9503, 0xa438, 0x8910, 0xa438, 0x8720, + 0xa438, 0xd700, 0xa438, 0x6083, 0xa438, 0x0c1f, 0xa438, 0x0d01, + 0xa438, 0xf003, 0xa438, 0x0c1f, 0xa438, 0x0d01, 0xa438, 0x1000, + 0xa438, 0x0a7d, 0xa438, 0x0c1f, 0xa438, 0x0f14, 0xa438, 0xcb23, + 0xa438, 0x8fc0, 0xa438, 0x1000, 0xa438, 0x0a25, 0xa438, 0xaf40, + 0xa438, 0x1000, 0xa438, 0x0a25, 0xa438, 0x0cc0, 0xa438, 0x0f80, + 0xa438, 0x1000, 0xa438, 0x0a25, 0xa438, 0xafc0, 0xa438, 0x1000, + 0xa438, 0x0a25, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd701, + 0xa438, 0x5dee, 0xa438, 0xcb24, 0xa438, 0x8f1f, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd701, 0xa438, 0x7f6e, 0xa438, 0xa111, + 0xa438, 0xa215, 0xa438, 0xa401, 0xa438, 0x8404, 0xa438, 0xa720, + 0xa438, 0xcb25, 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0x8640, + 0xa438, 0x9503, 0xa438, 0x1000, 0xa438, 0x0b43, 0xa438, 0x1000, + 0xa438, 0x0b86, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xb920, + 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, 0xa438, 0x5fac, + 0xa438, 0x9920, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, + 0xa438, 0x7f8c, 0xa438, 0xcb26, 0xa438, 0x1000, 0xa438, 0x0a5e, + 0xa438, 0xd71f, 0xa438, 0x5f82, 0xa438, 0x8111, 0xa438, 0x8205, + 0xa438, 0x8404, 0xa438, 0xcb27, 0xa438, 0xd404, 0xa438, 0x1000, + 0xa438, 0x0a37, 0xa438, 0xd700, 0xa438, 0x6083, 0xa438, 0x0c1f, + 0xa438, 0x0d02, 0xa438, 0xf003, 0xa438, 0x0c1f, 0xa438, 0x0d02, + 0xa438, 0x1000, 0xa438, 0x0a7d, 0xa438, 0xa710, 0xa438, 0xa104, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8104, 0xa438, 0xa001, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8001, 0xa438, 0xa120, + 0xa438, 0xaa0f, 0xa438, 0x8110, 0xa438, 0xa284, 0xa438, 0xa404, + 0xa438, 0xa00a, 0xa438, 0xd193, 0xa438, 0xd046, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xcb28, + 0xa438, 0xa110, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd700, + 0xa438, 0x5fa8, 0xa438, 0x8110, 0xa438, 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0xe085, 0xa438, 0x62e1, + 0xa438, 0x8563, 0xa438, 0xbf8b, 0xa438, 0x5102, 0xa438, 0x6c4e, + 0xa438, 0xe085, 0xa438, 0x68e1, 0xa438, 0x8569, 0xa438, 0xbf8b, + 0xa438, 0x5402, 0xa438, 0x6c4e, 0xa438, 0xe085, 0xa438, 0x6ee1, + 0xa438, 0x856f, 0xa438, 0xbf8b, 0xa438, 0x5702, 0xa438, 0x6c4e, + 0xa438, 0xe085, 0xa438, 0x74e1, 0xa438, 0x8575, 0xa438, 0xbf8b, + 0xa438, 0x5a02, 0xa438, 0x6c4e, 0xa438, 0xe18f, 0xa438, 0xb859, + 0xa438, 0x00f7, 0xa438, 0x28e5, 0xa438, 0x8fb8, 0xa438, 0xae4a, + 0xa438, 0x1f44, 0xa438, 0xe085, 0xa438, 0x64e1, 0xa438, 0x8565, + 0xa438, 0xbf8b, 0xa438, 0x5102, 0xa438, 0x6c4e, 0xa438, 0xe085, + 0xa438, 0x6ae1, 0xa438, 0x856b, 0xa438, 0xbf8b, 0xa438, 0x5402, + 0xa438, 0x6c4e, 0xa438, 0xe085, 0xa438, 0x70e1, 0xa438, 0x8571, + 0xa438, 0xbf8b, 0xa438, 0x5702, 0xa438, 0x6c4e, 0xa438, 0xe085, + 0xa438, 0x76e1, 0xa438, 0x8577, 0xa438, 0xbf8b, 0xa438, 0x5a02, + 0xa438, 0x6c4e, 0xa438, 0xe18f, 0xa438, 0xb859, 0xa438, 0x00f7, + 0xa438, 0x28e5, 0xa438, 0x8fb8, 0xa438, 0xae0c, 0xa438, 0xe18f, + 0xa438, 0xb839, 0xa438, 0x04ac, 0xa438, 0x2f04, 0xa438, 0xee8f, + 0xa438, 0xb800, 0xa438, 0xfefd, 0xa438, 0xfc04, 0xa438, 0xf0ac, + 0xa438, 0x8efc, 0xa438, 0xac8c, 0xa438, 0xf0ac, 0xa438, 0xfaf0, + 0xa438, 0xacf8, 0xa438, 0xf0ac, 0xa438, 0xf6f0, 0xa438, 0xad00, + 0xa438, 0xf0ac, 0xa438, 0xfef0, 0xa438, 0xacfc, 0xa438, 0xf0ac, + 0xa438, 0xf4f0, 0xa438, 0xacf2, 0xa438, 0xf0ac, 0xa438, 0xf0f0, + 0xa438, 0xacb0, 0xa438, 0xf0ac, 0xa438, 0xaef0, 0xa438, 0xacac, + 0xa438, 0xf0ac, 0xa438, 0xaaf0, 0xa438, 0xacee, 0xa438, 0xf0b0, + 0xa438, 0x24f0, 0xa438, 0xb0a4, 0xa438, 0xf0b1, 0xa438, 0x24f0, + 0xa438, 0xb1a4, 0xa438, 0xee8f, 0xa438, 0xb800, 0xa438, 0xd400, + 0xa438, 0x00af, 0xa438, 0x3976, 0xa438, 0x66ac, 0xa438, 0xeabb, + 0xa438, 0xa430, 0xa438, 0x6e50, 0xa438, 0x6e53, 0xa438, 0x6e56, + 0xa438, 0x6e59, 0xa438, 0x6e5c, 0xa438, 0x6e5f, 0xa438, 0x6e62, + 0xa438, 0x6e65, 0xa438, 0xd9ac, 0xa438, 0x70f0, 0xa438, 0xac6a, + 0xa436, 0xb85e, 0xa438, 0x23b7, 0xa436, 0xb860, 0xa438, 0x74db, + 0xa436, 0xb862, 0xa438, 0x268c, 0xa436, 0xb864, 0xa438, 0x3FE5, + 0xa436, 0xb886, 0xa438, 0x2250, 0xa436, 0xb888, 0xa438, 0x140e, + 0xa436, 0xb88a, 0xa438, 0x3696, 0xa436, 0xb88c, 0xa438, 0x3973, + 0xa436, 0xb838, 0xa438, 0x00ff, 0xb820, 0x0010, 0xa436, 0x8464, + 0xa438, 0xaf84, 0xa438, 0x7caf, 0xa438, 0x8485, 0xa438, 0xaf85, + 0xa438, 0x13af, 0xa438, 0x851e, 0xa438, 0xaf85, 0xa438, 0xb9af, + 0xa438, 0x8684, 0xa438, 0xaf87, 0xa438, 0x01af, 0xa438, 0x8701, + 0xa438, 0xac38, 0xa438, 0x03af, 0xa438, 0x38bb, 0xa438, 0xaf38, + 0xa438, 0xc302, 0xa438, 0x4618, 0xa438, 0xbf85, 0xa438, 0x0a02, + 0xa438, 0x54b7, 0xa438, 0xbf85, 0xa438, 0x1002, 0xa438, 0x54c0, + 0xa438, 0xd400, 0xa438, 0x0fbf, 0xa438, 0x8507, 0xa438, 0x024f, + 0xa438, 0x48bf, 0xa438, 0x8504, 0xa438, 0x024f, 0xa438, 0x6759, + 0xa438, 0xf0a1, 0xa438, 0x3008, 0xa438, 0xbf85, 0xa438, 0x0d02, + 0xa438, 0x54c0, 0xa438, 0xae06, 0xa438, 0xbf85, 0xa438, 0x0d02, + 0xa438, 0x54b7, 0xa438, 0xbf85, 0xa438, 0x0402, 0xa438, 0x4f67, + 0xa438, 0xa183, 0xa438, 0x02ae, 0xa438, 0x15a1, 0xa438, 0x8502, + 0xa438, 0xae10, 0xa438, 0x59f0, 0xa438, 0xa180, 0xa438, 0x16bf, + 0xa438, 0x8501, 0xa438, 0x024f, 0xa438, 0x67a1, 0xa438, 0x381b, + 0xa438, 0xae0b, 0xa438, 0xe18f, 0xa438, 0xffbf, 0xa438, 0x84fe, + 0xa438, 0x024f, 0xa438, 0x48ae, 0xa438, 0x17bf, 0xa438, 0x84fe, + 0xa438, 0x0254, 0xa438, 0xb7bf, 0xa438, 0x84fb, 0xa438, 0x0254, + 0xa438, 0xb7ae, 0xa438, 0x09a1, 0xa438, 0x5006, 0xa438, 0xbf84, + 0xa438, 0xfb02, 0xa438, 0x54c0, 0xa438, 0xaf04, 0xa438, 0x4700, + 0xa438, 0xad34, 0xa438, 0xfdad, 0xa438, 0x0670, 0xa438, 0xae14, + 0xa438, 0xf0a6, 0xa438, 0x00b8, 0xa438, 0xbd32, 0xa438, 0x30bd, + 0xa438, 0x30aa, 0xa438, 0xbd2c, 0xa438, 0xccbd, 0xa438, 0x2ca1, + 0xa438, 0x0705, 0xa438, 0xec80, 0xa438, 0xaf40, 0xa438, 0xf7af, + 0xa438, 0x40f5, 0xa438, 0xd101, 0xa438, 0xbf85, 0xa438, 0xa402, + 0xa438, 0x4f48, 0xa438, 0xbf85, 0xa438, 0xa702, 0xa438, 0x54c0, + 0xa438, 0xd10f, 0xa438, 0xbf85, 0xa438, 0xaa02, 0xa438, 0x4f48, + 0xa438, 0x024d, 0xa438, 0x6abf, 0xa438, 0x85ad, 0xa438, 0x024f, + 0xa438, 0x67bf, 0xa438, 0x8ff7, 0xa438, 0xddbf, 0xa438, 0x85b0, + 0xa438, 0x024f, 0xa438, 0x67bf, 0xa438, 0x8ff8, 0xa438, 0xddbf, + 0xa438, 0x85b3, 0xa438, 0x024f, 0xa438, 0x67bf, 0xa438, 0x8ff9, + 0xa438, 0xddbf, 0xa438, 0x85b6, 0xa438, 0x024f, 0xa438, 0x67bf, + 0xa438, 0x8ffa, 0xa438, 0xddd1, 0xa438, 0x00bf, 0xa438, 0x85aa, + 0xa438, 0x024f, 0xa438, 0x4802, 0xa438, 0x4d6a, 0xa438, 0xbf85, + 0xa438, 0xad02, 0xa438, 0x4f67, 0xa438, 0xbf8f, 0xa438, 0xfbdd, + 0xa438, 0xbf85, 0xa438, 0xb002, 0xa438, 0x4f67, 0xa438, 0xbf8f, + 0xa438, 0xfcdd, 0xa438, 0xbf85, 0xa438, 0xb302, 0xa438, 0x4f67, + 0xa438, 0xbf8f, 0xa438, 0xfddd, 0xa438, 0xbf85, 0xa438, 0xb602, + 0xa438, 0x4f67, 0xa438, 0xbf8f, 0xa438, 0xfedd, 0xa438, 0xbf85, + 0xa438, 0xa702, 0xa438, 0x54b7, 0xa438, 0xbf85, 0xa438, 0xa102, + 0xa438, 0x54b7, 0xa438, 0xaf3c, 0xa438, 0x2066, 0xa438, 0xb800, + 0xa438, 0xb8bd, 0xa438, 0x30ee, 0xa438, 0xbd2c, 0xa438, 0xb8bd, + 0xa438, 0x7040, 0xa438, 0xbd86, 0xa438, 0xc8bd, 0xa438, 0x8640, + 0xa438, 0xbd88, 0xa438, 0xc8bd, 0xa438, 0x8802, 0xa438, 0x1929, + 0xa438, 0xa202, 0xa438, 0x02ae, 0xa438, 0x03a2, 0xa438, 0x032e, + 0xa438, 0xd10f, 0xa438, 0xbf85, 0xa438, 0xaa02, 0xa438, 0x4f48, + 0xa438, 0xe18f, 0xa438, 0xf7bf, 0xa438, 0x85ad, 0xa438, 0x024f, + 0xa438, 0x48e1, 0xa438, 0x8ff8, 0xa438, 0xbf85, 0xa438, 0xb002, + 0xa438, 0x4f48, 0xa438, 0xe18f, 0xa438, 0xf9bf, 0xa438, 0x85b3, + 0xa438, 0x024f, 0xa438, 0x48e1, 0xa438, 0x8ffa, 0xa438, 0xbf85, + 0xa438, 0xb602, 0xa438, 0x4f48, 0xa438, 0xae2c, 0xa438, 0xd100, + 0xa438, 0xbf85, 0xa438, 0xaa02, 0xa438, 0x4f48, 0xa438, 0xe18f, + 0xa438, 0xfbbf, 0xa438, 0x85ad, 0xa438, 0x024f, 0xa438, 0x48e1, + 0xa438, 0x8ffc, 0xa438, 0xbf85, 0xa438, 0xb002, 0xa438, 0x4f48, + 0xa438, 0xe18f, 0xa438, 0xfdbf, 0xa438, 0x85b3, 0xa438, 0x024f, + 0xa438, 0x48e1, 0xa438, 0x8ffe, 0xa438, 0xbf85, 0xa438, 0xb602, + 0xa438, 0x4f48, 0xa438, 0xbf86, 0xa438, 0x7e02, 0xa438, 0x4f67, + 0xa438, 0xa100, 0xa438, 0x02ae, 0xa438, 0x25a1, 0xa438, 0x041d, + 0xa438, 0xe18f, 0xa438, 0xf1bf, 0xa438, 0x8675, 0xa438, 0x024f, + 0xa438, 0x48e1, 0xa438, 0x8ff2, 0xa438, 0xbf86, 0xa438, 0x7802, + 0xa438, 0x4f48, 0xa438, 0xe18f, 0xa438, 0xf3bf, 0xa438, 0x867b, + 0xa438, 0x024f, 0xa438, 0x48ae, 0xa438, 0x29a1, 0xa438, 0x070b, + 0xa438, 0xae24, 0xa438, 0xbf86, 0xa438, 0x8102, 0xa438, 0x4f67, + 0xa438, 0xad28, 0xa438, 0x1be1, 0xa438, 0x8ff4, 0xa438, 0xbf86, + 0xa438, 0x7502, 0xa438, 0x4f48, 0xa438, 0xe18f, 0xa438, 0xf5bf, + 0xa438, 0x8678, 0xa438, 0x024f, 0xa438, 0x48e1, 0xa438, 0x8ff6, + 0xa438, 0xbf86, 0xa438, 0x7b02, 0xa438, 0x4f48, 0xa438, 0xaf09, + 0xa438, 0x8420, 0xa438, 0xbc32, 0xa438, 0x20bc, 0xa438, 0x3e76, + 0xa438, 0xbc08, 0xa438, 0xfda6, 0xa438, 0x1a00, 0xa438, 0xb64e, + 0xa438, 0xd101, 0xa438, 0xbf85, 0xa438, 0xa402, 0xa438, 0x4f48, + 0xa438, 0xbf85, 0xa438, 0xa702, 0xa438, 0x54c0, 0xa438, 0xd10f, + 0xa438, 0xbf85, 0xa438, 0xaa02, 0xa438, 0x4f48, 0xa438, 0x024d, + 0xa438, 0x6abf, 0xa438, 0x85ad, 0xa438, 0x024f, 0xa438, 0x67bf, + 0xa438, 0x8ff7, 0xa438, 0xddbf, 0xa438, 0x85b0, 0xa438, 0x024f, + 0xa438, 0x67bf, 0xa438, 0x8ff8, 0xa438, 0xddbf, 0xa438, 0x85b3, + 0xa438, 0x024f, 0xa438, 0x67bf, 0xa438, 0x8ff9, 0xa438, 0xddbf, + 0xa438, 0x85b6, 0xa438, 0x024f, 0xa438, 0x67bf, 0xa438, 0x8ffa, + 0xa438, 0xddd1, 0xa438, 0x00bf, 0xa438, 0x85aa, 0xa438, 0x024f, + 0xa438, 0x4802, 0xa438, 0x4d6a, 0xa438, 0xbf85, 0xa438, 0xad02, + 0xa438, 0x4f67, 0xa438, 0xbf8f, 0xa438, 0xfbdd, 0xa438, 0xbf85, + 0xa438, 0xb002, 0xa438, 0x4f67, 0xa438, 0xbf8f, 0xa438, 0xfcdd, + 0xa438, 0xbf85, 0xa438, 0xb302, 0xa438, 0x4f67, 0xa438, 0xbf8f, + 0xa438, 0xfddd, 0xa438, 0xbf85, 0xa438, 0xb602, 0xa438, 0x4f67, + 0xa438, 0xbf8f, 0xa438, 0xfedd, 0xa438, 0xbf85, 0xa438, 0xa702, + 0xa438, 0x54b7, 0xa438, 0xaf00, 0xa438, 0x8800, 0xa436, 0xb818, + 0xa438, 0x38b8, 0xa436, 0xb81a, 0xa438, 0x0444, 0xa436, 0xb81c, + 0xa438, 0x40ee, 0xa436, 0xb81e, 0xa438, 0x3C1A, 0xa436, 0xb850, + 0xa438, 0x0981, 0xa436, 0xb852, 0xa438, 0x0085, 0xa436, 0xb878, + 0xa438, 0xffff, 0xa436, 0xb884, 0xa438, 0xffff, 0xa436, 0xb832, + 0xa438, 0x003f, 0xa436, 0x0000, 0xa438, 0x0000, 0xa436, 0xB82E, + 0xa438, 0x0000, 0xa436, 0x8024, 0xa438, 0x0000, 0xb820, 0x0000, + 0xa436, 0x801E, 0xa438, 0x0021, 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8125b_2[] = { + 0xa436, 0x8024, 0xa438, 0x3701, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x801a, 0xa438, 0x1800, 0xa438, 0x803f, + 0xa438, 0x1800, 0xa438, 0x8045, 0xa438, 0x1800, 0xa438, 0x8067, + 0xa438, 0x1800, 0xa438, 0x806d, 0xa438, 0x1800, 0xa438, 0x8071, + 0xa438, 0x1800, 0xa438, 0x80b1, 0xa438, 0xd093, 0xa438, 0xd1c4, + 0xa438, 0x1000, 0xa438, 0x135c, 0xa438, 0xd704, 0xa438, 0x5fbc, + 0xa438, 0xd504, 0xa438, 0xc9f1, 0xa438, 0x1800, 0xa438, 0x0fc9, + 0xa438, 0xbb50, 0xa438, 0xd505, 0xa438, 0xa202, 0xa438, 0xd504, + 0xa438, 0x8c0f, 0xa438, 0xd500, 0xa438, 0x1000, 0xa438, 0x1519, + 0xa438, 0x1000, 0xa438, 0x135c, 0xa438, 0xd75e, 0xa438, 0x5fae, + 0xa438, 0x9b50, 0xa438, 0x1000, 0xa438, 0x135c, 0xa438, 0xd75e, + 0xa438, 0x7fae, 0xa438, 0x1000, 0xa438, 0x135c, 0xa438, 0xd707, + 0xa438, 0x40a7, 0xa438, 0xd719, 0xa438, 0x4071, 0xa438, 0x1800, + 0xa438, 0x1557, 0xa438, 0xd719, 0xa438, 0x2f70, 0xa438, 0x803b, + 0xa438, 0x2f73, 0xa438, 0x156a, 0xa438, 0x5e70, 0xa438, 0x1800, + 0xa438, 0x155d, 0xa438, 0xd505, 0xa438, 0xa202, 0xa438, 0xd500, + 0xa438, 0xffed, 0xa438, 0xd709, 0xa438, 0x4054, 0xa438, 0xa788, + 0xa438, 0xd70b, 0xa438, 0x1800, 0xa438, 0x172a, 0xa438, 0xc0c1, + 0xa438, 0xc0c0, 0xa438, 0xd05a, 0xa438, 0xd1ba, 0xa438, 0xd701, + 0xa438, 0x2529, 0xa438, 0x022a, 0xa438, 0xd0a7, 0xa438, 0xd1b9, + 0xa438, 0xa208, 0xa438, 0x1000, 0xa438, 0x080e, 0xa438, 0xd701, + 0xa438, 0x408b, 0xa438, 0x1000, 0xa438, 0x0a65, 0xa438, 0xf003, + 0xa438, 0x1000, 0xa438, 0x0a6b, 0xa438, 0xd701, 0xa438, 0x1000, + 0xa438, 0x0920, 0xa438, 0x1000, 0xa438, 0x0915, 0xa438, 0x1000, + 0xa438, 0x0909, 0xa438, 0x228f, 0xa438, 0x804e, 0xa438, 0x9801, + 0xa438, 0xd71e, 0xa438, 0x5d61, 0xa438, 0xd701, 0xa438, 0x1800, + 0xa438, 0x022a, 0xa438, 0x2005, 0xa438, 0x091a, 0xa438, 0x3bd9, + 0xa438, 0x0919, 0xa438, 0x1800, 0xa438, 0x0916, 0xa438, 0xd090, + 0xa438, 0xd1c9, 0xa438, 0x1800, 0xa438, 0x1064, 0xa438, 0xd096, + 0xa438, 0xd1a9, 0xa438, 0xd503, 0xa438, 0xa104, 0xa438, 0x0c07, + 0xa438, 0x0902, 0xa438, 0xd500, 0xa438, 0xbc10, 0xa438, 0xd501, + 0xa438, 0xce01, 0xa438, 0xa201, 0xa438, 0x8201, 0xa438, 0xce00, + 0xa438, 0xd500, 0xa438, 0xc484, 0xa438, 0xd503, 0xa438, 0xcc02, + 0xa438, 0xcd0d, 0xa438, 0xaf01, 0xa438, 0xd500, 0xa438, 0xd703, + 0xa438, 0x4371, 0xa438, 0xbd08, 0xa438, 0x1000, 0xa438, 0x135c, + 0xa438, 0xd75e, 0xa438, 0x5fb3, 0xa438, 0xd503, 0xa438, 0xd0f5, + 0xa438, 0xd1c6, 0xa438, 0x0cf0, 0xa438, 0x0e50, 0xa438, 0xd704, + 0xa438, 0x401c, 0xa438, 0xd0f5, 0xa438, 0xd1c6, 0xa438, 0x0cf0, + 0xa438, 0x0ea0, 0xa438, 0x401c, 0xa438, 0xd07b, 0xa438, 0xd1c5, + 0xa438, 0x8ef0, 0xa438, 0x401c, 0xa438, 0x9d08, 0xa438, 0x1000, + 0xa438, 0x135c, 0xa438, 0xd75e, 0xa438, 0x7fb3, 0xa438, 0x1000, + 0xa438, 0x135c, 0xa438, 0xd75e, 0xa438, 0x5fad, 0xa438, 0x1000, + 0xa438, 0x14c5, 0xa438, 0xd703, 0xa438, 0x3181, 0xa438, 0x80af, + 0xa438, 0x60ad, 0xa438, 0x1000, 0xa438, 0x135c, 0xa438, 0xd703, + 0xa438, 0x5fba, 0xa438, 0x1800, 0xa438, 0x0cc7, 0xa438, 0xa802, + 0xa438, 0xa301, 0xa438, 0xa801, 0xa438, 0xc004, 0xa438, 0xd710, + 0xa438, 0x4000, 0xa438, 0x1800, 0xa438, 0x1e79, 0xa436, 0xA026, + 0xa438, 0x1e78, 0xa436, 0xA024, 0xa438, 0x0c93, 0xa436, 0xA022, + 0xa438, 0x1062, 0xa436, 0xA020, 0xa438, 0x0915, 0xa436, 0xA006, + 0xa438, 0x020a, 0xa436, 0xA004, 0xa438, 0x1726, 0xa436, 0xA002, + 0xa438, 0x1542, 0xa436, 0xA000, 0xa438, 0x0fc7, 0xa436, 0xA008, + 0xa438, 0xff00, 0xa436, 0xA016, 0xa438, 0x0010, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x801d, 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0xa438, 0xe58f, 0xa438, 0xffbf, 0xa438, 0x5322, 0xa438, 0x0252, + 0xa438, 0xc8a1, 0xa438, 0x4448, 0xa438, 0xaf85, 0xa438, 0xa7bf, + 0xa438, 0x5322, 0xa438, 0x0252, 0xa438, 0xc8a1, 0xa438, 0x313c, + 0xa438, 0xbf54, 0xa438, 0x7b02, 0xa438, 0x52c8, 0xa438, 0xe48f, + 0xa438, 0xf8e5, 0xa438, 0x8ff9, 0xa438, 0xbf54, 0xa438, 0x7e02, + 0xa438, 0x52c8, 0xa438, 0xe48f, 0xa438, 0xfae5, 0xa438, 0x8ffb, + 0xa438, 0xbf54, 0xa438, 0x8102, 0xa438, 0x52c8, 0xa438, 0xe48f, + 0xa438, 0xfce5, 0xa438, 0x8ffd, 0xa438, 0xbf54, 0xa438, 0x8402, + 0xa438, 0x52c8, 0xa438, 0xe48f, 0xa438, 0xfee5, 0xa438, 0x8fff, + 0xa438, 0xbf53, 0xa438, 0x2202, 0xa438, 0x52c8, 0xa438, 0xa131, + 0xa438, 0x03af, 0xa438, 0x85a7, 0xa438, 0xd480, 0xa438, 0x00bf, + 0xa438, 0x8684, 0xa438, 0x0252, 0xa438, 0xa9bf, 0xa438, 0x8687, + 0xa438, 0x0252, 0xa438, 0xa9bf, 0xa438, 0x868a, 0xa438, 0x0252, + 0xa438, 0xa9bf, 0xa438, 0x868d, 0xa438, 0x0252, 0xa438, 0xa9ef, + 0xa438, 0x95fd, 0xa438, 0xfc04, 0xa438, 0xf0d1, 0xa438, 0x2af0, + 0xa438, 0xd12c, 0xa438, 0xf0d1, 0xa438, 0x44f0, 0xa438, 0xd146, + 0xa438, 0xbf86, 0xa438, 0xa102, 0xa438, 0x52c8, 0xa438, 0xbf86, + 0xa438, 0xa102, 0xa438, 0x52c8, 0xa438, 0xd101, 0xa438, 0xaf06, + 0xa438, 0xa570, 0xa438, 0xce42, 0xa438, 0xee83, 0xa438, 0xc800, + 0xa438, 0x0286, 0xa438, 0xba02, 0xa438, 0x8728, 0xa438, 0x0287, + 0xa438, 0xbe02, 0xa438, 0x87f9, 0xa438, 0x0288, 0xa438, 0xc3af, + 0xa438, 0x4771, 0xa438, 0xf8f9, 0xa438, 0xfafb, 0xa438, 0xef69, + 0xa438, 0xfae0, 0xa438, 0x8015, 0xa438, 0xad25, 0xa438, 0x45d2, + 0xa438, 0x0002, 0xa438, 0x8714, 0xa438, 0xac4f, 0xa438, 0x02ae, + 0xa438, 0x0bef, 0xa438, 0x46f6, 0xa438, 0x273c, 0xa438, 0x0400, + 0xa438, 0xab26, 0xa438, 0xae30, 0xa438, 0xe08f, 0xa438, 0xe9e1, + 0xa438, 0x8fea, 0xa438, 0x1b46, 0xa438, 0xab26, 0xa438, 0xef32, + 0xa438, 0x0c31, 0xa438, 0xbf8f, 0xa438, 0xe91a, 0xa438, 0x93d8, + 0xa438, 0x19d9, 0xa438, 0x1b46, 0xa438, 0xab0a, 0xa438, 0x19d8, + 0xa438, 0x19d9, 0xa438, 0x1b46, 0xa438, 0xaa02, 0xa438, 0xae0c, + 0xa438, 0xbf57, 0xa438, 0x1202, 0xa438, 0x58b1, 0xa438, 0xbf57, + 0xa438, 0x1202, 0xa438, 0x58a8, 0xa438, 0xfeef, 0xa438, 0x96ff, + 0xa438, 0xfefd, 0xa438, 0xfc04, 0xa438, 0xf8fb, 0xa438, 0xef79, + 0xa438, 0xa200, 0xa438, 0x08bf, 0xa438, 0x892e, 0xa438, 0x0252, + 0xa438, 0xc8ef, 0xa438, 0x64ef, 0xa438, 0x97ff, 0xa438, 0xfc04, + 0xa438, 0xf8f9, 0xa438, 0xfafb, 0xa438, 0xef69, 0xa438, 0xfae0, + 0xa438, 0x8015, 0xa438, 0xad25, 0xa438, 0x50d2, 0xa438, 0x0002, + 0xa438, 0x878d, 0xa438, 0xac4f, 0xa438, 0x02ae, 0xa438, 0x0bef, + 0xa438, 0x46f6, 0xa438, 0x273c, 0xa438, 0x1000, 0xa438, 0xab31, + 0xa438, 0xae29, 0xa438, 0xe08f, 0xa438, 0xede1, 0xa438, 0x8fee, + 0xa438, 0x1b46, 0xa438, 0xab1f, 0xa438, 0xa200, 0xa438, 0x04ef, + 0xa438, 0x32ae, 0xa438, 0x02d3, 0xa438, 0x010c, 0xa438, 0x31bf, + 0xa438, 0x8fed, 0xa438, 0x1a93, 0xa438, 0xd819, 0xa438, 0xd91b, + 0xa438, 0x46ab, 0xa438, 0x0e19, 0xa438, 0xd819, 0xa438, 0xd91b, + 0xa438, 0x46aa, 0xa438, 0x0612, 0xa438, 0xa205, 0xa438, 0xc0ae, + 0xa438, 0x0cbf, 0xa438, 0x5712, 0xa438, 0x0258, 0xa438, 0xb1bf, + 0xa438, 0x5712, 0xa438, 0x0258, 0xa438, 0xa8fe, 0xa438, 0xef96, + 0xa438, 0xfffe, 0xa438, 0xfdfc, 0xa438, 0x04f8, 0xa438, 0xfbef, + 0xa438, 0x79a2, 0xa438, 0x0005, 0xa438, 0xbf89, 0xa438, 0x1fae, + 0xa438, 0x1ba2, 0xa438, 0x0105, 0xa438, 0xbf89, 0xa438, 0x22ae, + 0xa438, 0x13a2, 0xa438, 0x0205, 0xa438, 0xbf89, 0xa438, 0x25ae, + 0xa438, 0x0ba2, 0xa438, 0x0305, 0xa438, 0xbf89, 0xa438, 0x28ae, + 0xa438, 0x03bf, 0xa438, 0x892b, 0xa438, 0x0252, 0xa438, 0xc8ef, + 0xa438, 0x64ef, 0xa438, 0x97ff, 0xa438, 0xfc04, 0xa438, 0xf8f9, + 0xa438, 0xfaef, 0xa438, 0x69fa, 0xa438, 0xe080, 0xa438, 0x15ad, + 0xa438, 0x2628, 0xa438, 0xe081, 0xa438, 0xabe1, 0xa438, 0x81ac, + 0xa438, 0xef64, 0xa438, 0xbf57, 0xa438, 0x1802, 0xa438, 0x52c8, + 0xa438, 0x1b46, 0xa438, 0xaa0a, 0xa438, 0xbf57, 0xa438, 0x1b02, + 0xa438, 0x52c8, 0xa438, 0x1b46, 0xa438, 0xab0c, 0xa438, 0xbf57, + 0xa438, 0x1502, 0xa438, 0x58b1, 0xa438, 0xbf57, 0xa438, 0x1502, + 0xa438, 0x58a8, 0xa438, 0xfeef, 0xa438, 0x96fe, 0xa438, 0xfdfc, + 0xa438, 0x04f8, 0xa438, 0xf9ef, 0xa438, 0x59f9, 0xa438, 0xe080, + 0xa438, 0x15ad, 0xa438, 0x2622, 0xa438, 0xbf53, 0xa438, 0x2202, + 0xa438, 0x52c8, 0xa438, 0x3972, 0xa438, 0x9e10, 0xa438, 0xe083, + 0xa438, 0xc9ac, 0xa438, 0x2605, 0xa438, 0x0288, 0xa438, 0x2cae, + 0xa438, 0x0d02, 0xa438, 0x8870, 0xa438, 0xae08, 0xa438, 0xe283, + 0xa438, 0xc9f6, 0xa438, 0x36e6, 0xa438, 0x83c9, 0xa438, 0xfdef, + 0xa438, 0x95fd, 0xa438, 0xfc04, 0xa438, 0xf8f9, 0xa438, 0xfafb, + 0xa438, 0xef79, 0xa438, 0xfbbf, 0xa438, 0x5718, 0xa438, 0x0252, + 0xa438, 0xc8ef, 0xa438, 0x64e2, 0xa438, 0x8fe5, 0xa438, 0xe38f, + 0xa438, 0xe61b, 0xa438, 0x659e, 0xa438, 0x10e4, 0xa438, 0x8fe5, + 0xa438, 0xe58f, 0xa438, 0xe6e2, 0xa438, 0x83c9, 0xa438, 0xf636, + 0xa438, 0xe683, 0xa438, 0xc9ae, 0xa438, 0x13e2, 0xa438, 0x83c9, + 0xa438, 0xf736, 0xa438, 0xe683, 0xa438, 0xc902, 0xa438, 0x5820, + 0xa438, 0xef57, 0xa438, 0xe68f, 0xa438, 0xe7e7, 0xa438, 0x8fe8, + 0xa438, 0xffef, 0xa438, 0x97ff, 0xa438, 0xfefd, 0xa438, 0xfc04, + 0xa438, 0xf8f9, 0xa438, 0xfafb, 0xa438, 0xef79, 0xa438, 0xfbe2, + 0xa438, 0x8fe7, 0xa438, 0xe38f, 0xa438, 0xe8ef, 0xa438, 0x65e2, + 0xa438, 0x81b8, 0xa438, 0xe381, 0xa438, 0xb9ef, 0xa438, 0x7502, + 0xa438, 0x583b, 0xa438, 0xac50, 0xa438, 0x1abf, 0xa438, 0x5718, + 0xa438, 0x0252, 0xa438, 0xc8ef, 0xa438, 0x64e2, 0xa438, 0x8fe5, + 0xa438, 0xe38f, 0xa438, 0xe61b, 0xa438, 0x659e, 0xa438, 0x1ce4, + 0xa438, 0x8fe5, 0xa438, 0xe58f, 0xa438, 0xe6ae, 0xa438, 0x0cbf, + 0xa438, 0x5715, 0xa438, 0x0258, 0xa438, 0xb1bf, 0xa438, 0x5715, + 0xa438, 0x0258, 0xa438, 0xa8e2, 0xa438, 0x83c9, 0xa438, 0xf636, + 0xa438, 0xe683, 0xa438, 0xc9ff, 0xa438, 0xef97, 0xa438, 0xfffe, + 0xa438, 0xfdfc, 0xa438, 0x04f8, 0xa438, 0xf9fa, 0xa438, 0xef69, + 0xa438, 0xe080, 0xa438, 0x15ad, 0xa438, 0x264b, 0xa438, 0xbf53, + 0xa438, 0xca02, 0xa438, 0x52c8, 0xa438, 0xad28, 0xa438, 0x42bf, + 0xa438, 0x8931, 0xa438, 0x0252, 0xa438, 0xc8ef, 0xa438, 0x54bf, + 0xa438, 0x576c, 0xa438, 0x0252, 0xa438, 0xc8a1, 0xa438, 0x001b, + 0xa438, 0xbf53, 0xa438, 0x4c02, 0xa438, 0x52c8, 0xa438, 0xac29, + 0xa438, 0x0dac, 0xa438, 0x2805, 0xa438, 0xa302, 0xa438, 0x16ae, + 0xa438, 0x20a3, 0xa438, 0x0311, 0xa438, 0xae1b, 0xa438, 0xa304, + 0xa438, 0x0cae, 0xa438, 0x16a3, 0xa438, 0x0802, 0xa438, 0xae11, + 0xa438, 0xa309, 0xa438, 0x02ae, 0xa438, 0x0cbf, 0xa438, 0x5715, + 0xa438, 0x0258, 0xa438, 0xb1bf, 0xa438, 0x5715, 0xa438, 0x0258, + 0xa438, 0xa8ef, 0xa438, 0x96fe, 0xa438, 0xfdfc, 0xa438, 0x04f0, + 0xa438, 0xa300, 0xa438, 0xf0a3, 0xa438, 0x02f0, 0xa438, 0xa304, + 0xa438, 0xf0a3, 0xa438, 0x06f0, 0xa438, 0xa308, 0xa438, 0xf0a2, + 0xa438, 0x8074, 0xa438, 0xa600, 0xa438, 0xac4f, 0xa438, 0x02ae, + 0xa438, 0x0bef, 0xa438, 0x46f6, 0xa438, 0x273c, 0xa438, 0x1000, + 0xa438, 0xab1b, 0xa438, 0xae16, 0xa438, 0xe081, 0xa438, 0xabe1, + 0xa438, 0x81ac, 0xa438, 0x1b46, 0xa438, 0xab0c, 0xa438, 0xac32, + 0xa438, 0x04ef, 0xa438, 0x32ae, 0xa438, 0x02d3, 0xa438, 0x04af, + 0xa438, 0x486c, 0xa438, 0xaf48, 0xa438, 0x82af, 0xa438, 0x4888, + 0xa438, 0xe081, 0xa438, 0x9be1, 0xa438, 0x819c, 0xa438, 0xe28f, + 0xa438, 0xe3ad, 0xa438, 0x3009, 0xa438, 0x1f55, 0xa438, 0xe38f, + 0xa438, 0xe20c, 0xa438, 0x581a, 0xa438, 0x45e4, 0xa438, 0x83a6, + 0xa438, 0xe583, 0xa438, 0xa7af, 0xa438, 0x2a75, 0xa438, 0xe08f, + 0xa438, 0xe3ad, 0xa438, 0x201c, 0xa438, 0x1f44, 0xa438, 0xe18f, + 0xa438, 0xe10c, 0xa438, 0x44ef, 0xa438, 0x64e0, 0xa438, 0x8232, + 0xa438, 0xe182, 0xa438, 0x331b, 0xa438, 0x649f, 0xa438, 0x091f, + 0xa438, 0x44e1, 0xa438, 0x8fe2, 0xa438, 0x0c48, 0xa438, 0x1b54, + 0xa438, 0xe683, 0xa438, 0xa6e7, 0xa438, 0x83a7, 0xa438, 0xaf2b, + 0xa438, 0xd900, 0xa436, 0xb818, 0xa438, 0x043d, 0xa436, 0xb81a, + 0xa438, 0x06a3, 0xa436, 0xb81c, 0xa438, 0x476d, 0xa436, 0xb81e, + 0xa438, 0x4852, 0xa436, 0xb850, 0xa438, 0x2A69, 0xa436, 0xb852, + 0xa438, 0x2BD3, 0xa436, 0xb878, 0xa438, 0xffff, 0xa436, 0xb884, + 0xa438, 0xffff, 0xa436, 0xb832, 0xa438, 0x003f, 0xb844, 0xffff, + 0xa436, 0x8fe9, 0xa438, 0x0000, 0xa436, 0x8feb, 0xa438, 0x02fe, + 0xa436, 0x8fed, 0xa438, 0x0019, 0xa436, 0x8fef, 0xa438, 0x0bdb, + 0xa436, 0x8ff1, 0xa438, 0x0ca4, 0xa436, 0x0000, 0xa438, 0x0000, + 0xa436, 0xB82E, 0xa438, 0x0000, 0xa436, 0x8024, 0xa438, 0x0000, + 0xa436, 0x801E, 0xa438, 0x0024, 0xb820, 0x0000, 0xFFFF, 0xFFFF +}; + +static void +rtl_real_set_phy_mcu_8125b_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8125b_1, + ARRAY_SIZE(phy_mcu_ram_code_8125b_1)); +} + +void +rtl_set_phy_mcu_8125b_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8125b_1(hw); + + rtl_clear_phy_mcu_patch_request(hw); +} + +static void +rtl_real_set_phy_mcu_8125b_2(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8125b_2, + ARRAY_SIZE(phy_mcu_ram_code_8125b_2)); +} + +void +rtl_set_phy_mcu_8125b_2(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8125b_2(hw); + + rtl_clear_phy_mcu_patch_request(hw); +} + diff --git a/drivers/net/r8169/base/rtl8125b_mcu.h b/drivers/net/r8169/base/rtl8125b_mcu.h new file mode 100644 index 0000000000..c6744b9b7f --- /dev/null +++ b/drivers/net/r8169/base/rtl8125b_mcu.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _RTL8125B_MCU_H_ +#define _RTL8125B_MCU_H_ + +void rtl_set_mac_mcu_8125b_1(struct rtl_hw *hw); +void rtl_set_mac_mcu_8125b_2(struct rtl_hw *hw); + +void rtl_set_phy_mcu_8125b_1(struct rtl_hw *hw); +void rtl_set_phy_mcu_8125b_2(struct rtl_hw *hw); + +#endif + diff --git a/drivers/net/r8169/base/rtl8125bp.c b/drivers/net/r8169/base/rtl8125bp.c new file mode 100644 index 0000000000..fd69746904 --- /dev/null +++ b/drivers/net/r8169/base/rtl8125bp.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include "../r8169_ethdev.h" +#include "../r8169_hw.h" +#include "../r8169_phy.h" +#include "rtl8125bp_mcu.h" + +/* For RTL8125BP, CFG_METHOD_54,55 */ + +static void +hw_init_rxcfg_8125bp(struct rtl_hw *hw) +{ + RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | Rx_Close_Multiple | + RxCfg_pause_slot_en | (RX_DMA_BURST_256 << RxCfgDMAShift)); +} + +static void +hw_ephy_config_8125bp(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_54: + case CFG_METHOD_55: + /* Nothing to do */ + break; + } +} + +static void +rtl_hw_phy_config_8125bp_1(struct rtl_hw *hw) +{ + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA80C, BIT_14, + (BIT_15 | BIT_11 | BIT_10)); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8010); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_11); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8088); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9000); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x808F); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9000); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8174); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13, (BIT_12 | BIT_11)); +} + +static void +rtl_hw_phy_config_8125bp_2(struct rtl_hw *hw) +{ + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8010); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_11); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8088); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9000); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x808F); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9000); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8174); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13, (BIT_12 | BIT_11)); +} + +static void +hw_phy_config_8125bp(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_54: + rtl_hw_phy_config_8125bp_1(hw); + break; + case CFG_METHOD_55: + rtl_hw_phy_config_8125bp_2(hw); + break; + } +} + +static void +hw_mac_mcu_config_8125bp(struct rtl_hw *hw) +{ + if (hw->NotWrMcuPatchCode == TRUE) + return; + + switch (hw->mcfg) { + case CFG_METHOD_54: + rtl_set_mac_mcu_8125bp_1(hw); + break; + case CFG_METHOD_55: + rtl_set_mac_mcu_8125bp_2(hw); + break; + } +} + +static void +hw_phy_mcu_config_8125bp(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_54: + rtl_set_phy_mcu_8125bp_1(hw); + break; + case CFG_METHOD_55: + /* Nothing to do */ + break; + } +} + +const struct rtl_hw_ops rtl8125bp_ops = { + .hw_init_rxcfg = hw_init_rxcfg_8125bp, + .hw_ephy_config = hw_ephy_config_8125bp, + .hw_phy_config = hw_phy_config_8125bp, + .hw_mac_mcu_config = hw_mac_mcu_config_8125bp, + .hw_phy_mcu_config = hw_phy_mcu_config_8125bp, +}; + diff --git a/drivers/net/r8169/base/rtl8125bp_mcu.c b/drivers/net/r8169/base/rtl8125bp_mcu.c new file mode 100644 index 0000000000..45f21a86c2 --- /dev/null +++ b/drivers/net/r8169/base/rtl8125bp_mcu.c @@ -0,0 +1,289 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include "../r8169_ethdev.h" +#include "../r8169_hw.h" +#include "../r8169_phy.h" +#include "rtl8125bp_mcu.h" + +/* For RTL8125BP, CFG_METHOD_54,55 */ + +/* ------------------------------------MAC 8125BP------------------------------------- */ + +void +rtl_set_mac_mcu_8125bp_1(struct rtl_hw *hw) +{ + static const u16 mcu_patch_code_8125bp_1[] = { + 0xE003, 0xE007, 0xE01A, 0x1BC8, 0x46EB, 0xC302, 0xBB00, 0x0F14, 0xC211, + 0x400A, 0xF00A, 0xC20F, 0x400A, 0xF007, 0x73A4, 0xC20C, 0x400A, 0xF102, + 0x48B0, 0x9B20, 0x1B00, 0x9BA0, 0xC602, 0xBE00, 0x4364, 0xE6E0, 0xE6E2, + 0xC01C, 0xB406, 0x1000, 0xF016, 0xC61F, 0x400E, 0xF012, 0x218E, 0x25BE, + 0x1300, 0xF007, 0x7340, 0xC618, 0x400E, 0xF102, 0x48B0, 0x8320, 0xB400, + 0x2402, 0x1000, 0xF003, 0x7342, 0x8322, 0xB000, 0xE007, 0x7322, 0x9B42, + 0x7320, 0x9B40, 0x0300, 0x0300, 0xB006, 0xC302, 0xBB00, 0x413E, 0xE6E0, + 0xC01C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x1171, 0x0B17, 0x0816, 0x1108 + }; + + rtl_hw_disable_mac_mcu_bps(hw); + + rtl_write_mac_mcu_ram_code(hw, mcu_patch_code_8125bp_1, + ARRAY_SIZE(mcu_patch_code_8125bp_1)); + + rtl_mac_ocp_write(hw, 0xFC26, 0x8000); + + rtl_mac_ocp_write(hw, 0xFC28, 0x0f10); + rtl_mac_ocp_write(hw, 0xFC2A, 0x435c); + rtl_mac_ocp_write(hw, 0xFC2C, 0x4112); + + rtl_mac_ocp_write(hw, 0xFC48, 0x0007); +} + +void +rtl_set_mac_mcu_8125bp_2(struct rtl_hw *hw) +{ + static const u16 mcu_patch_code_8125bp_2[] = { + 0xE010, 0xE033, 0xE046, 0xE04A, 0xE04C, 0xE04E, 0xE050, 0xE052, 0xE054, + 0xE056, 0xE058, 0xE05A, 0xE05C, 0xE05E, 0xE060, 0xE062, 0xB406, 0x1000, + 0xF016, 0xC61F, 0x400E, 0xF012, 0x218E, 0x25BE, 0x1300, 0xF007, 0x7340, + 0xC618, 0x400E, 0xF102, 0x48B0, 0x8320, 0xB400, 0x2402, 0x1000, 0xF003, + 0x7342, 0x8322, 0xB000, 0xE007, 0x7322, 0x9B42, 0x7320, 0x9B40, 0x0300, + 0x0300, 0xB006, 0xC302, 0xBB00, 0x4168, 0xE6E0, 0xC01C, 0xC211, 0x400A, + 0xF00A, 0xC20F, 0x400A, 0xF007, 0x73A4, 0xC20C, 0x400A, 0xF102, 0x48B0, + 0x9B20, 0x1B00, 0x9BA0, 0xC602, 0xBE00, 0x4392, 0xE6E0, 0xE6E2, 0xC01C, + 0x4166, 0x9CF6, 0xC002, 0xB800, 0x143C, 0xC602, 0xBE00, 0x0000, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC102, + 0xB900, 0x0000, 0xC002, 0xB800, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1171, + 0x0B18, 0x030D, 0x0A2A + }; + rtl_hw_disable_mac_mcu_bps(hw); + rtl_write_mac_mcu_ram_code(hw, mcu_patch_code_8125bp_2, + ARRAY_SIZE(mcu_patch_code_8125bp_2)); + rtl_mac_ocp_write(hw, 0xFC26, 0x8000); + rtl_mac_ocp_write(hw, 0xFC28, 0x413C); + rtl_mac_ocp_write(hw, 0xFC2A, 0x438A); + rtl_mac_ocp_write(hw, 0xFC2C, 0x143A); + rtl_mac_ocp_write(hw, 0xFC48, 0x0007); +} + +/* ------------------------------------PHY 8125BP--------------------------------------- */ + +static const u16 phy_mcu_ram_code_8125bp_1_1[] = { + 0xa436, 0x8024, 0xa438, 0x3600, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x8014, 0xa438, 0x1800, 0xa438, 0x8018, + 0xa438, 0x1800, 0xa438, 0x801c, 0xa438, 0x1800, 0xa438, 0x8020, + 0xa438, 0x1800, 0xa438, 0x8024, 0xa438, 0x1800, 0xa438, 0x8028, + 0xa438, 0x1800, 0xa438, 0x8028, 0xa438, 0xdb20, 0xa438, 0xd501, + 0xa438, 0x1800, 0xa438, 0x034c, 0xa438, 0xdb10, 0xa438, 0xd501, + 0xa438, 0x1800, 0xa438, 0x032c, 0xa438, 0x8620, 0xa438, 0xa480, + 0xa438, 0x1800, 0xa438, 0x1cfe, 0xa438, 0xbf40, 0xa438, 0xd703, + 0xa438, 0x1800, 0xa438, 0x0ce9, 0xa438, 0x9c10, 0xa438, 0x9f40, + 0xa438, 0x1800, 0xa438, 0x137a, 0xa438, 0x9f20, 0xa438, 0x9f40, + 0xa438, 0x1800, 0xa438, 0x16c4, 0xa436, 0xA026, 0xa438, 0xffff, + 0xa436, 0xA024, 0xa438, 0xffff, 0xa436, 0xA022, 0xa438, 0x16c3, + 0xa436, 0xA020, 0xa438, 0x1379, 0xa436, 0xA006, 0xa438, 0x0ce8, + 0xa436, 0xA004, 0xa438, 0x1cfd, 0xa436, 0xA002, 0xa438, 0x032b, + 0xa436, 0xA000, 0xa438, 0x034b, 0xa436, 0xA008, 0xa438, 0x3f00, + 0xa436, 0xA016, 0xa438, 0x0020, 0xa436, 0xA012, 0xa438, 0x0000, + 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, 0xa438, 0x1800, + 0xa438, 0x8018, 0xa438, 0x1800, 0xa438, 0x8021, 0xa438, 0x1800, + 0xa438, 0x802b, 0xa438, 0x1800, 0xa438, 0x8055, 0xa438, 0x1800, + 0xa438, 0x805a, 0xa438, 0x1800, 0xa438, 0x805e, 0xa438, 0x1800, + 0xa438, 0x8062, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0xcb11, + 0xa438, 0xd1b9, 0xa438, 0xd05b, 0xa438, 0x0000, 0xa438, 0x1800, + 0xa438, 0x0284, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0xd700, + 0xa438, 0x5fb4, 0xa438, 0x5f95, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x1800, 0xa438, 0x02b7, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0xcb21, 0xa438, 0x1000, 0xa438, 0x0b34, 0xa438, 0xd71f, + 0xa438, 0x5f5e, 0xa438, 0x0000, 0xa438, 0x1800, 0xa438, 0x0322, + 0xa438, 0xd700, 0xa438, 0xd113, 0xa438, 0xd040, 0xa438, 0x1000, + 0xa438, 0x0a57, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xd700, + 0xa438, 0x6065, 0xa438, 0xd122, 0xa438, 0xf002, 0xa438, 0xd122, + 0xa438, 0xd040, 0xa438, 0x1000, 0xa438, 0x0b53, 0xa438, 0xa008, + 0xa438, 0xd704, 0xa438, 0x4052, 0xa438, 0xa002, 0xa438, 0xd704, + 0xa438, 0x4054, 0xa438, 0xa740, 0xa438, 0x1000, 0xa438, 0x0a57, + 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xcb9b, 0xa438, 0xd110, + 0xa438, 0xd040, 0xa438, 0x1000, 0xa438, 0x0c01, 0xa438, 0x1000, + 0xa438, 0x0a57, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0x801a, + 0xa438, 0x1000, 0xa438, 0x0a57, 0xa438, 0xd704, 0xa438, 0x7fb9, + 0xa438, 0x1800, 0xa438, 0x088d, 0xa438, 0xcb62, 0xa438, 0xd700, + 0xa438, 0x8880, 0xa438, 0x1800, 0xa438, 0x06cb, 0xa438, 0xbe02, + 0xa438, 0x0000, 0xa438, 0x1800, 0xa438, 0x002c, 0xa438, 0xbe04, + 0xa438, 0x0000, 0xa438, 0x1800, 0xa438, 0x002c, 0xa438, 0xbe08, + 0xa438, 0x0000, 0xa438, 0x1800, 0xa438, 0x002c, 0xa436, 0xA10E, + 0xa438, 0x802a, 0xa436, 0xA10C, 0xa438, 0x8026, 0xa436, 0xA10A, + 0xa438, 0x8022, 0xa436, 0xA108, 0xa438, 0x06ca, 0xa436, 0xA106, + 0xa438, 0x086f, 0xa436, 0xA104, 0xa438, 0x0321, 0xa436, 0xA102, + 0xa438, 0x02b5, 0xa436, 0xA100, 0xa438, 0x0283, 0xa436, 0xA110, + 0xa438, 0x001f, 0xb820, 0x0010, 0xb82e, 0x0000, 0xa436, 0x8024, + 0xa438, 0x0000, 0xB820, 0x0000, 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8125bp_1_2[] = { + 0xb892, 0x0000, 0xb88e, 0xC201, 0xb890, 0x2C01, 0xb890, 0xCD02, + 0xb890, 0x0602, 0xb890, 0x5502, 0xb890, 0xB903, 0xb890, 0x3303, + 0xb890, 0xC204, 0xb890, 0x6605, 0xb890, 0x1F05, 0xb890, 0xEE06, + 0xb890, 0xD207, 0xb890, 0xCC08, 0xb890, 0xDA09, 0xb890, 0xFF0B, + 0xb890, 0x380C, 0xb890, 0x87F3, 0xb88e, 0xC27F, 0xb890, 0x2B66, + 0xb890, 0x6666, 0xb890, 0x6666, 0xb890, 0x6666, 0xb890, 0x6666, + 0xb890, 0x6666, 0xb890, 0x6666, 0xb890, 0x6666, 0xb890, 0x66C2, + 0xb88e, 0xC26F, 0xb890, 0x751D, 0xb890, 0x1D1F, 0xb890, 0x2022, + 0xb890, 0x2325, 0xb890, 0x2627, 0xb890, 0x2829, 0xb890, 0x2929, + 0xb890, 0x2A2A, 0xb890, 0x2B66, 0xB820, 0x0000, 0xFFFF, 0xFFFF +}; + +static void +rtl_real_set_phy_mcu_8125bp_1_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8125bp_1_1, + ARRAY_SIZE(phy_mcu_ram_code_8125bp_1_1)); +} + +static void +rtl_real_set_phy_mcu_8125bp_1_2(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8125bp_1_2, + ARRAY_SIZE(phy_mcu_ram_code_8125bp_1_2)); +} + +void +rtl_set_phy_mcu_8125bp_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8125bp_1_1(hw); + + rtl_clear_phy_mcu_patch_request(hw); + + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8125bp_1_2(hw); + + rtl_clear_phy_mcu_patch_request(hw); +} + diff --git a/drivers/net/r8169/base/rtl8125bp_mcu.h b/drivers/net/r8169/base/rtl8125bp_mcu.h new file mode 100644 index 0000000000..8dc5f01958 --- /dev/null +++ b/drivers/net/r8169/base/rtl8125bp_mcu.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _RTL8125BP_MCU_H_ +#define _RTL8125BP_MCU_H_ + +void rtl_set_mac_mcu_8125bp_1(struct rtl_hw *hw); +void rtl_set_mac_mcu_8125bp_2(struct rtl_hw *hw); + +void rtl_set_phy_mcu_8125bp_1(struct rtl_hw *hw); + +#endif + diff --git a/drivers/net/r8169/base/rtl8125d.c b/drivers/net/r8169/base/rtl8125d.c new file mode 100644 index 0000000000..1713b4831e --- /dev/null +++ b/drivers/net/r8169/base/rtl8125d.c @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include "../r8169_ethdev.h" +#include "../r8169_hw.h" +#include "../r8169_phy.h" +#include "rtl8125d_mcu.h" + +/* For RTL8125D, CFG_METHOD_56,57 */ + +static void +hw_init_rxcfg_8125d(struct rtl_hw *hw) +{ + RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | Rx_Close_Multiple | + RxCfg_pause_slot_en | (RX_DMA_BURST_256 << RxCfgDMAShift)); +} + +static void +hw_ephy_config_8125d(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_56: + case CFG_METHOD_57: + /* Nothing to do */ + break; + } +} + +static void +rtl_hw_phy_config_8125d_1(struct rtl_hw *hw) +{ + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); + + rtl_set_phy_mcu_patch_request(hw); + + rtl_set_eth_phy_ocp_bit(hw, 0xBF96, BIT_15); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF94, 0x0007, 0x0005); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF8E, 0x3C00, 0x2800); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000); + rtl_set_eth_phy_ocp_bit(hw, 0xBCD8, (BIT_15 | BIT_14)); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0004); + rtl_set_eth_phy_ocp_bit(hw, 0xBC82, (BIT_15 | BIT_14 | BIT_13)); + rtl_set_eth_phy_ocp_bit(hw, 0xBC82, (BIT_12 | BIT_11 | BIT_10)); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0005); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC82, 0x00E0, 0x0040); + rtl_set_eth_phy_ocp_bit(hw, 0xBC82, (BIT_4 | BIT_3 | BIT_2)); + rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, (BIT_15 | BIT_14)); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x8000); + rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, (BIT_15 | BIT_14)); + + rtl_clear_phy_mcu_patch_request(hw); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x832C); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB106, 0x0700, 0x0100); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB206, 0x0700, 0x0200); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB306, 0x0700, 0x0300); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80CB); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0300); + rtl_mdio_direct_write_phy_ocp(hw, 0xBCF4, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xBCF6, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xBC12, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x844d); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0200); + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) { + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8feb); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8fe9); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0600); + } + + rtl_clear_eth_phy_ocp_bit(hw, 0xAD40, (BIT_5 | BIT_4)); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD66, 0x000F, 0x0007); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0xF000, 0x8000); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0x0F00, 0x0500); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0x000F, 0x0002); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD6A, 0xF000, 0x7000); + rtl_mdio_direct_write_phy_ocp(hw, 0xAC50, 0x01E8); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81FA); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5400); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA864, 0x00F0, 0x00C0); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA42C, 0x00FF, 0x0002); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E1); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0F00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DE); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xF000, 0x0700); + rtl_set_eth_phy_ocp_bit(hw, 0xA846, BIT_7); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BA); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8A04); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BD); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xCA00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B7); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xB300); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CE); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8A04); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D1); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xCA00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CB); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xBB00); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4909); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x05B8); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8200); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5800); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7078); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF3); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5D78); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7862); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF7); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1400); + + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) { + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x814C); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8455); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x814E); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x84A6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8163); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0600); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x816A); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0500); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8171); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1f00); + } + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC3A, 0x000F, 0x0006); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8064); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8067); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x806A); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x806D); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8070); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8073); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8076); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8079); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x807C); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x807F); + rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8)); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBFA0, 0xFF70, 0x5500); + rtl_mdio_direct_write_phy_ocp(hw, 0xBFA2, 0x9D00); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8165); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x0700, 0x0200); + + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) { + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8019); + rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FE3); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0005); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ED); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0502); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0B00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xD401); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2900); + } + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1700); + + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) { + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x815B); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1700); + } + + rtl_set_eth_phy_ocp_bit(hw, 0xA430, BIT_12 | BIT_0); + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_7); +} + +static void +rtl_hw_phy_config_8125d_2(struct rtl_hw *hw) +{ + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); +} + +static void +hw_phy_config_8125d(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_56: + rtl_hw_phy_config_8125d_1(hw); + break; + case CFG_METHOD_57: + rtl_hw_phy_config_8125d_2(hw); + break; + } +} + +static void +hw_mac_mcu_config_8125d(struct rtl_hw *hw) +{ + if (hw->NotWrMcuPatchCode == TRUE) + return; + + switch (hw->mcfg) { + case CFG_METHOD_56: + rtl_set_mac_mcu_8125d_1(hw); + break; + case CFG_METHOD_57: + rtl_set_mac_mcu_8125d_2(hw); + break; + } +} + +static void +hw_phy_mcu_config_8125d(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_56: + rtl_set_phy_mcu_8125d_1(hw); + break; + case CFG_METHOD_57: + /* Nothing to do */ + break; + } +} + +const struct rtl_hw_ops rtl8125d_ops = { + .hw_init_rxcfg = hw_init_rxcfg_8125d, + .hw_ephy_config = hw_ephy_config_8125d, + .hw_phy_config = hw_phy_config_8125d, + .hw_mac_mcu_config = hw_mac_mcu_config_8125d, + .hw_phy_mcu_config = hw_phy_mcu_config_8125d, +}; + diff --git a/drivers/net/r8169/base/rtl8125d_mcu.c b/drivers/net/r8169/base/rtl8125d_mcu.c new file mode 100644 index 0000000000..23652bf40a --- /dev/null +++ b/drivers/net/r8169/base/rtl8125d_mcu.c @@ -0,0 +1,618 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include "../r8169_ethdev.h" +#include "../r8169_hw.h" +#include "../r8169_phy.h" +#include "rtl8125d_mcu.h" + +/* For RTL8125D, CFG_METHOD_56,57 */ + +/* ------------------------------------MAC 8125D------------------------------------- */ + +void +rtl_set_mac_mcu_8125d_1(struct rtl_hw *hw) +{ + static const u16 mcu_patch_code_8125d_1[] = { + 0xE002, 0xE006, 0x4166, 0x9CF6, 0xC002, 0xB800, 0x14A4, 0xC102, 0xB900, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6938, + 0x0A18, 0x0217, 0x0D2A + }; + rtl_hw_disable_mac_mcu_bps(hw); + rtl_write_mac_mcu_ram_code(hw, mcu_patch_code_8125d_1, + ARRAY_SIZE(mcu_patch_code_8125d_1)); + rtl_mac_ocp_write(hw, 0xFC26, 0x8000); + rtl_mac_ocp_write(hw, 0xFC28, 0x14A2); + rtl_mac_ocp_write(hw, 0xFC48, 0x0001); +} + +void +rtl_set_mac_mcu_8125d_2(struct rtl_hw *hw) +{ + rtl_hw_disable_mac_mcu_bps(hw); +} + +/* ------------------------------------PHY 8125D--------------------------------------- */ + +static const u16 phy_mcu_ram_code_8125d_1_1[] = { + 0xa436, 0x8023, 0xa438, 0x3800, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x8018, 0xa438, 0x1800, 0xa438, 0x8021, + 0xa438, 0x1800, 0xa438, 0x8029, 0xa438, 0x1800, 0xa438, 0x8031, + 0xa438, 0x1800, 0xa438, 0x8035, 0xa438, 0x1800, 0xa438, 0x8035, + 0xa438, 0x1800, 0xa438, 0x8035, 0xa438, 0xd711, 0xa438, 0x6081, + 0xa438, 0x8904, 0xa438, 0x1800, 0xa438, 0x2021, 0xa438, 0xa904, + 0xa438, 0x1800, 0xa438, 0x2021, 0xa438, 0xd75f, 0xa438, 0x4083, + 0xa438, 0xd503, 0xa438, 0xa908, 0xa438, 0x87f0, 0xa438, 0x1000, + 0xa438, 0x17e0, 0xa438, 0x1800, 0xa438, 0x13c3, 0xa438, 0xd707, + 0xa438, 0x2005, 0xa438, 0x8027, 0xa438, 0xd75e, 0xa438, 0x1800, + 0xa438, 0x1434, 0xa438, 0x1800, 0xa438, 0x14a5, 0xa438, 0xc504, + 0xa438, 0xce20, 0xa438, 0xcf01, 0xa438, 0xd70a, 0xa438, 0x4005, + 0xa438, 0xcf02, 0xa438, 0x1800, 0xa438, 0x1c50, 0xa438, 0xa980, + 0xa438, 0xd500, 0xa438, 0x1800, 0xa438, 0x14f3, 0xa436, 0xA026, + 0xa438, 0xffff, 0xa436, 0xA024, 0xa438, 0xffff, 0xa436, 0xA022, + 0xa438, 0xffff, 0xa436, 0xA020, 0xa438, 0x14f2, 0xa436, 0xA006, + 0xa438, 0x1c4f, 0xa436, 0xA004, 0xa438, 0x1433, 0xa436, 0xA002, + 0xa438, 0x13c1, 0xa436, 0xA000, 0xa438, 0x2020, 0xa436, 0xA008, + 0xa438, 0x1f00, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x07f8, 0xa436, 0xA014, 0xa438, 0xd04d, 0xa438, 0x8904, + 0xa438, 0x813C, 0xa438, 0xA13D, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa436, 0xA152, 0xa438, 0x1384, + 0xa436, 0xA154, 0xa438, 0x1fa8, 0xa436, 0xA156, 0xa438, 0x218B, + 0xa436, 0xA158, 0xa438, 0x21B8, 0xa436, 0xA15A, 0xa438, 0x3fff, + 0xa436, 0xA15C, 0xa438, 0x3fff, 0xa436, 0xA15E, 0xa438, 0x3fff, + 0xa436, 0xA160, 0xa438, 0x3fff, 0xa436, 0xA150, 0xa438, 0x000f, + 0xa436, 0xA016, 0xa438, 0x0020, 0xa436, 0xA012, 0xa438, 0x1ff8, + 0xa436, 0xA014, 0xa438, 0x001c, 0xa438, 0xce15, 0xa438, 0xd105, + 0xa438, 0xa410, 0xa438, 0x8320, 0xa438, 0xFFD7, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa436, 0xA164, 0xa438, 0x0260, 0xa436, 0xA166, + 0xa438, 0x0add, 0xa436, 0xA168, 0xa438, 0x05CC, 0xa436, 0xA16A, + 0xa438, 0x05C5, 0xa436, 0xA16C, 0xa438, 0x0429, 0xa436, 0xA16E, + 0xa438, 0x07B6, 0xa436, 0xA170, 0xa438, 0x0259, 0xa436, 0xA172, + 0xa438, 0x3fff, 0xa436, 0xA162, 0xa438, 0x003f, 0xa436, 0xA016, + 0xa438, 0x0020, 0xa436, 0xA012, 0xa438, 0x0000, 0xa436, 0xA014, + 0xa438, 0x1800, 0xa438, 0x8010, 0xa438, 0x1800, 0xa438, 0x8023, + 0xa438, 0x1800, 0xa438, 0x80e6, 0xa438, 0x1800, 0xa438, 0x80f0, + 0xa438, 0x1800, 0xa438, 0x80f8, 0xa438, 0x1800, 0xa438, 0x816c, + 0xa438, 0x1800, 0xa438, 0x817d, 0xa438, 0x1800, 0xa438, 0x818b, + 0xa438, 0xa801, 0xa438, 0x9308, 0xa438, 0xb201, 0xa438, 0xb301, + 0xa438, 0xd701, 0xa438, 0x4000, 0xa438, 0xd2ff, 0xa438, 0xb302, + 0xa438, 0xd200, 0xa438, 0xb201, 0xa438, 0xb309, 0xa438, 0xd701, + 0xa438, 0x4000, 0xa438, 0xd2ff, 0xa438, 0xb302, 0xa438, 0xd200, + 0xa438, 0xa800, 0xa438, 0x1800, 0xa438, 0x0031, 0xa438, 0xd700, + 0xa438, 0x4543, 0xa438, 0xd71f, 0xa438, 0x40fe, 0xa438, 0xd1b7, + 0xa438, 0xd049, 0xa438, 0x1000, 0xa438, 0x109e, 0xa438, 0xd700, + 0xa438, 0x5fbb, 0xa438, 0xa220, 0xa438, 0x8501, 0xa438, 0x0c03, + 0xa438, 0x1502, 0xa438, 0x0c70, 0xa438, 0x0b00, 0xa438, 0x0c07, + 0xa438, 0x0604, 0xa438, 0x9503, 0xa438, 0xa510, 0xa438, 0xce49, + 0xa438, 0x1000, 0xa438, 0x10be, 0xa438, 0x8520, 0xa438, 0xa520, + 0xa438, 0xa501, 0xa438, 0xd105, 0xa438, 0xd047, 0xa438, 0x1000, + 0xa438, 0x109e, 0xa438, 0xd707, 0xa438, 0x6087, 0xa438, 0xd700, + 0xa438, 0x5f7b, 0xa438, 0xffe9, 0xa438, 0x1000, 0xa438, 0x109e, + 0xa438, 0x8501, 0xa438, 0xd707, 0xa438, 0x5e08, 0xa438, 0x8530, + 0xa438, 0xba20, 0xa438, 0xf00c, 0xa438, 0xd700, 0xa438, 0x4098, + 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0xa438, 0xbf64, 0xa438, 0xf102, + 0xa438, 0x6b9d, 0xa438, 0xad28, 0xa438, 0x03af, 0xa438, 0x15fc, + 0xa438, 0xbf65, 0xa438, 0xcb02, 0xa438, 0x6b9d, 0xa438, 0x0d11, + 0xa438, 0xf62f, 0xa438, 0xef31, 0xa438, 0xd202, 0xa438, 0xbf88, + 0xa438, 0x6402, 0xa438, 0x6b52, 0xa438, 0xe082, 0xa438, 0x020d, + 0xa438, 0x01f6, 0xa438, 0x271b, 0xa438, 0x03aa, 0xa438, 0x0182, + 0xa438, 0xe082, 0xa438, 0x010d, 0xa438, 0x01f6, 0xa438, 0x271b, + 0xa438, 0x03aa, 0xa438, 0x0782, 0xa438, 0xbf88, 0xa438, 0x6402, + 0xa438, 0x6b5b, 0xa438, 0xaf15, 0xa438, 0xf9bf, 0xa438, 0x65cb, + 0xa438, 0x026b, 0xa438, 0x9d0d, 0xa438, 0x11f6, 0xa438, 0x2fef, + 0xa438, 0x31e0, 0xa438, 0x8ff7, 0xa438, 0x0d01, 0xa438, 0xf627, + 0xa438, 0x1b03, 0xa438, 0xaa20, 0xa438, 0xe18f, 0xa438, 0xf4d0, + 0xa438, 0x00bf, 0xa438, 0x6587, 0xa438, 0x026b, 0xa438, 0x7ee1, + 0xa438, 0x8ff5, 0xa438, 0xbf65, 0xa438, 0x8a02, 0xa438, 0x6b7e, + 0xa438, 0xe18f, 0xa438, 0xf6bf, 0xa438, 0x6584, 0xa438, 0x026b, + 0xa438, 0x7eaf, 0xa438, 0x15fc, 0xa438, 0xe18f, 0xa438, 0xf1d0, + 0xa438, 0x00bf, 0xa438, 0x6587, 0xa438, 0x026b, 0xa438, 0x7ee1, + 0xa438, 0x8ff2, 0xa438, 0xbf65, 0xa438, 0x8a02, 0xa438, 0x6b7e, + 0xa438, 0xe18f, 0xa438, 0xf3bf, 0xa438, 0x6584, 0xa438, 0xaf15, + 0xa438, 0xfcd1, 0xa438, 0x07bf, 0xa438, 0x65ce, 0xa438, 0x026b, + 0xa438, 0x7ed1, 0xa438, 0x0cbf, 0xa438, 0x65d1, 0xa438, 0x026b, + 0xa438, 0x7ed1, 0xa438, 0x03bf, 0xa438, 0x885e, 0xa438, 0x026b, + 0xa438, 0x7ed1, 0xa438, 0x05bf, 0xa438, 0x8867, 0xa438, 0x026b, + 0xa438, 0x7ed1, 0xa438, 0x07bf, 0xa438, 0x886a, 0xa438, 0x026b, + 0xa438, 0x7ebf, 0xa438, 0x6a6c, 0xa438, 0x026b, 0xa438, 0x5b02, + 0xa438, 0x62b5, 0xa438, 0xbf6a, 0xa438, 0x0002, 0xa438, 0x6b5b, + 0xa438, 0xbf64, 0xa438, 0x4e02, 0xa438, 0x6b9d, 0xa438, 0xac28, + 0xa438, 0x0bbf, 0xa438, 0x6412, 0xa438, 0x026b, 0xa438, 0x9da1, + 0xa438, 0x0502, 0xa438, 0xaeec, 0xa438, 0xd104, 0xa438, 0xbf65, + 0xa438, 0xce02, 0xa438, 0x6b7e, 0xa438, 0xd104, 0xa438, 0xbf65, + 0xa438, 0xd102, 0xa438, 0x6b7e, 0xa438, 0xd102, 0xa438, 0xbf88, + 0xa438, 0x6702, 0xa438, 0x6b7e, 0xa438, 0xd104, 0xa438, 0xbf88, + 0xa438, 0x6a02, 0xa438, 0x6b7e, 0xa438, 0xaf62, 0xa438, 0x72f6, + 0xa438, 0x0af6, 0xa438, 0x09af, 0xa438, 0x34e3, 0xa438, 0x0285, + 0xa438, 0xbe02, 0xa438, 0x106c, 0xa438, 0xaf10, 0xa438, 0x6bf8, + 0xa438, 0xfaef, 0xa438, 0x69e0, 0xa438, 0x804c, 0xa438, 0xac25, + 0xa438, 0x17e0, 0xa438, 0x8040, 0xa438, 0xad25, 0xa438, 0x1a02, + 0xa438, 0x85ed, 0xa438, 0xe080, 0xa438, 0x40ac, 0xa438, 0x2511, + 0xa438, 0xbf87, 0xa438, 0x6502, 0xa438, 0x6b5b, 0xa438, 0xae09, + 0xa438, 0x0287, 0xa438, 0x2402, 0xa438, 0x875a, 0xa438, 0x0287, + 0xa438, 0x4fef, 0xa438, 0x96fe, 0xa438, 0xfc04, 0xa438, 0xf8e0, + 0xa438, 0x8019, 0xa438, 0xad20, 0xa438, 0x11e0, 0xa438, 0x8fe3, + 0xa438, 0xac20, 0xa438, 0x0502, 0xa438, 0x860a, 0xa438, 0xae03, + 0xa438, 0x0286, 0xa438, 0x7802, 0xa438, 0x86c1, 0xa438, 0x0287, + 0xa438, 0x4ffc, 0xa438, 0x04f8, 0xa438, 0xf9ef, 0xa438, 0x79fb, + 0xa438, 0xbf87, 0xa438, 0x6802, 0xa438, 0x6b9d, 0xa438, 0x5c20, + 0xa438, 0x000d, 0xa438, 0x4da1, 0xa438, 0x0151, 0xa438, 0xbf87, + 0xa438, 0x6802, 0xa438, 0x6b9d, 0xa438, 0x5c07, 0xa438, 0xffe3, + 0xa438, 0x8fe4, 0xa438, 0x1b31, 0xa438, 0x9f41, 0xa438, 0x0d48, + 0xa438, 0xe38f, 0xa438, 0xe51b, 0xa438, 0x319f, 0xa438, 0x38bf, + 0xa438, 0x876b, 0xa438, 0x026b, 0xa438, 0x9d5c, 0xa438, 0x07ff, + 0xa438, 0xe38f, 0xa438, 0xe61b, 0xa438, 0x319f, 0xa438, 0x280d, + 0xa438, 0x48e3, 0xa438, 0x8fe7, 0xa438, 0x1b31, 0xa438, 0x9f1f, + 0xa438, 0xbf87, 0xa438, 0x6e02, 0xa438, 0x6b9d, 0xa438, 0x5c07, + 0xa438, 0xffe3, 0xa438, 0x8fe8, 0xa438, 0x1b31, 0xa438, 0x9f0f, + 0xa438, 0x0d48, 0xa438, 0xe38f, 0xa438, 0xe91b, 0xa438, 0x319f, + 0xa438, 0x06ee, 0xa438, 0x8fe3, 0xa438, 0x01ae, 0xa438, 0x04ee, + 0xa438, 0x8fe3, 0xa438, 0x00ff, 0xa438, 0xef97, 0xa438, 0xfdfc, + 0xa438, 0x04f8, 0xa438, 0xf9ef, 0xa438, 0x79fb, 0xa438, 0xbf87, + 0xa438, 0x6802, 0xa438, 0x6b9d, 0xa438, 0x5c20, 0xa438, 0x000d, + 0xa438, 0x4da1, 0xa438, 0x0020, 0xa438, 0xbf87, 0xa438, 0x6802, + 0xa438, 0x6b9d, 0xa438, 0x5c06, 0xa438, 0x000d, 0xa438, 0x49e3, + 0xa438, 0x8fea, 0xa438, 0x1b31, 0xa438, 0x9f0e, 0xa438, 0xbf87, + 0xa438, 0x7102, 0xa438, 0x6b5b, 0xa438, 0xbf87, 0xa438, 0x7702, + 0xa438, 0x6b5b, 0xa438, 0xae0c, 0xa438, 0xbf87, 0xa438, 0x7102, + 0xa438, 0x6b52, 0xa438, 0xbf87, 0xa438, 0x7702, 0xa438, 0x6b52, + 0xa438, 0xee8f, 0xa438, 0xe300, 0xa438, 0xffef, 0xa438, 0x97fd, + 0xa438, 0xfc04, 0xa438, 0xf8f9, 0xa438, 0xef79, 0xa438, 0xfbbf, + 0xa438, 0x8768, 0xa438, 0x026b, 0xa438, 0x9d5c, 0xa438, 0x2000, + 0xa438, 0x0d4d, 0xa438, 0xa101, 0xa438, 0x4abf, 0xa438, 0x8768, + 0xa438, 0x026b, 0xa438, 0x9d5c, 0xa438, 0x07ff, 0xa438, 0xe38f, + 0xa438, 0xeb1b, 0xa438, 0x319f, 0xa438, 0x3a0d, 0xa438, 0x48e3, + 0xa438, 0x8fec, 0xa438, 0x1b31, 0xa438, 0x9f31, 0xa438, 0xbf87, + 0xa438, 0x6b02, 0xa438, 0x6b9d, 0xa438, 0xe38f, 0xa438, 0xed1b, + 0xa438, 0x319f, 0xa438, 0x240d, 0xa438, 0x48e3, 0xa438, 0x8fee, + 0xa438, 0x1b31, 0xa438, 0x9f1b, 0xa438, 0xbf87, 0xa438, 0x6e02, + 0xa438, 0x6b9d, 0xa438, 0xe38f, 0xa438, 0xef1b, 0xa438, 0x319f, + 0xa438, 0x0ebf, 0xa438, 0x8774, 0xa438, 0x026b, 0xa438, 0x5bbf, + 0xa438, 0x877a, 0xa438, 0x026b, 0xa438, 0x5bae, 0xa438, 0x00ff, + 0xa438, 0xef97, 0xa438, 0xfdfc, 0xa438, 0x04f8, 0xa438, 0xef79, + 0xa438, 0xfbe0, 0xa438, 0x8019, 0xa438, 0xad20, 0xa438, 0x1cee, + 0xa438, 0x8fe3, 0xa438, 0x00bf, 0xa438, 0x8771, 0xa438, 0x026b, + 0xa438, 0x52bf, 0xa438, 0x8777, 0xa438, 0x026b, 0xa438, 0x52bf, + 0xa438, 0x8774, 0xa438, 0x026b, 0xa438, 0x52bf, 0xa438, 0x877a, + 0xa438, 0x026b, 0xa438, 0x52ff, 0xa438, 0xef97, 0xa438, 0xfc04, + 0xa438, 0xf8e0, 0xa438, 0x8040, 0xa438, 0xf625, 0xa438, 0xe480, + 0xa438, 0x40fc, 0xa438, 0x04f8, 0xa438, 0xe080, 0xa438, 0x4cf6, + 0xa438, 0x25e4, 0xa438, 0x804c, 0xa438, 0xfc04, 0xa438, 0x55a4, + 0xa438, 0xbaf0, 0xa438, 0xa64a, 0xa438, 0xf0a6, 0xa438, 0x4cf0, + 0xa438, 0xa64e, 0xa438, 0x66a4, 0xa438, 0xb655, 0xa438, 0xa4b6, + 0xa438, 0x00ac, 0xa438, 0x0e11, 0xa438, 0xac0e, 0xa438, 0xee80, + 0xa438, 0x4c3a, 0xa438, 0xaf07, 0xa438, 0xd0af, 0xa438, 0x26d0, + 0xa438, 0xa201, 0xa438, 0x0ebf, 0xa438, 0x663d, 0xa438, 0x026b, + 0xa438, 0x52bf, 0xa438, 0x6643, 0xa438, 0x026b, 0xa438, 0x52ae, + 0xa438, 0x11bf, 0xa438, 0x6643, 0xa438, 0x026b, 0xa438, 0x5bd4, + 0xa438, 0x0054, 0xa438, 0xb4fe, 0xa438, 0xbf66, 0xa438, 0x3d02, + 0xa438, 0x6b5b, 0xa438, 0xd300, 0xa438, 0x020d, 0xa438, 0xf6a2, + 0xa438, 0x0405, 0xa438, 0xe081, 0xa438, 0x47ae, 0xa438, 0x03e0, + 0xa438, 0x8148, 0xa438, 0xac23, 0xa438, 0x02ae, 0xa438, 0x0268, + 0xa438, 0xf01a, 0xa438, 0x10ad, 0xa438, 0x2f04, 0xa438, 0xd100, + 0xa438, 0xae05, 0xa438, 0xad2c, 0xa438, 0x02d1, 0xa438, 0x0f1f, + 0xa438, 0x00a2, 0xa438, 0x0407, 0xa438, 0x3908, 0xa438, 0xad2f, + 0xa438, 0x02d1, 0xa438, 0x0002, 0xa438, 0x0e1c, 0xa438, 0x2b01, + 0xa438, 0xad3a, 0xa438, 0xc9af, 0xa438, 0x0dee, 0xa438, 0xa000, + 0xa438, 0x2702, 0xa438, 0x1beb, 0xa438, 0xe18f, 0xa438, 0xe1ac, + 0xa438, 0x2819, 0xa438, 0xee8f, 0xa438, 0xe101, 0xa438, 0x1f44, + 0xa438, 0xbf65, 0xa438, 0x9302, 0xa438, 0x6b9d, 0xa438, 0xe58f, + 0xa438, 0xe21f, 0xa438, 0x44d1, 0xa438, 0x02bf, 0xa438, 0x6593, + 0xa438, 0x026b, 0xa438, 0x7ee0, 0xa438, 0x82b1, 0xa438, 0xae49, + 0xa438, 0xa001, 0xa438, 0x0502, 0xa438, 0x1c4d, 0xa438, 0xae41, + 0xa438, 0xa002, 0xa438, 0x0502, 0xa438, 0x1c90, 0xa438, 0xae39, + 0xa438, 0xa003, 0xa438, 0x0502, 0xa438, 0x1c9d, 0xa438, 0xae31, + 0xa438, 0xa004, 0xa438, 0x0502, 0xa438, 0x1cbc, 0xa438, 0xae29, + 0xa438, 0xa005, 0xa438, 0x1e02, 0xa438, 0x1cc9, 0xa438, 0xe080, + 0xa438, 0xdfac, 0xa438, 0x2013, 0xa438, 0xac21, 0xa438, 0x10ac, + 0xa438, 0x220d, 0xa438, 0xe18f, 0xa438, 0xe2bf, 0xa438, 0x6593, + 0xa438, 0x026b, 0xa438, 0x7eee, 0xa438, 0x8fe1, 0xa438, 0x00ae, + 0xa438, 0x08a0, 0xa438, 0x0605, 0xa438, 0x021d, 0xa438, 0x07ae, + 0xa438, 0x00e0, 0xa438, 0x82b1, 0xa438, 0xaf1b, 0xa438, 0xe910, + 0xa438, 0xbf4a, 0xa438, 0x99bf, 0xa438, 0x4a00, 0xa438, 0xa86a, + 0xa438, 0xfdad, 0xa438, 0x5eca, 0xa438, 0xad5e, 0xa438, 0x88bd, + 0xa438, 0x2c99, 0xa438, 0xbd2c, 0xa438, 0x33bd, 0xa438, 0x3222, + 0xa438, 0xbd32, 0xa438, 0x11bd, 0xa438, 0x3200, 0xa438, 0xbd32, + 0xa438, 0x77bd, 0xa438, 0x3266, 0xa438, 0xbd32, 0xa438, 0x55bd, + 0xa438, 0x3244, 0xa438, 0xbd32, 0xa436, 0xb818, 0xa438, 0x15c5, + 0xa436, 0xb81a, 0xa438, 0x6255, 0xa436, 0xb81c, 0xa438, 0x34e1, + 0xa436, 0xb81e, 0xa438, 0x1068, 0xa436, 0xb850, 0xa438, 0x07cc, + 0xa436, 0xb852, 0xa438, 0x26ca, 0xa436, 0xb878, 0xa438, 0x0dbf, + 0xa436, 0xb884, 0xa438, 0x1BB1, 0xa436, 0xb832, 0xa438, 0x00ff, + 0xa436, 0x0000, 0xa438, 0x0000, 0xB82E, 0x0000, 0xa436, 0x8023, + 0xa438, 0x0000, 0xa436, 0x801E, 0xa438, 0x0023, 0xB820, 0x0000, + 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8125d_1_2[] = { + 0xb892, 0x0000, 0xB88E, 0xC28F, 0xB890, 0x252D, 0xB88E, 0xC290, + 0xB890, 0xC924, 0xB88E, 0xC291, 0xB890, 0xC92E, 0xB88E, 0xC292, + 0xB890, 0xF626, 0xB88E, 0xC293, 0xB890, 0xF630, 0xB88E, 0xC294, + 0xB890, 0xA328, 0xB88E, 0xC295, 0xB890, 0xA332, 0xB88E, 0xC296, + 0xB890, 0xD72B, 0xB88E, 0xC297, 0xB890, 0xD735, 0xB88E, 0xC298, + 0xB890, 0x8A2E, 0xB88E, 0xC299, 0xB890, 0x8A38, 0xB88E, 0xC29A, + 0xB890, 0xBE32, 0xB88E, 0xC29B, 0xB890, 0xBE3C, 0xB88E, 0xC29C, + 0xB890, 0x7436, 0xB88E, 0xC29D, 0xB890, 0x7440, 0xB88E, 0xC29E, + 0xB890, 0xAD3B, 0xB88E, 0xC29F, 0xB890, 0xAD45, 0xB88E, 0xC2A0, + 0xB890, 0x6640, 0xB88E, 0xC2A1, 0xB890, 0x664A, 0xB88E, 0xC2A2, + 0xB890, 0xA646, 0xB88E, 0xC2A3, 0xB890, 0xA650, 0xB88E, 0xC2A4, + 0xB890, 0x624C, 0xB88E, 0xC2A5, 0xB890, 0x6256, 0xB88E, 0xC2A6, + 0xB890, 0xA453, 0xB88E, 0xC2A7, 0xB890, 0xA45D, 0xB88E, 0xC2A8, + 0xB890, 0x665A, 0xB88E, 0xC2A9, 0xB890, 0x6664, 0xB88E, 0xC2AA, + 0xB890, 0xAC62, 0xB88E, 0xC2AB, 0xB890, 0xAC6C, 0xB88E, 0xC2AC, + 0xB890, 0x746A, 0xB88E, 0xC2AD, 0xB890, 0x7474, 0xB88E, 0xC2AE, + 0xB890, 0xBCFA, 0xB88E, 0xC2AF, 0xB890, 0xBCFD, 0xB88E, 0xC2B0, + 0xB890, 0x79FF, 0xB88E, 0xC2B1, 0xB890, 0x7901, 0xB88E, 0xC2B2, + 0xB890, 0xF703, 0xB88E, 0xC2B3, 0xB890, 0xF706, 0xB88E, 0xC2B4, + 0xB890, 0x7408, 0xB88E, 0xC2B5, 0xB890, 0x740A, 0xB88E, 0xC2B6, + 0xB890, 0xF10C, 0xB88E, 0xC2B7, 0xB890, 0xF10F, 0xB88E, 0xC2B8, + 0xB890, 0x6F10, 0xB88E, 0xC2B9, 0xB890, 0x6F13, 0xB88E, 0xC2BA, + 0xB890, 0xEC15, 0xB88E, 0xC2BB, 0xB890, 0xEC18, 0xB88E, 0xC2BC, + 0xB890, 0x6A1A, 0xB88E, 0xC2BD, 0xB890, 0x6A1C, 0xB88E, 0xC2BE, + 0xB890, 0xE71E, 0xB88E, 0xC2BF, 0xB890, 0xE721, 0xB88E, 0xC2C0, + 0xB890, 0x6424, 0xB88E, 0xC2C1, 0xB890, 0x6425, 0xB88E, 0xC2C2, + 0xB890, 0xE228, 0xB88E, 0xC2C3, 0xB890, 0xE22A, 0xB88E, 0xC2C4, + 0xB890, 0x5F2B, 0xB88E, 0xC2C5, 0xB890, 0x5F2E, 0xB88E, 0xC2C6, + 0xB890, 0xDC31, 0xB88E, 0xC2C7, 0xB890, 0xDC33, 0xB88E, 0xC2C8, + 0xB890, 0x2035, 0xB88E, 0xC2C9, 0xB890, 0x2036, 0xB88E, 0xC2CA, + 0xB890, 0x9F3A, 0xB88E, 0xC2CB, 0xB890, 0x9F3A, 0xB88E, 0xC2CC, + 0xB890, 0x4430, 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8125d_1_3[] = { + 0xa436, 0xacca, 0xa438, 0x0104, 0xa436, 0xaccc, 0xa438, 0x8000, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x0fff, + 0xa436, 0xacce, 0xa438, 0xfff8, 0xa436, 0xacd0, 0xa438, 0x0fff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xfb47, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xfb4f, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0x6087, 0xa436, 0xacd0, 0xa438, 0x0180, + 0xa436, 0xacce, 0xa438, 0x600f, 0xa436, 0xacd0, 0xa438, 0x0108, + 0xa436, 0xacce, 0xa438, 0x6807, 0xa436, 0xacd0, 0xa438, 0x0100, + 0xa436, 0xacce, 0xa438, 0x688f, 0xa436, 0xacd0, 0xa438, 0x0188, + 0xa436, 0xacce, 0xa438, 0x7027, 0xa436, 0xacd0, 0xa438, 0x0120, + 0xa436, 0xacce, 0xa438, 0x702f, 0xa436, 0xacd0, 0xa438, 0x0128, + 0xa436, 0xacce, 0xa438, 0x7847, 0xa436, 0xacd0, 0xa438, 0x0140, + 0xa436, 0xacce, 0xa438, 0x784f, 0xa436, 0xacd0, 0xa438, 0x0148, + 0xa436, 0xacce, 0xa438, 0x80a7, 0xa436, 0xacd0, 0xa438, 0x01a0, + 0xa436, 0xacce, 0xa438, 0x88af, 0xa436, 0xacd0, 0xa438, 0x01a8, + 0xa436, 0xacce, 0xa438, 0x8067, 0xa436, 0xacd0, 0xa438, 0x0161, + 0xa436, 0xacce, 0xa438, 0x886f, 0xa436, 0xacd0, 0xa438, 0x0169, + 0xa436, 0xacce, 0xa438, 0xfb57, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xfb5f, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0x6017, 0xa436, 0xacd0, 0xa438, 0x0110, + 0xa436, 0xacce, 0xa438, 0x601f, 0xa436, 0xacd0, 0xa438, 0x0118, + 0xa436, 0xacce, 0xa438, 0x6837, 0xa436, 0xacd0, 0xa438, 0x0130, + 0xa436, 0xacce, 0xa438, 0x683f, 0xa436, 0xacd0, 0xa438, 0x0138, + 0xa436, 0xacce, 0xa438, 0x7097, 0xa436, 0xacd0, 0xa438, 0x0190, + 0xa436, 0xacce, 0xa438, 0x705f, 0xa436, 0xacd0, 0xa438, 0x0158, + 0xa436, 0xacce, 0xa438, 0x7857, 0xa436, 0xacd0, 0xa438, 0x0150, + 0xa436, 0xacce, 0xa438, 0x789f, 0xa436, 0xacd0, 0xa438, 0x0198, + 0xa436, 0xacce, 0xa438, 0x90b7, 0xa436, 0xacd0, 0xa438, 0x01b0, + 0xa436, 0xacce, 0xa438, 0x98bf, 0xa436, 0xacd0, 0xa438, 0x01b8, + 0xa436, 0xacce, 0xa438, 0x9077, 0xa436, 0xacd0, 0xa438, 0x1171, + 0xa436, 0xacce, 0xa438, 0x987f, 0xa436, 0xacd0, 0xa438, 0x1179, + 0xa436, 0xacca, 0xa438, 0x0004, 0xa436, 0xacc6, 0xa438, 0x0015, + 0xa436, 0xacc8, 0xa438, 0xc000, 0xa436, 0xacc8, 0xa438, 0x0000, + 0xFFFF, 0xFFFF +}; + +static void +rtl_real_set_phy_mcu_8125d_1_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8125d_1_1, + ARRAY_SIZE(phy_mcu_ram_code_8125d_1_1)); +} + +static void +rtl_real_set_phy_mcu_8125d_1_2(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8125d_1_2, + ARRAY_SIZE(phy_mcu_ram_code_8125d_1_2)); +} + +static void +rtl_real_set_phy_mcu_8125d_1_3(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8125d_1_3, + ARRAY_SIZE(phy_mcu_ram_code_8125d_1_3)); +} + +void +rtl_set_phy_mcu_8125d_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8125d_1_1(hw); + + rtl_clear_phy_mcu_patch_request(hw); + + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8125d_1_2(hw); + + rtl_clear_phy_mcu_patch_request(hw); + + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8125d_1_3(hw); + + rtl_clear_phy_mcu_patch_request(hw); +} + diff --git a/drivers/net/r8169/base/rtl8125d_mcu.h b/drivers/net/r8169/base/rtl8125d_mcu.h new file mode 100644 index 0000000000..08c3104012 --- /dev/null +++ b/drivers/net/r8169/base/rtl8125d_mcu.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _RTL8125D_MCU_H_ +#define _RTL8125D_MCU_H_ + +void rtl_set_mac_mcu_8125d_1(struct rtl_hw *hw); +void rtl_set_mac_mcu_8125d_2(struct rtl_hw *hw); + +void rtl_set_phy_mcu_8125d_1(struct rtl_hw *hw); + +#endif + diff --git a/drivers/net/r8169/base/rtl8126a.c b/drivers/net/r8169/base/rtl8126a.c new file mode 100644 index 0000000000..3e4b66fdee --- /dev/null +++ b/drivers/net/r8169/base/rtl8126a.c @@ -0,0 +1,534 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include "../r8169_ethdev.h" +#include "../r8169_hw.h" +#include "../r8169_phy.h" +#include "rtl8126a_mcu.h" + +/* For RTL8126A, CFG_METHOD_69,70,71 */ + +static void +hw_init_rxcfg_8126a(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_69: + RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | RxCfg_pause_slot_en | + (RX_DMA_BURST_512 << RxCfgDMAShift)); + break; + case CFG_METHOD_70: + case CFG_METHOD_71: + RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | Rx_Close_Multiple | + RxCfg_pause_slot_en | (RX_DMA_BURST_512 << RxCfgDMAShift)); + break; + } +} + +static void +hw_ephy_config_8126a(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_69 ... CFG_METHOD_71: + /* nothing to do */ + break; + } +} + +static void +rtl_hw_phy_config_8126a_1(struct rtl_hw *hw) +{ + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); + + RTL_W16(hw, EEE_TXIDLE_TIMER_8125, hw->mtu + ETH_HLEN + 0x20); +} + +static void +rtl_hw_phy_config_8126a_2(struct rtl_hw *hw) +{ + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); + + RTL_W16(hw, EEE_TXIDLE_TIMER_8125, hw->mtu + ETH_HLEN + 0x20); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BF); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xED00); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CD); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D1); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC800); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D4); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC800); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E1); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x10CC); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E5); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4F0C); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8387); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x4700); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA80C, (BIT_7 | BIT_6), BIT_7); + + rtl_clear_eth_phy_ocp_bit(hw, 0xAC90, BIT_4); + rtl_clear_eth_phy_ocp_bit(hw, 0xAD2C, BIT_15); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8321); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100); + rtl_set_eth_phy_ocp_bit(hw, 0xACF8, (BIT_3 | BIT_2)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8183); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5900); + rtl_set_eth_phy_ocp_bit(hw, 0xAD94, BIT_5); + rtl_clear_eth_phy_ocp_bit(hw, 0xA654, BIT_11); + rtl_set_eth_phy_ocp_bit(hw, 0xB648, BIT_14); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x839E); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x2F00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83F2); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0800); + rtl_set_eth_phy_ocp_bit(hw, 0xADA0, BIT_1); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80F3); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9900); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8126); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xC100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x893A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x8080); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8647); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x862C); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1200); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864A); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80A0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xBCBC); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x805E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xBCBC); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8056); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3077); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8058); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5A00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8098); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3077); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x809A); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5A00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8052); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3733); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8094); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3733); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x807F); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C75); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x803D); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C75); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8036); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8078); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8031); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3300); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8073); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3300); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAE06, 0xFC00, 0x7C00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89D1); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0004); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FBD); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0A00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FBE); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0D09); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89CD); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F0F); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89CF); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F0F); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A4); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A6); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83C0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83C2); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8414); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8416); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83F8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83FA); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601); + + rtl_set_phy_mcu_patch_request(hw); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD96, 0x1F00, 0x1000); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF1C, 0x0007, 0x0007); + rtl_clear_eth_phy_ocp_bit(hw, 0xBFBE, BIT_15); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF40, 0x0380, 0x0280); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF90, BIT_7, (BIT_6 | BIT_5)); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF90, BIT_4, (BIT_3 | BIT_2)); + rtl_clear_phy_mcu_patch_request(hw); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x843B); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x843D); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2000); + + rtl_clear_eth_phy_ocp_bit(hw, 0xB516, 0x7F); + + rtl_clear_eth_phy_ocp_bit(hw, 0xBF80, (BIT_5 | BIT_4)); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8188); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0044); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00A8); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00D6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00EC); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00F6); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FC); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00BC); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0058); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x002A); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8015); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0800); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFD); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFF); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7F00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFB); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE9); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0002); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FEF); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00A5); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FF1); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0106); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE1); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0102); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE3); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400); + + rtl_set_eth_phy_ocp_bit(hw, 0xA654, BIT_11); + rtl_clear_eth_phy_ocp_bit(hw, 0XA65A, (BIT_1 | BIT_0)); + + rtl_mdio_direct_write_phy_ocp(hw, 0xAC3A, 0x5851); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0XAC3C, (BIT_15 | BIT_14 | BIT_12), + BIT_13); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC42, BIT_9, (BIT_8 | BIT_7 | BIT_6)); + rtl_clear_eth_phy_ocp_bit(hw, 0xAC3E, (BIT_15 | BIT_14 | BIT_13)); + rtl_clear_eth_phy_ocp_bit(hw, 0xAC42, (BIT_5 | BIT_4 | BIT_3)); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC42, BIT_1, (BIT_2 | BIT_0)); + + rtl_mdio_direct_write_phy_ocp(hw, 0xAC1A, 0x00DB); + rtl_mdio_direct_write_phy_ocp(hw, 0xADE4, 0x01B5); + rtl_clear_eth_phy_ocp_bit(hw, 0xAD9C, (BIT_11 | BIT_10)); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814B); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814D); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814F); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0B00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8142); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8144); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8150); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8118); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811A); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811C); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x810F); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8111); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811D); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + + rtl_set_eth_phy_ocp_bit(hw, 0xAC36, BIT_12); + rtl_clear_eth_phy_ocp_bit(hw, 0xAD1C, BIT_8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xADE8, 0xFFC0, 0x1400); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864B); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9D00); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8F97); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x003F); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3F02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x023C); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3B0A); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1C00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + + rtl_set_eth_phy_ocp_bit(hw, 0xAD9C, BIT_5); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8122); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82C8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80EF); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82A0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0006); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x001A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03D8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0023); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0054); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0322); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00DD); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03AB); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03DC); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0027); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E5); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F9); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0012); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0001); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018); + rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE4); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0000); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB54C, 0xFFC0, 0x3700); +} + +static void +rtl_hw_phy_config_8126a_3(struct rtl_hw *hw) +{ + rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11); + + RTL_W16(hw, EEE_TXIDLE_TIMER_8125, hw->mtu + ETH_HLEN + 0x20); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8183); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5900); + rtl_set_eth_phy_ocp_bit(hw, 0xA654, BIT_11); + rtl_set_eth_phy_ocp_bit(hw, 0xB648, BIT_14); + rtl_set_eth_phy_ocp_bit(hw, 0xAD2C, BIT_15); + rtl_set_eth_phy_ocp_bit(hw, 0xAD94, BIT_5); + rtl_set_eth_phy_ocp_bit(hw, 0xADA0, BIT_1); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAE06, + (BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10), + (BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10)); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8647); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8036); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8078); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89E9); + rtl_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFD); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFE); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0200); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFF); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400); + + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x7700); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8F9C); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0005); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ED); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0502); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0B00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xD401); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FA8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2900); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814B); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814D); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814F); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0B00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8142); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8144); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8150); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8118); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811A); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811C); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x810F); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8111); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811D); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100); + + rtl_set_eth_phy_ocp_bit(hw, 0xAD1C, BIT_8); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xADE8, + (BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 | + BIT_9 | BIT_8 | BIT_7 | BIT_6), + (BIT_12 | BIT_10)); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864B); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9D00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x862C); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1200); + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8566); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x003F); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3F02); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x023C); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3B0A); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1C00); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000); + + rtl_set_eth_phy_ocp_bit(hw, 0xAD9C, BIT_5); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8122); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82C8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED); + + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80EF); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82A0); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0006); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x001A); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03D8); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0023); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0054); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0322); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00DD); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03AB); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03DC); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0027); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E5); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F9); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0012); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0001); + rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1); + + rtl_set_eth_phy_ocp_bit(hw, 0xA430, (BIT_1 | BIT_0)); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB54C, 0xFFC0, 0x3700); +} + +static void +hw_phy_config_8126a(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_69: + rtl_hw_phy_config_8126a_1(hw); + break; + case CFG_METHOD_70: + rtl_hw_phy_config_8126a_2(hw); + break; + case CFG_METHOD_71: + rtl_hw_phy_config_8126a_3(hw); + break; + } +} + +static void +hw_mac_mcu_config_8126a(struct rtl_hw *hw) +{ + if (hw->NotWrMcuPatchCode == TRUE) + return; + + switch (hw->mcfg) { + case CFG_METHOD_69: + rtl_set_mac_mcu_8126a_1(hw); + break; + case CFG_METHOD_70: + rtl_set_mac_mcu_8126a_2(hw); + break; + case CFG_METHOD_71: + rtl_set_mac_mcu_8126a_3(hw); + break; + } +} + +static void +hw_phy_mcu_config_8126a(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_69: + rtl_set_phy_mcu_8126a_1(hw); + break; + case CFG_METHOD_70: + rtl_set_phy_mcu_8126a_2(hw); + break; + case CFG_METHOD_71: + rtl_set_phy_mcu_8126a_3(hw); + break; + } +} + +const struct rtl_hw_ops rtl8126a_ops = { + .hw_init_rxcfg = hw_init_rxcfg_8126a, + .hw_ephy_config = hw_ephy_config_8126a, + .hw_phy_config = hw_phy_config_8126a, + .hw_mac_mcu_config = hw_mac_mcu_config_8126a, + .hw_phy_mcu_config = hw_phy_mcu_config_8126a, +}; + diff --git a/drivers/net/r8169/base/rtl8126a_mcu.c b/drivers/net/r8169/base/rtl8126a_mcu.c new file mode 100644 index 0000000000..407666987f --- /dev/null +++ b/drivers/net/r8169/base/rtl8126a_mcu.c @@ -0,0 +1,2994 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include "../r8169_ethdev.h" +#include "../r8169_hw.h" +#include "../r8169_phy.h" +#include "rtl8126a_mcu.h" + +/* For RTL8126A, CFG_METHOD_69,70,71 */ + +/* ------------------------------------MAC 8126A------------------------------------- */ + +void +rtl_set_mac_mcu_8126a_1(struct rtl_hw *hw) +{ + static const u16 mcu_patch_code_8126a_1[] = { + 0xE010, 0xE019, 0xE01B, 0xE01D, 0xE01F, 0xE021, 0xE023, 0xE025, 0xE027, + 0xE029, 0xE02B, 0xE02D, 0xE02F, 0xE031, 0xE033, 0xE035, 0x48C0, 0x9C66, + 0x7446, 0x4840, 0x48C1, 0x48C2, 0x9C46, 0xC402, 0xBC00, 0x0AD6, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000 + }; + + rtl_hw_disable_mac_mcu_bps(hw); + + rtl_write_mac_mcu_ram_code(hw, mcu_patch_code_8126a_1, + ARRAY_SIZE(mcu_patch_code_8126a_1)); + + rtl_mac_ocp_write(hw, 0xFC26, 0x8000); + + rtl_mac_ocp_write(hw, 0xFC28, 0x0AAA); + + rtl_mac_ocp_write(hw, 0xFC48, 0x0001); +} + +void +rtl_set_mac_mcu_8126a_2(struct rtl_hw *hw) +{ + rtl_hw_disable_mac_mcu_bps(hw); +} + +void +rtl_set_mac_mcu_8126a_3(struct rtl_hw *hw) +{ + rtl_hw_disable_mac_mcu_bps(hw); +} + +/* ------------------------------------PHY 8126A------------------------------------- */ + +static const u16 phy_mcu_ram_code_8126a_1_1[] = { + 0xa436, 0x8023, 0xa438, 0x4900, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xBFBA, 0xE000, 0xBF1A, 0xC1B9, 0xBFA8, 0x10F0, 0xBFB0, 0x0210, + 0xBFB4, 0xE7E4, 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, + 0xa436, 0xA012, 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, + 0xa438, 0x8010, 0xa438, 0x1800, 0xa438, 0x8062, 0xa438, 0x1800, + 0xa438, 0x8069, 0xa438, 0x1800, 0xa438, 0x80e2, 0xa438, 0x1800, + 0xa438, 0x80eb, 0xa438, 0x1800, 0xa438, 0x80f5, 0xa438, 0x1800, + 0xa438, 0x811b, 0xa438, 0x1800, 0xa438, 0x8120, 0xa438, 0xd500, + 0xa438, 0xd049, 0xa438, 0xd1b9, 0xa438, 0xa208, 0xa438, 0x8208, + 0xa438, 0xd503, 0xa438, 0xa104, 0xa438, 0x0c07, 0xa438, 0x0902, + 0xa438, 0xd500, 0xa438, 0xbc10, 0xa438, 0xc484, 0xa438, 0xd503, + 0xa438, 0xcc02, 0xa438, 0xcd0d, 0xa438, 0xaf01, 0xa438, 0xd500, + 0xa438, 0xd703, 0xa438, 0x4531, 0xa438, 0xbd08, 0xa438, 0x1000, + 0xa438, 0x16bb, 0xa438, 0xd75e, 0xa438, 0x5fb3, 0xa438, 0xd503, + 0xa438, 0xd04d, 0xa438, 0xd1c7, 0xa438, 0x0cf0, 0xa438, 0x0e10, + 0xa438, 0xd704, 0xa438, 0x5ffc, 0xa438, 0xd04d, 0xa438, 0xd1c7, + 0xa438, 0x0cf0, 0xa438, 0x0e20, 0xa438, 0xd704, 0xa438, 0x5ffc, + 0xa438, 0xd04d, 0xa438, 0xd1c7, 0xa438, 0x0cf0, 0xa438, 0x0e40, + 0xa438, 0xd704, 0xa438, 0x5ffc, 0xa438, 0xd04d, 0xa438, 0xd1c7, + 0xa438, 0x0cf0, 0xa438, 0x0e80, 0xa438, 0xd704, 0xa438, 0x5ffc, + 0xa438, 0xd07b, 0xa438, 0xd1c5, 0xa438, 0x8ef0, 0xa438, 0xd704, + 0xa438, 0x5ffc, 0xa438, 0x9d08, 0xa438, 0x1000, 0xa438, 0x16bb, + 0xa438, 0xd75e, 0xa438, 0x7fb3, 0xa438, 0x1000, 0xa438, 0x16bb, + 0xa438, 0xd75e, 0xa438, 0x5fad, 0xa438, 0x1000, 0xa438, 0x181f, + 0xa438, 0xd703, 0xa438, 0x3181, 0xa438, 0x8059, 0xa438, 0x60ad, + 0xa438, 0x1000, 0xa438, 0x16bb, 0xa438, 0xd703, 0xa438, 0x5fbb, + 0xa438, 0x1000, 0xa438, 0x16bb, 0xa438, 0xd719, 0xa438, 0x7fa8, + 0xa438, 0xd500, 0xa438, 0xd049, 0xa438, 0xd1b9, 0xa438, 0x1800, + 0xa438, 0x0f0b, 0xa438, 0xd500, 0xa438, 0xd07b, 0xa438, 0xd1b5, + 0xa438, 0xd0f6, 0xa438, 0xd1c5, 0xa438, 0x1800, 0xa438, 0x1049, + 0xa438, 0xd707, 0xa438, 0x4121, 0xa438, 0xd706, 0xa438, 0x40fa, + 0xa438, 0xd099, 0xa438, 0xd1c6, 0xa438, 0x1000, 0xa438, 0x16bb, + 0xa438, 0xd704, 0xa438, 0x5fbc, 0xa438, 0xbc80, 0xa438, 0xc489, + 0xa438, 0xd503, 0xa438, 0xcc08, 0xa438, 0xcd46, 0xa438, 0xaf01, + 0xa438, 0xd500, 0xa438, 0x1000, 0xa438, 0x0903, 0xa438, 0x1000, + 0xa438, 0x16bb, 0xa438, 0xd75e, 0xa438, 0x5f6d, 0xa438, 0x1000, + 0xa438, 0x181f, 0xa438, 0xd504, 0xa438, 0xa210, 0xa438, 0xd500, + 0xa438, 0x1000, 0xa438, 0x16bb, 0xa438, 0xd719, 0xa438, 0x5fbc, + 0xa438, 0xd504, 0xa438, 0x8210, 0xa438, 0xd503, 0xa438, 0xc6d0, + 0xa438, 0xa521, 0xa438, 0xcd49, 0xa438, 0xaf01, 0xa438, 0xd504, + 0xa438, 0xa220, 0xa438, 0xd500, 0xa438, 0x1000, 0xa438, 0x16bb, + 0xa438, 0xd75e, 0xa438, 0x5fad, 0xa438, 0x1000, 0xa438, 0x181f, + 0xa438, 0xd503, 0xa438, 0xa704, 0xa438, 0x0c07, 0xa438, 0x0904, + 0xa438, 0xd504, 0xa438, 0xa102, 0xa438, 0xd500, 0xa438, 0x1000, + 0xa438, 0x16bb, 0xa438, 0xd718, 0xa438, 0x5fab, 0xa438, 0xd503, + 0xa438, 0xc6f0, 0xa438, 0xa521, 0xa438, 0xd505, 0xa438, 0xa404, + 0xa438, 0xd500, 0xa438, 0xd701, 0xa438, 0x6085, 0xa438, 0xd504, + 0xa438, 0xc9f1, 0xa438, 0xf003, 0xa438, 0xd504, 0xa438, 0xc9f0, + 0xa438, 0xd503, 0xa438, 0xcd4a, 0xa438, 0xaf01, 0xa438, 0xd500, + 0xa438, 0xd504, 0xa438, 0xa802, 0xa438, 0xd500, 0xa438, 0x1000, + 0xa438, 0x16bb, 0xa438, 0xd707, 0xa438, 0x5fb1, 0xa438, 0xd707, + 0xa438, 0x5f10, 0xa438, 0xd505, 0xa438, 0xa402, 0xa438, 0xd503, + 0xa438, 0xd707, 0xa438, 0x41a1, 0xa438, 0xd706, 0xa438, 0x60ba, + 0xa438, 0x60fc, 0xa438, 0x0c07, 0xa438, 0x0204, 0xa438, 0xf009, + 0xa438, 0x0c07, 0xa438, 0x0202, 0xa438, 0xf006, 0xa438, 0x0c07, + 0xa438, 0x0206, 0xa438, 0xf003, 0xa438, 0x0c07, 0xa438, 0x0202, + 0xa438, 0xd500, 0xa438, 0xd703, 0xa438, 0x3181, 0xa438, 0x80e0, + 0xa438, 0x616d, 0xa438, 0xd701, 0xa438, 0x6065, 0xa438, 0x1800, + 0xa438, 0x1229, 0xa438, 0x1000, 0xa438, 0x16bb, 0xa438, 0xd707, + 0xa438, 0x6061, 0xa438, 0xd704, 0xa438, 0x5f7c, 0xa438, 0x1800, + 0xa438, 0x124a, 0xa438, 0xd504, 0xa438, 0x8c0f, 0xa438, 0xd505, + 0xa438, 0xa20e, 0xa438, 0xd500, 0xa438, 0x1000, 0xa438, 0x1871, + 0xa438, 0x1800, 0xa438, 0x1899, 0xa438, 0xd70b, 0xa438, 0x60b0, + 0xa438, 0xd05a, 0xa438, 0xd19a, 0xa438, 0x1800, 0xa438, 0x1aef, + 0xa438, 0xd0ef, 0xa438, 0xd19a, 0xa438, 0x1800, 0xa438, 0x1aef, + 0xa438, 0x1000, 0xa438, 0x1d09, 0xa438, 0xd708, 0xa438, 0x3399, + 0xa438, 0x1b63, 0xa438, 0xd709, 0xa438, 0x5f5d, 0xa438, 0xd70b, + 0xa438, 0x6130, 0xa438, 0xd70d, 0xa438, 0x6163, 0xa438, 0xd709, + 0xa438, 0x430b, 0xa438, 0xd71e, 0xa438, 0x62c2, 0xa438, 0xb401, + 0xa438, 0xf014, 0xa438, 0xc901, 0xa438, 0x1000, 0xa438, 0x810e, + 0xa438, 0xf010, 0xa438, 0xc902, 0xa438, 0x1000, 0xa438, 0x810e, + 0xa438, 0xf00c, 0xa438, 0xce04, 0xa438, 0xcf01, 0xa438, 0xd70a, + 0xa438, 0x5fe2, 0xa438, 0xce04, 0xa438, 0xcf02, 0xa438, 0xc900, + 0xa438, 0xd70a, 0xa438, 0x4057, 0xa438, 0xb401, 0xa438, 0x0800, + 0xa438, 0x1800, 0xa438, 0x1b5d, 0xa438, 0xa480, 0xa438, 0xa2b0, + 0xa438, 0xa806, 0xa438, 0x1800, 0xa438, 0x225c, 0xa438, 0xa7e8, + 0xa438, 0xac08, 0xa438, 0x1800, 0xa438, 0x1a4e, 0xa436, 0xA026, + 0xa438, 0x1a4d, 0xa436, 0xA024, 0xa438, 0x225a, 0xa436, 0xA022, + 0xa438, 0x1b53, 0xa436, 0xA020, 0xa438, 0x1aed, 0xa436, 0xA006, + 0xa438, 0x1892, 0xa436, 0xA004, 0xa438, 0x11a4, 0xa436, 0xA002, + 0xa438, 0x103c, 0xa436, 0xA000, 0xa438, 0x0ea6, 0xa436, 0xA008, + 0xa438, 0xff00, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0ff8, 0xa436, 0xA014, 0xa438, 0x0000, 0xa438, 0xD098, + 0xa438, 0xc483, 0xa438, 0xc483, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa436, 0xA152, 0xa438, 0x3fff, + 0xa436, 0xA154, 0xa438, 0x0413, 0xa436, 0xA156, 0xa438, 0x1A32, + 0xa436, 0xA158, 0xa438, 0x1CC0, 0xa436, 0xA15A, 0xa438, 0x3fff, + 0xa436, 0xA15C, 0xa438, 0x3fff, 0xa436, 0xA15E, 0xa438, 0x3fff, + 0xa436, 0xA160, 0xa438, 0x3fff, 0xa436, 0xA150, 0xa438, 0x000E, + 0xa436, 0xA016, 0xa438, 0x0020, 0xa436, 0xA012, 0xa438, 0x0000, + 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, 0xa438, 0x1800, + 0xa438, 0x8021, 0xa438, 0x1800, 0xa438, 0x8037, 0xa438, 0x1800, + 0xa438, 0x803f, 0xa438, 0x1800, 0xa438, 0x8084, 0xa438, 0x1800, + 0xa438, 0x80c5, 0xa438, 0x1800, 0xa438, 0x80cc, 0xa438, 0x1800, + 0xa438, 0x80d5, 0xa438, 0xa00a, 0xa438, 0xa280, 0xa438, 0xa404, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x1800, 0xa438, 0x099b, 0xa438, 0x1000, 0xa438, 0x1021, + 0xa438, 0xd700, 0xa438, 0x5fab, 0xa438, 0xa208, 0xa438, 0x8204, + 0xa438, 0xcb38, 0xa438, 0xaa40, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x1800, 0xa438, 0x0b2a, + 0xa438, 0x82a0, 0xa438, 0x8404, 0xa438, 0xa110, 0xa438, 0xd706, + 0xa438, 0x4041, 0xa438, 0xa180, 0xa438, 0x1800, 0xa438, 0x0e7f, + 0xa438, 0x8190, 0xa438, 0xcb93, 0xa438, 0x1000, 0xa438, 0x0ef4, + 0xa438, 0xd704, 0xa438, 0x7fb8, 0xa438, 0xa008, 0xa438, 0xd706, + 0xa438, 0x4040, 0xa438, 0xa002, 0xa438, 0xd705, 0xa438, 0x4079, + 0xa438, 0x1000, 0xa438, 0x10ad, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0x85f0, 0xa438, 0x9503, 0xa438, 0xd705, 0xa438, 0x40d9, + 0xa438, 0xd70c, 0xa438, 0x6083, 0xa438, 0x0c1f, 0xa438, 0x0d09, + 0xa438, 0xf003, 0xa438, 0x0c1f, 0xa438, 0x0d0a, 0xa438, 0x0cc0, + 0xa438, 0x0d80, 0xa438, 0x1000, 0xa438, 0x104f, 0xa438, 0x1000, + 0xa438, 0x0ef4, 0xa438, 0x8020, 0xa438, 0xd705, 0xa438, 0x40d9, + 0xa438, 0xd704, 0xa438, 0x609f, 0xa438, 0xd70c, 0xa438, 0x6043, + 0xa438, 0x8504, 0xa438, 0xcb94, 0xa438, 0x1000, 0xa438, 0x0ef4, + 0xa438, 0xd706, 0xa438, 0x7fa2, 0xa438, 0x800a, 0xa438, 0x0c03, + 0xa438, 0x1502, 0xa438, 0x0cf0, 0xa438, 0x05a0, 0xa438, 0x9503, + 0xa438, 0xd705, 0xa438, 0x40b9, 0xa438, 0x0c1f, 0xa438, 0x0d00, + 0xa438, 0x8dc0, 0xa438, 0xf005, 0xa438, 0xa190, 0xa438, 0x0c1f, + 0xa438, 0x0d17, 0xa438, 0x8dc0, 0xa438, 0x1000, 0xa438, 0x104f, + 0xa438, 0xd705, 0xa438, 0x39cc, 0xa438, 0x0c7d, 0xa438, 0x1800, + 0xa438, 0x0e67, 0xa438, 0xcb96, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xab05, 0xa438, 0xac04, 0xa438, 0xac08, 0xa438, 0x9503, + 0xa438, 0x0c1f, 0xa438, 0x0d00, 0xa438, 0x8dc0, 0xa438, 0x1000, + 0xa438, 0x104f, 0xa438, 0x1000, 0xa438, 0x1021, 0xa438, 0xd706, + 0xa438, 0x2215, 0xa438, 0x8099, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xae02, 0xa438, 0x9503, 0xa438, 0xd706, 0xa438, 0x6451, + 0xa438, 0xd71f, 0xa438, 0x2e70, 0xa438, 0x0f00, 0xa438, 0xd706, + 0xa438, 0x3290, 0xa438, 0x80be, 0xa438, 0xd704, 0xa438, 0x2e70, + 0xa438, 0x8090, 0xa438, 0xd706, 0xa438, 0x339c, 0xa438, 0x8090, + 0xa438, 0x8718, 0xa438, 0x8910, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xc500, 0xa438, 0x9503, 0xa438, 0x0c1f, 0xa438, 0x0d17, + 0xa438, 0x8dc0, 0xa438, 0x1000, 0xa438, 0x104f, 0xa438, 0x0c03, + 0xa438, 0x1502, 0xa438, 0x8c04, 0xa438, 0x9503, 0xa438, 0xa00a, + 0xa438, 0xa190, 0xa438, 0xa280, 0xa438, 0xa404, 0xa438, 0x1800, + 0xa438, 0x0f35, 0xa438, 0x1800, 0xa438, 0x0f07, 0xa438, 0x0c03, + 0xa438, 0x1502, 0xa438, 0x8c08, 0xa438, 0x8c04, 0xa438, 0x9503, + 0xa438, 0x1800, 0xa438, 0x0f02, 0xa438, 0x1000, 0xa438, 0x1021, + 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xaa10, 0xa438, 0x1800, + 0xa438, 0x0c6b, 0xa438, 0x82a0, 0xa438, 0x8406, 0xa438, 0x0c03, + 0xa438, 0x1502, 0xa438, 0xac04, 0xa438, 0x8602, 0xa438, 0x9503, + 0xa438, 0x1800, 0xa438, 0x0e09, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x8308, 0xa438, 0x0c03, + 0xa438, 0x1502, 0xa438, 0xc555, 0xa438, 0x9503, 0xa438, 0xa728, + 0xa438, 0x8440, 0xa438, 0x0c03, 0xa438, 0x0901, 0xa438, 0x8801, + 0xa438, 0xd700, 0xa438, 0x4040, 0xa438, 0xa801, 0xa438, 0xd701, + 0xa438, 0x4052, 0xa438, 0xa810, 0xa438, 0xd701, 0xa438, 0x4054, + 0xa438, 0xa820, 0xa438, 0xd701, 0xa438, 0x4057, 0xa438, 0xa640, + 0xa438, 0xd704, 0xa438, 0x4046, 0xa438, 0xa840, 0xa438, 0xd706, + 0xa438, 0x40b5, 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0xae20, + 0xa438, 0x9503, 0xa438, 0xd401, 0xa438, 0x1000, 0xa438, 0x0fcf, + 0xa438, 0x1000, 0xa438, 0x0fda, 0xa438, 0x1000, 0xa438, 0x1008, + 0xa438, 0x1000, 0xa438, 0x0fe3, 0xa438, 0xcc00, 0xa438, 0x80c0, + 0xa438, 0x8103, 0xa438, 0x83e0, 0xa438, 0xd71e, 0xa438, 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0xf0ac, 0xa438, 0x2ef0, 0xa438, 0xac30, + 0xa438, 0xbf8e, 0xa438, 0xf102, 0xa438, 0x6bef, 0xa438, 0xac28, + 0xa438, 0x70bf, 0xa438, 0x8eeb, 0xa438, 0x026b, 0xa438, 0xefac, + 0xa438, 0x2867, 0xa438, 0xbf8e, 0xa438, 0xee02, 0xa438, 0x6bef, + 0xa438, 0xad28, 0xa438, 0x5bbf, 0xa438, 0x8ff2, 0xa438, 0xd8bf, + 0xa438, 0x8ff3, 0xa438, 0xd9bf, 0xa438, 0x8ef4, 0xa438, 0x026b, + 0xa438, 0xd0bf, 0xa438, 0x8ff0, 0xa438, 0xd8bf, 0xa438, 0x8ff1, + 0xa438, 0xd9bf, 0xa438, 0x8ef7, 0xa438, 0x026b, 0xa438, 0xd0bf, + 0xa438, 0x8fee, 0xa438, 0xd8bf, 0xa438, 0x8fef, 0xa438, 0xd9bf, + 0xa438, 0x8efa, 0xa438, 0x026b, 0xa438, 0xd0bf, 0xa438, 0x8fec, + 0xa438, 0xd8bf, 0xa438, 0x8fed, 0xa438, 0xd9bf, 0xa438, 0x8efd, + 0xa438, 0x026b, 0xa438, 0xd0bf, 0xa438, 0x8fea, 0xa438, 0xd8bf, + 0xa438, 0x8feb, 0xa438, 0xd9bf, 0xa438, 0x8f00, 0xa438, 0x026b, + 0xa438, 0xd0bf, 0xa438, 0x8fe8, 0xa438, 0xd8bf, 0xa438, 0x8fe9, + 0xa438, 0xd9bf, 0xa438, 0x8e0d, 0xa438, 0x026b, 0xa438, 0xd01f, + 0xa438, 0x00e1, 0xa438, 0x86ee, 0xa438, 0x1b64, 0xa438, 0xaf3d, + 0xa438, 0x7abf, 0xa438, 0x8ffe, 0xa438, 0xd8bf, 0xa438, 0x8fff, + 0xa438, 0xd9bf, 0xa438, 0x8ef4, 0xa438, 0x026b, 0xa438, 0xd0bf, + 0xa438, 0x8ffc, 0xa438, 0xd8bf, 0xa438, 0x8ffd, 0xa438, 0xd9bf, + 0xa438, 0x8ef7, 0xa438, 0x026b, 0xa438, 0xd0bf, 0xa438, 0x8ffa, + 0xa438, 0xd8bf, 0xa438, 0x8ffb, 0xa438, 0xd9bf, 0xa438, 0x8efa, + 0xa438, 0x026b, 0xa438, 0xd0bf, 0xa438, 0x8ff8, 0xa438, 0xd8bf, + 0xa438, 0x8ff9, 0xa438, 0xd9bf, 0xa438, 0x8efd, 0xa438, 0x026b, + 0xa438, 0xd0bf, 0xa438, 0x8ff6, 0xa438, 0xd8bf, 0xa438, 0x8ff7, + 0xa438, 0xd9bf, 0xa438, 0x8f00, 0xa438, 0x026b, 0xa438, 0xd0bf, + 0xa438, 0x8ff4, 0xa438, 0xd8bf, 0xa438, 0x8ff5, 0xa438, 0xd9bf, + 0xa438, 0x8e0d, 0xa438, 0x026b, 0xa438, 0xd0ae, 0xa438, 0xa766, + 0xa438, 0xac5c, 0xa438, 0xbbac, 0xa438, 0x5c99, 0xa438, 0xac5c, + 0xa438, 0xf0ac, 0xa438, 0x26f0, 0xa438, 0xac24, 0xa438, 0xf0ac, + 0xa438, 0x22f0, 0xa438, 0xac20, 0xa438, 0xf0ac, 0xa438, 0x1eaf, + 0xa438, 0x44f8, 0xa436, 0xb85e, 0xa438, 0x2344, 0xa436, 0xb860, + 0xa438, 0x2254, 0xa436, 0xb862, 0xa438, 0x2DB5, 0xa436, 0xb864, + 0xa438, 0x3D6C, 0xa436, 0xb886, 0xa438, 0x44ED, 0xa436, 0xb888, + 0xa438, 0xffff, 0xa436, 0xb88a, 0xa438, 0xffff, 0xa436, 0xb88c, + 0xa438, 0xffff, 0xa436, 0xb838, 0xa438, 0x001f, 0xb820, 0x0010, + 0xa436, 0x87ad, 0xa438, 0xaf87, 0xa438, 0xc5af, 0xa438, 0x87e4, + 0xa438, 0xaf8a, 0xa438, 0x3daf, 0xa438, 0x8a62, 0xa438, 0xaf8a, + 0xa438, 0x62af, 0xa438, 0x8a62, 0xa438, 0xaf8a, 0xa438, 0x62af, + 0xa438, 0x8a62, 0xa438, 0x2810, 0xa438, 0x0d01, 0xa438, 0xe484, + 0xa438, 0xbf29, 0xa438, 0x100d, 0xa438, 0x11e5, 0xa438, 0x84c0, + 0xa438, 0x2a10, 0xa438, 0x0d21, 0xa438, 0xe684, 0xa438, 0xc12b, + 0xa438, 0x100d, 0xa438, 0x31e7, 0xa438, 0x84c2, 0xa438, 0xaf3f, + 0xa438, 0x7cf8, 0xa438, 0xe080, 0xa438, 0x4cac, 0xa438, 0x222c, + 0xa438, 0xe080, 0xa438, 0x40ad, 0xa438, 0x2232, 0xa438, 0xbf8a, + 0xa438, 0x2502, 0xa438, 0x6752, 0xa438, 0xad29, 0xa438, 0x0502, + 0xa438, 0x8827, 0xa438, 0xae0d, 0xa438, 0xad28, 0xa438, 0x0502, + 0xa438, 0x8961, 0xa438, 0xae05, 0xa438, 0x0214, 0xa438, 0x04ae, + 0xa438, 0x00e0, 0xa438, 0x8040, 0xa438, 0xac22, 0xa438, 0x1102, + 0xa438, 0x13e1, 0xa438, 0xae0c, 0xa438, 0x0288, 0xa438, 0x7c02, + 0xa438, 0x8a10, 0xa438, 0x0214, 0xa438, 0x2502, 0xa438, 0x1404, + 0xa438, 0xfcaf, 0xa438, 0x13c6, 0xa438, 0xf8f8, 0xa438, 0xccf9, + 0xa438, 0xfaef, 0xa438, 0x69fb, 0xa438, 0xe080, 0xa438, 0x18ad, + 0xa438, 0x223b, 0xa438, 0xbf8a, 0xa438, 0x2b02, 0xa438, 0x6752, + 0xa438, 0xad28, 0xa438, 0x32bf, 0xa438, 0x8a28, 0xa438, 0x026f, + 0xa438, 0x17ee, 0xa438, 0x8ff3, 0xa438, 0x00bf, 0xa438, 0x6854, + 0xa438, 0x0267, 0xa438, 0x52ad, 0xa438, 0x281f, 0xa438, 0xbf68, + 0xa438, 0x5d02, 0xa438, 0x6752, 0xa438, 0xad28, 0xa438, 0x16e0, + 0xa438, 0x8ff4, 0xa438, 0xe18f, 0xa438, 0xf502, 0xa438, 0x8891, + 0xa438, 0xad50, 0xa438, 0x0abf, 0xa438, 0x8a28, 0xa438, 0x026f, + 0xa438, 0x20ee, 0xa438, 0x8ff3, 0xa438, 0x0102, 0xa438, 0x1404, + 0xa438, 0xffef, 0xa438, 0x96fe, 0xa438, 0xfdc4, 0xa438, 0xfcfc, + 0xa438, 0x04f8, 0xa438, 0xf9ef, 0xa438, 0x59e0, 0xa438, 0x8018, + 0xa438, 0xad22, 0xa438, 0x06bf, 0xa438, 0x8a28, 0xa438, 0x026f, + 0xa438, 0x17ef, 0xa438, 0x95fd, 0xa438, 0xfc04, 0xa438, 0xf8f9, + 0xa438, 0xf9ef, 0xa438, 0x59fa, 0xa438, 0xface, 0xa438, 0xe48f, + 0xa438, 0xfee5, 0xa438, 0x8fff, 0xa438, 0xbf6e, 0xa438, 0x1b02, + 0xa438, 0x6f20, 0xa438, 0xbf6e, 0xa438, 0x1802, 0xa438, 0x6f17, + 0xa438, 0xd102, 0xa438, 0xbf6e, 0xa438, 0x1202, 0xa438, 0x6733, + 0xa438, 0xbf6e, 0xa438, 0x1502, 0xa438, 0x6f17, 0xa438, 0xbe00, + 0xa438, 0x00cc, 0xa438, 0xbf69, 0xa438, 0xcb02, 0xa438, 0x6733, + 0xa438, 0xbf69, 0xa438, 0xce02, 0xa438, 0x6f17, 0xa438, 0xbf69, + 0xa438, 0xce02, 0xa438, 0x6f20, 0xa438, 0xbf69, 0xa438, 0xd102, + 0xa438, 0x6752, 0xa438, 0xad28, 0xa438, 0xf70c, 0xa438, 0x81bf, + 0xa438, 0x8ff6, 0xa438, 0x1a98, 0xa438, 0xef59, 0xa438, 0xbf69, + 0xa438, 0xd402, 0xa438, 0x6752, 0xa438, 0xef95, 0xa438, 0xdc19, + 0xa438, 0xdd0d, 0xa438, 0x8118, 0xa438, 0xa800, 0xa438, 0x04c9, + 0xa438, 0xbf69, 0xa438, 0xce02, 0xa438, 0x6f17, 0xa438, 0xe08f, + 0xa438, 0xfce1, 0xa438, 0x8ffd, 0xa438, 0xef74, 0xa438, 0xe08f, + 0xa438, 0xfae1, 0xa438, 0x8ffb, 0xa438, 0xef64, 0xa438, 0x026e, + 0xa438, 0x57ad, 0xa438, 0x5008, 0xa438, 0xe08f, 0xa438, 0xfce1, + 0xa438, 0x8ffd, 0xa438, 0xae06, 0xa438, 0xe08f, 0xa438, 0xfae1, + 0xa438, 0x8ffb, 0xa438, 0xe28f, 0xa438, 0xf8e3, 0xa438, 0x8ff9, + 0xa438, 0xef75, 0xa438, 0xe28f, 0xa438, 0xf6e3, 0xa438, 0x8ff7, + 0xa438, 0xef65, 0xa438, 0x026e, 0xa438, 0x57ad, 0xa438, 0x5008, + 0xa438, 0xe28f, 0xa438, 0xf8e3, 0xa438, 0x8ff9, 0xa438, 0xae06, + 0xa438, 0xe28f, 0xa438, 0xf6e3, 0xa438, 0x8ff7, 0xa438, 0x1b45, + 0xa438, 0xad27, 0xa438, 0x05d7, 0xa438, 0x0000, 0xa438, 0xae0d, + 0xa438, 0xef74, 0xa438, 0xe08f, 0xa438, 0xfee1, 0xa438, 0x8fff, + 0xa438, 0xef64, 0xa438, 0x026e, 0xa438, 0x57c6, 0xa438, 0xfefe, + 0xa438, 0xef95, 0xa438, 0xfdfd, 0xa438, 0xfc04, 0xa438, 0xf8f9, + 0xa438, 0xfaef, 0xa438, 0x69fb, 0xa438, 0xe080, 0xa438, 0x18ac, + 0xa438, 0x2103, 0xa438, 0xaf8a, 0xa438, 0x06bf, 0xa438, 0x8a2b, + 0xa438, 0xac21, 0xa438, 0x03af, 0xa438, 0x8a06, 0xa438, 0xbf8a, + 0xa438, 0x2802, 0xa438, 0x6f17, 0xa438, 0xee8f, 0xa438, 0xee00, + 0xa438, 0xee8f, 0xa438, 0xed00, 0xa438, 0xbf8a, 0xa438, 0x2e02, + 0xa438, 0x6752, 0xa438, 0xad28, 0xa438, 0x03af, 0xa438, 0x8a06, + 0xa438, 0xe28f, 0xa438, 0xefe3, 0xa438, 0x8ff0, 0xa438, 0xbf68, + 0xa438, 0x5102, 0xa438, 0x6752, 0xa438, 0xac28, 0xa438, 0x11e2, + 0xa438, 0x8ff1, 0xa438, 0xe38f, 0xa438, 0xf2bf, 0xa438, 0x6848, + 0xa438, 0x0267, 0xa438, 0x52ac, 0xa438, 0x2802, 0xa438, 0xae53, + 0xa438, 0xbf68, 0xa438, 0x5a02, 0xa438, 0x6752, 0xa438, 0xad28, + 0xa438, 0x0aef, 0xa438, 0x4502, 0xa438, 0x8891, 0xa438, 0xac50, + 0xa438, 0x38ae, 0xa438, 0x40bf, 0xa438, 0x8a31, 0xa438, 0x0267, + 0xa438, 0x52ef, 0xa438, 0x31bf, 0xa438, 0x8a34, 0xa438, 0x0267, + 0xa438, 0x520c, 0xa438, 0x311e, 0xa438, 0x31bf, 0xa438, 0x8a37, + 0xa438, 0x0267, 0xa438, 0x520c, 0xa438, 0x311e, 0xa438, 0x31bf, + 0xa438, 0x8a3a, 0xa438, 0x0267, 0xa438, 0x520c, 0xa438, 0x311e, + 0xa438, 0x31e7, 0xa438, 0x8fee, 0xa438, 0xa30c, 0xa438, 0x02ae, + 0xa438, 0x08a3, 0xa438, 0x0e02, 0xa438, 0xae03, 0xa438, 0xa30d, + 0xa438, 0x0aee, 0xa438, 0x8fed, 0xa438, 0x01bf, 0xa438, 0x8a28, + 0xa438, 0x026f, 0xa438, 0x2002, 0xa438, 0x1404, 0xa438, 0xffef, + 0xa438, 0x96fe, 0xa438, 0xfdfc, 0xa438, 0x04f8, 0xa438, 0xfaef, + 0xa438, 0x69e0, 0xa438, 0x8018, 0xa438, 0xad21, 0xa438, 0x06bf, + 0xa438, 0x8a28, 0xa438, 0x026f, 0xa438, 0x17ef, 0xa438, 0x96fe, + 0xa438, 0xfc04, 0xa438, 0xf8a4, 0xa438, 0xb677, 0xa438, 0xa4b6, + 0xa438, 0x22a4, 0xa438, 0x4222, 0xa438, 0xa668, 0xa438, 0x00b2, + 0xa438, 0x3e00, 0xa438, 0xb2be, 0xa438, 0x00b3, 0xa438, 0x3e00, + 0xa438, 0xb3be, 0xa438, 0xd10f, 0xa438, 0xbf8a, 0xa438, 0x5c02, + 0xa438, 0x6733, 0xa438, 0xbf8a, 0xa438, 0x5f02, 0xa438, 0x6733, + 0xa438, 0xbf8a, 0xa438, 0x5c02, 0xa438, 0x6f17, 0xa438, 0xbf8a, + 0xa438, 0x5f02, 0xa438, 0x6f17, 0xa438, 0x1f00, 0xa438, 0xaf3d, + 0xa438, 0x0c30, 0xa438, 0xa85a, 0xa438, 0xfcad, 0xa438, 0x0e00, + 0xa436, 0xb818, 0xa438, 0x3f31, 0xa436, 0xb81a, 0xa438, 0x13a4, + 0xa436, 0xb81c, 0xa438, 0x3d0a, 0xa436, 0xb81e, 0xa438, 0xffff, + 0xa436, 0xb850, 0xa438, 0xffff, 0xa436, 0xb852, 0xa438, 0xffff, + 0xa436, 0xb878, 0xa438, 0xffff, 0xa436, 0xb884, 0xa438, 0xffff, + 0xa436, 0xb832, 0xa438, 0x0007, 0xa436, 0x84cf, 0xa438, 0x0101, + 0xa466, 0x0002, 0xa436, 0x86a7, 0xa438, 0x0000, 0xa436, 0x0000, + 0xa438, 0x0000, 0xa436, 0xB82E, 0xa438, 0x0000, 0xa436, 0x8023, + 0xa438, 0x0000, 0xa436, 0x801E, 0xa438, 0x0023, 0xb820, 0x0000, + 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8126a_1_2[] = { + 0xB87C, 0x8a32, 0xB87E, 0x0400, 0xB87C, 0x8376, 0xB87E, 0x0300, + 0xce00, 0x6CAF, 0xB87C, 0x8301, 0xB87E, 0x1133, 0xB87C, 0x8105, + 0xB87E, 0xa000, 0xB87C, 0x8148, 0xB87E, 0xa000, 0xa436, 0x81d8, + 0xa438, 0x5865, 0xacf8, 0xCCC0, 0xac90, 0x52B0, 0xad2C, 0x8000, + 0xB87C, 0x83e6, 0xB87E, 0x4A0E, 0xB87C, 0x83d2, 0xB87E, 0x0A0E, + 0xB87C, 0x80a0, 0xB87E, 0xB8B6, 0xB87C, 0x805e, 0xB87E, 0xB8B6, + 0xB87C, 0x8057, 0xB87E, 0x305A, 0xB87C, 0x8099, 0xB87E, 0x305A, + 0xB87C, 0x8052, 0xB87E, 0x3333, 0xB87C, 0x8094, 0xB87E, 0x3333, + 0xB87C, 0x807F, 0xB87E, 0x7975, 0xB87C, 0x803D, 0xB87E, 0x7975, + 0xB87C, 0x8036, 0xB87E, 0x305A, 0xB87C, 0x8078, 0xB87E, 0x305A, + 0xB87C, 0x8031, 0xB87E, 0x3335, 0xB87C, 0x8073, 0xB87E, 0x3335, + 0xa436, 0x81D8, 0xa438, 0x5865, 0xB87C, 0x867c, 0xB87E, 0x0617, + 0xad94, 0x0092, 0xB87C, 0x89B1, 0xB87E, 0x5050, 0xB87C, 0x86E0, + 0xB87E, 0x809A, 0xB87C, 0x86E2, 0xB87E, 0xB34D, 0xB87C, 0x8FD2, + 0xB87E, 0x004B, 0xB87C, 0x8691, 0xB87E, 0x007D, 0xB87E, 0x00AF, + 0xB87E, 0x00E1, 0xB87E, 0x00FF, 0xB87C, 0x867F, 0xB87E, 0x0201, + 0xB87E, 0x0201, 0xB87E, 0x0201, 0xB87E, 0x0201, 0xB87E, 0x0201, + 0xB87E, 0x0201, 0xB87C, 0x86DA, 0xB87E, 0xCDCD, 0xB87E, 0xE6CD, + 0xB87E, 0xCDCD, 0xB87C, 0x8FE8, 0xB87E, 0x0368, 0xB87E, 0x033F, + 0xB87E, 0x1046, 0xB87E, 0x147D, 0xB87E, 0x147D, 0xB87E, 0x147D, + 0xB87E, 0x0368, 0xB87E, 0x033F, 0xB87E, 0x1046, 0xB87E, 0x147D, + 0xB87E, 0x147D, 0xB87E, 0x147D, 0xa436, 0x80dd, 0xa438, 0xf0AB, + 0xa436, 0x80df, 0xa438, 0xC009, 0xa436, 0x80e7, 0xa438, 0x401E, + 0xa436, 0x80e1, 0xa438, 0x120A, 0xa436, 0x86f2, 0xa438, 0x5094, + 0xa436, 0x8701, 0xa438, 0x5094, 0xa436, 0x80f1, 0xa438, 0x30CC, + 0xa436, 0x80f3, 0xa438, 0x0001, 0xa436, 0x80f5, 0xa438, 0x330B, + 0xa436, 0x80f8, 0xa438, 0xCB76, 0xa436, 0x8105, 0xa438, 0xf0D3, + 0xa436, 0x8107, 0xa438, 0x0002, 0xa436, 0x8109, 0xa438, 0xff0B, + 0xa436, 0x810c, 0xa438, 0xC86D, 0xB87C, 0x8a32, 0xB87E, 0x0400, + 0xa6f8, 0x0000, 0xa6f8, 0x0000, 0xa436, 0x81bc, 0xa438, 0x1300, + 0xa846, 0x2410, 0xa86A, 0x0801, 0xa85C, 0x9680, 0xa436, 0x841D, + 0xa438, 0x4A28, 0xa436, 0x8016, 0xa438, 0xBE05, 0xBF9C, 0x004A, + 0xBF96, 0x41FA, 0xBF9A, 0xDC81, 0xa436, 0x8018, 0xa438, 0x0700, + 0xa436, 0x8ff4, 0xa438, 0x01AE, 0xa436, 0x8fef, 0xa438, 0x0172, + 0xa438, 0x00dc, 0xc842, 0x0002, 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8126a_1_3[] = { + 0xb892, 0x0000, 0xB88E, 0xC236, 0xB890, 0x1A1C, 0xB88E, 0xC238, + 0xB890, 0x1C1C, 0xB890, 0x1C1C, 0xB890, 0x2D2D, 0xB890, 0x2D2D, + 0xB890, 0x2D2A, 0xB890, 0x2A2A, 0xB890, 0x2A2A, 0xB890, 0x2A19, + 0xB88E, 0xC272, 0xB890, 0x8484, 0xB890, 0x8484, 0xB890, 0x84B4, + 0xB890, 0xB4B4, 0xB890, 0xB4B4, 0xB890, 0xF8F8, 0xB890, 0xF8F8, + 0xB890, 0xF8F8, 0xB88E, 0xC000, 0xB890, 0x0303, 0xB890, 0x0405, + 0xB890, 0x0608, 0xB890, 0x0A0B, 0xB890, 0x0E11, 0xB890, 0x1519, + 0xB890, 0x2028, 0xB890, 0x3503, 0xB890, 0x0304, 0xB890, 0x0405, + 0xB890, 0x0606, 0xB890, 0x0708, 0xB890, 0x090A, 0xB890, 0x0B0D, + 0xB890, 0x0F11, 0xB890, 0x1315, 0xB890, 0x181A, 0xB890, 0x2029, + 0xB890, 0x2F36, 0xB890, 0x3D43, 0xB890, 0x0101, 0xB890, 0x0102, + 0xB890, 0x0202, 0xB890, 0x0303, 0xB890, 0x0405, 0xB890, 0x0607, + 0xB890, 0x090A, 0xB890, 0x0C0E, 0xB88E, 0xC038, 0xB890, 0x6AE1, + 0xB890, 0x8E6B, 0xB890, 0xA767, 0xB890, 0x01EF, 0xB890, 0x5A63, + 0xB890, 0x2B99, 0xB890, 0x7F5D, 0xB890, 0x361F, 0xB890, 0xA127, + 0xB890, 0xB558, 0xB890, 0x11C3, 0xB890, 0x7D85, 0xB890, 0xBAC5, + 0xB890, 0xE691, 0xB890, 0x8F79, 0xB890, 0x3164, 0xB890, 0x3293, + 0xB890, 0xB80D, 0xB890, 0xE2B7, 0xB890, 0x0D62, 0xB890, 0x4F85, + 0xB890, 0xC919, 0xB890, 0x78F3, 0xB890, 0x77FF, 0xB890, 0xBD9E, + 0xB890, 0x69D6, 0xB890, 0x6DA4, 0xB890, 0x0CC5, 0xB88E, 0xC1D2, + 0xB890, 0x2425, 0xB890, 0x2627, 0xB890, 0x2829, 0xB890, 0x2A2B, + 0xB890, 0x2C2D, 0xB890, 0x2E2F, 0xB890, 0x3031, 0xB890, 0x3233, + 0xB890, 0x2323, 0xB890, 0x2424, 0xB890, 0x2525, 0xB890, 0x2626, + 0xB890, 0x2727, 0xB890, 0x2828, 0xB890, 0x2929, 0xB890, 0x2A2A, + 0xB890, 0x2B2C, 0xB890, 0x2C2D, 0xB890, 0x2D2E, 0xB890, 0x2E2F, + 0xB890, 0x2F30, 0xB890, 0x1A1B, 0xB890, 0x1D1E, 0xB890, 0x1F20, + 0xB890, 0x2123, 0xB890, 0x2425, 0xB890, 0x2628, 0xB890, 0x292A, + 0xB890, 0x2B2C, 0xB890, 0x2E12, 0xB88E, 0xC09A, 0xB890, 0xD3D3, + 0xB890, 0xD3D3, 0xB890, 0xD3D3, 0xB890, 0xD3D3, 0xB890, 0xD3D3, + 0xB890, 0xD3D3, 0xB890, 0xD3D3, 0xB890, 0xD3D3, 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8126a_2_1[] = { + 0xa436, 0x8023, 0xa438, 0x4700, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x8025, 0xa438, 0x1800, 0xa438, 0x8033, + 0xa438, 0x1800, 0xa438, 0x8037, 0xa438, 0x1800, 0xa438, 0x803c, + 0xa438, 0x1800, 0xa438, 0x8044, 0xa438, 0x1800, 0xa438, 0x8054, + 0xa438, 0x1800, 0xa438, 0x8059, 0xa438, 0xd504, 0xa438, 0xc9b5, + 0xa438, 0xd500, 0xa438, 0xd707, 0xa438, 0x4070, 0xa438, 0x1800, + 0xa438, 0x107a, 0xa438, 0xd504, 0xa438, 0xc994, 0xa438, 0xd500, + 0xa438, 0xd707, 0xa438, 0x60d0, 0xa438, 0xd701, 0xa438, 0x252d, + 0xa438, 0x8023, 0xa438, 0x1800, 0xa438, 0x1064, 0xa438, 0x1800, + 0xa438, 0x107a, 0xa438, 0x1800, 0xa438, 0x1052, 0xa438, 0xd504, + 0xa438, 0xc9d0, 0xa438, 0xd500, 0xa438, 0xd707, 0xa438, 0x60d0, + 0xa438, 0xd701, 0xa438, 0x252d, 0xa438, 0x8031, 0xa438, 0x1800, + 0xa438, 0x1171, 0xa438, 0x1800, 0xa438, 0x1187, 0xa438, 0x1800, + 0xa438, 0x116a, 0xa438, 0xc0ff, 0xa438, 0xcaff, 0xa438, 0x1800, + 0xa438, 0x00d6, 0xa438, 0xd504, 0xa438, 0xa001, 0xa438, 0xd704, + 0xa438, 0x1800, 0xa438, 0x128b, 0xa438, 0xd707, 0xa438, 0x2005, + 0xa438, 0x8042, 0xa438, 0xd75e, 0xa438, 0x1800, 0xa438, 0x137a, + 0xa438, 0x1800, 0xa438, 0x13ed, 0xa438, 0x61d0, 0xa438, 0xd701, + 0xa438, 0x60a5, 0xa438, 0xd504, 0xa438, 0xc9b2, 0xa438, 0xd500, + 0xa438, 0xf004, 0xa438, 0xd504, 0xa438, 0xc9b1, 0xa438, 0xd500, + 0xa438, 0xd707, 0xa438, 0x6070, 0xa438, 0x1800, 0xa438, 0x10a8, + 0xa438, 0x1800, 0xa438, 0x10bd, 0xa438, 0xd500, 0xa438, 0xc492, + 0xa438, 0xd501, 0xa438, 0x1800, 0xa438, 0x13c1, 0xa438, 0xa980, + 0xa438, 0xd500, 0xa438, 0x1800, 0xa438, 0x143b, 0xa436, 0xA026, + 0xa438, 0x143a, 0xa436, 0xA024, 0xa438, 0x13c0, 0xa436, 0xA022, + 0xa438, 0x10bc, 0xa436, 0xA020, 0xa438, 0x1379, 0xa436, 0xA006, + 0xa438, 0x128a, 0xa436, 0xA004, 0xa438, 0x00d5, 0xa436, 0xA002, + 0xa438, 0x1182, 0xa436, 0xA000, 0xa438, 0x1075, 0xa436, 0xA008, + 0xa438, 0xff00, 0xa436, 0xA016, 0xa438, 0x0010, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x8015, 0xa438, 0x1800, 0xa438, 0x801a, + 0xa438, 0x1800, 0xa438, 0x801e, 0xa438, 0x1800, 0xa438, 0x8027, + 0xa438, 0x1800, 0xa438, 0x8027, 0xa438, 0x1800, 0xa438, 0x8027, + 0xa438, 0x1800, 0xa438, 0x8027, 0xa438, 0x0c0f, 0xa438, 0x0505, + 0xa438, 0xba01, 0xa438, 0x1800, 0xa438, 0x015e, 0xa438, 0x0c0f, + 0xa438, 0x0506, 0xa438, 0xba02, 0xa438, 0x1800, 0xa438, 0x017c, + 0xa438, 0x9910, 0xa438, 0x9a03, 0xa438, 0x1800, 0xa438, 0x02d4, + 0xa438, 0x8580, 0xa438, 0xc090, 0xa438, 0x9a03, 0xa438, 0x1000, + 0xa438, 0x02c9, 0xa438, 0xd700, 0xa438, 0x5fa3, 0xa438, 0x1800, + 0xa438, 0x0067, 0xa436, 0xA08E, 0xa438, 0xffff, 0xa436, 0xA08C, + 0xa438, 0xffff, 0xa436, 0xA08A, 0xa438, 0xffff, 0xa436, 0xA088, + 0xa438, 0xffff, 0xa436, 0xA086, 0xa438, 0x018c, 0xa436, 0xA084, + 0xa438, 0x02d3, 0xa436, 0xA082, 0xa438, 0x017a, 0xa436, 0xA080, + 0xa438, 0x015c, 0xa436, 0xA090, 0xa438, 0x000f, 0xa436, 0xA016, + 0xa438, 0x0020, 0xa436, 0xA012, 0xa438, 0x0000, 0xa436, 0xA014, + 0xa438, 0x1800, 0xa438, 0x8010, 0xa438, 0x1800, 0xa438, 0x8023, + 0xa438, 0x1800, 0xa438, 0x8313, 0xa438, 0x1800, 0xa438, 0x831a, + 0xa438, 0x1800, 0xa438, 0x8489, 0xa438, 0x1800, 0xa438, 0x86b9, + 0xa438, 0x1800, 0xa438, 0x86c1, 0xa438, 0x1800, 0xa438, 0x87ad, + 0xa438, 0x1000, 0xa438, 0x124e, 0xa438, 0x9308, 0xa438, 0xb201, + 0xa438, 0xb301, 0xa438, 0xd701, 0xa438, 0x5fe0, 0xa438, 0xd2ff, + 0xa438, 0xb302, 0xa438, 0xd200, 0xa438, 0xb201, 0xa438, 0xb309, + 0xa438, 0xd701, 0xa438, 0x5fe0, 0xa438, 0xd2ff, 0xa438, 0xb302, + 0xa438, 0xd200, 0xa438, 0x1800, 0xa438, 0x0025, 0xa438, 0xd706, + 0xa438, 0x6069, 0xa438, 0xd700, 0xa438, 0x6421, 0xa438, 0xd70c, + 0xa438, 0x43ab, 0xa438, 0x800a, 0xa438, 0x8190, 0xa438, 0x8204, + 0xa438, 0xa280, 0xa438, 0x8406, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xa108, 0xa438, 0x9503, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0x0c1f, 0xa438, 0x0f19, 0xa438, 0x9503, 0xa438, 0x1000, + 0xa438, 0x1175, 0xa438, 0xd70c, 0xa438, 0x5fb3, 0xa438, 0x0c03, + 0xa438, 0x1502, 0xa438, 0x8f1f, 0xa438, 0x9503, 0xa438, 0x1000, + 0xa438, 0x1175, 0xa438, 0xd70c, 0xa438, 0x7f33, 0xa438, 0x1000, + 0xa438, 0x11bd, 0xa438, 0x1800, 0xa438, 0x81aa, 0xa438, 0x8710, + 0xa438, 0xd701, 0xa438, 0x33b1, 0xa438, 0x8051, 0xa438, 0xd701, + 0xa438, 0x60b5, 0xa438, 0xd706, 0xa438, 0x6069, 0xa438, 0x1800, + 0xa438, 0x8056, 0xa438, 0xa00a, 0xa438, 0xa280, 0xa438, 0xa404, + 0xa438, 0x1800, 0xa438, 0x80f3, 0xa438, 0xd173, 0xa438, 0xd04d, + 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xd700, 0xa438, 0x5fb4, + 0xa438, 0xd173, 0xa438, 0xd05d, 0xa438, 0xd10d, 0xa438, 0xd049, + 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xd700, 0xa438, 0x5fb4, + 0xa438, 0xd700, 0xa438, 0x64f5, 0xa438, 0xd700, 0xa438, 0x5ee7, + 0xa438, 0xb920, 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xd71f, + 0xa438, 0x7fb4, 0xa438, 0x9920, 0xa438, 0xcb3c, 0xa438, 0x1000, + 0xa438, 0x1175, 0xa438, 0xd71f, 0xa438, 0x7d94, 0xa438, 0x6045, + 0xa438, 0xfffa, 0xa438, 0xb820, 0xa438, 0x1000, 0xa438, 0x1175, + 0xa438, 0xd71f, 0xa438, 0x7fa5, 0xa438, 0x9820, 0xa438, 0xcb3d, + 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xd700, 0xa438, 0x60b5, + 0xa438, 0xd71f, 0xa438, 0x7bb4, 0xa438, 0x61b6, 0xa438, 0xfff8, + 0xa438, 0xbb80, 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xd71f, + 0xa438, 0x5fb4, 0xa438, 0x9b80, 0xa438, 0xd700, 0xa438, 0x60e7, + 0xa438, 0xcb3f, 0xa438, 0x1800, 0xa438, 0x8094, 0xa438, 0xcb3e, + 0xa438, 0x1800, 0xa438, 0x810f, 0xa438, 0x1800, 0xa438, 0x80f3, + 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0xae04, 0xa438, 0x9503, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0x8e04, 0xa438, 0x9503, 0xa438, 0xd706, 0xa438, 0x65fe, + 0xa438, 0x0c1f, 0xa438, 0x0d04, 0xa438, 0x8dc0, 0xa438, 0x1000, + 0xa438, 0x11bd, 0xa438, 0xd70c, 0xa438, 0x414b, 0xa438, 0x0cc0, + 0xa438, 0x0040, 0xa438, 0x0c03, 0xa438, 0x0102, 0xa438, 0x0ce0, + 0xa438, 0x03e0, 0xa438, 0xccce, 0xa438, 0x1800, 0xa438, 0x80b7, + 0xa438, 0x0cc0, 0xa438, 0x0040, 0xa438, 0x0c03, 0xa438, 0x0100, + 0xa438, 0x0ce0, 0xa438, 0x0380, 0xa438, 0xcc9c, 0xa438, 0x8710, + 0xa438, 0x1000, 0xa438, 0x1118, 0xa438, 0xa104, 0xa438, 0x1000, + 0xa438, 0x112a, 0xa438, 0x8104, 0xa438, 0xa202, 0xa438, 0xa140, + 0xa438, 0x1000, 0xa438, 0x112a, 0xa438, 0x8140, 0xa438, 0x1000, + 0xa438, 0x1121, 0xa438, 0xaa0f, 0xa438, 0xa130, 0xa438, 0xaa2f, + 0xa438, 0xa2d5, 0xa438, 0xa405, 0xa438, 0xa720, 0xa438, 0xa00a, + 0xa438, 0x1800, 0xa438, 0x80f3, 0xa438, 0xd704, 0xa438, 0x3cf1, + 0xa438, 0x80d5, 0xa438, 0x0c1f, 0xa438, 0x0d02, 0xa438, 0x1800, + 0xa438, 0x80d7, 0xa438, 0x0c1f, 0xa438, 0x0d01, 0xa438, 0x0cc0, + 0xa438, 0x0d40, 0xa438, 0x1000, 0xa438, 0x11bd, 0xa438, 0x8710, + 0xa438, 0x1000, 0xa438, 0x1118, 0xa438, 0xa108, 0xa438, 0x1000, + 0xa438, 0x112a, 0xa438, 0x8108, 0xa438, 0xa203, 0xa438, 0x8a2f, + 0xa438, 0xa130, 0xa438, 0x8204, 0xa438, 0xa140, 0xa438, 0x1000, + 0xa438, 0x112a, 0xa438, 0x8140, 0xa438, 0x1000, 0xa438, 0x1121, + 0xa438, 0xd17a, 0xa438, 0xd04b, 0xa438, 0x1000, 0xa438, 0x1175, + 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xa204, 0xa438, 0x1000, + 0xa438, 0x1175, 0xa438, 0xd700, 0xa438, 0x5fa7, 0xa438, 0xb920, + 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xd71f, 0xa438, 0x7fb4, + 0xa438, 0x9920, 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xd71f, + 0xa438, 0x6125, 0xa438, 0x6054, 0xa438, 0xfffb, 0xa438, 0x1000, + 0xa438, 0x1175, 0xa438, 0xd700, 0xa438, 0x5fa7, 0xa438, 0x1800, + 0xa438, 0x80f7, 0xa438, 0xb820, 0xa438, 0x1000, 0xa438, 0x1175, + 0xa438, 0xd71f, 0xa438, 0x7fa5, 0xa438, 0x9820, 0xa438, 0x9b01, + 0xa438, 0xd402, 0xa438, 0x1000, 0xa438, 0x110d, 0xa438, 0xd701, + 0xa438, 0x33b1, 0xa438, 0x811c, 0xa438, 0xd701, 0xa438, 0x60b5, + 0xa438, 0xd706, 0xa438, 0x6069, 0xa438, 0x1800, 0xa438, 0x811e, + 0xa438, 0x1800, 0xa438, 0x8183, 0xa438, 0xd70c, 0xa438, 0x40ab, + 0xa438, 0x800a, 0xa438, 0x8110, 0xa438, 0x8284, 0xa438, 0x8404, + 0xa438, 0xa710, 0xa438, 0x8120, 0xa438, 0x8241, 0xa438, 0x1000, + 0xa438, 0x1118, 0xa438, 0xa104, 0xa438, 0x1000, 0xa438, 0x112a, + 0xa438, 0x8104, 0xa438, 0x1000, 0xa438, 0x1121, 0xa438, 0xaa2f, + 0xa438, 0xd70c, 0xa438, 0x438b, 0xa438, 0xa284, 0xa438, 0xd078, + 0xa438, 0x800a, 0xa438, 0x8110, 0xa438, 0xa284, 0xa438, 0x8404, + 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0xa108, 0xa438, 0x9503, + 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0x0c1f, 0xa438, 0x0f19, + 0xa438, 0x9503, 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xd70c, + 0xa438, 0x5fb3, 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0x8f1f, + 0xa438, 0x9503, 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xd70c, + 0xa438, 0x7f33, 0xa438, 0x0c1f, 0xa438, 0x0d06, 0xa438, 0x8dc0, + 0xa438, 0x1000, 0xa438, 0x11bd, 0xa438, 0x8110, 0xa438, 0xa284, + 0xa438, 0xa404, 0xa438, 0xa00a, 0xa438, 0xd70c, 0xa438, 0x40a1, + 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0xad10, 0xa438, 0x9503, + 0xa438, 0xd70c, 0xa438, 0x414b, 0xa438, 0x0cc0, 0xa438, 0x0080, + 0xa438, 0x0c03, 0xa438, 0x0102, 0xa438, 0x0ce0, 0xa438, 0x0340, + 0xa438, 0xcc52, 0xa438, 0x1800, 0xa438, 0x816b, 0xa438, 0x80c0, + 0xa438, 0x8103, 0xa438, 0x83e0, 0xa438, 0x8cff, 0xa438, 0xd193, + 0xa438, 0xd047, 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0x1000, + 0xa438, 0x1193, 0xa438, 0xd700, 0xa438, 0x5f74, 0xa438, 0xa110, + 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0x1000, 0xa438, 0x1193, + 0xa438, 0xd700, 0xa438, 0x5f6a, 0xa438, 0xa180, 0xa438, 0xd1f5, + 0xa438, 0xd049, 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0x1000, + 0xa438, 0x1193, 0xa438, 0xd700, 0xa438, 0x5f74, 0xa438, 0x8710, + 0xa438, 0xa00a, 0xa438, 0x8190, 0xa438, 0x8204, 0xa438, 0xa280, + 0xa438, 0xa404, 0xa438, 0xbb80, 0xa438, 0x1000, 0xa438, 0x1175, + 0xa438, 0xd71f, 0xa438, 0x5fb4, 0xa438, 0xb920, 0xa438, 0x9b80, + 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xd71f, 0xa438, 0x7fb4, + 0xa438, 0x9920, 0xa438, 0x1000, 0xa438, 0x1175, 0xa438, 0xcb33, + 0xa438, 0xd71f, 0xa438, 0x6105, 0xa438, 0x5f74, 0xa438, 0x1000, + 0xa438, 0x1175, 0xa438, 0xd700, 0xa438, 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0x0007, 0xa436, 0xad00, + 0xa438, 0x47ff, 0xa436, 0xad02, 0xa438, 0x3be6, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x67ff, 0xa436, 0xad02, + 0xa438, 0x2066, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x07ff, 0xa436, 0xad02, 0xa438, 0x2264, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x27ff, 0xa436, 0xad02, + 0xa438, 0x2464, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x47ff, 0xa436, 0xad02, 0xa438, 0x2664, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x67ff, 0xa436, 0xad02, + 0xa438, 0x0064, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x87ff, 0xa436, 0xad02, 0xa438, 0x0264, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xa7ff, 0xa436, 0xad02, + 0xa438, 0x0464, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xc7ff, 0xa436, 0xad02, 0xa438, 0x0664, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xe7ff, 0xa436, 0xad02, + 0xa438, 0x0864, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x07ff, 0xa436, 0xad02, 0xa438, 0x0a65, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x27ff, 0xa436, 0xad02, + 0xa438, 0x0c65, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x47ff, 0xa436, 0xad02, 0xa438, 0x0e65, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x67ff, 0xa436, 0xad02, + 0xa438, 0x1065, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x87ff, 0xa436, 0xad02, 0xa438, 0x1266, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xa7ff, 0xa436, 0xad02, + 0xa438, 0x1466, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xc7ff, 0xa436, 0xad02, 0xa438, 0x1666, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xe7ff, 0xa436, 0xad02, + 0xa438, 0x2866, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x0fff, 0xa436, 0xad02, 0xa438, 0x2a66, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x2fff, 0xa436, 0xad02, + 0xa438, 0x2c66, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x4fff, 0xa436, 0xad02, 0xa438, 0x2e66, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x6fff, 0xa436, 0xad02, + 0xa438, 0x20e6, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x0fff, 0xa436, 0xad02, 0xa438, 0x22e4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x2fff, 0xa436, 0xad02, + 0xa438, 0x24e4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x4fff, 0xa436, 0xad02, 0xa438, 0x26e4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x6fff, 0xa436, 0xad02, + 0xa438, 0x00e4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x8fff, 0xa436, 0xad02, 0xa438, 0x02e4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xafff, 0xa436, 0xad02, + 0xa438, 0x04e4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xcfff, 0xa436, 0xad02, 0xa438, 0x06e4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xefff, 0xa436, 0xad02, + 0xa438, 0x08e4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x0fff, 0xa436, 0xad02, 0xa438, 0x0ae5, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x2fff, 0xa436, 0xad02, + 0xa438, 0x0ce5, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x4fff, 0xa436, 0xad02, 0xa438, 0x0ee5, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x6fff, 0xa436, 0xad02, + 0xa438, 0x10e5, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x8fff, 0xa436, 0xad02, 0xa438, 0x12e6, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xafff, 0xa436, 0xad02, + 0xa438, 0x14e6, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xcfff, 0xa436, 0xad02, 0xa438, 0x16e6, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xefff, 0xa436, 0xad02, + 0xa438, 0x28e6, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x17ff, 0xa436, 0xad02, 0xa438, 0x2ae6, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x37ff, 0xa436, 0xad02, + 0xa438, 0x2ce6, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x57ff, 0xa436, 0xad02, 0xa438, 0x2ee6, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x77ff, 0xa436, 0xad02, + 0xa438, 0x2166, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x17ff, 0xa436, 0xad02, 0xa438, 0x2364, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x37ff, 0xa436, 0xad02, + 0xa438, 0x2564, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x57ff, 0xa436, 0xad02, 0xa438, 0x2764, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x77ff, 0xa436, 0xad02, + 0xa438, 0x0164, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x97ff, 0xa436, 0xad02, 0xa438, 0x0364, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xb7ff, 0xa436, 0xad02, + 0xa438, 0x0564, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xd7ff, 0xa436, 0xad02, 0xa438, 0x0764, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xf7ff, 0xa436, 0xad02, + 0xa438, 0x0964, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x17ff, 0xa436, 0xad02, 0xa438, 0x0b65, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x37ff, 0xa436, 0xad02, + 0xa438, 0x0d65, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x57ff, 0xa436, 0xad02, 0xa438, 0x0f65, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x77ff, 0xa436, 0xad02, + 0xa438, 0x1165, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x97ff, 0xa436, 0xad02, 0xa438, 0x1366, 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0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x7fff, 0xa436, 0xad02, + 0xa438, 0x21e6, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x1fff, 0xa436, 0xad02, 0xa438, 0x23e4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x3fff, 0xa436, 0xad02, + 0xa438, 0x25e4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x5fff, 0xa436, 0xad02, 0xa438, 0x27e4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x7fff, 0xa436, 0xad02, + 0xa438, 0x01e4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x9fff, 0xa436, 0xad02, 0xa438, 0x03e4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xbfff, 0xa436, 0xad02, + 0xa438, 0x05e4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xdfff, 0xa436, 0xad02, 0xa438, 0x07e4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0x09e4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x1fff, 0xa436, 0xad02, 0xa438, 0x0be5, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x3fff, 0xa436, 0xad02, + 0xa438, 0x0de5, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x5fff, 0xa436, 0xad02, 0xa438, 0x0fe5, 0xa436, 0xad04, + 0xa438, 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0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xa7ff, 0xa436, 0xad02, + 0xa438, 0x2de5, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xc7ff, 0xa436, 0xad02, 0xa438, 0x2fe5, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xe7ff, 0xa436, 0xad02, + 0xa438, 0x1865, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x8fff, 0xa436, 0xad02, 0xa438, 0x1a65, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xafff, 0xa436, 0xad02, + 0xa438, 0x1c65, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xcfff, 0xa436, 0xad02, 0xa438, 0x1e65, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xefff, 0xa436, 0xad02, + 0xa438, 0x18e5, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x97ff, 0xa436, 0xad02, 0xa438, 0x1ae5, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xb7ff, 0xa436, 0xad02, + 0xa438, 0x1ce5, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xd7ff, 0xa436, 0xad02, 0xa438, 0x1ee5, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xf7ff, 0xa436, 0xad02, + 0xa438, 0x1965, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x9fff, 0xa436, 0xad02, 0xa438, 0x1b65, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xbfff, 0xa436, 0xad02, + 0xa438, 0x1d65, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xdfff, 0xa436, 0xad02, 0xa438, 0x1f65, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0x19e5, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x07ff, 0xa436, 0xad02, 0xa438, 0x1b9c, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x27ff, 0xa436, 0xad02, + 0xa438, 0x1d9c, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x0fff, 0xa436, 0xad02, 0xa438, 0x1f9c, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 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0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0x5bff, 0xa436, 0xad04, 0xa438, 0x110e, 0xa436, 0xad06, + 0xa438, 0xfff6, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0x5fff, 0xa436, 0xad04, + 0xa438, 0x114e, 0xa436, 0xad06, 0xa438, 0xf817, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xffff, 0xa436, 0xad04, 0xa438, 0x120f, 0xa436, 0xad06, + 0xa438, 0xf836, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xc3c7, 0xa436, 0xad02, 0xa438, 0xffe3, 0xa436, 0xad04, + 0xa438, 0x124f, 0xa436, 0xad06, 0xa438, 0x0997, 0xa436, 0xad08, + 0xa438, 0x0004, 0xa436, 0xad00, 0xa438, 0xe3e7, 0xa436, 0xad02, + 0xa438, 0xffe3, 0xa436, 0xad04, 0xa438, 0x130f, 0xa436, 0xad06, + 0xa438, 0x19b6, 0xa436, 0xad08, 0xa438, 0x0004, 0xa436, 0xad00, + 0xa438, 0x0307, 0xa436, 0xad02, 0xa438, 0xffe3, 0xa436, 0xad04, + 0xa438, 0x134f, 0xa436, 0xad06, 0xa438, 0x4917, 0xa436, 0xad08, + 0xa438, 0x0004, 0xa436, 0xad00, 0xa438, 0x2327, 0xa436, 0xad02, + 0xa438, 0xffe3, 0xa436, 0xad04, 0xa438, 0x510f, 0xa436, 0xad06, + 0xa438, 0x5936, 0xa436, 0xad08, 0xa438, 0x0004, 0xa436, 0xad00, + 0xa438, 0x4347, 0xa436, 0xad02, 0xa438, 0xffe3, 0xa436, 0xad04, + 0xa438, 0x514f, 0xa436, 0xad06, 0xa438, 0x0997, 0xa436, 0xad08, + 0xa438, 0x0004, 0xa436, 0xad00, 0xa438, 0x6367, 0xa436, 0xad02, + 0xa438, 0xffe3, 0xa436, 0xad04, 0xa438, 0x500f, 0xa436, 0xad06, + 0xa438, 0x19b6, 0xa436, 0xad08, 0xa438, 0x0004, 0xa436, 0xad00, + 0xa438, 0x8387, 0xa436, 0xad02, 0xa438, 0xffe3, 0xa436, 0xad04, + 0xa438, 0x504f, 0xa436, 0xad06, 0xa438, 0x4817, 0xa436, 0xad08, + 0xa438, 0x0004, 0xa436, 0xad00, 0xa438, 0xa3a7, 0xa436, 0xad02, + 0xa438, 0xffe3, 0xa436, 0xad04, 0xa438, 0x520f, 0xa436, 0xad06, + 0xa438, 0x5836, 0xa436, 0xad08, 0xa438, 0x0004, 0xa436, 0xad00, + 0xa438, 0xcbcf, 0xa436, 0xad02, 0xa438, 0xffe3, 0xa436, 0xad04, + 0xa438, 0x524f, 0xa436, 0xad06, 0xa438, 0x0997, 0xa436, 0xad08, + 0xa438, 0x0004, 0xa436, 0xad00, 0xa438, 0xebef, 0xa436, 0xad02, + 0xa438, 0xffe3, 0xa436, 0xad04, 0xa438, 0x530f, 0xa436, 0xad06, + 0xa438, 0x19b6, 0xa436, 0xad08, 0xa438, 0x0004, 0xa436, 0xad00, + 0xa438, 0x0b0f, 0xa436, 0xad02, 0xa438, 0xffe3, 0xa436, 0xad04, + 0xa438, 0x534f, 0xa436, 0xad06, 0xa438, 0x4917, 0xa436, 0xad08, + 0xa438, 0x0004, 0xa436, 0xad00, 0xa438, 0x2b2f, 0xa436, 0xad02, + 0xa438, 0xffe3, 0xa436, 0xad04, 0xa438, 0x920f, 0xa436, 0xad06, + 0xa438, 0x5936, 0xa436, 0xad08, 0xa438, 0x0004, 0xa436, 0xad00, + 0xa438, 0x4b4f, 0xa436, 0xad02, 0xa438, 0xffe3, 0xa436, 0xad04, + 0xa438, 0x924f, 0xa436, 0xad06, 0xa438, 0x0997, 0xa436, 0xad08, + 0xa438, 0x0004, 0xa436, 0xad00, 0xa438, 0x6b6f, 0xa436, 0xad02, + 0xa438, 0xffe3, 0xa436, 0xad04, 0xa438, 0x900f, 0xa436, 0xad06, + 0xa438, 0x19b6, 0xa436, 0xad08, 0xa438, 0x0004, 0xa436, 0xad00, + 0xa438, 0x8b8f, 0xa436, 0xad02, 0xa438, 0xffe3, 0xa436, 0xad04, + 0xa438, 0x904f, 0xa436, 0xad06, 0xa438, 0x4817, 0xa436, 0xad08, + 0xa438, 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0xa438, 0x27ff, 0xa436, 0xad02, + 0xa438, 0xffa4, 0xa436, 0xad04, 0xa438, 0xffff, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x47ff, 0xa436, 0xad02, 0xa438, 0xffa4, 0xa436, 0xad04, + 0xa438, 0xffff, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x67ff, 0xa436, 0xad02, + 0xa438, 0x58a4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x0fff, 0xa436, 0xad02, 0xa438, 0x5ca4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x2fff, 0xa436, 0xad02, + 0xa438, 0x50a4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x4fff, 0xa436, 0xad02, 0xa438, 0x54a4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x6fff, 0xa436, 0xad02, + 0xa438, 0x59a4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x17ff, 0xa436, 0xad02, 0xa438, 0x5da4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x37ff, 0xa436, 0xad02, + 0xa438, 0x51a4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x57ff, 0xa436, 0xad02, 0xa438, 0x55a4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x77ff, 0xa436, 0xad02, + 0xa438, 0x5aa4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x1fff, 0xa436, 0xad02, 0xa438, 0x5ea4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x3fff, 0xa436, 0xad02, + 0xa438, 0x52a4, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0x5fff, 0xa436, 0xad02, 0xa438, 0x56a4, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0x7fff, 0xa436, 0xad02, + 0xa438, 0x5ba4, 0xa436, 0xad04, 0xa438, 0x2a06, 0xa436, 0xad06, + 0xa438, 0xfff6, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0x5fff, 0xa436, 0xad04, + 0xa438, 0x2b06, 0xa436, 0xad06, 0xa438, 0xfff7, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0x53ff, 0xa436, 0xad04, 0xa438, 0x2a06, 0xa436, 0xad06, + 0xa438, 0xfff4, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0x57ff, 0xa436, 0xad04, + 0xa438, 0x2b06, 0xa436, 0xad06, 0xa438, 0xf615, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xffff, 0xa436, 0xad04, 0xa438, 0xffff, 0xa436, 0xad06, + 0xa438, 0xf63f, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xffff, 0xa436, 0xad04, + 0xa438, 0xffff, 0xa436, 0xad06, 0xa438, 0x069f, 0xa436, 0xad08, + 0xa438, 0x0003, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xffff, 0xa436, 0xad04, 0xa438, 0xffff, 0xa436, 0xad06, + 0xa438, 0x16bf, 0xa436, 0xad08, 0xa438, 0x0003, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xffff, 0xa436, 0xad04, + 0xa438, 0xffff, 0xa436, 0xad06, 0xa438, 0x4fff, 0xa436, 0xad08, + 0xa438, 0x0003, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xd0ff, 0xa436, 0xad04, 0xa438, 0x6a46, 0xa436, 0xad06, + 0xa438, 0x5ff6, 0xa436, 0xad08, 0xa438, 0x0003, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xd4ff, 0xa436, 0xad04, + 0xa438, 0x6b46, 0xa436, 0xad06, 0xa438, 0xfff7, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xd8ff, 0xa436, 0xad04, 0xa438, 0x6a46, 0xa436, 0xad06, + 0xa438, 0xfff4, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xdcff, 0xa436, 0xad04, + 0xa438, 0x6b46, 0xa436, 0xad06, 0xa438, 0xf615, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xffff, 0xa436, 0xad04, 0xa438, 0xffff, 0xa436, 0xad06, + 0xa438, 0xf63f, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xffff, 0xa436, 0xad04, + 0xa438, 0xffff, 0xa436, 0xad06, 0xa438, 0x069f, 0xa436, 0xad08, + 0xa438, 0x0003, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xffff, 0xa436, 0xad04, 0xa438, 0xffff, 0xa436, 0xad06, + 0xa438, 0x16bf, 0xa436, 0xad08, 0xa438, 0x0003, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xffff, 0xa436, 0xad04, + 0xa438, 0xffff, 0xa436, 0xad06, 0xa438, 0x4fff, 0xa436, 0xad08, + 0xa438, 0x0003, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xd1ff, 0xa436, 0xad04, 0xa438, 0xaa86, 0xa436, 0xad06, + 0xa438, 0x5ff6, 0xa436, 0xad08, 0xa438, 0x0003, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xd5ff, 0xa436, 0xad04, + 0xa438, 0xab86, 0xa436, 0xad06, 0xa438, 0xfff7, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xd9ff, 0xa436, 0xad04, 0xa438, 0xaa86, 0xa436, 0xad06, + 0xa438, 0xfff4, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xddff, 0xa436, 0xad04, + 0xa438, 0xab86, 0xa436, 0xad06, 0xa438, 0xf615, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xffff, 0xa436, 0xad04, 0xa438, 0xffff, 0xa436, 0xad06, + 0xa438, 0xf63f, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xffff, 0xa436, 0xad04, + 0xa438, 0xffff, 0xa436, 0xad06, 0xa438, 0x069f, 0xa436, 0xad08, + 0xa438, 0x0003, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xffff, 0xa436, 0xad04, 0xa438, 0xffff, 0xa436, 0xad06, + 0xa438, 0x16bf, 0xa436, 0xad08, 0xa438, 0x0003, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xffff, 0xa436, 0xad04, + 0xa438, 0xffff, 0xa436, 0xad06, 0xa438, 0x4fff, 0xa436, 0xad08, + 0xa438, 0x0003, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xd2ff, 0xa436, 0xad04, 0xa438, 0xeac6, 0xa436, 0xad06, + 0xa438, 0x5ff6, 0xa436, 0xad08, 0xa438, 0x0003, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xd6ff, 0xa436, 0xad04, + 0xa438, 0xebc6, 0xa436, 0xad06, 0xa438, 0xfff7, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xdaff, 0xa436, 0xad04, 0xa438, 0xeac6, 0xa436, 0xad06, + 0xa438, 0xfff4, 0xa436, 0xad08, 0xa438, 0x0007, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xdeff, 0xa436, 0xad04, + 0xa438, 0xebc6, 0xa436, 0xad06, 0xa438, 0xf615, 0xa436, 0xad08, + 0xa438, 0x0007, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xffff, 0xa436, 0xad04, 0xa438, 0xffff, 0xa436, 0xad06, + 0xa438, 0xf63f, 0xa436, 0xad08, 0xa438, 0x0017, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xffff, 0xa436, 0xad04, + 0xa438, 0xffff, 0xa436, 0xad06, 0xa438, 0x069f, 0xa436, 0xad08, + 0xa438, 0x0013, 0xa436, 0xad00, 0xa438, 0xffff, 0xa436, 0xad02, + 0xa438, 0xffff, 0xa436, 0xad04, 0xa438, 0xffff, 0xa436, 0xad06, + 0xa438, 0x16bf, 0xa436, 0xad08, 0xa438, 0x0013, 0xa436, 0xad00, + 0xa438, 0xffff, 0xa436, 0xad02, 0xa438, 0xffff, 0xa436, 0xad04, + 0xa438, 0xffff, 0xa436, 0xad06, 0xa438, 0x4fff, 0xa436, 0xad08, + 0xa438, 0x0013, 0xa436, 0xad00, 0xa438, 0xfffa, 0xa436, 0xad02, + 0xa438, 0xd3ff, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0x5fff, 0xa436, 0xad08, 0xa438, 0x0013, 0xa436, 0xad00, + 0xa438, 0xc7ff, 0xa436, 0xad02, 0xa438, 0xd7e7, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0017, 0xa436, 0xad00, 0xa438, 0xe7ff, 0xa436, 0xad02, + 0xa438, 0xdbe7, 0xa436, 0xad04, 0xa438, 0xfffe, 0xa436, 0xad06, + 0xa438, 0xffff, 0xa436, 0xad08, 0xa438, 0x0017, 0xa436, 0xad00, + 0xa438, 0x07ff, 0xa436, 0xad02, 0xa438, 0xdfe7, 0xa436, 0xad04, + 0xa438, 0xfffe, 0xa436, 0xad06, 0xa438, 0xffff, 0xa436, 0xad08, + 0xa438, 0x0017, 0xa436, 0xacfc, 0xa438, 0x0000, 0xa436, 0xaccc, + 0xa438, 0x2000, 0xa436, 0xacce, 0xa438, 0x6000, 0xa436, 0xaccc, + 0xa438, 0x2001, 0xa436, 0xacce, 0xa438, 0x6008, 0xa436, 0xaccc, + 0xa438, 0x2002, 0xa436, 0xacce, 0xa438, 0x6010, 0xa436, 0xaccc, + 0xa438, 0x2003, 0xa436, 0xacce, 0xa438, 0x6020, 0xa436, 0xaccc, + 0xa438, 0x2004, 0xa436, 0xacce, 0xa438, 0x6060, 0xa436, 0xaccc, + 0xa438, 0x2005, 0xa436, 0xacce, 0xa438, 0x60a0, 0xa436, 0xaccc, + 0xa438, 0x2006, 0xa436, 0xacce, 0xa438, 0x60e0, 0xa436, 0xaccc, + 0xa438, 0x2007, 0xa436, 0xacce, 0xa438, 0x6128, 0xa436, 0xaccc, + 0xa438, 0x2008, 0xa436, 0xacce, 0xa438, 0x6178, 0xa436, 0xaccc, + 0xa438, 0x2009, 0xa436, 0xacce, 0xa438, 0x61a8, 0xa436, 0xaccc, + 0xa438, 0x200a, 0xa436, 0xacce, 0xa438, 0x61f0, 0xa436, 0xaccc, + 0xa438, 0x200b, 0xa436, 0xacce, 0xa438, 0x6248, 0xa436, 0xaccc, + 0xa438, 0x200c, 0xa436, 0xacce, 0xa438, 0x6258, 0xa436, 0xaccc, + 0xa438, 0x200d, 0xa436, 0xacce, 0xa438, 0x6268, 0xa436, 0xaccc, + 0xa438, 0x200e, 0xa436, 0xacce, 0xa438, 0x6270, 0xa436, 0xaccc, + 0xa438, 0x200f, 0xa436, 0xacce, 0xa438, 0x6274, 0xa436, 0xaccc, + 0xa438, 0x2010, 0xa436, 0xacce, 0xa438, 0x627c, 0xa436, 0xaccc, + 0xa438, 0x2011, 0xa436, 0xacce, 0xa438, 0x6284, 0xa436, 0xaccc, + 0xa438, 0x2012, 0xa436, 0xacce, 0xa438, 0x6294, 0xa436, 0xaccc, + 0xa438, 0x2013, 0xa436, 0xacce, 0xa438, 0x629c, 0xa436, 0xaccc, + 0xa438, 0x2014, 0xa436, 0xacce, 0xa438, 0x62ac, 0xa436, 0xaccc, + 0xa438, 0x2015, 0xa436, 0xacce, 0xa438, 0x62bc, 0xa436, 0xaccc, + 0xa438, 0x2016, 0xa436, 0xacce, 0xa438, 0x62c4, 0xa436, 0xaccc, + 0xa438, 0x2017, 0xa436, 0xacce, 0xa438, 0x7000, 0xa436, 0xaccc, + 0xa438, 0x2018, 0xa436, 0xacce, 0xa438, 0x6000, 0xa436, 0xaccc, + 0xa438, 0x2019, 0xa436, 0xacce, 0xa438, 0x6000, 0xa436, 0xaccc, + 0xa438, 0x201a, 0xa436, 0xacce, 0xa438, 0x6000, 0xa436, 0xaccc, + 0xa438, 0x201b, 0xa436, 0xacce, 0xa438, 0x6000, 0xa436, 0xaccc, + 0xa438, 0x201c, 0xa436, 0xacce, 0xa438, 0x6000, 0xa436, 0xaccc, + 0xa438, 0x201d, 0xa436, 0xacce, 0xa438, 0x6000, 0xa436, 0xaccc, + 0xa438, 0x201e, 0xa436, 0xacce, 0xa438, 0x6000, 0xa436, 0xaccc, + 0xa438, 0x201f, 0xa436, 0xacce, 0xa438, 0x6000, 0xa436, 0xacce, + 0xa438, 0x0000, 0xa436, 0x0000, 0xa438, 0x0000, 0xb82e, 0x0000, + 0xa436, 0x8023, 0xa438, 0x0000, 0xa436, 0x801E, 0xa438, 0x0027, + 0xB820, 0x0000, 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8126a_2_3[] = { + 0xb892, 0x0000, 0xb88e, 0xC15C, 0xb890, 0x0303, 0xb890, 0x0506, + 0xb890, 0x0807, 0xb890, 0x090B, 0xb890, 0x0E12, 0xb890, 0x1617, + 0xb890, 0x1C24, 0xb890, 0x2B37, 0xb890, 0x0203, 0xb890, 0x0304, + 0xb890, 0x0504, 0xb890, 0x0506, 0xb890, 0x0708, 0xb890, 0x090A, + 0xb890, 0x0B0E, 0xb890, 0x1013, 0xb890, 0x1519, 0xb890, 0x1D22, + 0xb890, 0x282E, 0xb890, 0x363E, 0xb890, 0x474B, 0xb88e, 0xC196, + 0xb890, 0x3F5E, 0xb890, 0xF834, 0xb890, 0x6C01, 0xb890, 0xA67F, + 0xb890, 0xA06C, 0xb890, 0x043B, 0xb890, 0x6190, 0xb890, 0x88DB, + 0xb890, 0x9ECD, 0xb890, 0x4DBC, 0xb890, 0x6E0E, 0xb890, 0x9F2D, + 0xb890, 0x2C18, 0xb890, 0x5E8C, 0xb890, 0x5BFE, 0xb890, 0x183C, + 0xb890, 0x23C9, 0xb890, 0x3E84, 0xb890, 0x3C20, 0xb890, 0xCC56, + 0xb890, 0x3480, 0xb890, 0x0040, 0xb88e, 0xC00F, 0xb890, 0x3502, + 0xb890, 0x0203, 0xb890, 0x0303, 0xb890, 0x0404, 0xb890, 0x0506, + 0xb890, 0x0607, 0xb890, 0x080A, 0xb890, 0x0B0D, 0xb890, 0x0E10, + 0xb890, 0x1114, 0xb890, 0x171B, 0xb890, 0x1F22, 0xb890, 0x2832, + 0xb890, 0x0101, 0xb890, 0x0101, 0xb890, 0x0202, 0xb890, 0x0303, + 0xb890, 0x0404, 0xb890, 0x0506, 0xb890, 0x0709, 0xb890, 0x0A0D, + 0xb88e, 0xC047, 0xb890, 0x365F, 0xb890, 0xBE10, 0xb890, 0x84E4, + 0xb890, 0x60E9, 0xb890, 0xA86A, 0xb890, 0xF1E3, 0xb890, 0xF73F, + 0xb890, 0x5C02, 0xb890, 0x9547, 0xb890, 0xC30C, 0xb890, 0xB064, + 0xb890, 0x079A, 0xb890, 0x1E23, 0xb890, 0x1B5D, 0xb890, 0x92E7, + 0xb890, 0x4BAF, 0xb890, 0x2386, 0xb890, 0x01B6, 0xb890, 0x6F82, + 0xb890, 0xDC1C, 0xb890, 0x8C92, 0xb88e, 0xC110, 0xb890, 0x0C7F, + 0xb890, 0x1014, 0xb890, 0x231D, 0xb890, 0x2023, 0xb890, 0x2628, + 0xb890, 0x2A2D, 0xb890, 0x2D2C, 0xb890, 0x2C2E, 0xb890, 0x320D, + 0xb88e, 0xC186, 0xb890, 0x0306, 0xb890, 0x0804, 0xb890, 0x0406, + 0xb890, 0x0707, 0xb890, 0x0709, 0xb890, 0x0B0F, 0xb890, 0x161D, + 0xb890, 0x202A, 0xb890, 0x3F5E, 0xb88e, 0xC1C1, 0xb890, 0x0040, + 0xb890, 0x5920, 0xb890, 0x88CD, 0xb890, 0x1CA1, 0xb890, 0x3D20, + 0xb890, 0x3AE4, 0xb890, 0x6A43, 0xb890, 0x30AF, 0xb890, 0xDD16, + 0xb88e, 0xC283, 0xb890, 0x1611, 0xb890, 0x161C, 0xb890, 0x2127, + 0xb890, 0x2C32, 0xb890, 0x373D, 0xb890, 0x4247, 0xb890, 0x4D52, + 0xb890, 0x585A, 0xb890, 0x0004, 0xb890, 0x080C, 0xb890, 0x1014, + 0xb890, 0x181B, 0xb890, 0x1F23, 0xb890, 0x272B, 0xb890, 0x2F33, + 0xb890, 0x363A, 0xb890, 0x3E42, 0xb890, 0x464A, 0xb890, 0x4D51, + 0xb890, 0x5559, 0xb890, 0x5D65, 0xb890, 0xE769, 0xb890, 0xEB56, + 0xb890, 0xC04B, 0xb890, 0xD502, 0xb890, 0x2FB1, 0xb890, 0x33B5, + 0xb890, 0x37F8, 0xb890, 0xBB98, 0xb890, 0x7450, 0xb890, 0x4C48, + 0xb890, 0x12DC, 0xb890, 0xDCDC, 0xb890, 0x934A, 0xb890, 0x3E33, + 0xb890, 0xE496, 0xb890, 0x724E, 0xb890, 0x2B07, 0xb890, 0xE4C0, + 0xb890, 0x9C79, 0xb890, 0x5512, 0xb88e, 0xC212, 0xb890, 0x2020, + 0xb890, 0x2020, 0xb890, 0x2020, 0xb890, 0x2020, 0xb890, 0x2020, + 0xb890, 0x2019, 0xb88e, 0xC24D, 0xb890, 0x8400, 0xb890, 0x0000, + 0xb890, 0x0000, 0xb890, 0x0000, 0xb890, 0x0000, 0xb890, 0x0000, + 0xb88e, 0xC2D3, 0xb890, 0x5524, 0xb890, 0x2526, 0xb890, 0x2728, + 0xb88e, 0xC2E3, 0xb890, 0x3323, 0xb890, 0x2324, 0xb890, 0x2425, + 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8126a_3_1[] = { + 0xa436, 0x8023, 0xa438, 0x4701, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x801a, 0xa438, 0x1800, 0xa438, 0x802a, + 0xa438, 0x1800, 0xa438, 0x8032, 0xa438, 0x1800, 0xa438, 0x803a, + 0xa438, 0x1800, 0xa438, 0x803e, 0xa438, 0x1800, 0xa438, 0x8044, + 0xa438, 0x1800, 0xa438, 0x804b, 0xa438, 0xd504, 0xa438, 0xc9b5, + 0xa438, 0xd500, 0xa438, 0xd707, 0xa438, 0x4070, 0xa438, 0x1800, + 0xa438, 0x1082, 0xa438, 0xd504, 0xa438, 0x1800, 0xa438, 0x107a, + 0xa438, 0x61d0, 0xa438, 0xd701, 0xa438, 0x60a5, 0xa438, 0xd504, + 0xa438, 0xc9b2, 0xa438, 0xd500, 0xa438, 0xf004, 0xa438, 0xd504, + 0xa438, 0xc9b1, 0xa438, 0xd500, 0xa438, 0xd707, 0xa438, 0x6070, + 0xa438, 0x1800, 0xa438, 0x10b0, 0xa438, 0x1800, 0xa438, 0x10c5, + 0xa438, 0xd707, 0xa438, 0x2005, 0xa438, 0x8030, 0xa438, 0xd75e, + 0xa438, 0x1800, 0xa438, 0x138c, 0xa438, 0x1800, 0xa438, 0x13ff, + 0xa438, 0xc504, 0xa438, 0xce20, 0xa438, 0xcf01, 0xa438, 0xd70a, + 0xa438, 0x4005, 0xa438, 0xcf02, 0xa438, 0x1800, 0xa438, 0x1b99, + 0xa438, 0xa980, 0xa438, 0xd500, 0xa438, 0x1800, 0xa438, 0x144d, + 0xa438, 0x907f, 0xa438, 0x91a3, 0xa438, 0x9306, 0xa438, 0xb118, + 0xa438, 0x1800, 0xa438, 0x2147, 0xa438, 0x907f, 0xa438, 0x9209, + 0xa438, 0x91a3, 0xa438, 0x9306, 0xa438, 0xb118, 0xa438, 0x1800, + 0xa438, 0x203c, 0xa436, 0xA026, 0xa438, 0xffff, 0xa436, 0xA024, + 0xa438, 0x2033, 0xa436, 0xA022, 0xa438, 0x213f, 0xa436, 0xA020, + 0xa438, 0x144c, 0xa436, 0xA006, 0xa438, 0x1b98, 0xa436, 0xA004, + 0xa438, 0x138b, 0xa436, 0xA002, 0xa438, 0x10c4, 0xa436, 0xA000, + 0xa438, 0x1079, 0xa436, 0xA008, 0xa438, 0x7f00, 0xa436, 0xA016, + 0xa438, 0x0000, 0xa436, 0xA012, 0xa438, 0x0ff8, 0xa436, 0xA014, + 0xa438, 0xd04d, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa436, 0xA152, 0xa438, 0x12dc, 0xa436, 0xA154, 0xa438, 0x3fff, + 0xa436, 0xA156, 0xa438, 0x3fff, 0xa436, 0xA158, 0xa438, 0x3fff, + 0xa436, 0xA15A, 0xa438, 0x3fff, 0xa436, 0xA15C, 0xa438, 0x3fff, + 0xa436, 0xA15E, 0xa438, 0x3fff, 0xa436, 0xA160, 0xa438, 0x3fff, + 0xa436, 0xA150, 0xa438, 0x0001, 0xa436, 0xA016, 0xa438, 0x0020, + 0xa436, 0xA012, 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, + 0xa438, 0x8010, 0xa438, 0x1800, 0xa438, 0x801a, 0xa438, 0x1800, + 0xa438, 0x8022, 0xa438, 0x1800, 0xa438, 0x8112, 0xa438, 0x1800, + 0xa438, 0x8206, 0xa438, 0x1800, 0xa438, 0x8433, 0xa438, 0x1800, + 0xa438, 0x84ed, 0xa438, 0x1800, 0xa438, 0x8583, 0xa438, 0xd706, + 0xa438, 0x60a9, 0xa438, 0xd700, 0xa438, 0x60a1, 0xa438, 0x1800, + 0xa438, 0x0962, 0xa438, 0x1800, 0xa438, 0x0962, 0xa438, 0x1800, + 0xa438, 0x0982, 0xa438, 0x800a, 0xa438, 0x0c1f, 0xa438, 0x0d00, + 0xa438, 0x8dc0, 0xa438, 0x1000, 0xa438, 0x12b5, 0xa438, 0x1800, + 0xa438, 0x0f99, 0xa438, 0xd70d, 0xa438, 0x40fd, 0xa438, 0xd702, + 0xa438, 0x40a0, 0xa438, 0xd70c, 0xa438, 0x4066, 0xa438, 0x8710, + 0xa438, 0xf002, 0xa438, 0xa710, 0xa438, 0x9580, 0xa438, 0x0c03, + 0xa438, 0x1502, 0xa438, 0xa304, 0xa438, 0x9503, 0xa438, 0x0c1f, + 0xa438, 0x0d07, 0xa438, 0x8dc0, 0xa438, 0x1000, 0xa438, 0x12b5, + 0xa438, 0xcb81, 0xa438, 0xd70c, 0xa438, 0x4882, 0xa438, 0xd706, + 0xa438, 0x407a, 0xa438, 0xd70c, 0xa438, 0x4807, 0xa438, 0xd706, + 0xa438, 0x405a, 0xa438, 0x8910, 0xa438, 0xa210, 0xa438, 0xd704, + 0xa438, 0x611c, 0xa438, 0x0cc0, 0xa438, 0x0080, 0xa438, 0x0c03, + 0xa438, 0x0101, 0xa438, 0x0ce0, 0xa438, 0x03a0, 0xa438, 0xccb5, + 0xa438, 0x0cc0, 0xa438, 0x0080, 0xa438, 0x0c03, 0xa438, 0x0102, + 0xa438, 0x0ce0, 0xa438, 0x0340, 0xa438, 0xcc52, 0xa438, 0xd706, + 0xa438, 0x42ba, 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0x0c1f, + 0xa438, 0x0f1c, 0xa438, 0x9503, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0xd70c, 0xa438, 0x5fb3, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0x8f1f, 0xa438, 0x9503, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0xd70c, 0xa438, 0x7f33, 0xa438, 0x8190, 0xa438, 0x8204, + 0xa438, 0xf016, 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0x0c1f, + 0xa438, 0x0f1b, 0xa438, 0x9503, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0xd70c, 0xa438, 0x5fb3, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0x8f1f, 0xa438, 0x9503, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0xd70c, 0xa438, 0x7f33, 0xa438, 0xd70c, 0xa438, 0x6047, + 0xa438, 0xf002, 0xa438, 0xf00c, 0xa438, 0xd403, 0xa438, 0xcb82, + 0xa438, 0x1000, 0xa438, 0x1203, 0xa438, 0xd40a, 0xa438, 0x1000, + 0xa438, 0x1203, 0xa438, 0xd70c, 0xa438, 0x4247, 0xa438, 0x1000, + 0xa438, 0x131d, 0xa438, 0x8a40, 0xa438, 0x1000, 0xa438, 0x120e, + 0xa438, 0xa104, 0xa438, 0x1000, 0xa438, 0x1220, 0xa438, 0x8104, + 0xa438, 0x1000, 0xa438, 0x1217, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xa704, 0xa438, 0x9503, 0xa438, 0xcb88, 0xa438, 0xf012, + 0xa438, 0xa210, 0xa438, 0xa00a, 0xa438, 0xaa40, 0xa438, 0x1000, + 0xa438, 0x120e, 0xa438, 0xa104, 0xa438, 0x1000, 0xa438, 0x1220, + 0xa438, 0x8104, 0xa438, 0x1000, 0xa438, 0x1217, 0xa438, 0xa190, + 0xa438, 0xa284, 0xa438, 0xa404, 0xa438, 0x8a10, 0xa438, 0x8a80, + 0xa438, 0xcb84, 0xa438, 0xd13e, 0xa438, 0xd05a, 0xa438, 0xd13e, + 0xa438, 0xd06b, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd700, + 0xa438, 0x3559, 0xa438, 0x80b0, 0xa438, 0xfffb, 0xa438, 0xd700, + 0xa438, 0x604b, 0xa438, 0xcb8a, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0xd700, 0xa438, 0x3659, 0xa438, 0x80b9, 0xa438, 0xfffb, + 0xa438, 0xd700, 0xa438, 0x606b, 0xa438, 0xcb8b, 0xa438, 0x5eeb, + 0xa438, 0xd700, 0xa438, 0x6041, 0xa438, 0xa402, 0xa438, 0xcb8c, + 0xa438, 0xd706, 0xa438, 0x609a, 0xa438, 0xd1b7, 0xa438, 0xd049, + 0xa438, 0xf003, 0xa438, 0xd160, 0xa438, 0xd04b, 0xa438, 0x1000, + 0xa438, 0x126b, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xcb8d, + 0xa438, 0x8710, 0xa438, 0xd71f, 0xa438, 0x5fd4, 0xa438, 0xb920, + 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd71f, 0xa438, 0x7fb4, + 0xa438, 0x9920, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd71f, + 0xa438, 0x6105, 0xa438, 0x6054, 0xa438, 0xfffb, 0xa438, 0x1000, + 0xa438, 0x126b, 0xa438, 0xd700, 0xa438, 0x5fab, 0xa438, 0xfff0, + 0xa438, 0xa710, 0xa438, 0xb820, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0xd71f, 0xa438, 0x7fa5, 0xa438, 0x9820, 0xa438, 0xd114, + 0xa438, 0xd040, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd700, + 0xa438, 0x5fba, 0xa438, 0xd704, 0xa438, 0x5f76, 0xa438, 0xd700, + 0xa438, 0x5f34, 0xa438, 0xd700, 0xa438, 0x6081, 0xa438, 0xd706, + 0xa438, 0x405a, 0xa438, 0xa480, 0xa438, 0xcb86, 0xa438, 0xd706, + 0xa438, 0x609a, 0xa438, 0xd1c8, 0xa438, 0xd045, 0xa438, 0xf003, + 0xa438, 0xd17a, 0xa438, 0xd04b, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0x0cc0, 0xa438, 0x0000, + 0xa438, 0x0c03, 0xa438, 0x0101, 0xa438, 0x0ce0, 0xa438, 0x0320, + 0xa438, 0xcc29, 0xa438, 0xa208, 0xa438, 0x8204, 0xa438, 0xd114, + 0xa438, 0xd040, 0xa438, 0xd700, 0xa438, 0x5ff4, 0xa438, 0x1800, + 0xa438, 0x0c3e, 0xa438, 0xd706, 0xa438, 0x609d, 0xa438, 0xd417, + 0xa438, 0x1000, 0xa438, 0x1203, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0x1000, 0xa438, 0x1289, 0xa438, 0xd700, 0xa438, 0x5f7a, + 0xa438, 0xd704, 0xa438, 0x5f36, 0xa438, 0xd706, 0xa438, 0x6089, + 0xa438, 0xd40c, 0xa438, 0x1000, 0xa438, 0x1203, 0xa438, 0xaa40, + 0xa438, 0xbb10, 0xa438, 0xcb50, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xa310, 0xa438, 0x9503, 0xa438, 0xcb5f, 0xa438, 0x1000, + 0xa438, 0x126b, 0xa438, 0x1000, 0xa438, 0x1289, 0xa438, 0xd71f, + 0xa438, 0x5f75, 0xa438, 0x8190, 0xa438, 0x82a0, 0xa438, 0x8402, + 0xa438, 0xa404, 0xa438, 0x800a, 0xa438, 0x8718, 0xa438, 0x9b10, + 0xa438, 0x9b20, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd71f, + 0xa438, 0x7fb5, 0xa438, 0xcb51, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0xd71f, 0xa438, 0x5f94, 0xa438, 0xd706, 0xa438, 0x6089, + 0xa438, 0xd141, 0xa438, 0xd043, 0xa438, 0xf003, 0xa438, 0xd141, + 0xa438, 0xd044, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd700, + 0xa438, 0x5fb4, 0xa438, 0xd700, 0xa438, 0x60e5, 0xa438, 0xd704, + 0xa438, 0x60be, 0xa438, 0xd706, 0xa438, 0x29b1, 0xa438, 0x8156, + 0xa438, 0xf002, 0xa438, 0xa880, 0xa438, 0xa00a, 0xa438, 0xa190, + 0xa438, 0x8220, 0xa438, 0xa280, 0xa438, 0xa404, 0xa438, 0xa620, + 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0xc5aa, 0xa438, 0x9503, + 0xa438, 0xd700, 0xa438, 0x6061, 0xa438, 0xa402, 0xa438, 0xa480, + 0xa438, 0xcb52, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd700, + 0xa438, 0x5fba, 0xa438, 0xd704, 0xa438, 0x5f76, 0xa438, 0xb920, + 0xa438, 0xcb53, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd71f, + 0xa438, 0x7fb4, 0xa438, 0x9920, 0xa438, 0xa00a, 0xa438, 0xa190, + 0xa438, 0xa280, 0xa438, 0x8220, 0xa438, 0xa404, 0xa438, 0xb580, + 0xa438, 0xd700, 0xa438, 0x40a1, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xa602, 0xa438, 0x9503, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xa310, 0xa438, 0x9503, 0xa438, 0xcb60, 0xa438, 0xd1c8, + 0xa438, 0xd045, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd700, + 0xa438, 0x5fb4, 0xa438, 0xaa10, 0xa438, 0xd70c, 0xa438, 0x2833, + 0xa438, 0x818f, 0xa438, 0xf003, 0xa438, 0x1000, 0xa438, 0x1330, + 0xa438, 0xd70c, 0xa438, 0x40a6, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xa140, 0xa438, 0x9503, 0xa438, 0xd70c, 0xa438, 0x40a3, + 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0xac20, 0xa438, 0x9503, + 0xa438, 0xa90c, 0xa438, 0xaa80, 0xa438, 0x0c1f, 0xa438, 0x0d07, + 0xa438, 0x8dc0, 0xa438, 0x1000, 0xa438, 0x12b5, 0xa438, 0xa00a, + 0xa438, 0xa190, 0xa438, 0xa280, 0xa438, 0x8220, 0xa438, 0xa404, + 0xa438, 0xb580, 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0xc500, + 0xa438, 0x9503, 0xa438, 0x83e0, 0xa438, 0x8e01, 0xa438, 0xd700, + 0xa438, 0x40a1, 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0xa602, + 0xa438, 0x9503, 0xa438, 0xd14a, 0xa438, 0xd058, 0xa438, 0x1000, + 0xa438, 0x12d7, 0xa438, 0xd70c, 0xa438, 0x4063, 0xa438, 0x1000, + 0xa438, 0x12ea, 0xa438, 0xcb6f, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0xd704, 0xa438, 0x2e70, 0xa438, 0x81fd, 0xa438, 0xd71f, + 0xa438, 0x676e, 0xa438, 0xd704, 0xa438, 0x3868, 0xa438, 0x81d8, + 0xa438, 0xd706, 0xa438, 0x61c2, 0xa438, 0xd70c, 0xa438, 0x2f18, + 0xa438, 0x81de, 0xa438, 0xd700, 0xa438, 0x5d35, 0xa438, 0x0c03, + 0xa438, 0x1502, 0xa438, 0xc5aa, 0xa438, 0x9503, 0xa438, 0x0ce0, + 0xa438, 0x0320, 0xa438, 0x1800, 0xa438, 0x81e4, 0xa438, 0x0c03, + 0xa438, 0x1502, 0xa438, 0xc5aa, 0xa438, 0x9503, 0xa438, 0x1800, + 0xa438, 0x8202, 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0xc5aa, + 0xa438, 0x9503, 0xa438, 0x1800, 0xa438, 0x8204, 0xa438, 0x1000, + 0xa438, 0x12d7, 0xa438, 0xae02, 0xa438, 0xd70c, 0xa438, 0x4063, + 0xa438, 0x1000, 0xa438, 0x12ea, 0xa438, 0xcb61, 0xa438, 0x1000, + 0xa438, 0x126b, 0xa438, 0xd704, 0xa438, 0x2e70, 0xa438, 0x81fd, + 0xa438, 0xd704, 0xa438, 0x3868, 0xa438, 0x8202, 0xa438, 0xd706, + 0xa438, 0x61a2, 0xa438, 0xd71f, 0xa438, 0x612e, 0xa438, 0xd70c, + 0xa438, 0x2f18, 0xa438, 0x8204, 0xa438, 0x1800, 0xa438, 0x81e4, + 0xa438, 0x8e02, 0xa438, 0x1800, 0xa438, 0x0f99, 0xa438, 0x1800, + 0xa438, 0x0e31, 0xa438, 0x1800, 0xa438, 0x8480, 0xa438, 0x1800, + 0xa438, 0x0e07, 0xa438, 0x1000, 0xa438, 0x17be, 0xa438, 0xd70c, + 0xa438, 0x5fa4, 0xa438, 0xa706, 0xa438, 0xd70c, 0xa438, 0x404b, + 0xa438, 0xa880, 0xa438, 0x8801, 0xa438, 0x8e01, 0xa438, 0xca50, + 0xa438, 0x1000, 0xa438, 0x82a9, 0xa438, 0xca51, 0xa438, 0xd70e, + 0xa438, 0x2210, 0xa438, 0x82a7, 0xa438, 0xd70c, 0xa438, 0x4084, + 0xa438, 0xd705, 0xa438, 0x5efd, 0xa438, 0xf007, 0xa438, 0x1000, + 0xa438, 0x17c2, 0xa438, 0xd70c, 0xa438, 0x5ce2, 0xa438, 0x1800, + 0xa438, 0x1692, 0xa438, 0xd70c, 0xa438, 0x605a, 0xa438, 0x9a10, + 0xa438, 0x8e40, 0xa438, 0x8404, 0xa438, 0x1000, 0xa438, 0x1827, + 0xa438, 0x8e80, 0xa438, 0xca62, 0xa438, 0xd705, 0xa438, 0x3084, + 0xa438, 0x8289, 0xa438, 0xba10, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x1000, 0xa438, 0x8382, 0xa438, 0x0c03, 0xa438, 0x0100, + 0xa438, 0xd702, 0xa438, 0x4638, 0xa438, 0xd1c4, 0xa438, 0xd044, + 0xa438, 0x1000, 0xa438, 0x17be, 0xa438, 0x1000, 0xa438, 0x17e8, + 0xa438, 0xd70c, 0xa438, 0x5f7c, 0xa438, 0x8108, 0xa438, 0x0c1f, + 0xa438, 0x0907, 0xa438, 0x8940, 0xa438, 0x1000, 0xa438, 0x17db, + 0xa438, 0xa0c4, 0xa438, 0x8610, 0xa438, 0x8030, 0xa438, 0x8706, + 0xa438, 0x0c07, 0xa438, 0x0b06, 0xa438, 0x8410, 0xa438, 0xa980, + 0xa438, 0xa702, 0xa438, 0xd1c4, 0xa438, 0xd045, 0xa438, 0x1000, + 0xa438, 0x17be, 0xa438, 0x1000, 0xa438, 0x17e8, 0xa438, 0xd70c, + 0xa438, 0x5f7c, 0xa438, 0x0c07, 0xa438, 0x0b06, 0xa438, 0xa030, + 0xa438, 0xa610, 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0xa438, 0x1000, + 0xa438, 0x1217, 0xa438, 0x0c03, 0xa438, 0x0902, 0xa438, 0x1800, + 0xa438, 0x04ed, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd71f, + 0xa438, 0x5fab, 0xa438, 0xba08, 0xa438, 0x1000, 0xa438, 0x126b, + 0xa438, 0xd71f, 0xa438, 0x7f8b, 0xa438, 0x9a08, 0xa438, 0x1800, + 0xa438, 0x0581, 0xa438, 0x800a, 0xa438, 0xd702, 0xa438, 0x6555, + 0xa438, 0x1000, 0xa438, 0x120e, 0xa438, 0xa004, 0xa438, 0x1000, + 0xa438, 0x1220, 0xa438, 0x8004, 0xa438, 0xa001, 0xa438, 0x1000, + 0xa438, 0x1220, 0xa438, 0x8001, 0xa438, 0x1000, 0xa438, 0x1217, + 0xa438, 0xa00a, 0xa438, 0xa780, 0xa438, 0xcb14, 0xa438, 0xd1b8, + 0xa438, 0xd04a, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd700, + 0xa438, 0x5fb4, 0xa438, 0x6286, 0xa438, 0xd706, 0xa438, 0x5f5b, + 0xa438, 0x800a, 0xa438, 0x1000, 0xa438, 0x120e, 0xa438, 0xa004, + 0xa438, 0x1000, 0xa438, 0x1220, 0xa438, 0x8004, 0xa438, 0xa001, + 0xa438, 0x1000, 0xa438, 0x1220, 0xa438, 0x8001, 0xa438, 0x1000, + 0xa438, 0x1217, 0xa438, 0x0c03, 0xa438, 0x0902, 0xa438, 0x1800, + 0xa438, 0x8545, 0xa438, 0xa00a, 0xa438, 0x9308, 0xa438, 0xb210, + 0xa438, 0xb301, 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd701, + 0xa438, 0x5fa4, 0xa438, 0xb302, 0xa438, 0x9210, 0xa438, 0xd409, + 0xa438, 0x1000, 0xa438, 0x1203, 0xa438, 0xd103, 0xa438, 0xd04c, + 0xa438, 0x1000, 0xa438, 0x126b, 0xa438, 0xd700, 0xa438, 0x5fb4, + 0xa438, 0x1800, 0xa438, 0x0581, 0xa438, 0xd70c, 0xa438, 0x60b3, + 0xa438, 0x1800, 0xa438, 0x8587, 0xa438, 0x1800, 0xa438, 0x001a, + 0xa438, 0x1800, 0xa438, 0x12cb, 0xa436, 0xA10E, 0xa438, 0x12cf, + 0xa436, 0xA10C, 0xa438, 0x04f8, 0xa436, 0xA10A, 0xa438, 0x1003, + 0xa436, 0xA108, 0xa438, 0x15fb, 0xa436, 0xA106, 0xa438, 0x0d2b, + 0xa436, 0xA104, 0xa438, 0x0ecb, 0xa436, 0xA102, 0xa438, 0x1119, + 0xa436, 0xA100, 0xa438, 0x0960, 0xa436, 0xA110, 0xa438, 0x00ff, + 0xa436, 0xA016, 0xa438, 0x0020, 0xa436, 0xA012, 0xa438, 0x1ff8, + 0xa436, 0xA014, 0xa438, 0xa704, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x819d, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa436, 0xA164, 0xa438, 0x119F, 0xa436, 0xA166, + 0xa438, 0x3fff, 0xa436, 0xA168, 0xa438, 0x3fff, 0xa436, 0xA16A, + 0xa438, 0x11A1, 0xa436, 0xA16C, 0xa438, 0x3fff, 0xa436, 0xA16E, + 0xa438, 0x3fff, 0xa436, 0xA170, 0xa438, 0x3fff, 0xa436, 0xA172, + 0xa438, 0x3fff, 0xa436, 0xA162, 0xa438, 0x0009, 0xa436, 0xb87c, + 0xa438, 0x8a63, 0xa436, 0xb87e, 0xa438, 0xaf8a, 0xa438, 0x7baf, + 0xa438, 0x8ab6, 0xa438, 0xaf8a, 0xa438, 0xd6af, 0xa438, 0x8ae4, + 0xa438, 0xaf8a, 0xa438, 0xf2af, 0xa438, 0x8b07, 0xa438, 0xaf8b, + 0xa438, 0x07af, 0xa438, 0x8b07, 0xa438, 0xad35, 0xa438, 0x27bf, + 0xa438, 0x7308, 0xa438, 0x027b, 0xa438, 0x07ac, 0xa438, 0x280d, + 0xa438, 0xbf73, 0xa438, 0x0b02, 0xa438, 0x7b07, 0xa438, 0xac28, + 0xa438, 0x04d0, 0xa438, 0x05ae, 0xa438, 0x02d0, 0xa438, 0x01d1, + 0xa438, 0x01d3, 0xa438, 0x04ee, 0xa438, 0x8640, 0xa438, 0x00ee, + 0xa438, 0x8641, 0xa438, 0x00af, 0xa438, 0x6aa6, 0xa438, 0xd100, + 0xa438, 0xd300, 0xa438, 0xee86, 0xa438, 0x4001, 0xa438, 0xee86, + 0xa438, 0x4124, 0xa438, 0xd00f, 0xa438, 0xaf6a, 0xa438, 0xa6bf, + 0xa438, 0x739e, 0xa438, 0x027b, 0xa438, 0x07ad, 0xa438, 0x280b, + 0xa438, 0xe18f, 0xa438, 0xfdad, 0xa438, 0x2805, 0xa438, 0xe08f, + 0xa438, 0xfeae, 0xa438, 0x03e0, 0xa438, 0x8fff, 0xa438, 0xe489, + 0xa438, 0xe7e0, 0xa438, 0x89e7, 0xa438, 0xaf67, 0xa438, 0x9fa0, + 0xa438, 0x9402, 0xa438, 0xae03, 0xa438, 0xa0b5, 0xa438, 0x03af, + 0xa438, 0x0d89, 0xa438, 0xaf0d, 0xa438, 0xafa0, 0xa438, 0x9402, + 0xa438, 0xae03, 0xa438, 0xa0b5, 0xa438, 0x03af, 0xa438, 0x0c64, + 0xa438, 0xaf0c, 0xa438, 0xcce0, 0xa438, 0x8013, 0xa438, 0x026b, + 0xa438, 0xa4ad, 0xa438, 0x2109, 0xa438, 0x0264, 0xa438, 0x47bf, + 0xa438, 0x769b, 0xa438, 0x027a, 0xa438, 0xbcaf, 0xa438, 0x6562, + 0xa436, 0xb85e, 0xa438, 0x6A7F, 0xa436, 0xb860, 0xa438, 0x679C, + 0xa436, 0xb862, 0xa438, 0x0d86, 0xa436, 0xb864, 0xa438, 0x0c61, + 0xa436, 0xb886, 0xa438, 0x6553, 0xa436, 0xb888, 0xa438, 0xffff, + 0xa436, 0xb88a, 0xa438, 0xffff, 0xa436, 0xb88c, 0xa438, 0xffff, + 0xa436, 0xb838, 0xa438, 0x001f, 0xb820, 0x0010, 0xa436, 0x8629, + 0xa438, 0xaf86, 0xa438, 0x41af, 0xa438, 0x8644, 0xa438, 0xaf88, + 0xa438, 0x0caf, 0xa438, 0x8813, 0xa438, 0xaf88, 0xa438, 0x4baf, + 0xa438, 0x884b, 0xa438, 0xaf88, 0xa438, 0x4baf, 0xa438, 0x884b, + 0xa438, 0xaf1d, 0xa438, 0x8a02, 0xa438, 0x864d, 0xa438, 0x0210, + 0xa438, 0x64af, 0xa438, 0x1063, 0xa438, 0xf8fa, 0xa438, 0xef69, + 0xa438, 0xe080, 0xa438, 0x4cac, 0xa438, 0x2517, 0xa438, 0xe080, + 0xa438, 0x40ad, 0xa438, 0x251a, 0xa438, 0x0286, 0xa438, 0x7ce0, + 0xa438, 0x8040, 0xa438, 0xac25, 0xa438, 0x11bf, 0xa438, 0x87f4, + 0xa438, 0x0277, 0xa438, 0xf6ae, 0xa438, 0x0902, 0xa438, 0x87b3, + 0xa438, 0x0287, 0xa438, 0xe902, 0xa438, 0x87de, 0xa438, 0xef96, + 0xa438, 0xfefc, 0xa438, 0x04f8, 0xa438, 0xe080, 0xa438, 0x18ad, + 0xa438, 0x2611, 0xa438, 0xe08f, 0xa438, 0x9cac, 0xa438, 0x2005, + 0xa438, 0x0286, 0xa438, 0x99ae, 0xa438, 0x0302, 0xa438, 0x8707, + 0xa438, 0x0287, 0xa438, 0x5002, 0xa438, 0x87de, 0xa438, 0xfc04, + 0xa438, 0xf8f9, 0xa438, 0xef79, 0xa438, 0xfbbf, 0xa438, 0x87f7, + 0xa438, 0x0278, 0xa438, 0x385c, 0xa438, 0x2000, 0xa438, 0x0d4d, + 0xa438, 0xa101, 0xa438, 0x51bf, 0xa438, 0x87f7, 0xa438, 0x0278, + 0xa438, 0x385c, 0xa438, 0x07ff, 0xa438, 0xe38f, 0xa438, 0x9d1b, + 0xa438, 0x319f, 0xa438, 0x410d, 0xa438, 0x48e3, 0xa438, 0x8f9e, + 0xa438, 0x1b31, 0xa438, 0x9f38, 0xa438, 0xbf87, 0xa438, 0xfa02, + 0xa438, 0x7838, 0xa438, 0x5c07, 0xa438, 0xffe3, 0xa438, 0x8f9f, + 0xa438, 0x1b31, 0xa438, 0x9f28, 0xa438, 0x0d48, 0xa438, 0xe38f, + 0xa438, 0xa01b, 0xa438, 0x319f, 0xa438, 0x1fbf, 0xa438, 0x87fd, + 0xa438, 0x0278, 0xa438, 0x385c, 0xa438, 0x07ff, 0xa438, 0xe38f, + 0xa438, 0xa11b, 0xa438, 0x319f, 0xa438, 0x0f0d, 0xa438, 0x48e3, + 0xa438, 0x8fa2, 0xa438, 0x1b31, 0xa438, 0x9f06, 0xa438, 0xee8f, + 0xa438, 0x9c01, 0xa438, 0xae04, 0xa438, 0xee8f, 0xa438, 0x9c00, + 0xa438, 0xffef, 0xa438, 0x97fd, 0xa438, 0xfc04, 0xa438, 0xf8f9, + 0xa438, 0xef79, 0xa438, 0xfbbf, 0xa438, 0x87f7, 0xa438, 0x0278, + 0xa438, 0x385c, 0xa438, 0x2000, 0xa438, 0x0d4d, 0xa438, 0xa100, + 0xa438, 0x20bf, 0xa438, 0x87f7, 0xa438, 0x0278, 0xa438, 0x385c, + 0xa438, 0x0600, 0xa438, 0x0d49, 0xa438, 0xe38f, 0xa438, 0xa31b, + 0xa438, 0x319f, 0xa438, 0x0ebf, 0xa438, 0x8800, 0xa438, 0x0277, + 0xa438, 0xf6bf, 0xa438, 0x8806, 0xa438, 0x0277, 0xa438, 0xf6ae, + 0xa438, 0x0cbf, 0xa438, 0x8800, 0xa438, 0x0277, 0xa438, 0xedbf, + 0xa438, 0x8806, 0xa438, 0x0277, 0xa438, 0xedee, 0xa438, 0x8f9c, + 0xa438, 0x00ff, 0xa438, 0xef97, 0xa438, 0xfdfc, 0xa438, 0x04f8, + 0xa438, 0xf9ef, 0xa438, 0x79fb, 0xa438, 0xbf87, 0xa438, 0xf702, + 0xa438, 0x7838, 0xa438, 0x5c20, 0xa438, 0x000d, 0xa438, 0x4da1, + 0xa438, 0x014a, 0xa438, 0xbf87, 0xa438, 0xf702, 0xa438, 0x7838, + 0xa438, 0x5c07, 0xa438, 0xffe3, 0xa438, 0x8fa4, 0xa438, 0x1b31, + 0xa438, 0x9f3a, 0xa438, 0x0d48, 0xa438, 0xe38f, 0xa438, 0xa51b, + 0xa438, 0x319f, 0xa438, 0x31bf, 0xa438, 0x87fa, 0xa438, 0x0278, + 0xa438, 0x38e3, 0xa438, 0x8fa6, 0xa438, 0x1b31, 0xa438, 0x9f24, + 0xa438, 0x0d48, 0xa438, 0xe38f, 0xa438, 0xa71b, 0xa438, 0x319f, + 0xa438, 0x1bbf, 0xa438, 0x87fd, 0xa438, 0x0278, 0xa438, 0x38e3, + 0xa438, 0x8fa8, 0xa438, 0x1b31, 0xa438, 0x9f0e, 0xa438, 0xbf88, + 0xa438, 0x0302, 0xa438, 0x77f6, 0xa438, 0xbf88, 0xa438, 0x0902, + 0xa438, 0x77f6, 0xa438, 0xae00, 0xa438, 0xffef, 0xa438, 0x97fd, + 0xa438, 0xfc04, 0xa438, 0xf8ef, 0xa438, 0x79fb, 0xa438, 0xe080, + 0xa438, 0x18ad, 0xa438, 0x261c, 0xa438, 0xee8f, 0xa438, 0x9c00, + 0xa438, 0xbf88, 0xa438, 0x0002, 0xa438, 0x77ed, 0xa438, 0xbf88, + 0xa438, 0x0602, 0xa438, 0x77ed, 0xa438, 0xbf88, 0xa438, 0x0302, + 0xa438, 0x77ed, 0xa438, 0xbf88, 0xa438, 0x0902, 0xa438, 0x77ed, + 0xa438, 0xffef, 0xa438, 0x97fc, 0xa438, 0x04f8, 0xa438, 0xe080, + 0xa438, 0x40f6, 0xa438, 0x25e4, 0xa438, 0x8040, 0xa438, 0xfc04, + 0xa438, 0xf8e0, 0xa438, 0x804c, 0xa438, 0xf625, 0xa438, 0xe480, + 0xa438, 0x4cfc, 0xa438, 0x0455, 0xa438, 0xa4ba, 0xa438, 0xf0a6, + 0xa438, 0x4af0, 0xa438, 0xa64c, 0xa438, 0xf0a6, 0xa438, 0x4e66, + 0xa438, 0xa4b6, 0xa438, 0x55a4, 0xa438, 0xb600, 0xa438, 0xac56, + 0xa438, 0x11ac, 0xa438, 0x56ee, 0xa438, 0x804c, 0xa438, 0x3aaf, + 0xa438, 0x0627, 0xa438, 0xbf88, 0xa438, 0x4802, 0xa438, 0x77ed, + 0xa438, 0xd203, 0xa438, 0xe083, 0xa438, 0x8a0d, 0xa438, 0x01f6, + 0xa438, 0x271b, 0xa438, 0x03aa, 0xa438, 0x0182, 0xa438, 0xe083, + 0xa438, 0x890d, 0xa438, 0x01f6, 0xa438, 0x271b, 0xa438, 0x03aa, + 0xa438, 0x0182, 0xa438, 0xe083, 0xa438, 0x880d, 0xa438, 0x01f6, + 0xa438, 0x271b, 0xa438, 0x03aa, 0xa438, 0x0782, 0xa438, 0xbf88, + 0xa438, 0x4802, 0xa438, 0x77f6, 0xa438, 0xaf16, 0xa438, 0x1500, + 0xa438, 0xa86a, 0xa436, 0xb818, 0xa438, 0x1D84, 0xa436, 0xb81a, + 0xa438, 0x1060, 0xa436, 0xb81c, 0xa438, 0x0623, 0xa436, 0xb81e, + 0xa438, 0x15ef, 0xa436, 0xb850, 0xa438, 0xffff, 0xa436, 0xb852, + 0xa438, 0xffff, 0xa436, 0xb878, 0xa438, 0xffff, 0xa436, 0xb884, + 0xa438, 0xffff, 0xa436, 0xb832, 0xa438, 0x000f, 0xa436, 0x0000, + 0xa438, 0x0000, 0xB82E, 0x0000, 0xa436, 0x8023, 0xa438, 0x0000, + 0xB820, 0x0000, 0xFFFF, 0xFFFF +}; + +static void +rtl_real_set_phy_mcu_8126a_1_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8126a_1_1, + ARRAY_SIZE(phy_mcu_ram_code_8126a_1_1)); +} + +static void +rtl_real_set_phy_mcu_8126a_1_2(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8126a_1_2, + ARRAY_SIZE(phy_mcu_ram_code_8126a_1_2)); +} + +static void +rtl_real_set_phy_mcu_8126a_1_3(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8126a_1_3, + ARRAY_SIZE(phy_mcu_ram_code_8126a_1_3)); +} + +void +rtl_set_phy_mcu_8126a_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8126a_1_1(hw); + + rtl_clear_phy_mcu_patch_request(hw); + + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8126a_1_2(hw); + + rtl_clear_phy_mcu_patch_request(hw); + + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8126a_1_3(hw); + + rtl_clear_phy_mcu_patch_request(hw); +} + +static void +rtl_real_set_phy_mcu_8126a_2_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8126a_2_1, + ARRAY_SIZE(phy_mcu_ram_code_8126a_2_1)); +} + +static void +rtl_real_set_phy_mcu_8126a_2_3(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8126a_2_3, + ARRAY_SIZE(phy_mcu_ram_code_8126a_2_3)); +} + +void +rtl_set_phy_mcu_8126a_2(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8126a_2_1(hw); + + rtl_clear_phy_mcu_patch_request(hw); + + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8126a_2_3(hw); + + rtl_clear_phy_mcu_patch_request(hw); +} + +static void +rtl_real_set_phy_mcu_8126a_3_1(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_ram_code(hw, phy_mcu_ram_code_8126a_3_1, + ARRAY_SIZE(phy_mcu_ram_code_8126a_3_1)); +} + +void +rtl_set_phy_mcu_8126a_3(struct rtl_hw *hw) +{ + rtl_set_phy_mcu_patch_request(hw); + + rtl_real_set_phy_mcu_8126a_3_1(hw); + + rtl_clear_phy_mcu_patch_request(hw); +} + diff --git a/drivers/net/r8169/base/rtl8126a_mcu.h b/drivers/net/r8169/base/rtl8126a_mcu.h new file mode 100644 index 0000000000..ae4aa5f3d4 --- /dev/null +++ b/drivers/net/r8169/base/rtl8126a_mcu.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _RTL8126A_MCU_H_ +#define _RTL8126A_MCU_H_ + +void rtl_set_mac_mcu_8126a_1(struct rtl_hw *hw); +void rtl_set_mac_mcu_8126a_2(struct rtl_hw *hw); +void rtl_set_mac_mcu_8126a_3(struct rtl_hw *hw); + +void rtl_set_phy_mcu_8126a_1(struct rtl_hw *hw); +void rtl_set_phy_mcu_8126a_2(struct rtl_hw *hw); +void rtl_set_phy_mcu_8126a_3(struct rtl_hw *hw); +#endif + diff --git a/drivers/net/r8169/meson.build b/drivers/net/r8169/meson.build index 56f857ac8c..08995453c7 100644 --- a/drivers/net/r8169/meson.build +++ b/drivers/net/r8169/meson.build @@ -6,5 +6,15 @@ sources = files( 'r8169_hw.c', 'r8169_rxtx.c', 'r8169_phy.c', + 'base/rtl8125a.c', + 'base/rtl8125a_mcu.c', + 'base/rtl8125b.c', + 'base/rtl8125b_mcu.c', + 'base/rtl8125bp.c', + 'base/rtl8125bp_mcu.c', + 'base/rtl8125d.c', + 'base/rtl8125d_mcu.c', + 'base/rtl8126a.c', + 'base/rtl8126a_mcu.c', ) diff --git a/drivers/net/r8169/r8169_base.h b/drivers/net/r8169/r8169_base.h index 2e72faeb2c..e01b1e3470 100644 --- a/drivers/net/r8169/r8169_base.h +++ b/drivers/net/r8169/r8169_base.h @@ -504,6 +504,7 @@ enum RTL_register_content { #define RX_DMA_BURST_unlimited 7 /* Maximum PCI burst, '7' is unlimited */ #define RX_DMA_BURST_512 5 +#define RX_DMA_BURST_256 4 #define TX_DMA_BURST_unlimited 7 #define TX_DMA_BURST_1024 6 #define TX_DMA_BURST_512 5 @@ -513,6 +514,13 @@ enum RTL_register_content { #define TX_DMA_BURST_32 1 #define TX_DMA_BURST_16 0 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ +#define Rx_Fetch_Number_8 (1 << 30) +#define Rx_Close_Multiple (1 << 21) + +#define TRUE 1 +#define FALSE 0 + +#define ETH_HLEN 14 static inline u32 rtl_read32(volatile void *addr) diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index a23370c6a1..f4a79b494a 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -143,6 +143,9 @@ rtl_dev_init(struct rte_eth_dev *dev) rte_eth_copy_pci_info(dev, pci_dev); + if (rtl_set_hw_ops(hw)) + return -ENOTSUP; + return 0; } diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index 9656a26eb0..c9acaabf8e 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -13,13 +13,33 @@ #include "r8169_base.h" +struct rtl_hw; + +struct rtl_hw_ops { + void (*hw_init_rxcfg)(struct rtl_hw *hw); + void (*hw_ephy_config)(struct rtl_hw *hw); + void (*hw_phy_config)(struct rtl_hw *hw); + void (*hw_mac_mcu_config)(struct rtl_hw *hw); + void (*hw_phy_mcu_config)(struct rtl_hw *hw); +}; + struct rtl_hw { + struct rtl_hw_ops hw_ops; u8 adapter_stopped; u8 *mmio_addr; u32 mcfg; + u32 mtu; u8 HwSuppIntMitiVer; u16 cur_page; + u8 RequirePhyMdiSwapPatch; + u8 NotWrMcuPatchCode; + u8 HwSuppMacMcuVer; + u16 MacMcuPageSize; + + u8 NotWrRamCodeToMicroP; + u8 HwHasWrRamCodeToMicroP; + /* Enable Tx No Close */ u8 EnableTxNoClose; diff --git a/drivers/net/r8169/r8169_hw.c b/drivers/net/r8169/r8169_hw.c index 06d2ca27d9..fb4ea21237 100644 --- a/drivers/net/r8169/r8169_hw.c +++ b/drivers/net/r8169/r8169_hw.c @@ -358,7 +358,8 @@ void rtl_disable_rxdvgate(struct rtl_hw *hw) { switch (hw->mcfg) { - case CFG_METHOD_1 ... CFG_METHOD_3: + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: RTL_W8(hw, 0xF2, RTL_R8(hw, 0xF2) & ~BIT_3); mdelay(2); } @@ -802,3 +803,120 @@ rtl_hw_config(struct rtl_hw *hw) udelay(10); } +int +rtl_set_hw_ops(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + /* 8125A */ + case CFG_METHOD_48: + case CFG_METHOD_49: + hw->hw_ops = rtl8125a_ops; + return 0; + /* 8125B */ + case CFG_METHOD_50: + case CFG_METHOD_51: + hw->hw_ops = rtl8125b_ops; + return 0; + /* 8125BP */ + case CFG_METHOD_54: + case CFG_METHOD_55: + hw->hw_ops = rtl8125bp_ops; + return 0; + /* 8125D */ + case CFG_METHOD_56: + case CFG_METHOD_57: + hw->hw_ops = rtl8125d_ops; + return 0; + /* 8126A */ + case CFG_METHOD_69 ... CFG_METHOD_71: + hw->hw_ops = rtl8126a_ops; + return 0; + default: + return -ENOTSUP; + } +} + +void +rtl_hw_disable_mac_mcu_bps(struct rtl_hw *hw) +{ + u16 reg_addr; + + rtl_enable_aspm_clkreq_lock(hw, 0); + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_mac_ocp_write(hw, 0xFC48, 0x0000); + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + for (reg_addr = 0xFC28; reg_addr < 0xFC48; reg_addr += 2) + rtl_mac_ocp_write(hw, reg_addr, 0x0000); + + mdelay(3); + + rtl_mac_ocp_write(hw, 0xFC26, 0x0000); + break; + } +} + +static void +rtl_switch_mac_mcu_ram_code_page(struct rtl_hw *hw, u16 page) +{ + u16 tmp_ushort; + + page &= (BIT_1 | BIT_0); + tmp_ushort = rtl_mac_ocp_read(hw, 0xE446); + tmp_ushort &= ~(BIT_1 | BIT_0); + tmp_ushort |= page; + rtl_mac_ocp_write(hw, 0xE446, tmp_ushort); +} + +static void +_rtl_write_mac_mcu_ram_code(struct rtl_hw *hw, const u16 *entry, u16 entry_cnt) +{ + u16 i; + + for (i = 0; i < entry_cnt; i++) + rtl_mac_ocp_write(hw, 0xF800 + i * 2, entry[i]); +} + +static void +_rtl_write_mac_mcu_ram_code_with_page(struct rtl_hw *hw, const u16 *entry, + u16 entry_cnt, u16 page_size) +{ + u16 i; + u16 offset; + u16 page; + + if (page_size == 0) + return; + + for (i = 0; i < entry_cnt; i++) { + offset = i % page_size; + if (offset == 0) { + page = (i / page_size); + rtl_switch_mac_mcu_ram_code_page(hw, page); + } + rtl_mac_ocp_write(hw, 0xF800 + offset * 2, entry[i]); + } +} + +void +rtl_write_mac_mcu_ram_code(struct rtl_hw *hw, const u16 *entry, u16 entry_cnt) +{ + if (FALSE == HW_SUPPORT_MAC_MCU(hw)) + return; + if (entry == NULL || entry_cnt == 0) + return; + + if (hw->MacMcuPageSize > 0) + _rtl_write_mac_mcu_ram_code_with_page(hw, entry, entry_cnt, + hw->MacMcuPageSize); + else + _rtl_write_mac_mcu_ram_code(hw, entry, entry_cnt); +} + diff --git a/drivers/net/r8169/r8169_hw.h b/drivers/net/r8169/r8169_hw.h index 4effe2c6c7..8fd48a3077 100644 --- a/drivers/net/r8169/r8169_hw.h +++ b/drivers/net/r8169/r8169_hw.h @@ -35,6 +35,19 @@ void rtl8125_oob_mutex_unlock(struct rtl_hw *hw); void rtl_disable_rxdvgate(struct rtl_hw *hw); +int rtl_set_hw_ops(struct rtl_hw *hw); + +void rtl_hw_disable_mac_mcu_bps(struct rtl_hw *hw); + +void rtl_write_mac_mcu_ram_code(struct rtl_hw *hw, const u16 *entry, + u16 entry_cnt); + +extern const struct rtl_hw_ops rtl8125a_ops; +extern const struct rtl_hw_ops rtl8125b_ops; +extern const struct rtl_hw_ops rtl8125bp_ops; +extern const struct rtl_hw_ops rtl8125d_ops; +extern const struct rtl_hw_ops rtl8126a_ops; + #define NO_BASE_ADDRESS 0x00000000 /* Channel wait count */ @@ -42,5 +55,10 @@ void rtl_disable_rxdvgate(struct rtl_hw *hw); #define RTL_CHANNEL_WAIT_TIME 1 /* 1 us */ #define RTL_CHANNEL_EXIT_DELAY_TIME 20 /* 20 us */ +#define ARRAY_SIZE(arr) RTE_DIM(arr) + +#define HW_SUPPORT_MAC_MCU(_M) ((_M)->HwSuppMacMcuVer > 0) +#define HW_HAS_WRITE_PHY_MCU_RAM_CODE(_M) (((_M)->HwHasWrRamCodeToMicroP == TRUE) ? 1 : 0) + #endif diff --git a/drivers/net/r8169/r8169_phy.c b/drivers/net/r8169/r8169_phy.c index cfec426ee1..bd707ee5b6 100644 --- a/drivers/net/r8169/r8169_phy.c +++ b/drivers/net/r8169/r8169_phy.c @@ -258,3 +258,75 @@ rtl_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask) rtl_clear_and_set_pcie_phy_bit(hw, addr, 0, mask); } +bool +rtl_set_phy_mcu_patch_request(struct rtl_hw *hw) +{ + u16 gphy_val; + u16 wait_cnt; + bool bool_success = TRUE; + + rtl_set_eth_phy_ocp_bit(hw, 0xB820, BIT_4); + + wait_cnt = 0; + do { + gphy_val = rtl_mdio_direct_read_phy_ocp(hw, 0xB800); + udelay(100); + wait_cnt++; + } while (!(gphy_val & BIT_6) && (wait_cnt < 1000)); + + if (!(gphy_val & BIT_6) && (wait_cnt == 1000)) + bool_success = FALSE; + + if (!bool_success) + PMD_INIT_LOG(NOTICE, "rtl_set_phy_mcu_patch_request fail."); + + return bool_success; +} + +bool +rtl_clear_phy_mcu_patch_request(struct rtl_hw *hw) +{ + u16 gphy_val; + u16 wait_cnt; + bool bool_success = TRUE; + + rtl_clear_eth_phy_ocp_bit(hw, 0xB820, BIT_4); + + wait_cnt = 0; + do { + gphy_val = rtl_mdio_direct_read_phy_ocp(hw, 0xB800); + udelay(100); + wait_cnt++; + } while ((gphy_val & BIT_6) && (wait_cnt < 1000)); + + if ((gphy_val & BIT_6) && (wait_cnt == 1000)) + bool_success = FALSE; + + if (!bool_success) + PMD_INIT_LOG(NOTICE, "rtl_clear_phy_mcu_patch_request fail."); + + return bool_success; +} + +void +rtl_set_phy_mcu_ram_code(struct rtl_hw *hw, const u16 *ramcode, u16 codesize) +{ + u16 i; + u16 addr; + u16 val; + + if (ramcode == NULL || codesize % 2) + goto out; + + for (i = 0; i < codesize; i += 2) { + addr = ramcode[i]; + val = ramcode[i + 1]; + if (addr == 0xFFFF && val == 0xFFFF) + break; + rtl_mdio_direct_write_phy_ocp(hw, addr, val); + } + +out: + return; +} + diff --git a/drivers/net/r8169/r8169_phy.h b/drivers/net/r8169/r8169_phy.h index da5a6575d4..f067e2a28c 100644 --- a/drivers/net/r8169/r8169_phy.h +++ b/drivers/net/r8169/r8169_phy.h @@ -35,5 +35,11 @@ void rtl_clear_and_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 clearmask, void rtl_clear_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask); void rtl_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask); +bool rtl_set_phy_mcu_patch_request(struct rtl_hw *hw); +bool rtl_clear_phy_mcu_patch_request(struct rtl_hw *hw); + +void rtl_set_phy_mcu_ram_code(struct rtl_hw *hw, const u16 *ramcode, + u16 codesize); + #endif From patchwork Tue Oct 15 03:09:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145938 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AA17945B3C; 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Tue, 15 Oct 2024 11:10:44 +0800 Received: from RSEXDAG02.realsil.com.cn (172.29.17.196) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:10:44 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXDAG02.realsil.com.cn (172.29.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:10:43 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:10:43 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 08/18] net/r8169: add support for phy configuration Date: Tue, 15 Oct 2024 11:09:18 +0800 Message-ID: <20241015030928.70642-9-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch contains phy config, ephy config and so on. Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_ethdev.c | 10 + drivers/net/r8169/r8169_ethdev.h | 6 + drivers/net/r8169/r8169_phy.c | 445 +++++++++++++++++++++++++++++++ drivers/net/r8169/r8169_phy.h | 100 +++++++ 4 files changed, 561 insertions(+) diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index f4a79b494a..294d942862 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -72,6 +72,12 @@ rtl_dev_start(struct rte_eth_dev *dev) struct rtl_hw *hw = &adapter->hw; int err; + rtl_powerup_pll(hw); + + rtl_hw_ephy_config(hw); + + rtl_hw_phy_config(hw); + rtl_hw_config(hw); /* Initialize transmission unit */ @@ -84,6 +90,8 @@ rtl_dev_start(struct rte_eth_dev *dev) goto error; } + rtl_mdio_write(hw, 0x1F, 0x0000); + hw->adapter_stopped = 0; return 0; @@ -103,6 +111,8 @@ rtl_dev_stop(struct rte_eth_dev *dev) if (hw->adapter_stopped) return 0; + rtl_powerdown_pll(hw); + hw->adapter_stopped = 1; dev->data->dev_started = 0; diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index c9acaabf8e..a0da173685 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -39,6 +39,12 @@ struct rtl_hw { u8 NotWrRamCodeToMicroP; u8 HwHasWrRamCodeToMicroP; + u8 HwSuppCheckPhyDisableModeVer; + + u16 sw_ram_code_ver; + u16 hw_ram_code_ver; + + u32 HwSuppMaxPhyLinkSpeed; /* Enable Tx No Close */ u8 EnableTxNoClose; diff --git a/drivers/net/r8169/r8169_phy.c b/drivers/net/r8169/r8169_phy.c index bd707ee5b6..3198116946 100644 --- a/drivers/net/r8169/r8169_phy.c +++ b/drivers/net/r8169/r8169_phy.c @@ -330,3 +330,448 @@ rtl_set_phy_mcu_ram_code(struct rtl_hw *hw, const u16 *ramcode, u16 codesize) return; } +static u8 +rtl_is_phy_disable_mode_enabled(struct rtl_hw *hw) +{ + u8 phy_disable_mode_enabled = FALSE; + + switch (hw->HwSuppCheckPhyDisableModeVer) { + case 3: + if (RTL_R8(hw, 0xF2) & BIT_5) + phy_disable_mode_enabled = TRUE; + break; + } + + return phy_disable_mode_enabled; +} + +static u8 +rtl_is_gpio_low(struct rtl_hw *hw) +{ + u8 gpio_low = FALSE; + + switch (hw->HwSuppCheckPhyDisableModeVer) { + case 3: + if (!(rtl_mac_ocp_read(hw, 0xDC04) & BIT_13)) + gpio_low = TRUE; + break; + } + + return gpio_low; +} + +static u8 +rtl_is_in_phy_disable_mode(struct rtl_hw *hw) +{ + u8 in_phy_disable_mode = FALSE; + + if (rtl_is_phy_disable_mode_enabled(hw) && rtl_is_gpio_low(hw)) + in_phy_disable_mode = TRUE; + + return in_phy_disable_mode; +} + +static void +rtl_wait_phy_ups_resume(struct rtl_hw *hw, u16 PhyState) +{ + u16 tmp_phy_state; + int i = 0; + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + do { + tmp_phy_state = rtl_mdio_direct_read_phy_ocp(hw, 0xA420); + tmp_phy_state &= 0x7; + mdelay(1); + i++; + } while ((i < 100) && (tmp_phy_state != PhyState)); + } +} + +static void +rtl_phy_power_up(struct rtl_hw *hw) +{ + if (rtl_is_in_phy_disable_mode(hw)) + return; + + rtl_mdio_write(hw, 0x1F, 0x0000); + rtl_mdio_write(hw, MII_BMCR, BMCR_ANENABLE); + + /* Wait ups resume (phy state 3) */ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_wait_phy_ups_resume(hw, 3); + } +} + +void +rtl_powerup_pll(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + RTL_W8(hw, PMCH, RTL_R8(hw, PMCH) | BIT_7 | BIT_6); + } + + rtl_phy_power_up(hw); +} + +static void +rtl_phy_power_down(struct rtl_hw *hw) +{ + rtl_mdio_write(hw, 0x1F, 0x0000); + rtl_mdio_write(hw, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); +} + +void +rtl_powerdown_pll(struct rtl_hw *hw) +{ + if (hw->DASH) + return; + + rtl_phy_power_down(hw); + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + RTL_W8(hw, PMCH, RTL_R8(hw, PMCH) & ~BIT_7); + break; + } +} + +void +rtl_hw_ephy_config(struct rtl_hw *hw) +{ + hw->hw_ops.hw_ephy_config(hw); +} + +static int +rtl_wait_phy_reset_complete(struct rtl_hw *hw) +{ + int i, val; + + for (i = 0; i < 2500; i++) { + val = rtl_mdio_read(hw, MII_BMCR) & BMCR_RESET; + if (!val) + return 0; + + mdelay(1); + } + + return -1; +} + +static void +rtl_xmii_reset_enable(struct rtl_hw *hw) +{ + if (rtl_is_in_phy_disable_mode(hw)) + return; + + rtl_mdio_write(hw, 0x1F, 0x0000); + rtl_mdio_write(hw, MII_ADVERTISE, rtl_mdio_read(hw, MII_ADVERTISE) & + ~(ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL)); + rtl_mdio_write(hw, MII_CTRL1000, rtl_mdio_read(hw, MII_CTRL1000) & + ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL)); + rtl_mdio_direct_write_phy_ocp(hw, 0xA5D4, rtl_mdio_direct_read_phy_ocp(hw, + 0xA5D4) & ~(RTK_ADVERTISE_2500FULL | RTK_ADVERTISE_5000FULL)); + rtl_mdio_write(hw, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); + + if (rtl_wait_phy_reset_complete(hw) == 0) + return; +} + +static void +rtl8125_set_hw_phy_before_init_phy_mcu(struct rtl_hw *hw) +{ + u16 phy_reg_value; + + switch (hw->mcfg) { + case CFG_METHOD_4: + rtl_mdio_direct_write_phy_ocp(hw, 0xBF86, 0x9000); + + rtl_set_eth_phy_ocp_bit(hw, 0xC402, BIT_10); + rtl_clear_eth_phy_ocp_bit(hw, 0xC402, BIT_10); + + phy_reg_value = rtl_mdio_direct_read_phy_ocp(hw, 0xBF86); + phy_reg_value &= (BIT_1 | BIT_0); + if (phy_reg_value != 0) + PMD_INIT_LOG(NOTICE, "PHY watch dog not clear, value = 0x%x", phy_reg_value); + + rtl_mdio_direct_write_phy_ocp(hw, 0xBD86, 0x1010); + rtl_mdio_direct_write_phy_ocp(hw, 0xBD88, 0x1010); + + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD4E, (BIT_11 | BIT_10), BIT_11); + rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF46, (BIT_11 | BIT_10 | BIT_9 | BIT_8), + (BIT_10 | BIT_9 | BIT_8)); + break; + } +} + +static u16 +rtl_get_hw_phy_mcu_code_ver(struct rtl_hw *hw) +{ + u16 hw_ram_code_ver = ~0; + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x801E); + hw_ram_code_ver = rtl_mdio_direct_read_phy_ocp(hw, 0xA438); + break; + } + + return hw_ram_code_ver; +} + +static int +rtl_check_hw_phy_mcu_code_ver(struct rtl_hw *hw) +{ + int ram_code_ver_match = 0; + + hw->hw_ram_code_ver = rtl_get_hw_phy_mcu_code_ver(hw); + + if (hw->hw_ram_code_ver == hw->sw_ram_code_ver) { + ram_code_ver_match = 1; + hw->HwHasWrRamCodeToMicroP = TRUE; + } else + hw->HwHasWrRamCodeToMicroP = FALSE; + + return ram_code_ver_match; +} + +static void +rtl_write_hw_phy_mcu_code_ver(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x801E); + rtl_mdio_direct_write_phy_ocp(hw, 0xA438, hw->sw_ram_code_ver); + hw->hw_ram_code_ver = hw->sw_ram_code_ver; + break; + } +} + +static void +rtl_enable_phy_disable_mode(struct rtl_hw *hw) +{ + switch (hw->HwSuppCheckPhyDisableModeVer) { + case 3: + RTL_W8(hw, 0xF2, RTL_R8(hw, 0xF2) | BIT_5); + break; + } +} + +static void +rtl_disable_phy_disable_mode(struct rtl_hw *hw) +{ + switch (hw->HwSuppCheckPhyDisableModeVer) { + case 3: + RTL_W8(hw, 0xF2, RTL_R8(hw, 0xF2) & ~BIT_5); + break; + } + + mdelay(1); +} + +static void +rtl_init_hw_phy_mcu(struct rtl_hw *hw) +{ + u8 require_disable_phy_disable_mode = FALSE; + + if (hw->NotWrRamCodeToMicroP == TRUE) + return; + + if (rtl_check_hw_phy_mcu_code_ver(hw)) + return; + + if (HW_SUPPORT_CHECK_PHY_DISABLE_MODE(hw) && rtl_is_in_phy_disable_mode(hw)) + require_disable_phy_disable_mode = TRUE; + + if (require_disable_phy_disable_mode) + rtl_disable_phy_disable_mode(hw); + + hw->hw_ops.hw_phy_mcu_config(hw); + + if (require_disable_phy_disable_mode) + rtl_enable_phy_disable_mode(hw); + + rtl_write_hw_phy_mcu_code_ver(hw); + + rtl_mdio_write(hw, 0x1F, 0x0000); + + hw->HwHasWrRamCodeToMicroP = TRUE; +} + +static void +rtl_disable_aldps(struct rtl_hw *hw) +{ + u16 tmp_ushort; + u32 timeout, wait_cnt; + + tmp_ushort = rtl_mdio_real_read_phy_ocp(hw, 0xA430); + if (tmp_ushort & BIT_2) { + timeout = 0; + wait_cnt = 200; + rtl_clear_eth_phy_ocp_bit(hw, 0xA430, BIT_2); + + do { + udelay(100); + + tmp_ushort = rtl_mac_ocp_read(hw, 0xE908); + + timeout++; + } while (!(tmp_ushort & BIT_7) && timeout < wait_cnt); + } +} + +static bool +rtl_is_adv_eee_enabled(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_55: + case CFG_METHOD_69 ... CFG_METHOD_71: + if (rtl_mdio_direct_read_phy_ocp(hw, 0xA430) & BIT_15) + return true; + break; + default: + break; + } + + return false; +} + +static void +_rtl_disable_adv_eee(struct rtl_hw *hw) +{ + bool lock; + + if (rtl_is_adv_eee_enabled(hw)) + lock = true; + else + lock = false; + + if (lock) + rtl_set_phy_mcu_patch_request(hw); + + rtl_clear_mac_ocp_bit(hw, 0xE052, BIT_0); + rtl_clear_eth_phy_ocp_bit(hw, 0xA442, (BIT_12 | BIT_13)); + rtl_clear_eth_phy_ocp_bit(hw, 0xA430, BIT_15); + + if (lock) + rtl_clear_phy_mcu_patch_request(hw); +} + +static void +rtl_disable_adv_eee(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + case CFG_METHOD_52: + case CFG_METHOD_54: + case CFG_METHOD_55: + rtl8125_oob_mutex_lock(hw); + break; + } + + _rtl_disable_adv_eee(hw); + + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + case CFG_METHOD_52: + case CFG_METHOD_54: + case CFG_METHOD_55: + rtl8125_oob_mutex_unlock(hw); + break; + } +} + +static void +rtl_disable_eee(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + case CFG_METHOD_52: + rtl_clear_mac_ocp_bit(hw, 0xE040, (BIT_1 | BIT_0)); + rtl_clear_mac_ocp_bit(hw, 0xEB62, (BIT_2 | BIT_1)); + + rtl_clear_eth_phy_ocp_bit(hw, 0xA432, BIT_4); + rtl_clear_eth_phy_ocp_bit(hw, 0xA5D0, (BIT_2 | BIT_1)); + rtl_clear_eth_phy_ocp_bit(hw, 0xA6D4, BIT_0); + + rtl_clear_eth_phy_ocp_bit(hw, 0xA6D8, BIT_4); + rtl_clear_eth_phy_ocp_bit(hw, 0xA428, BIT_7); + rtl_clear_eth_phy_ocp_bit(hw, 0xA4A2, BIT_9); + break; + case CFG_METHOD_50: + case CFG_METHOD_51: + case CFG_METHOD_53 ... CFG_METHOD_57: + rtl_clear_mac_ocp_bit(hw, 0xE040, (BIT_1 | BIT_0)); + + rtl_set_eth_phy_ocp_bit(hw, 0xA432, BIT_4); + rtl_clear_eth_phy_ocp_bit(hw, 0xA5D0, (BIT_2 | BIT_1)); + rtl_clear_eth_phy_ocp_bit(hw, 0xA6D4, BIT_0); + + rtl_clear_eth_phy_ocp_bit(hw, 0xA6D8, BIT_4); + rtl_clear_eth_phy_ocp_bit(hw, 0xA428, BIT_7); + rtl_clear_eth_phy_ocp_bit(hw, 0xA4A2, BIT_9); + break; + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_clear_mac_ocp_bit(hw, 0xE040, (BIT_1 | BIT_0)); + + rtl_clear_eth_phy_ocp_bit(hw, 0xA5D0, (MDIO_EEE_100TX | MDIO_EEE_1000T)); + rtl_clear_eth_phy_ocp_bit(hw, 0xA6D4, MDIO_EEE_2_5GT); + if (HW_SUPP_PHY_LINK_SPEED_5000M(hw)) + rtl_clear_eth_phy_ocp_bit(hw, 0xA6D4, MDIO_EEE_5GT); + + rtl_clear_eth_phy_ocp_bit(hw, 0xA6D8, BIT_4); + rtl_clear_eth_phy_ocp_bit(hw, 0xA428, BIT_7); + rtl_clear_eth_phy_ocp_bit(hw, 0xA4A2, BIT_9); + break; + default: + /* Not support EEE */ + break; + } + + /* Advanced EEE */ + rtl_disable_adv_eee(hw); +} + +void +rtl_hw_phy_config(struct rtl_hw *hw) +{ + rtl_xmii_reset_enable(hw); + + rtl8125_set_hw_phy_before_init_phy_mcu(hw); + + rtl_init_hw_phy_mcu(hw); + + hw->hw_ops.hw_phy_config(hw); + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_disable_aldps(hw); + break; + } + + /* Legacy force mode (chap 22) */ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + default: + rtl_clear_eth_phy_ocp_bit(hw, 0xA5B4, BIT_15); + break; + } + + rtl_mdio_write(hw, 0x1F, 0x0000); + + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) + rtl_disable_eee(hw); +} + diff --git a/drivers/net/r8169/r8169_phy.h b/drivers/net/r8169/r8169_phy.h index f067e2a28c..f4da9f50ed 100644 --- a/drivers/net/r8169/r8169_phy.h +++ b/drivers/net/r8169/r8169_phy.h @@ -14,6 +14,101 @@ #include "r8169_base.h" #include "r8169_ethdev.h" +/* Generic MII registers. */ +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_CTRL1000 0x09 /* 1000BASE-T control */ +#define MII_STAT1000 0x0a /* 1000BASE-T status */ +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ +#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ +#define BMCR_PDOWN 0x0800 /* Enable low power state */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset to default state */ +#define BMCR_SPEED10 0x0000 /* Select 10Mbps */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x00c0 /* Unused... */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ +#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ +#define ADVERTISE_RESV 0x1000 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +/* 1000BASE-T Control register */ +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ +#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ + +#define RTK_ADVERTISE_2500FULL 0x80 +#define RTK_ADVERTISE_5000FULL 0x100 +#define RTK_ADVERTISE_10000FULL 0x1000 +#define RTK_LPA_ADVERTISE_2500FULL 0x20 +#define RTK_LPA_ADVERTISE_5000FULL 0x40 +#define RTK_LPA_ADVERTISE_10000FULL 0x800 + +#define HW_SUPPORT_CHECK_PHY_DISABLE_MODE(_M) ((_M)->HwSuppCheckPhyDisableModeVer > 0) + +#define HW_SUPP_PHY_LINK_SPEED_5000M(_M) ((_M)->HwSuppMaxPhyLinkSpeed >= 5000) + +#define MDIO_EEE_100TX 0x0002 +#define MDIO_EEE_1000T 0x0004 +#define MDIO_EEE_2_5GT 0x0001 +#define MDIO_EEE_5GT 0x0002 + void rtl_clear_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); void rtl_set_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); @@ -41,5 +136,10 @@ bool rtl_clear_phy_mcu_patch_request(struct rtl_hw *hw); void rtl_set_phy_mcu_ram_code(struct rtl_hw *hw, const u16 *ramcode, u16 codesize); +void rtl_powerup_pll(struct rtl_hw *hw); +void rtl_powerdown_pll(struct rtl_hw *hw); + +void rtl_hw_ephy_config(struct rtl_hw *hw); +void rtl_hw_phy_config(struct rtl_hw *hw); #endif From patchwork Tue Oct 15 03:09:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145939 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) 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Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:10:50 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 09/18] net/r8169: add support for hw initialization Date: Tue, 15 Oct 2024 11:09:19 +0800 Message-ID: <20241015030928.70642-10-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Signed-off-by: Howard Wang --- drivers/net/r8169/meson.build | 1 + drivers/net/r8169/r8169_base.h | 43 +++ drivers/net/r8169/r8169_dash.c | 89 +++++ drivers/net/r8169/r8169_dash.h | 35 ++ drivers/net/r8169/r8169_ethdev.c | 47 ++- drivers/net/r8169/r8169_ethdev.h | 30 +- drivers/net/r8169/r8169_hw.c | 583 +++++++++++++++++++++++++++++++ drivers/net/r8169/r8169_hw.h | 42 +++ drivers/net/r8169/r8169_phy.h | 16 +- 9 files changed, 876 insertions(+), 10 deletions(-) create mode 100644 drivers/net/r8169/r8169_dash.c create mode 100644 drivers/net/r8169/r8169_dash.h diff --git a/drivers/net/r8169/meson.build b/drivers/net/r8169/meson.build index 08995453c7..8235e8ca43 100644 --- a/drivers/net/r8169/meson.build +++ b/drivers/net/r8169/meson.build @@ -6,6 +6,7 @@ sources = files( 'r8169_hw.c', 'r8169_rxtx.c', 'r8169_phy.c', + 'r8169_dash.c', 'base/rtl8125a.c', 'base/rtl8125a_mcu.c', 'base/rtl8125b.c', diff --git a/drivers/net/r8169/r8169_base.h b/drivers/net/r8169/r8169_base.h index e01b1e3470..2ee6fc6782 100644 --- a/drivers/net/r8169/r8169_base.h +++ b/drivers/net/r8169/r8169_base.h @@ -237,6 +237,10 @@ enum RTL_registers { IMR_V4_L2_CLEAR_REG_8125 = 0x0D10, IMR_V4_L2_SET_REG_8125 = 0x0D18, ISR_V4_L2_8125 = 0x0D14, + SW_TAIL_PTR0_8125BP = 0x0D30, + SW_TAIL_PTR1_8125BP = 0x0D38, + HW_CLO_PTR0_8125BP = 0x0D34, + HW_CLO_PTR1_8125BP = 0x0D3C, DOUBLE_VLAN_CONFIG = 0x1000, TX_NEW_CTRL = 0x203E, TNPDS_Q1_LOW_8125 = 0x2100, @@ -482,6 +486,16 @@ enum RTL_register_content { ISRIMR_V2_LINKCHG = (1 << 21), }; +enum RTL_chipset_name { + RTL8125A = 0, + RTL8125B, + RTL8168KB, + RTL8125BP, + RTL8125D, + RTL8126A, + UNKNOWN +}; + #define PCI_VENDOR_ID_REALTEK 0x10EC #define RTL_PCI_REG_ADDR(hw, reg) ((u8 *)(hw)->mmio_addr + (reg)) @@ -522,6 +536,35 @@ enum RTL_register_content { #define ETH_HLEN 14 +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_5000 5000 + +#define DUPLEX_HALF 1 +#define DUPLEX_FULL 2 + +#define AUTONEG_ENABLE 1 +#define AUTONEG_DISABLE 0 + +#define ADVERTISE_10_HALF 0x0001 +#define ADVERTISE_10_FULL 0x0002 +#define ADVERTISE_100_HALF 0x0004 +#define ADVERTISE_100_FULL 0x0008 +#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ +#define ADVERTISE_1000_FULL 0x0020 +#define ADVERTISE_2500_HALF 0x0040 /* NOT used, just FYI */ +#define ADVERTISE_2500_FULL 0x0080 +#define ADVERTISE_5000_HALF 0x0100 /* NOT used, just FYI */ +#define ADVERTISE_5000_FULL 0x0200 + +#define RTL8126_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ + ADVERTISE_100_HALF | ADVERTISE_100_FULL | ADVERTISE_1000_FULL | \ + ADVERTISE_2500_FULL | ADVERTISE_5000_FULL) + +#define MAC_ADDR_LEN RTE_ETHER_ADDR_LEN + static inline u32 rtl_read32(volatile void *addr) { diff --git a/drivers/net/r8169/r8169_dash.c b/drivers/net/r8169/r8169_dash.c new file mode 100644 index 0000000000..e803ce8305 --- /dev/null +++ b/drivers/net/r8169/r8169_dash.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include "r8169_base.h" +#include "r8169_dash.h" +#include "r8169_hw.h" + +bool +rtl_is_allow_access_dash_ocp(struct rtl_hw *hw) +{ + bool allow_access = false; + u16 mac_ocp_data; + + if (!HW_DASH_SUPPORT_DASH(hw)) + goto exit; + + allow_access = true; + switch (hw->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + mac_ocp_data = rtl_mac_ocp_read(hw, 0xd460); + if (mac_ocp_data == 0xffff || !(mac_ocp_data & BIT_0)) + allow_access = false; + break; + case CFG_METHOD_8: + case CFG_METHOD_9: + mac_ocp_data = rtl_mac_ocp_read(hw, 0xd4c0); + if (mac_ocp_data == 0xffff || (mac_ocp_data & BIT_3)) + allow_access = false; + break; + default: + goto exit; + } +exit: + return allow_access; +} + +static u32 +rtl_get_dash_fw_ver(struct rtl_hw *hw) +{ + u32 ver = 0xffffffff; + + if (FALSE == HW_DASH_SUPPORT_GET_FIRMWARE_VERSION(hw)) + goto exit; + + ver = rtl_ocp_read(hw, OCP_REG_FIRMWARE_MAJOR_VERSION, 4); + +exit: + return ver; +} + +static int +_rtl_check_dash(struct rtl_hw *hw) +{ + if (!hw->AllowAccessDashOcp) + return 0; + + if (HW_DASH_SUPPORT_TYPE_2(hw) || HW_DASH_SUPPORT_TYPE_4(hw)) { + if (rtl_ocp_read(hw, 0x128, 1) & BIT_0) + return 1; + } + + return 0; +} + +int +rtl_check_dash(struct rtl_hw *hw) +{ + u32 ver; + + if (_rtl_check_dash(hw)) { + ver = rtl_get_dash_fw_ver(hw); + if (!(ver == 0 || ver == 0xffffffff)) + return 1; + } + + return 0; +} + diff --git a/drivers/net/r8169/r8169_dash.h b/drivers/net/r8169/r8169_dash.h new file mode 100644 index 0000000000..d89b2e2d3b --- /dev/null +++ b/drivers/net/r8169/r8169_dash.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Realtek Corporation. All rights reserved + */ + +#ifndef _R8169_DASH_H_ +#define _R8169_DASH_H_ + +#include +#include + +#include +#include + +#include "r8169_base.h" +#include "r8169_hw.h" + +#define HW_DASH_SUPPORT_DASH(_M) ((_M)->HwSuppDashVer > 0) +#define HW_DASH_SUPPORT_TYPE_1(_M) ((_M)->HwSuppDashVer == 1) +#define HW_DASH_SUPPORT_TYPE_2(_M) ((_M)->HwSuppDashVer == 2) +#define HW_DASH_SUPPORT_TYPE_3(_M) ((_M)->HwSuppDashVer == 3) +#define HW_DASH_SUPPORT_TYPE_4(_M) ((_M)->HwSuppDashVer == 4) + +#define HW_DASH_SUPPORT_GET_FIRMWARE_VERSION(_M) (HW_DASH_SUPPORT_TYPE_2(_M) || \ + HW_DASH_SUPPORT_TYPE_3(_M) || \ + HW_DASH_SUPPORT_TYPE_4(_M)) + +#define OCP_REG_FIRMWARE_MAJOR_VERSION 0x120 + +bool rtl_is_allow_access_dash_ocp(struct rtl_hw *hw); + +int rtl_check_dash(struct rtl_hw *hw); + + +#endif + diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index 294d942862..9af46b390c 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -111,6 +111,15 @@ rtl_dev_stop(struct rte_eth_dev *dev) if (hw->adapter_stopped) return 0; + rtl_nic_reset(hw); + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_mac_ocp_write(hw, 0xE00A, hw->mcu_pme_setting); + break; + } + rtl_powerdown_pll(hw); hw->adapter_stopped = 1; @@ -125,6 +134,8 @@ rtl_dev_stop(struct rte_eth_dev *dev) static int rtl_dev_close(struct rte_eth_dev *dev) { + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; int ret_stp; if (rte_eal_process_type() != RTE_PROC_PRIMARY) @@ -132,6 +143,9 @@ rtl_dev_close(struct rte_eth_dev *dev) ret_stp = rtl_dev_stop(dev); + /* Reprogram the RAR[0] in case user changed it. */ + rtl_rar_set(hw, hw->mac_addr); + return ret_stp; } @@ -139,9 +153,10 @@ static int rtl_dev_init(struct rte_eth_dev *dev) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); struct rtl_hw *hw = &adapter->hw; + struct rte_ether_addr *perm_addr = (struct rte_ether_addr *)hw->mac_addr; + char buf[RTE_ETHER_ADDR_FMT_SIZE]; dev->dev_ops = &rtl_eth_dev_ops; dev->tx_pkt_burst = &rtl_xmit_pkts; @@ -153,9 +168,39 @@ rtl_dev_init(struct rte_eth_dev *dev) rte_eth_copy_pci_info(dev, pci_dev); + hw->mmio_addr = (u8 *)pci_dev->mem_resource[2].addr; /* RTL8169 uses BAR2 */ + + rtl_get_mac_version(hw, pci_dev); + if (rtl_set_hw_ops(hw)) return -ENOTSUP; + rtl_hw_initialize(hw); + + /* Read the permanent MAC address out of ROM */ + rtl_get_mac_address(hw, perm_addr); + + if (!rte_is_valid_assigned_ether_addr(perm_addr)) { + rte_eth_random_addr(&perm_addr->addr_bytes[0]); + + rte_ether_format_addr(buf, sizeof(buf), perm_addr); + + PMD_INIT_LOG(NOTICE, "r8169: Assign randomly generated MAC address %s", buf); + } + + /* Allocate memory for storing MAC addresses */ + dev->data->mac_addrs = rte_zmalloc("r8169", RTE_ETHER_ADDR_LEN, 0); + + if (dev->data->mac_addrs == NULL) { + PMD_INIT_LOG(ERR, "MAC Malloc failed"); + return -ENOMEM; + } + + /* Copy the permanent MAC address */ + rte_ether_addr_copy(perm_addr, &dev->data->mac_addrs[0]); + + rtl_rar_set(hw, &perm_addr->addr_bytes[0]); + return 0; } diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index a0da173685..de90b33289 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -23,14 +23,28 @@ struct rtl_hw_ops { void (*hw_phy_mcu_config)(struct rtl_hw *hw); }; +/* Flow control settings */ +enum rtl_fc_mode { + rtl_fc_none = 0, + rtl_fc_rx_pause, + rtl_fc_tx_pause, + rtl_fc_full, + rtl_fc_default +}; + struct rtl_hw { struct rtl_hw_ops hw_ops; u8 adapter_stopped; u8 *mmio_addr; + u8 *cmac_ioaddr; /* cmac memory map physical address */ + u8 chipset_name; + u8 efuse_ver; + u8 HwIcVerUnknown; u32 mcfg; u32 mtu; u8 HwSuppIntMitiVer; u16 cur_page; + u8 mac_addr[MAC_ADDR_LEN]; u8 RequirePhyMdiSwapPatch; u8 NotWrMcuPatchCode; @@ -44,10 +58,24 @@ struct rtl_hw { u16 sw_ram_code_ver; u16 hw_ram_code_ver; + u8 autoneg; + u8 duplex; + u32 speed; + u32 advertising; + enum rtl_fc_mode fcpause; + u32 HwSuppMaxPhyLinkSpeed; + u8 HwSuppNowIsOobVer; + + u16 mcu_pme_setting; + /* Enable Tx No Close */ - u8 EnableTxNoClose; + u8 HwSuppTxNoCloseVer; + u8 EnableTxNoClose; + u16 hw_clo_ptr_reg; + u16 sw_tail_ptr_reg; + u32 MaxTxDescPtrMask; /* Dash */ u8 HwSuppDashVer; diff --git a/drivers/net/r8169/r8169_hw.c b/drivers/net/r8169/r8169_hw.c index fb4ea21237..e5d1b249e2 100644 --- a/drivers/net/r8169/r8169_hw.c +++ b/drivers/net/r8169/r8169_hw.c @@ -13,6 +13,7 @@ #include "r8169_hw.h" #include "r8169_logs.h" +#include "r8169_dash.h" static u32 rtl_eri_read_with_oob_base_address(struct rtl_hw *hw, int addr, int len, @@ -920,3 +921,585 @@ rtl_write_mac_mcu_ram_code(struct rtl_hw *hw, const u16 *entry, u16 entry_cnt) _rtl_write_mac_mcu_ram_code(hw, entry, entry_cnt); } +bool +rtl_is_speed_mode_valid(u32 speed) +{ + switch (speed) { + case SPEED_5000: + case SPEED_2500: + case SPEED_1000: + case SPEED_100: + case SPEED_10: + return true; + default: + return false; + } +} + +static bool +rtl_is_duplex_mode_valid(u8 duplex) +{ + switch (duplex) { + case DUPLEX_FULL: + case DUPLEX_HALF: + return true; + default: + return false; + } +} + +static bool +rtl_is_autoneg_mode_valid(u32 autoneg) +{ + switch (autoneg) { + case AUTONEG_ENABLE: + case AUTONEG_DISABLE: + return true; + default: + return false; + } +} + +static void +rtl_set_link_option(struct rtl_hw *hw, u8 autoneg, u32 speed, u8 duplex, + enum rtl_fc_mode fc) +{ + u64 adv; + + if (!rtl_is_speed_mode_valid(speed)) + speed = SPEED_5000; + + if (!rtl_is_duplex_mode_valid(duplex)) + duplex = DUPLEX_FULL; + + if (!rtl_is_autoneg_mode_valid(autoneg)) + autoneg = AUTONEG_ENABLE; + + speed = RTE_MIN(speed, hw->HwSuppMaxPhyLinkSpeed); + + adv = 0; + switch (speed) { + case SPEED_5000: + adv |= ADVERTISE_5000_FULL; + /* Fall through */ + case SPEED_2500: + adv |= ADVERTISE_2500_FULL; + /* Fall through */ + default: + adv |= (ADVERTISE_10_HALF | ADVERTISE_10_FULL | + ADVERTISE_100_HALF | ADVERTISE_100_FULL | + ADVERTISE_1000_HALF | ADVERTISE_1000_FULL); + break; + } + + hw->autoneg = autoneg; + hw->speed = speed; + hw->duplex = duplex; + hw->advertising = adv; + hw->fcpause = fc; +} + +static void +rtl_init_software_variable(struct rtl_hw *hw) +{ + int tx_no_close_enable = 1; + unsigned int speed_mode = SPEED_5000; + unsigned int duplex_mode = DUPLEX_FULL; + unsigned int autoneg_mode = AUTONEG_ENABLE; + u8 tmp; + + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + tmp = (u8)rtl_mac_ocp_read(hw, 0xD006); + if (tmp == 0x02 || tmp == 0x04) + hw->HwSuppDashVer = 2; + break; + case CFG_METHOD_54: + case CFG_METHOD_55: + hw->HwSuppDashVer = 4; + break; + default: + hw->HwSuppDashVer = 0; + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + if (HW_DASH_SUPPORT_DASH(hw)) + hw->HwSuppOcpChannelVer = 2; + break; + case CFG_METHOD_54: + case CFG_METHOD_55: + hw->HwSuppOcpChannelVer = 2; + break; + } + + hw->AllowAccessDashOcp = rtl_is_allow_access_dash_ocp(hw); + + if (HW_DASH_SUPPORT_DASH(hw) && rtl_check_dash(hw)) + hw->DASH = 1; + else + hw->DASH = 0; + + if (HW_DASH_SUPPORT_TYPE_2(hw)) + hw->cmac_ioaddr = hw->mmio_addr; + + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + hw->chipset_name = RTL8125A; + break; + case CFG_METHOD_50: + case CFG_METHOD_51: + hw->chipset_name = RTL8125B; + break; + case CFG_METHOD_52: + case CFG_METHOD_53: + hw->chipset_name = RTL8168KB; + break; + case CFG_METHOD_54: + case CFG_METHOD_55: + hw->chipset_name = RTL8125BP; + break; + case CFG_METHOD_56: + case CFG_METHOD_57: + hw->chipset_name = RTL8125D; + break; + case CFG_METHOD_69 ... CFG_METHOD_71: + hw->chipset_name = RTL8126A; + break; + default: + hw->chipset_name = UNKNOWN; + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + hw->HwSuppNowIsOobVer = 1; + } + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + hw->HwSuppCheckPhyDisableModeVer = 3; + } + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_51: + case CFG_METHOD_54 ... CFG_METHOD_57: + hw->HwSuppMaxPhyLinkSpeed = 2500; + break; + case CFG_METHOD_69 ... CFG_METHOD_71: + hw->HwSuppMaxPhyLinkSpeed = 5000; + break; + default: + hw->HwSuppMaxPhyLinkSpeed = 1000; + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_53: + hw->HwSuppTxNoCloseVer = 3; + break; + case CFG_METHOD_54 ... CFG_METHOD_57: + hw->HwSuppTxNoCloseVer = 6; + break; + case CFG_METHOD_69: + hw->HwSuppTxNoCloseVer = 4; + break; + case CFG_METHOD_70: + case CFG_METHOD_71: + hw->HwSuppTxNoCloseVer = 5; + break; + } + + switch (hw->HwSuppTxNoCloseVer) { + case 5: + case 6: + hw->MaxTxDescPtrMask = MAX_TX_NO_CLOSE_DESC_PTR_MASK_V4; + break; + case 4: + hw->MaxTxDescPtrMask = MAX_TX_NO_CLOSE_DESC_PTR_MASK_V3; + break; + case 3: + hw->MaxTxDescPtrMask = MAX_TX_NO_CLOSE_DESC_PTR_MASK_V2; + break; + default: + tx_no_close_enable = 0; + break; + } + + if (hw->HwSuppTxNoCloseVer > 0 && tx_no_close_enable == 1) + hw->EnableTxNoClose = TRUE; + + switch (hw->HwSuppTxNoCloseVer) { + case 4: + case 5: + hw->hw_clo_ptr_reg = HW_CLO_PTR0_8126; + hw->sw_tail_ptr_reg = SW_TAIL_PTR0_8126; + break; + case 6: + hw->hw_clo_ptr_reg = HW_CLO_PTR0_8125BP; + hw->sw_tail_ptr_reg = SW_TAIL_PTR0_8125BP; + break; + default: + hw->hw_clo_ptr_reg = HW_CLO_PTR0_8125; + hw->sw_tail_ptr_reg = SW_TAIL_PTR0_8125; + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_48: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_48; + break; + case CFG_METHOD_49: + case CFG_METHOD_52: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_49; + break; + case CFG_METHOD_50: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_50; + break; + case CFG_METHOD_51: + case CFG_METHOD_53: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_51; + break; + case CFG_METHOD_54: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_54; + break; + case CFG_METHOD_55: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_55; + break; + case CFG_METHOD_56: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_56; + break; + case CFG_METHOD_57: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_57; + break; + case CFG_METHOD_69: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_69; + break; + case CFG_METHOD_70: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_70; + break; + case CFG_METHOD_71: + hw->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_71; + break; + } + + if (hw->HwIcVerUnknown) { + hw->NotWrRamCodeToMicroP = TRUE; + hw->NotWrMcuPatchCode = TRUE; + } + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + hw->HwSuppMacMcuVer = 2; + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + hw->MacMcuPageSize = RTL_MAC_MCU_PAGE_SIZE; + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_49: + case CFG_METHOD_52: + if ((rtl_mac_ocp_read(hw, 0xD442) & BIT_5) && + (rtl_mdio_direct_read_phy_ocp(hw, 0xD068) & BIT_1)) + hw->RequirePhyMdiSwapPatch = TRUE; + break; + } + + switch (hw->mcfg) { + case CFG_METHOD_48: + case CFG_METHOD_49: + case CFG_METHOD_52: + hw->HwSuppIntMitiVer = 3; + break; + case CFG_METHOD_50: + case CFG_METHOD_51: + case CFG_METHOD_53: + case CFG_METHOD_69: + hw->HwSuppIntMitiVer = 4; + break; + case CFG_METHOD_54 ... CFG_METHOD_57: + hw->HwSuppIntMitiVer = 6; + break; + case CFG_METHOD_70: + case CFG_METHOD_71: + hw->HwSuppIntMitiVer = 5; + break; + } + + rtl_set_link_option(hw, autoneg_mode, speed_mode, duplex_mode, rtl_fc_full); + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + hw->mcu_pme_setting = rtl_mac_ocp_read(hw, 0xE00A); + break; + } + + hw->mtu = RTL_DEFAULT_MTU; +} + +static void +rtl_exit_realwow(struct rtl_hw *hw) +{ + /* Disable realwow function */ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_mac_ocp_write(hw, 0xC0BC, 0x00FF); + break; + } +} + +static void +rtl_disable_now_is_oob(struct rtl_hw *hw) +{ + if (hw->HwSuppNowIsOobVer == 1) + RTL_W8(hw, MCUCmd_reg, RTL_R8(hw, MCUCmd_reg) & ~Now_is_oob); +} + +static void +rtl_wait_ll_share_fifo_ready(struct rtl_hw *hw) +{ + int i; + + for (i = 0; i < 10; i++) { + udelay(100); + if (RTL_R16(hw, 0xD2) & BIT_9) + break; + } +} + +static void +rtl_exit_oob(struct rtl_hw *hw) +{ + u16 data16; + + rtl_disable_rx_packet_filter(hw); + + rtl_exit_realwow(hw); + + rtl_nic_reset(hw); + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_disable_now_is_oob(hw); + + data16 = rtl_mac_ocp_read(hw, 0xE8DE) & ~BIT_14; + rtl_mac_ocp_write(hw, 0xE8DE, data16); + rtl_wait_ll_share_fifo_ready(hw); + + rtl_mac_ocp_write(hw, 0xC0AA, 0x07D0); + + rtl_mac_ocp_write(hw, 0xC0A6, 0x01B5); + + rtl_mac_ocp_write(hw, 0xC01E, 0x5555); + + rtl_wait_ll_share_fifo_ready(hw); + break; + } +} + +static void +rtl_disable_ups(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_mac_ocp_write(hw, 0xD40A, rtl_mac_ocp_read(hw, 0xD40A) & ~BIT_4); + break; + } +} + +static void +rtl8125_disable_ocp_phy_power_saving(struct rtl_hw *hw) +{ + u16 val; + + if (hw->mcfg == CFG_METHOD_48 || hw->mcfg == CFG_METHOD_49 || + hw->mcfg == CFG_METHOD_52) { + val = rtl_mdio_direct_read_phy_ocp(hw, 0xC416); + if (val != 0x0050) { + rtl_set_phy_mcu_patch_request(hw); + rtl_mdio_direct_write_phy_ocp(hw, 0xC416, 0x0000); + rtl_mdio_direct_write_phy_ocp(hw, 0xC416, 0x0500); + rtl_clear_phy_mcu_patch_request(hw); + } + } +} + +static void +rtl_hw_init(struct rtl_hw *hw) +{ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_enable_aspm_clkreq_lock(hw, 0); + rtl_enable_force_clkreq(hw, 0); + break; + } + + rtl_disable_ups(hw); + + hw->hw_ops.hw_mac_mcu_config(hw); + + /* Disable ocp phy power saving */ + rtl8125_disable_ocp_phy_power_saving(hw); +} + +void +rtl_hw_initialize(struct rtl_hw *hw) +{ + rtl_init_software_variable(hw); + + rtl_exit_oob(hw); + + rtl_hw_init(hw); + + rtl_nic_reset(hw); +} + +void +rtl_get_mac_version(struct rtl_hw *hw, struct rte_pci_device *pci_dev) +{ + u32 reg, val32; + u32 ic_version_id; + + val32 = RTL_R32(hw, TxConfig); + reg = val32 & 0x7c800000; + ic_version_id = val32 & 0x00700000; + + switch (reg) { + case 0x60800000: + if (ic_version_id == 0x00000000) + hw->mcfg = CFG_METHOD_48; + + else if (ic_version_id == 0x100000) + hw->mcfg = CFG_METHOD_49; + + else { + hw->mcfg = CFG_METHOD_49; + hw->HwIcVerUnknown = TRUE; + } + + hw->efuse_ver = EFUSE_SUPPORT_V4; + break; + case 0x64000000: + if (ic_version_id == 0x00000000) + hw->mcfg = CFG_METHOD_50; + + else if (ic_version_id == 0x100000) + hw->mcfg = CFG_METHOD_51; + + else { + hw->mcfg = CFG_METHOD_51; + hw->HwIcVerUnknown = TRUE; + } + + hw->efuse_ver = EFUSE_SUPPORT_V4; + break; + case 0x68000000: + if (ic_version_id == 0x00000000) + hw->mcfg = CFG_METHOD_54; + else if (ic_version_id == 0x100000) + hw->mcfg = CFG_METHOD_55; + else { + hw->mcfg = CFG_METHOD_55; + hw->HwIcVerUnknown = TRUE; + } + + hw->efuse_ver = EFUSE_SUPPORT_V4; + break; + case 0x68800000: + if (ic_version_id == 0x00000000) + hw->mcfg = CFG_METHOD_56; + else if (ic_version_id == 0x100000) + hw->mcfg = CFG_METHOD_57; + else { + hw->mcfg = CFG_METHOD_57; + hw->HwIcVerUnknown = TRUE; + } + + hw->efuse_ver = EFUSE_SUPPORT_V4; + break; + case 0x64800000: + if (ic_version_id == 0x00000000) + hw->mcfg = CFG_METHOD_69; + else if (ic_version_id == 0x100000) + hw->mcfg = CFG_METHOD_70; + else if (ic_version_id == 0x200000) + hw->mcfg = CFG_METHOD_71; + else { + hw->mcfg = CFG_METHOD_71; + hw->HwIcVerUnknown = TRUE; + } + + hw->efuse_ver = EFUSE_SUPPORT_V4; + break; + default: + PMD_INIT_LOG(NOTICE, "unknown chip version (%x)", reg); + hw->mcfg = CFG_METHOD_DEFAULT; + hw->HwIcVerUnknown = TRUE; + hw->efuse_ver = EFUSE_NOT_SUPPORT; + break; + } + + if (pci_dev->id.device_id == 0x8162) { + if (hw->mcfg == CFG_METHOD_49) + hw->mcfg = CFG_METHOD_52; + else if (hw->mcfg == CFG_METHOD_51) + hw->mcfg = CFG_METHOD_53; + } +} + +int +rtl_get_mac_address(struct rtl_hw *hw, struct rte_ether_addr *ea) +{ + u8 mac_addr[MAC_ADDR_LEN]; + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + *(u32 *)&mac_addr[0] = RTL_R32(hw, BACKUP_ADDR0_8125); + *(u16 *)&mac_addr[4] = RTL_R16(hw, BACKUP_ADDR1_8125); + break; + default: + break; + } + + rte_ether_addr_copy((struct rte_ether_addr *)mac_addr, ea); + + return 0; +} + +void +rtl_rar_set(struct rtl_hw *hw, uint8_t *addr) +{ + uint32_t rar_low = 0; + uint32_t rar_high = 0; + + rar_low = ((uint32_t)addr[0] | ((uint32_t)addr[1] << 8) | + ((uint32_t)addr[2] << 16) | ((uint32_t)addr[3] << 24)); + + rar_high = ((uint32_t)addr[4] | ((uint32_t)addr[5] << 8)); + + rtl_enable_cfg9346_write(hw); + + RTL_W32(hw, MAC0, rar_low); + RTL_W32(hw, MAC4, rar_high); + + rtl_disable_cfg9346_write(hw); +} + diff --git a/drivers/net/r8169/r8169_hw.h b/drivers/net/r8169/r8169_hw.h index 8fd48a3077..3746b46084 100644 --- a/drivers/net/r8169/r8169_hw.h +++ b/drivers/net/r8169/r8169_hw.h @@ -42,6 +42,15 @@ void rtl_hw_disable_mac_mcu_bps(struct rtl_hw *hw); void rtl_write_mac_mcu_ram_code(struct rtl_hw *hw, const u16 *entry, u16 entry_cnt); +void rtl_hw_initialize(struct rtl_hw *hw); + +bool rtl_is_speed_mode_valid(u32 speed); + +void rtl_get_mac_version(struct rtl_hw *hw, struct rte_pci_device *pci_dev); +int rtl_get_mac_address(struct rtl_hw *hw, struct rte_ether_addr *ea); + +void rtl_rar_set(struct rtl_hw *hw, uint8_t *addr); + extern const struct rtl_hw_ops rtl8125a_ops; extern const struct rtl_hw_ops rtl8125b_ops; extern const struct rtl_hw_ops rtl8125bp_ops; @@ -60,5 +69,38 @@ extern const struct rtl_hw_ops rtl8126a_ops; #define HW_SUPPORT_MAC_MCU(_M) ((_M)->HwSuppMacMcuVer > 0) #define HW_HAS_WRITE_PHY_MCU_RAM_CODE(_M) (((_M)->HwHasWrRamCodeToMicroP == TRUE) ? 1 : 0) +/* Tx NO CLOSE */ +#define MAX_TX_NO_CLOSE_DESC_PTR_V2 0x10000 +#define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V2 0xFFFF +#define MAX_TX_NO_CLOSE_DESC_PTR_V3 0x100000000 +#define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V3 0xFFFFFFFF +#define MAX_TX_NO_CLOSE_DESC_PTR_V4 0x80000000 +#define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V4 0x7FFFFFFF +#define TX_NO_CLOSE_SW_PTR_MASK_V2 0x1FFFF + +/* Ram code version */ +#define NIC_RAMCODE_VERSION_CFG_METHOD_48 (0x0b11) +#define NIC_RAMCODE_VERSION_CFG_METHOD_49 (0x0b33) +#define NIC_RAMCODE_VERSION_CFG_METHOD_50 (0x0b17) +#define NIC_RAMCODE_VERSION_CFG_METHOD_51 (0x0b99) +#define NIC_RAMCODE_VERSION_CFG_METHOD_54 (0x0013) +#define NIC_RAMCODE_VERSION_CFG_METHOD_55 (0x0001) +#define NIC_RAMCODE_VERSION_CFG_METHOD_56 (0x0016) +#define NIC_RAMCODE_VERSION_CFG_METHOD_57 (0x0001) +#define NIC_RAMCODE_VERSION_CFG_METHOD_69 (0x0023) +#define NIC_RAMCODE_VERSION_CFG_METHOD_70 (0x0033) +#define NIC_RAMCODE_VERSION_CFG_METHOD_71 (0x0051) + +#define RTL_MAC_MCU_PAGE_SIZE 256 +#define RTL_DEFAULT_MTU 1500 + +enum effuse { + EFUSE_NOT_SUPPORT = 0, + EFUSE_SUPPORT_V1, + EFUSE_SUPPORT_V2, + EFUSE_SUPPORT_V3, + EFUSE_SUPPORT_V4, +}; + #endif diff --git a/drivers/net/r8169/r8169_phy.h b/drivers/net/r8169/r8169_phy.h index f4da9f50ed..599a8957c4 100644 --- a/drivers/net/r8169/r8169_phy.h +++ b/drivers/net/r8169/r8169_phy.h @@ -20,17 +20,17 @@ #define MII_PHYSID1 0x02 /* PHYS ID 1 */ #define MII_PHYSID2 0x03 /* PHYS ID 2 */ #define MII_ADVERTISE 0x04 /* Advertisement control reg */ -#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ -#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ #define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ -#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ #define MII_SREVISION 0x16 /* Silicon revision */ #define MII_RESV1 0x17 /* Reserved... */ #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ @@ -80,14 +80,14 @@ #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ -#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ +#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ #define ADVERTISE_RESV 0x1000 /* Unused... */ #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ -#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ -#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ /* 1000BASE-T Control register */ #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ @@ -95,7 +95,7 @@ #define RTK_ADVERTISE_2500FULL 0x80 #define RTK_ADVERTISE_5000FULL 0x100 -#define RTK_ADVERTISE_10000FULL 0x1000 +#define RTK_ADVERTISE_10000FULL 0x1000 #define RTK_LPA_ADVERTISE_2500FULL 0x20 #define RTK_LPA_ADVERTISE_5000FULL 0x40 #define RTK_LPA_ADVERTISE_10000FULL 0x800 From patchwork Tue Oct 15 03:09:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145940 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C606345B3C; Tue, 15 Oct 2024 05:11:07 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D261440669; Tue, 15 Oct 2024 05:11:04 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id BD8EA40156 for ; Tue, 15 Oct 2024 05:11:02 +0200 (CEST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 49F3B0GU0820232, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realsil.com.cn; s=dkim; t=1728961861; bh=4RTvefu6F5RAFt+Z297iKe6GawQT6LNPYLF3pgP6e0M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; 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Tue, 15 Oct 2024 11:11:00 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:11:00 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 10/18] net/r8169: add link status and interrupt management Date: Tue, 15 Oct 2024 11:09:20 +0800 Message-ID: <20241015030928.70642-11-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_base.h | 5 +- drivers/net/r8169/r8169_ethdev.c | 279 ++++++++++++++++++++++++++++++- drivers/net/r8169/r8169_ethdev.h | 3 + drivers/net/r8169/r8169_hw.c | 8 +- drivers/net/r8169/r8169_hw.h | 3 + drivers/net/r8169/r8169_phy.c | 121 ++++++++++++++ drivers/net/r8169/r8169_phy.h | 3 + 7 files changed, 413 insertions(+), 9 deletions(-) diff --git a/drivers/net/r8169/r8169_base.h b/drivers/net/r8169/r8169_base.h index 2ee6fc6782..2960288981 100644 --- a/drivers/net/r8169/r8169_base.h +++ b/drivers/net/r8169/r8169_base.h @@ -379,6 +379,7 @@ enum RTL_register_content { /* PHY status */ PowerSaveStatus = 0x80, + _5000bpsF = 0x1000, _2500bpsF = 0x400, TxFlowCtrl = 0x40, RxFlowCtrl = 0x20, @@ -559,10 +560,6 @@ enum RTL_chipset_name { #define ADVERTISE_5000_HALF 0x0100 /* NOT used, just FYI */ #define ADVERTISE_5000_FULL 0x0200 -#define RTL8126_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ - ADVERTISE_100_HALF | ADVERTISE_100_FULL | ADVERTISE_1000_FULL | \ - ADVERTISE_2500_FULL | ADVERTISE_5000_FULL) - #define MAC_ADDR_LEN RTE_ETHER_ADDR_LEN static inline u32 diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index 9af46b390c..ecf4a4e984 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -35,6 +35,9 @@ static int rtl_dev_start(struct rte_eth_dev *dev); static int rtl_dev_stop(struct rte_eth_dev *dev); static int rtl_dev_reset(struct rte_eth_dev *dev); static int rtl_dev_close(struct rte_eth_dev *dev); +static int rtl_dev_link_update(struct rte_eth_dev *dev, int wait __rte_unused); +static int rtl_dev_set_link_up(struct rte_eth_dev *dev); +static int rtl_dev_set_link_down(struct rte_eth_dev *dev); /* * The set of PCI devices this driver supports @@ -53,6 +56,10 @@ static const struct eth_dev_ops rtl_eth_dev_ops = { .dev_stop = rtl_dev_stop, .dev_close = rtl_dev_close, .dev_reset = rtl_dev_reset, + .dev_set_link_up = rtl_dev_set_link_up, + .dev_set_link_down = rtl_dev_set_link_down, + + .link_update = rtl_dev_link_update, }; static int @@ -61,6 +68,119 @@ rtl_dev_configure(struct rte_eth_dev *dev __rte_unused) return 0; } +static void +rtl_disable_intr(struct rtl_hw *hw) +{ + PMD_INIT_FUNC_TRACE(); + RTL_W32(hw, IMR0_8125, 0x0000); + RTL_W32(hw, ISR0_8125, RTL_R32(hw, ISR0_8125)); +} + +static void +rtl_enable_intr(struct rtl_hw *hw) +{ + PMD_INIT_FUNC_TRACE(); + RTL_W32(hw, IMR0_8125, LinkChg); +} + +static int +_rtl_setup_link(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + u64 adv = 0; + u32 *link_speeds = &dev->data->dev_conf.link_speeds; + + /* Setup link speed and duplex */ + if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) + rtl_set_link_option(hw, AUTONEG_ENABLE, SPEED_5000, DUPLEX_FULL, rtl_fc_full); + else if (*link_speeds != 0) { + + if (*link_speeds & ~(RTE_ETH_LINK_SPEED_10M_HD | RTE_ETH_LINK_SPEED_10M | + RTE_ETH_LINK_SPEED_100M_HD | RTE_ETH_LINK_SPEED_100M | + RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G | + RTE_ETH_LINK_SPEED_5G | RTE_ETH_LINK_SPEED_FIXED)) + goto error_invalid_config; + + if (*link_speeds & RTE_ETH_LINK_SPEED_10M_HD) { + hw->speed = SPEED_10; + hw->duplex = DUPLEX_HALF; + adv |= ADVERTISE_10_HALF; + } + if (*link_speeds & RTE_ETH_LINK_SPEED_10M) { + hw->speed = SPEED_10; + hw->duplex = DUPLEX_FULL; + adv |= ADVERTISE_10_FULL; + } + if (*link_speeds & RTE_ETH_LINK_SPEED_100M_HD) { + hw->speed = SPEED_100; + hw->duplex = DUPLEX_HALF; + adv |= ADVERTISE_100_HALF; + } + if (*link_speeds & RTE_ETH_LINK_SPEED_100M) { + hw->speed = SPEED_100; + hw->duplex = DUPLEX_FULL; + adv |= ADVERTISE_100_FULL; + } + if (*link_speeds & RTE_ETH_LINK_SPEED_1G) { + hw->speed = SPEED_1000; + hw->duplex = DUPLEX_FULL; + adv |= ADVERTISE_1000_FULL; + } + if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G) { + hw->speed = SPEED_2500; + hw->duplex = DUPLEX_FULL; + adv |= ADVERTISE_2500_FULL; + } + if (*link_speeds & RTE_ETH_LINK_SPEED_5G) { + hw->speed = SPEED_5000; + hw->duplex = DUPLEX_FULL; + adv |= ADVERTISE_5000_FULL; + } + + hw->autoneg = AUTONEG_ENABLE; + hw->advertising = adv; + } + + rtl_set_speed(hw); + + return 0; + +error_invalid_config: + PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u", + dev->data->dev_conf.link_speeds, dev->data->port_id); + return -EINVAL; +} + +static int +rtl_setup_link(struct rte_eth_dev *dev) +{ +#ifdef RTE_EXEC_ENV_FREEBSD + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + struct rte_eth_link link; + int count; +#endif + + _rtl_setup_link(dev); + +#ifdef RTE_EXEC_ENV_FREEBSD + for (count = 0; count < R8169_LINK_CHECK_TIMEOUT; count++) { + if (!(RTL_R16(hw, PHYstatus) & LinkStatus)) { + msleep(R8169_LINK_CHECK_INTERVAL); + continue; + } + + rtl_dev_link_update(dev, 0); + + rte_eth_linkstatus_get(dev, &link); + + return 0; + } +#endif + return 0; +} + /* * Configure device link speed and setup link. * It returns 0 on success. @@ -70,8 +190,13 @@ rtl_dev_start(struct rte_eth_dev *dev) { struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); struct rtl_hw *hw = &adapter->hw; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; int err; + /* Disable uio/vfio intr/eventfd mapping */ + rte_intr_disable(intr_handle); + rtl_powerup_pll(hw); rtl_hw_ephy_config(hw); @@ -90,6 +215,14 @@ rtl_dev_start(struct rte_eth_dev *dev) goto error; } + /* Enable uio/vfio intr/eventfd mapping */ + rte_intr_enable(intr_handle); + + /* Resume enabled intr since hw reset */ + rtl_enable_intr(hw); + + rtl_setup_link(dev); + rtl_mdio_write(hw, 0x1F, 0x0000); hw->adapter_stopped = 0; @@ -107,10 +240,13 @@ rtl_dev_stop(struct rte_eth_dev *dev) { struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); struct rtl_hw *hw = &adapter->hw; + struct rte_eth_link link; if (hw->adapter_stopped) return 0; + rtl_disable_intr(hw); + rtl_nic_reset(hw); switch (hw->mcfg) { @@ -122,21 +258,140 @@ rtl_dev_stop(struct rte_eth_dev *dev) rtl_powerdown_pll(hw); + /* Clear the recorded link status */ + memset(&link, 0, sizeof(link)); + rte_eth_linkstatus_set(dev, &link); + hw->adapter_stopped = 1; dev->data->dev_started = 0; return 0; } +static int +rtl_dev_set_link_up(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + rtl_powerup_pll(hw); + + return 0; +} + +static int +rtl_dev_set_link_down(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + /* mcu pme intr masks */ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + rtl_mac_ocp_write(hw, 0xE00A, hw->mcu_pme_setting & ~(BIT_11 | BIT_14)); + break; + } + + rtl_powerdown_pll(hw); + + return 0; +} + +/* Return 0 means link status changed, -1 means not changed */ +static int +rtl_dev_link_update(struct rte_eth_dev *dev, int wait __rte_unused) +{ + struct rte_eth_link link, old; + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + u32 speed; + u16 status; + + link.link_status = RTE_ETH_LINK_DOWN; + link.link_speed = 0; + link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; + link.link_autoneg = RTE_ETH_LINK_AUTONEG; + + memset(&old, 0, sizeof(old)); + + /* Load old link status */ + rte_eth_linkstatus_get(dev, &old); + + /* Read current link status */ + status = RTL_R16(hw, PHYstatus); + + if (status & LinkStatus) { + link.link_status = RTE_ETH_LINK_UP; + + if (status & FullDup) { + link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; + if (hw->mcfg == CFG_METHOD_2) + RTL_W32(hw, TxConfig, (RTL_R32(hw, TxConfig) | + (BIT_24 | BIT_25)) & ~BIT_19); + + } else { + link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; + if (hw->mcfg == CFG_METHOD_2) + RTL_W32(hw, TxConfig, (RTL_R32(hw, TxConfig) | BIT_25) & + ~(BIT_19 | BIT_24)); + } + + if (status & _5000bpsF) + speed = 5000; + else if (status & _2500bpsF) + speed = 2500; + else if (status & _1000bpsF) + speed = 1000; + else if (status & _100bps) + speed = 100; + else + speed = 10; + + link.link_speed = speed; + } + + if (link.link_status == old.link_status) + return -1; + + rte_eth_linkstatus_set(dev, &link); + + return 0; +} + +static void +rtl_dev_interrupt_handler(void *param) +{ + struct rte_eth_dev *dev = (struct rte_eth_dev *)param; + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + uint32_t intr; + + intr = RTL_R32(hw, ISR0_8125); + + /* Clear all cause mask */ + rtl_disable_intr(hw); + + if (intr & LinkChg) + rtl_dev_link_update(dev, 0); + else + PMD_DRV_LOG(ERR, "r8169: interrupt unhandled."); + + rtl_enable_intr(hw); +} + /* * Reset and stop device. */ static int rtl_dev_close(struct rte_eth_dev *dev) { + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); struct rtl_hw *hw = &adapter->hw; - int ret_stp; + int retries = 0; + int ret_unreg, ret_stp; if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; @@ -146,6 +401,20 @@ rtl_dev_close(struct rte_eth_dev *dev) /* Reprogram the RAR[0] in case user changed it. */ rtl_rar_set(hw, hw->mac_addr); + /* Disable uio intr before callback unregister */ + rte_intr_disable(intr_handle); + + do { + ret_unreg = rte_intr_callback_unregister(intr_handle, rtl_dev_interrupt_handler, + dev); + if (ret_unreg >= 0 || ret_unreg == -ENOENT) + break; + else if (ret_unreg != -EAGAIN) + PMD_DRV_LOG(ERR, "r8169: intr callback unregister failed: %d", ret_unreg); + + rte_delay_ms(100); + } while (retries++ < (10 + 90)); + return ret_stp; } @@ -153,6 +422,7 @@ static int rtl_dev_init(struct rte_eth_dev *dev) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); struct rtl_hw *hw = &adapter->hw; struct rte_ether_addr *perm_addr = (struct rte_ether_addr *)hw->mac_addr; @@ -175,6 +445,8 @@ rtl_dev_init(struct rte_eth_dev *dev) if (rtl_set_hw_ops(hw)) return -ENOTSUP; + rtl_disable_intr(hw); + rtl_hw_initialize(hw); /* Read the permanent MAC address out of ROM */ @@ -201,6 +473,11 @@ rtl_dev_init(struct rte_eth_dev *dev) rtl_rar_set(hw, &perm_addr->addr_bytes[0]); + rte_intr_callback_register(intr_handle, rtl_dev_interrupt_handler, dev); + + /* Enable uio/vfio intr/eventfd mapping */ + rte_intr_enable(intr_handle); + return 0; } diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index de90b33289..03012365ca 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -101,6 +101,9 @@ struct rtl_adapter { #define RTL_DEV_PRIVATE(eth_dev) \ ((struct rtl_adapter *)((eth_dev)->data->dev_private)) +#define R8169_LINK_CHECK_TIMEOUT 50 /* 10s */ +#define R8169_LINK_CHECK_INTERVAL 200 /* ms */ + int rtl_rx_init(struct rte_eth_dev *dev); int rtl_tx_init(struct rte_eth_dev *dev); diff --git a/drivers/net/r8169/r8169_hw.c b/drivers/net/r8169/r8169_hw.c index e5d1b249e2..3be56061cf 100644 --- a/drivers/net/r8169/r8169_hw.c +++ b/drivers/net/r8169/r8169_hw.c @@ -960,7 +960,7 @@ rtl_is_autoneg_mode_valid(u32 autoneg) } } -static void +void rtl_set_link_option(struct rtl_hw *hw, u8 autoneg, u32 speed, u8 duplex, enum rtl_fc_mode fc) { @@ -1090,13 +1090,13 @@ rtl_init_software_variable(struct rtl_hw *hw) switch (hw->mcfg) { case CFG_METHOD_48 ... CFG_METHOD_51: case CFG_METHOD_54 ... CFG_METHOD_57: - hw->HwSuppMaxPhyLinkSpeed = 2500; + hw->HwSuppMaxPhyLinkSpeed = SPEED_2500; break; case CFG_METHOD_69 ... CFG_METHOD_71: - hw->HwSuppMaxPhyLinkSpeed = 5000; + hw->HwSuppMaxPhyLinkSpeed = SPEED_5000; break; default: - hw->HwSuppMaxPhyLinkSpeed = 1000; + hw->HwSuppMaxPhyLinkSpeed = SPEED_1000; break; } diff --git a/drivers/net/r8169/r8169_hw.h b/drivers/net/r8169/r8169_hw.h index 3746b46084..857f71deac 100644 --- a/drivers/net/r8169/r8169_hw.h +++ b/drivers/net/r8169/r8169_hw.h @@ -51,6 +51,9 @@ int rtl_get_mac_address(struct rtl_hw *hw, struct rte_ether_addr *ea); void rtl_rar_set(struct rtl_hw *hw, uint8_t *addr); +void rtl_set_link_option(struct rtl_hw *hw, u8 autoneg, u32 speed, u8 duplex, + enum rtl_fc_mode fc); + extern const struct rtl_hw_ops rtl8125a_ops; extern const struct rtl_hw_ops rtl8125b_ops; extern const struct rtl_hw_ops rtl8125bp_ops; diff --git a/drivers/net/r8169/r8169_phy.c b/drivers/net/r8169/r8169_phy.c index 3198116946..da033de79e 100644 --- a/drivers/net/r8169/r8169_phy.c +++ b/drivers/net/r8169/r8169_phy.c @@ -775,3 +775,124 @@ rtl_hw_phy_config(struct rtl_hw *hw) rtl_disable_eee(hw); } +static void +rtl_phy_restart_nway(struct rtl_hw *hw) +{ + if (rtl_is_in_phy_disable_mode(hw)) + return; + + rtl_mdio_write(hw, 0x1F, 0x0000); + rtl_mdio_write(hw, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); +} + +static void +rtl_phy_setup_force_mode(struct rtl_hw *hw, u32 speed, u8 duplex) +{ + u16 bmcr_true_force = 0; + + if (rtl_is_in_phy_disable_mode(hw)) + return; + + if (speed == SPEED_10 && duplex == DUPLEX_HALF) + bmcr_true_force = BMCR_SPEED10; + else if (speed == SPEED_10 && duplex == DUPLEX_FULL) + bmcr_true_force = BMCR_SPEED10 | BMCR_FULLDPLX; + else if (speed == SPEED_100 && duplex == DUPLEX_HALF) + bmcr_true_force = BMCR_SPEED100; + else if (speed == SPEED_100 && duplex == DUPLEX_FULL) + bmcr_true_force = BMCR_SPEED100 | BMCR_FULLDPLX; + else + return; + + rtl_mdio_write(hw, 0x1F, 0x0000); + rtl_mdio_write(hw, MII_BMCR, bmcr_true_force); +} + +static int +rtl_set_speed_xmii(struct rtl_hw *hw, u8 autoneg, u32 speed, u8 duplex, u32 adv) +{ + int auto_nego = 0; + int giga_ctrl = 0; + int ctrl_2500 = 0; + int rc = -EINVAL; + + /* Disable giga lite */ + rtl_clear_eth_phy_ocp_bit(hw, 0xA428, BIT_9); + rtl_clear_eth_phy_ocp_bit(hw, 0xA5EA, BIT_0); + + if (HW_SUPP_PHY_LINK_SPEED_5000M(hw)) + rtl_clear_eth_phy_ocp_bit(hw, 0xA5EA, BIT_1); + + if (!rtl_is_speed_mode_valid(speed)) { + speed = hw->HwSuppMaxPhyLinkSpeed; + duplex = DUPLEX_FULL; + adv |= hw->advertising; + } + + giga_ctrl = rtl_mdio_read(hw, MII_CTRL1000); + giga_ctrl &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); + ctrl_2500 = rtl_mdio_direct_read_phy_ocp(hw, 0xA5D4); + ctrl_2500 &= ~(RTK_ADVERTISE_2500FULL | RTK_ADVERTISE_5000FULL); + + if (autoneg == AUTONEG_ENABLE) { + /* N-way force */ + auto_nego = rtl_mdio_read(hw, MII_ADVERTISE); + auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | + ADVERTISE_100HALF | ADVERTISE_100FULL | + ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); + + if (adv & ADVERTISE_10_HALF) + auto_nego |= ADVERTISE_10HALF; + if (adv & ADVERTISE_10_FULL) + auto_nego |= ADVERTISE_10FULL; + if (adv & ADVERTISE_100_HALF) + auto_nego |= ADVERTISE_100HALF; + if (adv & ADVERTISE_100_FULL) + auto_nego |= ADVERTISE_100FULL; + if (adv & ADVERTISE_1000_HALF) + giga_ctrl |= ADVERTISE_1000HALF; + if (adv & ADVERTISE_1000_FULL) + giga_ctrl |= ADVERTISE_1000FULL; + if (adv & ADVERTISE_2500_FULL) + ctrl_2500 |= RTK_ADVERTISE_2500FULL; + if (adv & ADVERTISE_5000_FULL) + ctrl_2500 |= RTK_ADVERTISE_5000FULL; + + /* Flow control */ + if (hw->fcpause == rtl_fc_full) + auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; + + rtl_mdio_write(hw, 0x1f, 0x0000); + rtl_mdio_write(hw, MII_ADVERTISE, auto_nego); + rtl_mdio_write(hw, MII_CTRL1000, giga_ctrl); + rtl_mdio_direct_write_phy_ocp(hw, 0xA5D4, ctrl_2500); + rtl_phy_restart_nway(hw); + mdelay(20); + } else { + /* True force */ + if (speed == SPEED_10 || speed == SPEED_100) + rtl_phy_setup_force_mode(hw, speed, duplex); + else + goto out; + } + hw->autoneg = autoneg; + hw->speed = speed; + hw->duplex = duplex; + hw->advertising = adv; + + rc = 0; +out: + return rc; +} + +int +rtl_set_speed(struct rtl_hw *hw) +{ + int ret; + + ret = rtl_set_speed_xmii(hw, hw->autoneg, hw->speed, hw->duplex, + hw->advertising); + + return ret; +} + diff --git a/drivers/net/r8169/r8169_phy.h b/drivers/net/r8169/r8169_phy.h index 599a8957c4..7675fd6cc9 100644 --- a/drivers/net/r8169/r8169_phy.h +++ b/drivers/net/r8169/r8169_phy.h @@ -141,5 +141,8 @@ void rtl_powerdown_pll(struct rtl_hw *hw); void rtl_hw_ephy_config(struct rtl_hw *hw); void rtl_hw_phy_config(struct rtl_hw *hw); + +int rtl_set_speed(struct rtl_hw *hw); + #endif From patchwork Tue Oct 15 03:09:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145941 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 417D145B3C; Tue, 15 Oct 2024 05:11:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 357434065C; 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Tue, 15 Oct 2024 11:11:13 +0800 Received: from RSEXDAG02.realsil.com.cn (172.29.17.196) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:11:13 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXDAG02.realsil.com.cn (172.29.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:11:13 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:11:13 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 11/18] net/r8169: implement Rx path Date: Tue, 15 Oct 2024 11:09:21 +0800 Message-ID: <20241015030928.70642-12-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add implementation for RX datapath. Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_base.h | 27 ++ drivers/net/r8169/r8169_ethdev.c | 76 ++- drivers/net/r8169/r8169_ethdev.h | 18 + drivers/net/r8169/r8169_rxtx.c | 787 ++++++++++++++++++++++++++++++- 4 files changed, 905 insertions(+), 3 deletions(-) diff --git a/drivers/net/r8169/r8169_base.h b/drivers/net/r8169/r8169_base.h index 2960288981..53a58e10fa 100644 --- a/drivers/net/r8169/r8169_base.h +++ b/drivers/net/r8169/r8169_base.h @@ -562,6 +562,33 @@ enum RTL_chipset_name { #define MAC_ADDR_LEN RTE_ETHER_ADDR_LEN +#define RTL_MAX_TX_DESC 4096 +#define RTL_MAX_RX_DESC 4096 +#define RTL_MIN_TX_DESC 64 +#define RTL_MIN_RX_DESC 64 + +#define RTL_RING_ALIGN 256 + +#define RTL_MAX_TX_SEG 64 +#define RTL_DESC_ALIGN 64 + +#define RTL_RX_FREE_THRESH 32 +#define RTL_TX_FREE_THRESH 32 + +#define VLAN_TAG_SIZE 4 + +/* + * The overhead from MTU to max frame size. + * Considering VLAN so a tag needs to be counted. + */ +#define RTL_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE) + +#define ETH_HLEN 14 +#define VLAN_HLEN 4 +#define Jumbo_Frame_9k (9 * 1024 - ETH_HLEN - VLAN_HLEN - RTE_ETHER_CRC_LEN) + +#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL << (n)) - 1)) + static inline u32 rtl_read32(volatile void *addr) { diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index ecf4a4e984..6c06f71385 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -38,6 +38,8 @@ static int rtl_dev_close(struct rte_eth_dev *dev); static int rtl_dev_link_update(struct rte_eth_dev *dev, int wait __rte_unused); static int rtl_dev_set_link_up(struct rte_eth_dev *dev); static int rtl_dev_set_link_down(struct rte_eth_dev *dev); +static int rtl_dev_infos_get(struct rte_eth_dev *dev, + struct rte_eth_dev_info *dev_info); /* * The set of PCI devices this driver supports @@ -50,6 +52,20 @@ static const struct rte_pci_id pci_id_r8169_map[] = { {.vendor_id = 0, /* sentinel */ }, }; +static const struct rte_eth_desc_lim rx_desc_lim = { + .nb_max = RTL_MAX_RX_DESC, + .nb_min = RTL_MIN_RX_DESC, + .nb_align = RTL_DESC_ALIGN, +}; + +static const struct rte_eth_desc_lim tx_desc_lim = { + .nb_max = RTL_MAX_TX_DESC, + .nb_min = RTL_MIN_TX_DESC, + .nb_align = RTL_DESC_ALIGN, + .nb_seg_max = RTL_MAX_TX_SEG, + .nb_mtu_seg_max = RTL_MAX_TX_SEG, +}; + static const struct eth_dev_ops rtl_eth_dev_ops = { .dev_configure = rtl_dev_configure, .dev_start = rtl_dev_start, @@ -58,8 +74,13 @@ static const struct eth_dev_ops rtl_eth_dev_ops = { .dev_reset = rtl_dev_reset, .dev_set_link_up = rtl_dev_set_link_up, .dev_set_link_down = rtl_dev_set_link_down, + .dev_infos_get = rtl_dev_infos_get, .link_update = rtl_dev_link_update, + + .rx_queue_setup = rtl_rx_queue_setup, + .rx_queue_release = rtl_rx_queue_release, + .rxq_info_get = rtl_rxq_info_get, }; static int @@ -149,6 +170,7 @@ _rtl_setup_link(struct rte_eth_dev *dev) error_invalid_config: PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u", dev->data->dev_conf.link_speeds, dev->data->port_id); + rtl_stop_queues(dev); return -EINVAL; } @@ -229,6 +251,7 @@ rtl_dev_start(struct rte_eth_dev *dev) return 0; error: + rtl_stop_queues(dev); return -EIO; } @@ -258,6 +281,8 @@ rtl_dev_stop(struct rte_eth_dev *dev) rtl_powerdown_pll(hw); + rtl_stop_queues(dev); + /* Clear the recorded link status */ memset(&link, 0, sizeof(link)); rte_eth_linkstatus_set(dev, &link); @@ -298,6 +323,50 @@ rtl_dev_set_link_down(struct rte_eth_dev *dev) return 0; } +static int +rtl_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + dev_info->min_rx_bufsize = 1024; + dev_info->max_rx_pktlen = Jumbo_Frame_9k; + dev_info->max_mac_addrs = 1; + + dev_info->max_rx_queues = 1; + dev_info->max_tx_queues = 1; + + dev_info->default_rxconf = (struct rte_eth_rxconf) { + .rx_free_thresh = RTL_RX_FREE_THRESH, + }; + + dev_info->default_txconf = (struct rte_eth_txconf) { + .tx_free_thresh = RTL_TX_FREE_THRESH, + }; + + dev_info->rx_desc_lim = rx_desc_lim; + dev_info->tx_desc_lim = tx_desc_lim; + + dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD | RTE_ETH_LINK_SPEED_10M | + RTE_ETH_LINK_SPEED_100M_HD | RTE_ETH_LINK_SPEED_100M | + RTE_ETH_LINK_SPEED_1G; + + switch (hw->chipset_name) { + case RTL8126A: + dev_info->speed_capa |= RTE_ETH_LINK_SPEED_5G; + /* fallthrough */ + case RTL8125A: + case RTL8125B: + dev_info->speed_capa |= RTE_ETH_LINK_SPEED_2_5G; + break; + } + + dev_info->rx_offload_capa = (rtl_get_rx_port_offloads() | + dev_info->rx_queue_offload_capa); + + return 0; +} + /* Return 0 means link status changed, -1 means not changed */ static int rtl_dev_link_update(struct rte_eth_dev *dev, int wait __rte_unused) @@ -398,6 +467,8 @@ rtl_dev_close(struct rte_eth_dev *dev) ret_stp = rtl_dev_stop(dev); + rtl_free_queues(dev); + /* Reprogram the RAR[0] in case user changed it. */ rtl_rar_set(hw, hw->mac_addr); @@ -433,8 +504,11 @@ rtl_dev_init(struct rte_eth_dev *dev) dev->rx_pkt_burst = &rtl_recv_pkts; /* For secondary processes, the primary process has done all the work */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + if (dev->data->scattered_rx) + dev->rx_pkt_burst = &rtl_recv_scattered_pkts; return 0; + } rte_eth_copy_pci_info(dev, pci_dev); diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index 03012365ca..cfcf576bc1 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -45,6 +45,7 @@ struct rtl_hw { u8 HwSuppIntMitiVer; u16 cur_page; u8 mac_addr[MAC_ADDR_LEN]; + u32 rx_buf_sz; u8 RequirePhyMdiSwapPatch; u8 NotWrMcuPatchCode; @@ -109,6 +110,23 @@ int rtl_tx_init(struct rte_eth_dev *dev); uint16_t rtl_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); uint16_t rtl_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); +uint16_t rtl_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts); + +void rtl_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id); + +void rtl_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_rxq_info *qinfo); + +uint64_t rtl_get_rx_port_offloads(void); + +int rtl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_rx_desc, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mb_pool); + +int rtl_stop_queues(struct rte_eth_dev *dev); +void rtl_free_queues(struct rte_eth_dev *dev); #endif diff --git a/drivers/net/r8169/r8169_rxtx.c b/drivers/net/r8169/r8169_rxtx.c index cce78d4e60..8c4bcdf4e5 100644 --- a/drivers/net/r8169/r8169_rxtx.c +++ b/drivers/net/r8169/r8169_rxtx.c @@ -29,17 +29,773 @@ #include "r8169_hw.h" #include "r8169_logs.h" +/* Struct RxDesc in kernel r8169 */ +struct rtl_rx_desc { + u32 opts1; + u32 opts2; + u64 addr; +}; + +/* Structure associated with each descriptor of the RX ring of a RX queue. */ +struct rtl_rx_entry { + struct rte_mbuf *mbuf; +}; + +/* Structure associated with each RX queue. */ +struct rtl_rx_queue { + struct rte_mempool *mb_pool; + struct rtl_rx_desc *hw_ring; + struct rtl_rx_entry *sw_ring; + struct rte_mbuf *pkt_first_seg; /* First segment of current packet. */ + struct rte_mbuf *pkt_last_seg; /* Last segment of current packet. */ + struct rtl_hw *hw; + uint64_t hw_ring_phys_addr; + uint64_t offloads; + uint16_t nb_rx_desc; + uint16_t rx_tail; + uint16_t nb_rx_hold; + uint16_t queue_id; + uint16_t port_id; + uint16_t rx_free_thresh; +}; + +enum _DescStatusBit { + DescOwn = (1 << 31), /* Descriptor is owned by NIC. */ + RingEnd = (1 << 30), /* End of descriptor ring */ + FirstFrag = (1 << 29), /* First segment of a packet */ + LastFrag = (1 << 28), /* Final segment of a packet */ + + DescOwn_V3 = DescOwn, /* Descriptor is owned by NIC. */ + RingEnd_V3 = RingEnd, /* End of descriptor ring */ + FirstFrag_V3 = (1 << 25), /* First segment of a packet */ + LastFrag_V3 = (1 << 24), /* Final segment of a packet */ + + /* TX private */ + /*------ offset 0 of TX descriptor ------*/ + LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ + GiantSendv4 = (1 << 26), /* TCP Giant Send Offload V4 (GSOv4) */ + GiantSendv6 = (1 << 25), /* TCP Giant Send Offload V6 (GSOv6) */ + LargeSend_DP = (1 << 16), /* TCP Large Send Offload (TSO) */ + MSSShift = 16, /* MSS value position */ + MSSMask = 0x7FFU, /* MSS value 11 bits */ + TxIPCS = (1 << 18), /* Calculate IP checksum */ + TxUDPCS = (1 << 17), /* Calculate UDP/IP checksum */ + TxTCPCS = (1 << 16), /* Calculate TCP/IP checksum */ + TxVlanTag = (1 << 17), /* Add VLAN tag */ + + /*@@@@@@ offset 4 of TX descriptor => bits for RTL8169 only begin @@@@@@*/ + TxUDPCS_C = (1 << 31), /* Calculate UDP/IP checksum */ + TxTCPCS_C = (1 << 30), /* Calculate TCP/IP checksum */ + TxIPCS_C = (1 << 29), /* Calculate IP checksum */ + TxIPV6F_C = (1 << 28), /* Indicate it is an IPv6 packet */ + /*@@@@@@ offset 4 of tx descriptor => bits for RTL8169 only end @@@@@@*/ + + /* RX private */ + /* ------ offset 0 of RX descriptor ------ */ + PID1 = (1 << 18), /* Protocol ID bit 1/2 */ + PID0 = (1 << 17), /* Protocol ID bit 2/2 */ + +#define RxProtoUDP PID1 +#define RxProtoTCP PID0 +#define RxProtoIP (PID1 | PID0) +#define RxProtoMask RxProtoIP + + RxIPF = (1 << 16), /* IP checksum failed */ + RxUDPF = (1 << 15), /* UDP/IP checksum failed */ + RxTCPF = (1 << 14), /* TCP/IP checksum failed */ + RxVlanTag = (1 << 16), /* VLAN tag available */ + + /*@@@@@@ offset 0 of RX descriptor => bits for RTL8169 only begin @@@@@@*/ + RxUDPT = (1 << 18), + RxTCPT = (1 << 17), + /*@@@@@@ offset 0 of RX descriptor => bits for RTL8169 only end @@@@@@*/ + + /*@@@@@@ offset 4 of RX descriptor => bits for RTL8169 only begin @@@@@@*/ + RxV6F = (1 << 31), + RxV4F = (1 << 30), + /*@@@@@@ offset 4 of RX descriptor => bits for RTL8169 only end @@@@@@*/ + + PID1_v3 = (1 << 29), /* Protocol ID bit 1/2 */ + PID0_v3 = (1 << 28), /* Protocol ID bit 2/2 */ + +#define RxProtoUDP_v3 PID1_v3 +#define RxProtoTCP_v3 PID0_v3 +#define RxProtoIP_v3 (PID1_v3 | PID0_v3) +#define RxProtoMask_v3 RxProtoIP_v3 + + RxIPF_v3 = (1 << 26), /* IP checksum failed */ + RxUDPF_v3 = (1 << 25), /* UDP/IP checksum failed */ + RxTCPF_v3 = (1 << 24), /* TCP/IP checksum failed */ + RxSCTPF_v3 = (1 << 23), /* TCP/IP checksum failed */ + RxVlanTag_v3 = (RxVlanTag), /* VLAN tag available */ + + /*@@@@@@ offset 0 of RX descriptor => bits for RTL8169 only begin @@@@@@*/ + RxUDPT_v3 = (1 << 29), + RxTCPT_v3 = (1 << 28), + RxSCTP_v3 = (1 << 27), + /*@@@@@@ offset 0 of RX descriptor => bits for RTL8169 only end @@@@@@*/ + + /*@@@@@@ offset 4 of RX descriptor => bits for RTL8169 only begin @@@@@@*/ + RxV6F_v3 = RxV6F, + RxV4F_v3 = RxV4F, + /*@@@@@@ offset 4 of RX descriptor => bits for RTL8169 only end @@@@@@*/ +}; /* ---------------------------------RX---------------------------------- */ + +static void +rtl_rx_queue_release_mbufs(struct rtl_rx_queue *rxq) +{ + int i; + + PMD_INIT_FUNC_TRACE(); + + if (rxq != NULL) { + if (rxq->sw_ring != NULL) { + for (i = 0; i < rxq->nb_rx_desc; i++) { + if (rxq->sw_ring[i].mbuf != NULL) { + rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf); + rxq->sw_ring[i].mbuf = NULL; + } + } + } + } +} + +void +rtl_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct rtl_rx_queue *rxq = dev->data->rx_queues[rx_queue_id]; + + PMD_INIT_FUNC_TRACE(); + + if (rxq != NULL) { + rtl_rx_queue_release_mbufs(rxq); + rte_free(rxq->sw_ring); + rte_free(rxq); + } +} + +void +rtl_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_rxq_info *qinfo) +{ + struct rtl_rx_queue *rxq; + + rxq = dev->data->rx_queues[queue_id]; + + qinfo->mp = rxq->mb_pool; + qinfo->scattered_rx = dev->data->scattered_rx; + qinfo->nb_desc = rxq->nb_rx_desc; + + qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; + qinfo->conf.offloads = rxq->offloads; +} + +static void +rtl_reset_rx_queue(struct rtl_rx_queue *rxq) +{ + static const struct rtl_rx_desc zero_rxd = {0}; + int i; + + for (i = 0; i < rxq->nb_rx_desc; i++) + rxq->hw_ring[i] = zero_rxd; + + rxq->hw_ring[rxq->nb_rx_desc - 1].opts1 = rte_cpu_to_le_32(RingEnd); + rxq->rx_tail = 0; + rxq->pkt_first_seg = NULL; + rxq->pkt_last_seg = NULL; +} + +uint64_t +rtl_get_rx_port_offloads(void) +{ + uint64_t offloads; + + offloads = RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_RX_OFFLOAD_UDP_CKSUM | + RTE_ETH_RX_OFFLOAD_TCP_CKSUM | + RTE_ETH_RX_OFFLOAD_SCATTER | + RTE_ETH_RX_OFFLOAD_VLAN_STRIP; + + return offloads; +} + +int +rtl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_rx_desc, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mb_pool) +{ + struct rtl_rx_queue *rxq; + const struct rte_memzone *mz; + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + uint32_t size; + + PMD_INIT_FUNC_TRACE(); + if (nb_rx_desc > RTL_MAX_RX_DESC || nb_rx_desc < RTL_MIN_RX_DESC) { + PMD_INIT_LOG(ERR, "Number of Rx descriptors must be " + "less than or equal to %d, " + "greater than or equal to %d", + RTL_MAX_RX_DESC, RTL_MIN_RX_DESC); + return -EINVAL; + } + + /* + * If this queue existed already, free the associated memory. The + * queue cannot be reused in case we need to allocate memory on + * different socket than was previously used. + */ + if (dev->data->rx_queues[queue_idx] != NULL) { + rtl_rx_queue_release(dev, queue_idx); + dev->data->rx_queues[queue_idx] = NULL; + } + + /* First allocate the rx queue data structure */ + rxq = rte_zmalloc_socket("r8169 RX queue", sizeof(struct rtl_rx_queue), + RTE_CACHE_LINE_SIZE, socket_id); + + if (rxq == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate Rx queue structure"); + return -ENOMEM; + } + + /* Setup queue */ + rxq->mb_pool = mb_pool; + rxq->nb_rx_desc = nb_rx_desc; + rxq->port_id = dev->data->port_id; + rxq->queue_id = queue_idx; + rxq->rx_free_thresh = rx_conf->rx_free_thresh; + + /* Allocate memory for the software ring */ + rxq->sw_ring = rte_zmalloc_socket("r8169 sw rx ring", + nb_rx_desc * sizeof(struct rtl_rx_entry), + RTE_CACHE_LINE_SIZE, socket_id); + + if (rxq->sw_ring == NULL) { + PMD_INIT_LOG(ERR, + "Port %d: Cannot allocate software ring for queue %d", + rxq->port_id, rxq->queue_id); + rte_free(rxq); + return -ENOMEM; + } + + /* + * Allocate RX ring hardware descriptors. A memzone large enough to + * handle the maximum ring size is allocated in order to allow for + * resizing in later calls to the queue setup function. + */ + size = sizeof(struct rtl_rx_desc) * (nb_rx_desc + 1); + mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size, + RTL_RING_ALIGN, socket_id); + if (mz == NULL) { + PMD_INIT_LOG(ERR, + "Port %d: Cannot allocate software ring for queue %d", + rxq->port_id, rxq->queue_id); + rtl_rx_queue_release(dev, rxq->queue_id); + return -ENOMEM; + } + + rxq->hw = hw; + rxq->hw_ring = mz->addr; + rxq->hw_ring_phys_addr = mz->iova; + rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; + + rtl_reset_rx_queue(rxq); + + dev->data->rx_queues[queue_idx] = rxq; + + return 0; +} + +static int +rtl_alloc_rx_queue_mbufs(struct rtl_rx_queue *rxq) +{ + struct rtl_rx_entry *rxe = rxq->sw_ring; + struct rtl_hw *hw = rxq->hw; + struct rtl_rx_desc *rxd; + int i; + uint64_t dma_addr; + + rxd = &rxq->hw_ring[0]; + + /* Initialize software ring entries */ + for (i = 0; i < rxq->nb_rx_desc; i++) { + struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool); + + if (mbuf == NULL) { + PMD_INIT_LOG(ERR, "RX mbuf alloc failed " + "queue_id=%hu", rxq->queue_id); + return -ENOMEM; + } + + dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); + + rxd = &rxq->hw_ring[i]; + rxd->addr = dma_addr; + rxd->opts2 = 0; + rte_wmb(); + rxd->opts1 = rte_cpu_to_le_32(DescOwn | hw->rx_buf_sz); + rxe[i].mbuf = mbuf; + } + + /* Mark as last desc */ + rxd->opts1 |= rte_cpu_to_le_32(RingEnd); + + return 0; +} + +static int +rtl_hw_set_features(struct rtl_hw *hw, uint64_t offloads) +{ + u16 cp_cmd; + u32 rx_config; + + rx_config = RTL_R32(hw, RxConfig); + if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) + rx_config |= (EnableInnerVlan | EnableOuterVlan); + else + rx_config &= ~(EnableInnerVlan | EnableOuterVlan); + + RTL_W32(hw, RxConfig, rx_config); + + cp_cmd = RTL_R16(hw, CPlusCmd); + + if (offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM) + cp_cmd |= RxChkSum; + else + cp_cmd &= ~RxChkSum; + + RTL_W16(hw, CPlusCmd, cp_cmd); + + return 0; +} + +static void +rtl_hw_set_rx_packet_filter(struct rtl_hw *hw) +{ + int rx_mode; + + hw->hw_ops.hw_init_rxcfg(hw); + + rx_mode = AcceptBroadcast | AcceptMyPhys; + RTL_W32(hw, RxConfig, rx_mode | (RTL_R32(hw, RxConfig))); +} + int rtl_rx_init(struct rte_eth_dev *dev) { + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + struct rtl_rx_queue *rxq; + int ret; + u32 max_rx_pkt_size; + + rxq = dev->data->rx_queues[0]; + + if (rxq->mb_pool == NULL) { + PMD_INIT_LOG(ERR, "r8169 rx queue pool not setup!"); + return -ENOMEM; + } + + RTL_W32(hw, RxDescAddrLow, ((u64)rxq->hw_ring_phys_addr & DMA_BIT_MASK(32))); + RTL_W32(hw, RxDescAddrHigh, ((u64)rxq->hw_ring_phys_addr >> 32)); + + dev->rx_pkt_burst = rtl_recv_pkts; + hw->rx_buf_sz = rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM; + + max_rx_pkt_size = dev->data->mtu + RTL_ETH_OVERHEAD; + + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER || + max_rx_pkt_size > hw->rx_buf_sz) { + if (!dev->data->scattered_rx) + PMD_INIT_LOG(DEBUG, "forcing scatter mode"); + dev->rx_pkt_burst = rtl_recv_scattered_pkts; + dev->data->scattered_rx = 1; + } + + RTL_W16(hw, RxMaxSize, max_rx_pkt_size); + + ret = rtl_alloc_rx_queue_mbufs(rxq); + if (ret) { + PMD_INIT_LOG(ERR, "r8169 rx mbuf alloc failed!"); + return ret; + } + + rtl_enable_cfg9346_write(hw); + + /* RX accept type and csum vlan offload */ + rtl_hw_set_features(hw, rxq->offloads); + + rtl_disable_rxdvgate(hw); + + /* Set Rx packet filter */ + rtl_hw_set_rx_packet_filter(hw); + + rtl_disable_cfg9346_write(hw); + + RTL_W8(hw, ChipCmd, RTL_R8(hw, ChipCmd) | CmdRxEnb); + + dev->data->rx_queue_state[0] = RTE_ETH_QUEUE_STATE_STARTED; + return 0; } +static inline void +rtl_mark_to_asic(struct rtl_rx_desc *rxd, u32 size) +{ + u32 eor = rte_le_to_cpu_32(rxd->opts1) & RingEnd; + + rxd->opts1 = rte_cpu_to_le_32(DescOwn | eor | size); +} + +static inline uint64_t +rtl_rx_desc_error_to_pkt_flags(struct rtl_rx_queue *rxq, uint32_t opts1, + uint32_t opts2) +{ + uint64_t pkt_flags = 0; + + if (!(rxq->offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM)) + goto exit; + + /* RX csum offload for RTL8169*/ + if (((opts2 & RxV4F) && !(opts1 & RxIPF)) || (opts2 & RxV6F)) { + pkt_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; + if (((opts1 & RxTCPT) && !(opts1 & RxTCPF)) || + ((opts1 & RxUDPT) && !(opts1 & RxUDPF))) + pkt_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD; + } + +exit: + return pkt_flags; +} + +/* PMD receive function */ uint16_t -rtl_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) +rtl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) { - return 0; + struct rtl_rx_queue *rxq = (struct rtl_rx_queue *)rx_queue; + struct rte_eth_dev *dev = &rte_eth_devices[rxq->port_id]; + struct rtl_hw *hw = rxq->hw; + struct rtl_rx_desc *rxd; + struct rtl_rx_desc *hw_ring; + struct rtl_rx_entry *rxe; + struct rtl_rx_entry *sw_ring = rxq->sw_ring; + struct rte_mbuf *new_mb; + struct rte_mbuf *rmb; + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_sw_stats *stats = &adapter->sw_stats; + uint16_t nb_rx = 0; + uint16_t nb_hold = 0; + uint16_t tail = rxq->rx_tail; + const uint16_t nb_rx_desc = rxq->nb_rx_desc; + uint32_t opts1; + uint32_t opts2; + uint16_t pkt_len = 0; + uint64_t dma_addr; + + hw_ring = rxq->hw_ring; + + RTE_ASSERT(RTL_R8(hw, ChipCmd) & CmdRxEnb); + + while (nb_rx < nb_pkts) { + rxd = &hw_ring[tail]; + + opts1 = rte_le_to_cpu_32(rxd->opts1); + if (opts1 & DescOwn) + break; + + /* + * This barrier is needed to keep us from reading + * any other fields out of the Rx descriptor until + * we know the status of DescOwn. + */ + rte_rmb(); + + if (unlikely(opts1 & RxRES)) { + stats->rx_errors++; + rtl_mark_to_asic(rxd, hw->rx_buf_sz); + nb_hold++; + tail = (tail + 1) % nb_rx_desc; + } else { + opts2 = rte_le_to_cpu_32(rxd->opts2); + + new_mb = rte_mbuf_raw_alloc(rxq->mb_pool); + if (new_mb == NULL) { + PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u " + "queue_id=%u", + (uint32_t)rxq->port_id, (uint32_t)rxq->queue_id); + dev->data->rx_mbuf_alloc_failed++; + break; + } + + nb_hold++; + rxe = &sw_ring[tail]; + + rmb = rxe->mbuf; + + tail = (tail + 1) % nb_rx_desc; + + /* Prefetch next mbufs */ + rte_prefetch0(sw_ring[tail].mbuf); + + /* + * When next RX descriptor is on a cache-line boundary, + * prefetch the next 4 RX descriptors and the next 8 pointers + * to mbufs. + */ + if ((tail & 0x3) == 0) { + rte_prefetch0(&sw_ring[tail]); + rte_prefetch0(&hw_ring[tail]); + } + + /* Refill the RX desc */ + rxe->mbuf = new_mb; + dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(new_mb)); + + /* Setup RX descriptor */ + rxd->addr = dma_addr; + rxd->opts2 = 0; + rte_wmb(); + rtl_mark_to_asic(rxd, hw->rx_buf_sz); + + pkt_len = opts1 & 0x00003fff; + pkt_len -= RTE_ETHER_CRC_LEN; + + rmb->data_off = RTE_PKTMBUF_HEADROOM; + rte_prefetch1((char *)rmb->buf_addr + rmb->data_off); + rmb->nb_segs = 1; + rmb->next = NULL; + rmb->pkt_len = pkt_len; + rmb->data_len = pkt_len; + rmb->port = rxq->port_id; + + if (opts2 & RxVlanTag) + rmb->vlan_tci = rte_bswap16(opts2 & 0xffff); + + rmb->ol_flags = rtl_rx_desc_error_to_pkt_flags(rxq, opts1, opts2); + + /* + * Store the mbuf address into the next entry of the array + * of returned packets. + */ + rx_pkts[nb_rx++] = rmb; + + stats->rx_bytes += pkt_len; + stats->rx_packets++; + } + } + + rxq->rx_tail = tail; + + nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold); + if (nb_hold > rxq->rx_free_thresh) { + rte_wmb(); + + /* Clear RDU */ + RTL_W32(hw, ISR0_8125, (RxOK | RxErr | RxDescUnavail)); + + nb_hold = 0; + } + + rxq->nb_rx_hold = nb_hold; + + return nb_rx; +} + +/* PMD receive function for scattered pkts */ +uint16_t +rtl_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts) +{ + struct rtl_rx_queue *rxq = (struct rtl_rx_queue *)rx_queue; + struct rte_eth_dev *dev = &rte_eth_devices[rxq->port_id]; + struct rtl_hw *hw = rxq->hw; + struct rtl_rx_desc *rxd; + struct rtl_rx_desc *hw_ring; + struct rtl_rx_entry *rxe; + struct rtl_rx_entry *sw_ring = rxq->sw_ring; + struct rte_mbuf *first_seg; + struct rte_mbuf *last_seg; + struct rte_mbuf *new_mb; + struct rte_mbuf *rmb; + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_sw_stats *stats = &adapter->sw_stats; + uint16_t nb_rx = 0; + uint16_t nb_hold = 0; + uint16_t data_len = 0; + uint16_t tail = rxq->rx_tail; + const uint16_t nb_rx_desc = rxq->nb_rx_desc; + uint32_t opts1; + uint32_t opts2; + uint64_t dma_addr; + + hw_ring = rxq->hw_ring; + + /* + * Retrieve RX context of current packet, if any. + */ + first_seg = rxq->pkt_first_seg; + last_seg = rxq->pkt_last_seg; + + RTE_ASSERT(RTL_R8(hw, ChipCmd) & CmdRxEnb); + + while (nb_rx < nb_pkts) { +next_desc: + rxd = &hw_ring[tail]; + + opts1 = rte_le_to_cpu_32(rxd->opts1); + if (opts1 & DescOwn) + break; + + /* + * This barrier is needed to keep us from reading + * any other fields out of the Rx descriptor until + * we know the status of DescOwn + */ + rte_rmb(); + + if (unlikely(opts1 & RxRES)) { + stats->rx_errors++; + rtl_mark_to_asic(rxd, hw->rx_buf_sz); + nb_hold++; + tail = (tail + 1) % nb_rx_desc; + } else { + opts2 = rte_le_to_cpu_32(rxd->opts2); + + new_mb = rte_mbuf_raw_alloc(rxq->mb_pool); + if (new_mb == NULL) { + PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u " + "queue_id=%u", + (uint32_t)rxq->port_id, (uint32_t)rxq->queue_id); + dev->data->rx_mbuf_alloc_failed++; + break; + } + + nb_hold++; + rxe = &sw_ring[tail]; + + rmb = rxe->mbuf; + + /* Prefetch next mbufs */ + tail = (tail + 1) % nb_rx_desc; + rte_prefetch0(sw_ring[tail].mbuf); + + /* + * When next RX descriptor is on a cache-line boundary, + * prefetch the next 4 RX descriptors and the next 8 pointers + * to mbufs. + */ + if ((tail & 0x3) == 0) { + rte_prefetch0(&sw_ring[tail]); + rte_prefetch0(&hw_ring[tail]); + } + + /* Refill the RX desc */ + rxe->mbuf = new_mb; + dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(new_mb)); + + /* Setup RX descriptor */ + rxd->addr = dma_addr; + rxd->opts2 = 0; + rte_wmb(); + rtl_mark_to_asic(rxd, hw->rx_buf_sz); + + data_len = opts1 & 0x00003fff; + rmb->data_len = data_len; + rmb->data_off = RTE_PKTMBUF_HEADROOM; + + /* + * If this is the first buffer of the received packet, + * set the pointer to the first mbuf of the packet and + * initialize its context. + * Otherwise, update the total length and the number of segments + * of the current scattered packet, and update the pointer to + * the last mbuf of the current packet. + */ + if (first_seg == NULL) { + first_seg = rmb; + first_seg->pkt_len = data_len; + first_seg->nb_segs = 1; + } else { + first_seg->pkt_len += data_len; + first_seg->nb_segs++; + last_seg->next = rmb; + } + + /* + * If this is not the last buffer of the received packet, + * update the pointer to the last mbuf of the current scattered + * packet and continue to parse the RX ring. + */ + if (!(opts1 & LastFrag)) { + last_seg = rmb; + goto next_desc; + } + + /* + * This is the last buffer of the received packet. + */ + rmb->next = NULL; + + first_seg->pkt_len -= RTE_ETHER_CRC_LEN; + if (data_len <= RTE_ETHER_CRC_LEN) { + rte_pktmbuf_free_seg(rmb); + first_seg->nb_segs--; + last_seg->data_len = last_seg->data_len - (RTE_ETHER_CRC_LEN - data_len); + last_seg->next = NULL; + } else + rmb->data_len = data_len - RTE_ETHER_CRC_LEN; + + first_seg->port = rxq->port_id; + + if (opts2 & RxVlanTag) + first_seg->vlan_tci = rte_bswap16(opts2 & 0xffff); + + first_seg->ol_flags = rtl_rx_desc_error_to_pkt_flags(rxq, opts1, opts2); + + rte_prefetch1((char *)first_seg->buf_addr + first_seg->data_off); + + /* + * Store the mbuf address into the next entry of the array + * of returned packets. + */ + rx_pkts[nb_rx++] = first_seg; + + stats->rx_bytes += first_seg->pkt_len; + stats->rx_packets++; + + /* + * Setup receipt context for a new packet. + */ + first_seg = NULL; + } + } + + /* + * Record index of the next RX descriptor to probe. + */ + rxq->rx_tail = tail; + + /* + * Save receive context. + */ + rxq->pkt_first_seg = first_seg; + rxq->pkt_last_seg = last_seg; + + nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold); + if (nb_hold > rxq->rx_free_thresh) { + rte_wmb(); + + /* Clear RDU */ + RTL_W32(hw, ISR0_8125, (RxOK | RxErr | RxDescUnavail)); + + nb_hold = 0; + } + + rxq->nb_rx_hold = nb_hold; + + return nb_rx; } /* ---------------------------------TX---------------------------------- */ @@ -55,3 +811,30 @@ rtl_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) return 0; } +int +rtl_stop_queues(struct rte_eth_dev *dev) +{ + struct rtl_rx_queue *rxq; + + PMD_INIT_FUNC_TRACE(); + + rxq = dev->data->rx_queues[0]; + + rtl_rx_queue_release_mbufs(rxq); + rtl_reset_rx_queue(rxq); + dev->data->rx_queue_state[0] = RTE_ETH_QUEUE_STATE_STOPPED; + + return 0; +} + +void +rtl_free_queues(struct rte_eth_dev *dev) +{ + PMD_INIT_FUNC_TRACE(); + + rte_eth_dma_zone_free(dev, "rx_ring", 0); + rtl_rx_queue_release(dev, 0); + dev->data->rx_queues[0] = 0; + dev->data->nb_rx_queues = 0; +} + From patchwork Tue Oct 15 03:09:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145942 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 99BD145B3C; Tue, 15 Oct 2024 05:11:28 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8F95A4066A; Tue, 15 Oct 2024 05:11:28 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id 4536E4066A for ; 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Tue, 15 Oct 2024 11:11:22 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXDAG02.realsil.com.cn (172.29.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:11:21 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:11:21 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 12/18] net/r8169: implement Tx path Date: Tue, 15 Oct 2024 11:09:22 +0800 Message-ID: <20241015030928.70642-13-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add implementation for TX datapath. Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_base.h | 7 + drivers/net/r8169/r8169_ethdev.c | 6 + drivers/net/r8169/r8169_ethdev.h | 11 + drivers/net/r8169/r8169_rxtx.c | 687 ++++++++++++++++++++++++++++++- 4 files changed, 695 insertions(+), 16 deletions(-) diff --git a/drivers/net/r8169/r8169_base.h b/drivers/net/r8169/r8169_base.h index 53a58e10fa..043d66f6c2 100644 --- a/drivers/net/r8169/r8169_base.h +++ b/drivers/net/r8169/r8169_base.h @@ -589,6 +589,13 @@ enum RTL_chipset_name { #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL << (n)) - 1)) +#ifndef WRITE_ONCE +#define WRITE_ONCE(var, val) (*((volatile typeof(val) *)(&(var))) = (val)) +#endif +#ifndef READ_ONCE +#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) +#endif + static inline u32 rtl_read32(volatile void *addr) { diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index 6c06f71385..61aa16cc10 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -81,6 +81,11 @@ static const struct eth_dev_ops rtl_eth_dev_ops = { .rx_queue_setup = rtl_rx_queue_setup, .rx_queue_release = rtl_rx_queue_release, .rxq_info_get = rtl_rxq_info_get, + + .tx_queue_setup = rtl_tx_queue_setup, + .tx_queue_release = rtl_tx_queue_release, + .tx_done_cleanup = rtl_tx_done_cleanup, + .txq_info_get = rtl_txq_info_get, }; static int @@ -363,6 +368,7 @@ rtl_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->rx_offload_capa = (rtl_get_rx_port_offloads() | dev_info->rx_queue_offload_capa); + dev_info->tx_offload_capa = rtl_get_tx_port_offloads(); return 0; } diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index cfcf576bc1..5776601081 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -77,6 +77,8 @@ struct rtl_hw { u16 hw_clo_ptr_reg; u16 sw_tail_ptr_reg; u32 MaxTxDescPtrMask; + u32 NextHwDesCloPtr0; + u32 BeginHwDesCloPtr0; /* Dash */ u8 HwSuppDashVer; @@ -114,16 +116,25 @@ uint16_t rtl_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); void rtl_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id); +void rtl_tx_queue_release(struct rte_eth_dev *dev, uint16_t tx_queue_id); void rtl_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, struct rte_eth_rxq_info *qinfo); +void rtl_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_txq_info *qinfo); uint64_t rtl_get_rx_port_offloads(void); +uint64_t rtl_get_tx_port_offloads(void); int rtl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t nb_rx_desc, unsigned int socket_id, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mb_pool); +int rtl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_tx_desc, unsigned int socket_id, + const struct rte_eth_txconf *tx_conf); + +int rtl_tx_done_cleanup(void *tx_queue, uint32_t free_cnt); int rtl_stop_queues(struct rte_eth_dev *dev); void rtl_free_queues(struct rte_eth_dev *dev); diff --git a/drivers/net/r8169/r8169_rxtx.c b/drivers/net/r8169/r8169_rxtx.c index 8c4bcdf4e5..cb354e19fe 100644 --- a/drivers/net/r8169/r8169_rxtx.c +++ b/drivers/net/r8169/r8169_rxtx.c @@ -29,6 +29,28 @@ #include "r8169_hw.h" #include "r8169_logs.h" +/* Bit mask to indicate what bits required for building TX context */ +#define RTL_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_IPV6 | \ + RTE_MBUF_F_TX_IPV4 | \ + RTE_MBUF_F_TX_VLAN | \ + RTE_MBUF_F_TX_IP_CKSUM | \ + RTE_MBUF_F_TX_L4_MASK | \ + RTE_MBUF_F_TX_TCP_SEG) + +#define MIN_PATCH_LENGTH 47 +#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ + +/* Struct TxDesc in kernel r8169 */ +struct rtl_tx_desc { + u32 opts1; + u32 opts2; + u64 addr; + u32 reserved0; + u32 reserved1; + u32 reserved2; + u32 reserved3; +}; + /* Struct RxDesc in kernel r8169 */ struct rtl_rx_desc { u32 opts1; @@ -36,27 +58,47 @@ struct rtl_rx_desc { u64 addr; }; +/* Structure associated with each descriptor of the TX ring of a TX queue. */ +struct rtl_tx_entry { + struct rte_mbuf *mbuf; +}; + /* Structure associated with each descriptor of the RX ring of a RX queue. */ struct rtl_rx_entry { struct rte_mbuf *mbuf; }; +/* Structure associated with each TX queue. */ +struct rtl_tx_queue { + struct rtl_tx_desc *hw_ring; + struct rtl_tx_entry *sw_ring; + struct rtl_hw *hw; + uint64_t hw_ring_phys_addr; + uint16_t nb_tx_desc; + uint32_t tx_tail; + uint16_t tx_head; + uint16_t queue_id; + uint16_t port_id; + uint16_t tx_free_thresh; + uint16_t tx_free; +}; + /* Structure associated with each RX queue. */ struct rtl_rx_queue { - struct rte_mempool *mb_pool; - struct rtl_rx_desc *hw_ring; - struct rtl_rx_entry *sw_ring; - struct rte_mbuf *pkt_first_seg; /* First segment of current packet. */ - struct rte_mbuf *pkt_last_seg; /* Last segment of current packet. */ - struct rtl_hw *hw; - uint64_t hw_ring_phys_addr; - uint64_t offloads; - uint16_t nb_rx_desc; - uint16_t rx_tail; - uint16_t nb_rx_hold; - uint16_t queue_id; - uint16_t port_id; - uint16_t rx_free_thresh; + struct rte_mempool *mb_pool; + struct rtl_rx_desc *hw_ring; + struct rtl_rx_entry *sw_ring; + struct rte_mbuf *pkt_first_seg; /* First segment of current packet. */ + struct rte_mbuf *pkt_last_seg; /* Last segment of current packet. */ + struct rtl_hw *hw; + uint64_t hw_ring_phys_addr; + uint64_t offloads; + uint16_t nb_rx_desc; + uint16_t rx_tail; + uint16_t nb_rx_hold; + uint16_t queue_id; + uint16_t port_id; + uint16_t rx_free_thresh; }; enum _DescStatusBit { @@ -140,6 +182,15 @@ enum _DescStatusBit { RxV4F_v3 = RxV4F, /*@@@@@@ offset 4 of RX descriptor => bits for RTL8169 only end @@@@@@*/ }; + +#define GTTCPHO_SHIFT 18 +#define GTTCPHO_MAX 0x70U +#define GTPKTSIZE_MAX 0x3ffffU +#define TCPHO_SHIFT 18 +#define TCPHO_MAX 0x3ffU +#define LSOPKTSIZE_MAX 0xffffU +#define MSS_MAX 0x07ffu /* MSS value */ + /* ---------------------------------RX---------------------------------- */ static void @@ -799,25 +850,624 @@ rtl_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, } /* ---------------------------------TX---------------------------------- */ +static void +rtl_tx_queue_release_mbufs(struct rtl_tx_queue *txq) +{ + int i; + + PMD_INIT_FUNC_TRACE(); + + if (txq != NULL) { + if (txq->sw_ring != NULL) { + for (i = 0; i < txq->nb_tx_desc; i++) { + if (txq->sw_ring[i].mbuf != NULL) { + rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf); + txq->sw_ring[i].mbuf = NULL; + } + } + } + } +} + +void +rtl_tx_queue_release(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct rtl_tx_queue *txq = dev->data->tx_queues[tx_queue_id]; + + PMD_INIT_FUNC_TRACE(); + + if (txq != NULL) { + rtl_tx_queue_release_mbufs(txq); + rte_free(txq->sw_ring); + rte_free(txq); + } +} + +void +rtl_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_txq_info *qinfo) +{ + struct rtl_tx_queue *txq; + + txq = dev->data->tx_queues[queue_id]; + + qinfo->nb_desc = txq->nb_tx_desc; +} + +static void +rtl_reset_tx_queue(struct rtl_tx_queue *txq) +{ + static const struct rtl_tx_desc zero_txd = {0}; + int i; + + for (i = 0; i < txq->nb_tx_desc; i++) + txq->hw_ring[i] = zero_txd; + + txq->hw_ring[txq->nb_tx_desc - 1].opts1 = rte_cpu_to_le_32(RingEnd); + + txq->tx_tail = 0; + txq->tx_head = 0; + txq->tx_free = txq->nb_tx_desc - 1; +} + +uint64_t +rtl_get_tx_port_offloads(void) +{ + uint64_t tx_offload_capa; + + tx_offload_capa = RTE_ETH_TX_OFFLOAD_VLAN_INSERT | + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_TX_OFFLOAD_UDP_CKSUM | + RTE_ETH_TX_OFFLOAD_TCP_CKSUM | + RTE_ETH_TX_OFFLOAD_TCP_TSO | + RTE_ETH_TX_OFFLOAD_MULTI_SEGS; + + return tx_offload_capa; +} + +int +rtl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_tx_desc, unsigned int socket_id, + const struct rte_eth_txconf *tx_conf) +{ + struct rtl_tx_queue *txq; + const struct rte_memzone *mz; + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + u32 size; + + PMD_INIT_FUNC_TRACE(); + + if (nb_tx_desc < RTL_MIN_TX_DESC || nb_tx_desc > RTL_MAX_TX_DESC) { + PMD_INIT_LOG(ERR, "r8169: Number of Tx descriptors must be " + "less than or equal to %d " + "greater than or equal to %d\n", RTL_MAX_TX_DESC, + RTL_MIN_TX_DESC); + return -EINVAL; + } + + /* + * If this queue existed already, free the associated memory. The + * queue cannot be reused in case we need to allocate memory on + * different socket than was previously used. + */ + if (dev->data->tx_queues[queue_idx] != NULL) { + rtl_tx_queue_release(dev, queue_idx); + dev->data->tx_queues[queue_idx] = NULL; + } + + txq = rte_zmalloc_socket("r8169 TX queue", + sizeof(struct rtl_tx_queue), + RTE_CACHE_LINE_SIZE, socket_id); + + if (txq == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate Tx queue structure"); + return -ENOMEM; + } + + /* Setup queue */ + txq->nb_tx_desc = nb_tx_desc; + txq->port_id = dev->data->port_id; + txq->queue_id = queue_idx; + txq->tx_free_thresh = tx_conf->tx_free_thresh; + + /* Allocate memory for the software ring */ + txq->sw_ring = rte_zmalloc_socket("r8169 sw tx ring", + nb_tx_desc * sizeof(struct rtl_tx_entry), + RTE_CACHE_LINE_SIZE, socket_id); + + if (txq->sw_ring == NULL) { + PMD_INIT_LOG(ERR, + "Port %d: Cannot allocate software ring for queue %d", + txq->port_id, txq->queue_id); + rte_free(txq); + return -ENOMEM; + } + + /* + * Allocate TX ring hardware descriptors. A memzone large enough to + * handle the maximum ring size is allocated in order to allow for + * resizing in later calls to the queue setup function. + */ + size = sizeof(struct rtl_tx_desc) * (nb_tx_desc + 1); + mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, size, + RTL_RING_ALIGN, socket_id); + if (mz == NULL) { + PMD_INIT_LOG(ERR, + "Port %d: Cannot allocate hardware ring for queue %d", + txq->port_id, txq->queue_id); + rtl_tx_queue_release(dev, txq->queue_id); + return -ENOMEM; + } + + txq->hw = hw; + txq->hw_ring = mz->addr; + txq->hw_ring_phys_addr = mz->iova; + + rtl_reset_tx_queue(txq); + + /* EnableTxNoClose */ + hw->NextHwDesCloPtr0 = 0; + hw->BeginHwDesCloPtr0 = 0; + + dev->data->tx_queues[queue_idx] = txq; + + return 0; +} + int rtl_tx_init(struct rte_eth_dev *dev) { + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + struct rtl_tx_queue *txq; + + txq = dev->data->tx_queues[0]; + + RTL_W32(hw, TxDescStartAddrLow, + ((u64)txq->hw_ring_phys_addr & DMA_BIT_MASK(32))); + RTL_W32(hw, TxDescStartAddrHigh, ((u64)txq->hw_ring_phys_addr >> 32)); + + rtl_enable_cfg9346_write(hw); + + /* Set TDFNR: TX Desc Fetch NumbeR */ + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_57: + case CFG_METHOD_69 ... CFG_METHOD_71: + RTL_W8(hw, TDFNR, 0x10); + break; + } + + rtl_disable_cfg9346_write(hw); + + RTL_W8(hw, ChipCmd, RTL_R8(hw, ChipCmd) | CmdTxEnb); + + dev->data->tx_queue_state[0] = RTE_ETH_QUEUE_STATE_STARTED; + return 0; } -uint16_t -rtl_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) +static inline uint32_t +rtl_tx_vlan_tag(struct rte_mbuf *tx_pkt, uint64_t ol_flags) +{ + return (ol_flags & RTE_MBUF_F_TX_VLAN) ? + (TxVlanTag | rte_bswap16(tx_pkt->vlan_tci)) : + 0; +} + +static inline int +rtl_tso_setup(struct rte_mbuf *tx_pkt, uint64_t ol_flags, u32 *opts) +{ + uint32_t mss; + uint64_t l4_offset; + + /* Check if TCP segmentation required for this packet */ + if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) { + mss = tx_pkt->tso_segsz; + l4_offset = tx_pkt->l2_len + tx_pkt->l3_len; + if (l4_offset <= GTTCPHO_MAX) { + /* Implies IP cksum in IPv4 */ + if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) + opts[0] |= GiantSendv4; + else + opts[0] |= GiantSendv6; + + opts[0] |= l4_offset << GTTCPHO_SHIFT; + opts[1] |= RTE_MIN(mss, MSS_MAX) << 18; + + return 1; + } + } + + return 0; +} + +static inline void +rtl_setup_csum_offload(struct rte_mbuf *tx_pkt, uint64_t ol_flags, + uint32_t *opts) +{ + uint32_t csum_cmd = 0; + uint64_t l4_offset; + + if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) + csum_cmd |= TxIPCS_C; + + switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) { + case RTE_MBUF_F_TX_UDP_CKSUM: + csum_cmd |= TxUDPCS_C; + break; + case RTE_MBUF_F_TX_TCP_CKSUM: + csum_cmd |= TxTCPCS_C; + break; + } + + if (csum_cmd != 0) { + if (ol_flags & RTE_MBUF_F_TX_IPV6) { + l4_offset = tx_pkt->l2_len + tx_pkt->l3_len; + csum_cmd |= TxIPV6F_C; + csum_cmd |= l4_offset << TCPHO_SHIFT; + } else + csum_cmd |= TxIPCS_C; + opts[1] |= csum_cmd; + } +} + +static uint32_t +rtl8125_get_patch_pad_len(struct rte_mbuf *tx_pkt) { + uint16_t dest_port = 0; + uint32_t pad_len = 0; + int udp_hdr_len = 8; + int trans_data_len, l4_offset; + + if (!(tx_pkt->l4_len && (tx_pkt->data_len < 175))) + goto no_padding; + + l4_offset = tx_pkt->l2_len + tx_pkt->l3_len; + trans_data_len = tx_pkt->data_len - l4_offset; + + if (trans_data_len > 3 && trans_data_len < MIN_PATCH_LENGTH) { + rte_memcpy(&dest_port, rte_pktmbuf_mtod(tx_pkt, + struct rte_ether_hdr *) + l4_offset + 2, 2); + dest_port = ntohs(dest_port); + if (dest_port == 0x13f || dest_port == 0x140) { + pad_len = MIN_PATCH_LENGTH - trans_data_len; + goto out; + } + } + + if (trans_data_len < udp_hdr_len) + pad_len = udp_hdr_len - trans_data_len; + +out: + if ((tx_pkt->data_len + pad_len) < ETH_ZLEN) + pad_len = ETH_ZLEN - tx_pkt->data_len; + + return pad_len; + +no_padding: + return 0; } +static void +rtl8125_ptp_patch(struct rte_mbuf *tx_pkt) +{ + uint32_t pad_len; + char *padding; + + if (tx_pkt->packet_type & RTE_PTYPE_L4_UDP) { + pad_len = rtl8125_get_patch_pad_len(tx_pkt); + if (pad_len > 0) { + padding = rte_pktmbuf_append(tx_pkt, pad_len); + if (unlikely(padding == NULL)) + PMD_DRV_LOG(ERR, "not enough mbuf trailing space\n"); + memset(padding, 0, pad_len); + } + } +} + +static inline void +rtl_xmit_pkt(struct rtl_hw *hw, struct rtl_tx_queue *txq, + struct rte_mbuf *tx_pkt) +{ + + struct rte_mbuf *m_seg; + struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id]; + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_sw_stats *stats = &adapter->sw_stats; + struct rtl_tx_desc *txd; + struct rtl_tx_entry *txe = NULL; + uint16_t desc_count = 0; + const uint16_t nb_tx_desc = txq->nb_tx_desc; + uint16_t tail; + u32 len; + u32 opts[2] = {0}; + u32 opts1; + u32 opts2; + int large_send; + uint64_t buf_dma_addr; + uint64_t ol_flags; + uint64_t tx_ol_flags; + + /* Like cur_tx */ + tail = (uint16_t)(txq->tx_tail % nb_tx_desc); + + /* If hardware offload required */ + ol_flags = tx_pkt->ol_flags; + tx_ol_flags = ol_flags & RTL_TX_OFFLOAD_MASK; + + opts[0] = DescOwn; + opts[1] = rtl_tx_vlan_tag(tx_pkt, tx_ol_flags); + + large_send = rtl_tso_setup(tx_pkt, tx_ol_flags, opts); + + /* No TSO */ + if (large_send == 0) { + rtl_setup_csum_offload(tx_pkt, tx_ol_flags, opts); + + switch (hw->mcfg) { + case CFG_METHOD_48 ... CFG_METHOD_53: + rtl8125_ptp_patch(tx_pkt); + break; + } + } + + for (m_seg = tx_pkt; m_seg; m_seg = m_seg->next) { + opts1 = opts[0]; + opts2 = opts[1]; + + len = m_seg->data_len; + + if (len == 0) + break; + + txd = &txq->hw_ring[tail]; + + buf_dma_addr = rte_mbuf_data_iova(m_seg); + txd->addr = rte_cpu_to_le_64(buf_dma_addr); + + opts1 |= len; + if (m_seg == tx_pkt) + opts1 |= FirstFrag; + if (!m_seg->next) + opts1 |= LastFrag; + if (tail == nb_tx_desc - 1) + opts1 |= RingEnd; + + /* Store mbuf for freeing later */ + txe = &txq->sw_ring[tail]; + + if (txe->mbuf) + rte_pktmbuf_free_seg(txe->mbuf); + + txe->mbuf = m_seg; + + txd->opts2 = rte_cpu_to_le_32(opts2); + rte_wmb(); + txd->opts1 = rte_cpu_to_le_32(opts1); + + tail = (tail + 1) % nb_tx_desc; + + desc_count++; + + stats->tx_bytes += len; + } + + txq->tx_tail += desc_count; + txq->tx_free -= desc_count; + + stats->tx_packets++; +} + +static inline u32 +rtl_fast_mod_mask(const u32 input, const u32 mask) +{ + return input > mask ? input & mask : input; +} + +static u32 +rtl_get_hw_clo_ptr(struct rtl_hw *hw) +{ + switch (hw->HwSuppTxNoCloseVer) { + case 3: + return RTL_R16(hw, hw->hw_clo_ptr_reg); + case 4: + case 5: + case 6: + return RTL_R32(hw, hw->hw_clo_ptr_reg); + default: + return 0; + } +} + +static u32 +rtl_get_opts1(struct rtl_tx_desc *txd) +{ + rte_smp_rmb(); + + return rte_le_to_cpu_32(txd->opts1); +} + +static void +rtl_tx_clean(struct rtl_hw *hw, struct rtl_tx_queue *txq) +{ + struct rtl_tx_entry *sw_ring = txq->sw_ring; + struct rtl_tx_entry *txe; + struct rtl_tx_desc *txd; + const uint8_t enable_tx_no_close = hw->EnableTxNoClose; + const uint16_t nb_tx_desc = txq->nb_tx_desc; + uint16_t head = txq->tx_head; + uint16_t desc_freed = 0; + uint32_t tx_left; + uint32_t tx_desc_closed, next_hw_desc_clo_ptr0; + + if (txq == NULL) + return; + + if (enable_tx_no_close) { + next_hw_desc_clo_ptr0 = rtl_get_hw_clo_ptr(hw); + hw->NextHwDesCloPtr0 = next_hw_desc_clo_ptr0; + tx_desc_closed = rtl_fast_mod_mask(next_hw_desc_clo_ptr0 - + hw->BeginHwDesCloPtr0, hw->MaxTxDescPtrMask); + tx_left = RTE_MIN(((READ_ONCE(txq->tx_tail) % nb_tx_desc) - head), + tx_desc_closed); + hw->BeginHwDesCloPtr0 += tx_left; + } else + tx_left = (READ_ONCE(txq->tx_tail) % nb_tx_desc) - head; + + while (tx_left > 0) { + txd = &txq->hw_ring[head]; + + if (!enable_tx_no_close && (rtl_get_opts1(txd) & DescOwn)) + break; + + txe = &sw_ring[head]; + if (txe->mbuf) { + rte_pktmbuf_free_seg(txe->mbuf); + txe->mbuf = NULL; + } + + head = (head + 1) % nb_tx_desc; + desc_freed++; + tx_left--; + } + txq->tx_free += desc_freed; + txq->tx_head = head; +} + +int +rtl_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) +{ + struct rtl_tx_queue *txq = tx_queue; + struct rtl_hw *hw = txq->hw; + struct rtl_tx_entry *sw_ring = txq->sw_ring; + struct rtl_tx_entry *txe; + struct rtl_tx_desc *txd; + const uint8_t enable_tx_no_close = hw->EnableTxNoClose; + const uint16_t nb_tx_desc = txq->nb_tx_desc; + uint16_t head = txq->tx_head; + uint16_t desc_freed = 0; + uint32_t tx_left; + uint32_t count = 0; + uint32_t status; + uint32_t tx_desc_closed, next_hw_desc_clo_ptr0; + + if (txq == NULL) + return -ENODEV; + + if (enable_tx_no_close) { + next_hw_desc_clo_ptr0 = rtl_get_hw_clo_ptr(hw); + hw->NextHwDesCloPtr0 = next_hw_desc_clo_ptr0; + tx_desc_closed = rtl_fast_mod_mask(next_hw_desc_clo_ptr0 - + hw->BeginHwDesCloPtr0, hw->MaxTxDescPtrMask); + tx_left = RTE_MIN(((READ_ONCE(txq->tx_tail) % nb_tx_desc) - head), + tx_desc_closed); + hw->BeginHwDesCloPtr0 += tx_left; + } else + tx_left = (READ_ONCE(txq->tx_tail) % nb_tx_desc) - head; + + while (tx_left > 0) { + txd = &txq->hw_ring[head]; + + status = rtl_get_opts1(txd); + + if (!enable_tx_no_close && (status & DescOwn)) + break; + + txe = &sw_ring[head]; + if (txe->mbuf) { + rte_pktmbuf_free_seg(txe->mbuf); + txe->mbuf = NULL; + } + + head = (head + 1) % nb_tx_desc; + + desc_freed++; + tx_left--; + + if (status & LastFrag) { + count++; + if (count == free_cnt) + break; + } + + } + + txq->tx_free += desc_freed; + txq->tx_head = head; + + return count; +} + +static void +rtl_doorbell(struct rtl_hw *hw, struct rtl_tx_queue *txq) +{ + if (hw->EnableTxNoClose) + if (hw->HwSuppTxNoCloseVer > 3) + RTL_W32(hw, hw->sw_tail_ptr_reg, txq->tx_tail); + else + RTL_W16(hw, hw->sw_tail_ptr_reg, txq->tx_tail); + else + RTL_W16(hw, TPPOLL_8125, BIT_0); +} + +/* PMD transmit function */ +uint16_t +rtl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) +{ + struct rtl_tx_queue *txq = tx_queue; + struct rtl_hw *hw = txq->hw; + struct rte_mbuf *tx_pkt; + uint16_t nb_tx; + + RTE_ASSERT(RTL_R8(hw, ChipCmd) & CmdTxEnb); + + PMD_TX_LOG(DEBUG, + "port %d txq %d pkts: %d tx_free=%d tx_tail=%d tx_head=%d", + txq->port_id, txq->queue_id, nb_pkts, txq->tx_free, + txq->tx_tail, txq->tx_head); + + for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) { + tx_pkt = *tx_pkts++; + + if (txq->tx_free < tx_pkt->nb_segs) + break; + + /* Check mbuf is valid */ + if (tx_pkt->nb_segs == 0 || tx_pkt->pkt_len == 0 || + (tx_pkt->nb_segs > 1 && tx_pkt->next == NULL)) + break; + + rtl_xmit_pkt(hw, txq, tx_pkt); + } + + rte_wmb(); + + if (nb_tx > 0) + rtl_doorbell(hw, txq); + + PMD_TX_LOG(DEBUG, "rtl_xmit_pkts %d transmitted", nb_tx); + + rtl_tx_clean(hw, txq); + + return nb_tx; +} + int rtl_stop_queues(struct rte_eth_dev *dev) { + struct rtl_tx_queue *txq; struct rtl_rx_queue *rxq; PMD_INIT_FUNC_TRACE(); + txq = dev->data->tx_queues[0]; + + rtl_tx_queue_release_mbufs(txq); + rtl_reset_tx_queue(txq); + dev->data->tx_queue_state[0] = RTE_ETH_QUEUE_STATE_STOPPED; + rxq = dev->data->rx_queues[0]; rtl_rx_queue_release_mbufs(rxq); @@ -836,5 +1486,10 @@ rtl_free_queues(struct rte_eth_dev *dev) rtl_rx_queue_release(dev, 0); dev->data->rx_queues[0] = 0; dev->data->nb_rx_queues = 0; + + rte_eth_dma_zone_free(dev, "tx_ring", 0); + rtl_tx_queue_release(dev, 0); + dev->data->tx_queues[0] = 0; + dev->data->nb_tx_queues = 0; } From patchwork Tue Oct 15 03:09:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145943 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C4B8445B3C; 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Tue, 15 Oct 2024 11:11:32 +0800 Received: from RSEXDAG02.realsil.com.cn (172.29.17.196) by RSEXMBS03.realsil.com.cn (172.29.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:11:32 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXDAG02.realsil.com.cn (172.29.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:11:32 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:11:32 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 13/18] net/r8169: implement device statistics Date: Tue, 15 Oct 2024 11:09:23 +0800 Message-ID: <20241015030928.70642-14-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_base.h | 16 +++++++ drivers/net/r8169/r8169_ethdev.c | 49 ++++++++++++++++++- drivers/net/r8169/r8169_ethdev.h | 3 ++ drivers/net/r8169/r8169_hw.c | 80 ++++++++++++++++++++++++++++++++ drivers/net/r8169/r8169_hw.h | 6 +++ 5 files changed, 153 insertions(+), 1 deletion(-) diff --git a/drivers/net/r8169/r8169_base.h b/drivers/net/r8169/r8169_base.h index 043d66f6c2..98c965ac23 100644 --- a/drivers/net/r8169/r8169_base.h +++ b/drivers/net/r8169/r8169_base.h @@ -23,6 +23,22 @@ typedef uint16_t u16; typedef uint32_t u32; typedef uint64_t u64; +struct rtl_counters { + u64 tx_packets; + u64 rx_packets; + u64 tx_errors; + u32 rx_errors; + u16 rx_missed; + u16 align_errors; + u32 tx_one_collision; + u32 tx_multi_collision; + u64 rx_unicast; + u64 rx_broadcast; + u32 rx_multicast; + u16 tx_aborted; + u16 tx_underun; +}; + enum mcfg { CFG_METHOD_1 = 1, CFG_METHOD_2, diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index 61aa16cc10..cf9ea4dca4 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -40,7 +40,9 @@ static int rtl_dev_set_link_up(struct rte_eth_dev *dev); static int rtl_dev_set_link_down(struct rte_eth_dev *dev); static int rtl_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); - +static int rtl_dev_stats_get(struct rte_eth_dev *dev, + struct rte_eth_stats *rte_stats); +static int rtl_dev_stats_reset(struct rte_eth_dev *dev); /* * The set of PCI devices this driver supports */ @@ -78,6 +80,9 @@ static const struct eth_dev_ops rtl_eth_dev_ops = { .link_update = rtl_dev_link_update, + .stats_get = rtl_dev_stats_get, + .stats_reset = rtl_dev_stats_reset, + .rx_queue_setup = rtl_rx_queue_setup, .rx_queue_release = rtl_rx_queue_release, .rxq_info_get = rtl_rxq_info_get, @@ -242,6 +247,11 @@ rtl_dev_start(struct rte_eth_dev *dev) goto error; } + /* This can fail when allocating mem for tally counters */ + err = rtl_tally_init(dev); + if (err) + goto error; + /* Enable uio/vfio intr/eventfd mapping */ rte_intr_enable(intr_handle); @@ -288,6 +298,8 @@ rtl_dev_stop(struct rte_eth_dev *dev) rtl_stop_queues(dev); + rtl_tally_free(dev); + /* Clear the recorded link status */ memset(&link, 0, sizeof(link)); rte_eth_linkstatus_set(dev, &link); @@ -373,6 +385,41 @@ rtl_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) return 0; } +static int +rtl_dev_stats_reset(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + rtl_clear_tally_stats(hw); + + memset(&adapter->sw_stats, 0, sizeof(adapter->sw_stats)); + + return 0; +} + +static void +rtl_sw_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_sw_stats *sw_stats = &adapter->sw_stats; + + rte_stats->ibytes = sw_stats->rx_bytes; + rte_stats->obytes = sw_stats->tx_bytes; +} + +static int +rtl_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + rtl_get_tally_stats(hw, rte_stats); + rtl_sw_stats_get(dev, rte_stats); + + return 0; +} + /* Return 0 means link status changed, -1 means not changed */ static int rtl_dev_link_update(struct rte_eth_dev *dev, int wait __rte_unused) diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index 5776601081..c209b49db4 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -47,6 +47,9 @@ struct rtl_hw { u8 mac_addr[MAC_ADDR_LEN]; u32 rx_buf_sz; + struct rtl_counters *tally_vaddr; + u64 tally_paddr; + u8 RequirePhyMdiSwapPatch; u8 NotWrMcuPatchCode; u8 HwSuppMacMcuVer; diff --git a/drivers/net/r8169/r8169_hw.c b/drivers/net/r8169/r8169_hw.c index 3be56061cf..27b67c1ed6 100644 --- a/drivers/net/r8169/r8169_hw.c +++ b/drivers/net/r8169/r8169_hw.c @@ -1503,3 +1503,83 @@ rtl_rar_set(struct rtl_hw *hw, uint8_t *addr) rtl_disable_cfg9346_write(hw); } +void +rtl_get_tally_stats(struct rtl_hw *hw, struct rte_eth_stats *rte_stats) +{ + struct rtl_counters *counters; + uint64_t paddr; + u32 cmd; + u32 wait_cnt; + + counters = hw->tally_vaddr; + paddr = hw->tally_paddr; + if (!counters) + return; + + RTL_W32(hw, CounterAddrHigh, (u64)paddr >> 32); + cmd = (u64)paddr & DMA_BIT_MASK(32); + RTL_W32(hw, CounterAddrLow, cmd); + RTL_W32(hw, CounterAddrLow, cmd | CounterDump); + + wait_cnt = 0; + while (RTL_R32(hw, CounterAddrLow) & CounterDump) { + udelay(10); + + wait_cnt++; + if (wait_cnt > 20) + break; + } + + /* RX errors */ + rte_stats->imissed = rte_le_to_cpu_64(counters->rx_missed); + rte_stats->ierrors = rte_le_to_cpu_64(counters->rx_errors); + + /* TX errors */ + rte_stats->oerrors = rte_le_to_cpu_64(counters->tx_errors); + + rte_stats->ipackets = rte_le_to_cpu_64(counters->rx_packets); + rte_stats->opackets = rte_le_to_cpu_64(counters->tx_packets); +} + +void +rtl_clear_tally_stats(struct rtl_hw *hw) +{ + if (!hw->tally_paddr) + return; + + RTL_W32(hw, CounterAddrHigh, (u64)hw->tally_paddr >> 32); + RTL_W32(hw, CounterAddrLow, + ((u64)hw->tally_paddr & (DMA_BIT_MASK(32))) | CounterReset); +} + +int +rtl_tally_init(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + const struct rte_memzone *mz; + + mz = rte_eth_dma_zone_reserve(dev, "tally_counters", 0, + sizeof(struct rtl_counters), 64, rte_socket_id()); + if (mz == NULL) + return -ENOMEM; + + hw->tally_vaddr = mz->addr; + hw->tally_paddr = mz->iova; + + /* Fill tally addrs */ + RTL_W32(hw, CounterAddrHigh, (u64)hw->tally_paddr >> 32); + RTL_W32(hw, CounterAddrLow, (u64)hw->tally_paddr & (DMA_BIT_MASK(32))); + + /* Reset the hw statistics */ + rtl_clear_tally_stats(hw); + + return 0; +} + +void +rtl_tally_free(struct rte_eth_dev *dev) +{ + rte_eth_dma_zone_free(dev, "tally_counters", 0); +} + diff --git a/drivers/net/r8169/r8169_hw.h b/drivers/net/r8169/r8169_hw.h index 857f71deac..36d9c06b14 100644 --- a/drivers/net/r8169/r8169_hw.h +++ b/drivers/net/r8169/r8169_hw.h @@ -54,6 +54,12 @@ void rtl_rar_set(struct rtl_hw *hw, uint8_t *addr); void rtl_set_link_option(struct rtl_hw *hw, u8 autoneg, u32 speed, u8 duplex, enum rtl_fc_mode fc); +void rtl_get_tally_stats(struct rtl_hw *hw, struct rte_eth_stats *rte_stats); +void rtl_clear_tally_stats(struct rtl_hw *hw); + +int rtl_tally_init(struct rte_eth_dev *dev); +void rtl_tally_free(struct rte_eth_dev *dev); + extern const struct rtl_hw_ops rtl8125a_ops; extern const struct rtl_hw_ops rtl8125b_ops; extern const struct rtl_hw_ops rtl8125bp_ops; From patchwork Tue Oct 15 03:09:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145944 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 661BD45B3C; Tue, 15 Oct 2024 05:11:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5EDFF4027F; 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Tue, 15 Oct 2024 11:11:40 +0800 Received: from RSEXDAG02.realsil.com.cn (172.29.17.196) by RSEXMBS01.realsil.com.cn (172.29.17.195) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:11:40 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXDAG02.realsil.com.cn (172.29.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:11:40 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:11:40 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 14/18] net/r8169: implement promisc and allmulti modes Date: Tue, 15 Oct 2024 11:09:24 +0800 Message-ID: <20241015030928.70642-15-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for promiscuous/allmulticast modes configuration. Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_ethdev.c | 68 ++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index cf9ea4dca4..3e6bc570d6 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -43,6 +43,11 @@ static int rtl_dev_infos_get(struct rte_eth_dev *dev, static int rtl_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats); static int rtl_dev_stats_reset(struct rte_eth_dev *dev); +static int rtl_promiscuous_enable(struct rte_eth_dev *dev); +static int rtl_promiscuous_disable(struct rte_eth_dev *dev); +static int rtl_allmulticast_enable(struct rte_eth_dev *dev); +static int rtl_allmulticast_disable(struct rte_eth_dev *dev); + /* * The set of PCI devices this driver supports */ @@ -78,6 +83,11 @@ static const struct eth_dev_ops rtl_eth_dev_ops = { .dev_set_link_down = rtl_dev_set_link_down, .dev_infos_get = rtl_dev_infos_get, + .promiscuous_enable = rtl_promiscuous_enable, + .promiscuous_disable = rtl_promiscuous_disable, + .allmulticast_enable = rtl_allmulticast_enable, + .allmulticast_disable = rtl_allmulticast_disable, + .link_update = rtl_dev_link_update, .stats_get = rtl_dev_stats_get, @@ -385,6 +395,64 @@ rtl_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) return 0; } +static int +rtl_promiscuous_enable(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + int rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys; + + RTL_W32(hw, RxConfig, rx_mode | (RTL_R32(hw, RxConfig))); + rtl_allmulticast_enable(dev); + + return 0; +} + +static int +rtl_promiscuous_disable(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + int rx_mode = ~AcceptAllPhys; + + RTL_W32(hw, RxConfig, rx_mode & (RTL_R32(hw, RxConfig))); + + if (dev->data->all_multicast == 1) + rtl_allmulticast_enable(dev); + else + rtl_allmulticast_disable(dev); + + return 0; +} + +static int +rtl_allmulticast_enable(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + RTL_W32(hw, MAR0 + 0, 0xffffffff); + RTL_W32(hw, MAR0 + 4, 0xffffffff); + + return 0; +} + +static int +rtl_allmulticast_disable(struct rte_eth_dev *dev) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + + if (dev->data->promiscuous == 1) + return 0; /* Must remain in all_multicast mode */ + + RTL_W32(hw, MAR0 + 0, 0); + RTL_W32(hw, MAR0 + 4, 0); + + return 0; +} + static int rtl_dev_stats_reset(struct rte_eth_dev *dev) { From patchwork Tue Oct 15 03:09:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145945 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7D3E45B3C; Tue, 15 Oct 2024 05:11:52 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9E1FB40697; Tue, 15 Oct 2024 05:11:52 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id 9F5D940689 for ; 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Tue, 15 Oct 2024 11:11:49 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXDAG02.realsil.com.cn (172.29.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:11:49 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:11:49 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 15/18] net/r8169: impelment MTU configuration Date: Tue, 15 Oct 2024 11:09:25 +0800 Message-ID: <20241015030928.70642-16-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for updating MTU value. Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_ethdev.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index 3e6bc570d6..70c3661691 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -47,6 +47,7 @@ static int rtl_promiscuous_enable(struct rte_eth_dev *dev); static int rtl_promiscuous_disable(struct rte_eth_dev *dev); static int rtl_allmulticast_enable(struct rte_eth_dev *dev); static int rtl_allmulticast_disable(struct rte_eth_dev *dev); +static int rtl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); /* * The set of PCI devices this driver supports @@ -93,6 +94,8 @@ static const struct eth_dev_ops rtl_eth_dev_ops = { .stats_get = rtl_dev_stats_get, .stats_reset = rtl_dev_stats_reset, + .mtu_set = rtl_dev_mtu_set, + .rx_queue_setup = rtl_rx_queue_setup, .rx_queue_release = rtl_rx_queue_release, .rxq_info_get = rtl_rxq_info_get, @@ -388,6 +391,9 @@ rtl_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) break; } + dev_info->min_mtu = RTE_ETHER_MIN_MTU; + dev_info->max_mtu = dev_info->max_rx_pktlen - RTL_ETH_OVERHEAD; + dev_info->rx_offload_capa = (rtl_get_rx_port_offloads() | dev_info->rx_queue_offload_capa); dev_info->tx_offload_capa = rtl_get_tx_port_offloads(); @@ -610,6 +616,29 @@ rtl_dev_close(struct rte_eth_dev *dev) return ret_stp; } +static int +rtl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) +{ + struct rte_eth_dev_info dev_info; + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + int ret; + uint32_t frame_size = mtu + RTL_ETH_OVERHEAD; + + ret = rtl_dev_infos_get(dev, &dev_info); + if (ret != 0) + return ret; + + if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) + return -EINVAL; + + hw->mtu = mtu; + + RTL_W16(hw, RxMaxSize, frame_size); + + return 0; +} + static int rtl_dev_init(struct rte_eth_dev *dev) { From patchwork Tue Oct 15 03:09:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145946 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CB90445B3C; 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Tue, 15 Oct 2024 11:11:58 +0800 Received: from RSEXDAG02.realsil.com.cn (172.29.17.196) by RSEXH36501.realsil.com.cn (172.29.17.2) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:11:58 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXDAG02.realsil.com.cn (172.29.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:11:57 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:11:57 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 16/18] net/r8169: add support for getting fw version Date: Tue, 15 Oct 2024 11:09:26 +0800 Message-ID: <20241015030928.70642-17-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_ethdev.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index 70c3661691..dd2c7dda24 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -48,6 +48,8 @@ static int rtl_promiscuous_disable(struct rte_eth_dev *dev); static int rtl_allmulticast_enable(struct rte_eth_dev *dev); static int rtl_allmulticast_disable(struct rte_eth_dev *dev); static int rtl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); +static int rtl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, + size_t fw_size); /* * The set of PCI devices this driver supports @@ -96,6 +98,8 @@ static const struct eth_dev_ops rtl_eth_dev_ops = { .mtu_set = rtl_dev_mtu_set, + .fw_version_get = rtl_fw_version_get, + .rx_queue_setup = rtl_rx_queue_setup, .rx_queue_release = rtl_rx_queue_release, .rxq_info_get = rtl_rxq_info_get, @@ -639,6 +643,22 @@ rtl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) return 0; } +static int +rtl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) +{ + struct rtl_adapter *adapter = RTL_DEV_PRIVATE(dev); + struct rtl_hw *hw = &adapter->hw; + int ret; + + ret = snprintf(fw_version, fw_size, "0x%08x", hw->hw_ram_code_ver); + + ret += 1; /* Add the size of '\0' */ + if (fw_size < (u32)ret) + return ret; + else + return 0; +} + static int rtl_dev_init(struct rte_eth_dev *dev) { From patchwork Tue Oct 15 03:09:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145947 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EFC2845B3C; Tue, 15 Oct 2024 05:12:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E37C14067A; Tue, 15 Oct 2024 05:12:08 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id 1033A4067A for ; Tue, 15 Oct 2024 05:12:06 +0200 (CEST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 49F3C4VS0820958, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; 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Tue, 15 Oct 2024 11:12:04 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXDAG02.realsil.com.cn (172.29.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:12:04 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:12:04 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 17/18] net/r8169: add driver_start and driver_stop Date: Tue, 15 Oct 2024 11:09:27 +0800 Message-ID: <20241015030928.70642-18-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org rtl8125ap and rtl8125bp need driver start and stop whether dash is enabled or not. Signed-off-by: Howard Wang --- drivers/net/r8169/base/rtl8126a_mcu.h | 1 + drivers/net/r8169/r8169_base.h | 6 +- drivers/net/r8169/r8169_dash.c | 149 +++++++++++++++++++++++++- drivers/net/r8169/r8169_dash.h | 25 ++++- drivers/net/r8169/r8169_ethdev.c | 4 + drivers/net/r8169/r8169_hw.c | 5 + 6 files changed, 184 insertions(+), 6 deletions(-) diff --git a/drivers/net/r8169/base/rtl8126a_mcu.h b/drivers/net/r8169/base/rtl8126a_mcu.h index ae4aa5f3d4..89e600d87c 100644 --- a/drivers/net/r8169/base/rtl8126a_mcu.h +++ b/drivers/net/r8169/base/rtl8126a_mcu.h @@ -12,5 +12,6 @@ void rtl_set_mac_mcu_8126a_3(struct rtl_hw *hw); void rtl_set_phy_mcu_8126a_1(struct rtl_hw *hw); void rtl_set_phy_mcu_8126a_2(struct rtl_hw *hw); void rtl_set_phy_mcu_8126a_3(struct rtl_hw *hw); + #endif diff --git a/drivers/net/r8169/r8169_base.h b/drivers/net/r8169/r8169_base.h index 98c965ac23..6e05ab3f3c 100644 --- a/drivers/net/r8169/r8169_base.h +++ b/drivers/net/r8169/r8169_base.h @@ -271,7 +271,11 @@ enum RTL_registers { Q_NUM_CTRL_8125 = 0x4800, RSS_KEY_8125 = 0x4600, RSS_INDIRECTION_TBL_8125_V2 = 0x4700, - EEE_TXIDLE_TIMER_8125 = 0x6048, + EEE_TXIDLE_TIMER_8125 = 0x6048, + IB2SOC_SET = 0x0010, + IB2SOC_DATA = 0x0014, + IB2SOC_CMD = 0x0018, + IB2SOC_IMR = 0x001C, }; enum RTL_register_content { diff --git a/drivers/net/r8169/r8169_dash.c b/drivers/net/r8169/r8169_dash.c index e803ce8305..0b2fd59de1 100644 --- a/drivers/net/r8169/r8169_dash.c +++ b/drivers/net/r8169/r8169_dash.c @@ -26,14 +26,14 @@ rtl_is_allow_access_dash_ocp(struct rtl_hw *hw) allow_access = true; switch (hw->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: + case CFG_METHOD_48: + case CFG_METHOD_49: mac_ocp_data = rtl_mac_ocp_read(hw, 0xd460); if (mac_ocp_data == 0xffff || !(mac_ocp_data & BIT_0)) allow_access = false; break; - case CFG_METHOD_8: - case CFG_METHOD_9: + case CFG_METHOD_54: + case CFG_METHOD_55: mac_ocp_data = rtl_mac_ocp_read(hw, 0xd4c0); if (mac_ocp_data == 0xffff || (mac_ocp_data & BIT_3)) allow_access = false; @@ -87,3 +87,144 @@ rtl_check_dash(struct rtl_hw *hw) return 0; } +static void +rtl8125_dash2_disable_tx(struct rtl_hw *hw) +{ + u16 wait_cnt = 0; + u8 tmp_uchar; + + if (!HW_DASH_SUPPORT_CMAC(hw)) + return; + + if (!hw->DASH) + return; + + /* Disable oob Tx */ + RTL_CMAC_W8(hw, CMAC_IBCR2, RTL_CMAC_R8(hw, CMAC_IBCR2) & ~BIT_0); + + /* Wait oob Tx disable */ + do { + tmp_uchar = RTL_CMAC_R8(hw, CMAC_IBISR0); + if (tmp_uchar & ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE) + break; + + udelay(50); + wait_cnt++; + } while (wait_cnt < 2000); + + /* Clear ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE */ + RTL_CMAC_W8(hw, CMAC_IBISR0, RTL_CMAC_R8(hw, CMAC_IBISR0) | + ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE); +} + +static void +rtl8125_dash2_disable_rx(struct rtl_hw *hw) +{ + if (!HW_DASH_SUPPORT_CMAC(hw)) + return; + + if (!hw->DASH) + return; + + RTL_CMAC_W8(hw, CMAC_IBCR0, RTL_CMAC_R8(hw, CMAC_IBCR0) & ~BIT_0); +} + +void +rtl8125_dash2_disable_txrx(struct rtl_hw *hw) +{ + if (!HW_DASH_SUPPORT_CMAC(hw)) + return; + + rtl8125_dash2_disable_tx(hw); + rtl8125_dash2_disable_rx(hw); +} + +static void +rtl8125_notify_dash_oob_cmac(struct rtl_hw *hw, u32 cmd) +{ + u32 tmp_value; + + if (!HW_DASH_SUPPORT_CMAC(hw)) + return; + + rtl_ocp_write(hw, 0x180, 4, cmd); + tmp_value = rtl_ocp_read(hw, 0x30, 4); + tmp_value |= BIT_0; + rtl_ocp_write(hw, 0x30, 4, tmp_value); +} + +static void +rtl8125_notify_dash_oob_ipc2(struct rtl_hw *hw, u32 cmd) +{ + if (FALSE == HW_DASH_SUPPORT_TYPE_4(hw)) + return; + + rtl_ocp_write(hw, IB2SOC_DATA, 4, cmd); + rtl_ocp_write(hw, IB2SOC_CMD, 4, 0x00); + rtl_ocp_write(hw, IB2SOC_SET, 4, 0x01); +} + +static void +rtl8125_notify_dash_oob(struct rtl_hw *hw, u32 cmd) +{ + switch (hw->HwSuppDashVer) { + case 2: + case 3: + rtl8125_notify_dash_oob_cmac(hw, cmd); + break; + case 4: + rtl8125_notify_dash_oob_ipc2(hw, cmd); + break; + default: + break; + } +} + +static int +rtl8125_wait_dash_fw_ready(struct rtl_hw *hw) +{ + int rc = -1; + int timeout; + + if (!hw->DASH) + goto out; + + for (timeout = 0; timeout < 10; timeout++) { + mdelay(10); + if (rtl_ocp_read(hw, 0x124, 1) & BIT_0) { + rc = 1; + goto out; + } + } + + rc = 0; + +out: + return rc; +} + +void +rtl8125_driver_start(struct rtl_hw *hw) +{ + if (!hw->AllowAccessDashOcp) + return; + + rtl8125_notify_dash_oob(hw, OOB_CMD_DRIVER_START); + + rtl8125_wait_dash_fw_ready(hw); +} + +void +rtl8125_driver_stop(struct rtl_hw *hw) +{ + if (!hw->AllowAccessDashOcp) + return; + + if (HW_DASH_SUPPORT_CMAC(hw)) + rtl8125_dash2_disable_txrx(hw); + + rtl8125_notify_dash_oob(hw, OOB_CMD_DRIVER_STOP); + + rtl8125_wait_dash_fw_ready(hw); +} + diff --git a/drivers/net/r8169/r8169_dash.h b/drivers/net/r8169/r8169_dash.h index d89b2e2d3b..6dbc6b6539 100644 --- a/drivers/net/r8169/r8169_dash.h +++ b/drivers/net/r8169/r8169_dash.h @@ -19,17 +19,40 @@ #define HW_DASH_SUPPORT_TYPE_2(_M) ((_M)->HwSuppDashVer == 2) #define HW_DASH_SUPPORT_TYPE_3(_M) ((_M)->HwSuppDashVer == 3) #define HW_DASH_SUPPORT_TYPE_4(_M) ((_M)->HwSuppDashVer == 4) - +#define HW_DASH_SUPPORT_CMAC(_M) (HW_DASH_SUPPORT_TYPE_2(_M) || HW_DASH_SUPPORT_TYPE_3(_M)) #define HW_DASH_SUPPORT_GET_FIRMWARE_VERSION(_M) (HW_DASH_SUPPORT_TYPE_2(_M) || \ HW_DASH_SUPPORT_TYPE_3(_M) || \ HW_DASH_SUPPORT_TYPE_4(_M)) +#define OOB_CMD_DRIVER_START 0x05 +#define OOB_CMD_DRIVER_STOP 0x06 + #define OCP_REG_FIRMWARE_MAJOR_VERSION 0x120 +#define ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE BIT_5 + +/* CMAC write/read MMIO register */ +#define RTL_CMAC_REG_ADDR(hw, reg) ((u8 *)(hw)->cmac_ioaddr + (reg)) +#define RTL_CMAC_R32(hw, reg) rtl_read32(RTL_CMAC_REG_ADDR(hw, reg)) +#define RTL_CMAC_R16(hw, reg) rtl_read16(RTL_CMAC_REG_ADDR(hw, reg)) +#define RTL_CMAC_R8(hw, reg) rte_read8(RTL_CMAC_REG_ADDR(hw, reg)) + +#define RTL_CMAC_W32(hw, reg, val) \ + rte_write32((rte_cpu_to_le_32(val)), RTL_CMAC_REG_ADDR(hw, reg)) + +#define RTL_CMAC_W16(hw, reg, val) \ + rte_write16((rte_cpu_to_le_16(val)), RTL_CMAC_REG_ADDR(hw, reg)) + +#define RTL_CMAC_W8(hw, reg, val) \ + rte_write8((val), RTL_CMAC_REG_ADDR(hw, reg)) + bool rtl_is_allow_access_dash_ocp(struct rtl_hw *hw); int rtl_check_dash(struct rtl_hw *hw); +void rtl8125_driver_start(struct rtl_hw *hw); +void rtl8125_driver_stop(struct rtl_hw *hw); +void rtl8125_dash2_disable_txrx(struct rtl_hw *hw); #endif diff --git a/drivers/net/r8169/r8169_ethdev.c b/drivers/net/r8169/r8169_ethdev.c index dd2c7dda24..3130f831dd 100644 --- a/drivers/net/r8169/r8169_ethdev.c +++ b/drivers/net/r8169/r8169_ethdev.c @@ -29,6 +29,7 @@ #include "r8169_base.h" #include "r8169_logs.h" #include "r8169_hw.h" +#include "r8169_dash.h" static int rtl_dev_configure(struct rte_eth_dev *dev __rte_unused); static int rtl_dev_start(struct rte_eth_dev *dev); @@ -596,6 +597,9 @@ rtl_dev_close(struct rte_eth_dev *dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; + if (HW_DASH_SUPPORT_DASH(hw)) + rtl8125_driver_stop(hw); + ret_stp = rtl_dev_stop(dev); rtl_free_queues(dev); diff --git a/drivers/net/r8169/r8169_hw.c b/drivers/net/r8169/r8169_hw.c index 27b67c1ed6..ed316687a9 100644 --- a/drivers/net/r8169/r8169_hw.c +++ b/drivers/net/r8169/r8169_hw.c @@ -1288,6 +1288,11 @@ rtl_exit_oob(struct rtl_hw *hw) rtl_disable_rx_packet_filter(hw); + if (HW_DASH_SUPPORT_DASH(hw)) { + rtl8125_driver_start(hw); + rtl8125_dash2_disable_txrx(hw); + } + rtl_exit_realwow(hw); rtl_nic_reset(hw); From patchwork Tue Oct 15 03:09:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Howard Wang X-Patchwork-Id: 145948 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 431BC45B3C; Tue, 15 Oct 2024 05:12:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3F10E4065D; Tue, 15 Oct 2024 05:12:22 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id A0E84402D3 for ; Tue, 15 Oct 2024 05:12:20 +0200 (CEST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 49F3CIF50821015, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; 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Tue, 15 Oct 2024 11:12:18 +0800 Received: from RSEXH36502.realsil.com.cn (172.29.17.3) by RSEXDAG02.realsil.com.cn (172.29.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 15 Oct 2024 11:12:18 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36502.realsil.com.cn (172.29.17.3) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 15 Oct 2024 11:12:18 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH v1 18/18] doc/guides/nics: add documents for r8169 pmd Date: Tue, 15 Oct 2024 11:09:28 +0800 Message-ID: <20241015030928.70642-19-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015030928.70642-1-howard_wang@realsil.com.cn> References: <20241015030928.70642-1-howard_wang@realsil.com.cn> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Signed-off-by: Howard Wang --- MAINTAINERS | 2 ++ doc/guides/nics/features/r8169.ini | 32 ++++++++++++++++++++++++++++++ doc/guides/nics/r8169.rst | 17 ++++++++++++++++ 3 files changed, 51 insertions(+) create mode 100644 doc/guides/nics/features/r8169.ini create mode 100644 doc/guides/nics/r8169.rst diff --git a/MAINTAINERS b/MAINTAINERS index 5f9eccc43f..6f56c966fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1082,6 +1082,8 @@ M: ChunHao Lin M: Xing Wang M: Realtek NIC SW F: drivers/net/r8169 +F: doc/guides/nics/r8169.rst +F: doc/guides/nics/features/r8169.ini Crypto Drivers diff --git a/doc/guides/nics/features/r8169.ini b/doc/guides/nics/features/r8169.ini new file mode 100644 index 0000000000..8e4142f64e --- /dev/null +++ b/doc/guides/nics/features/r8169.ini @@ -0,0 +1,32 @@ +; +; Supported features of the 'r8169' network poll mode driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Speed capabilities = Y +Link speed configuration = Y +Link status = Y +Link status event = Y +MTU update = Y +Scattered Rx = Y +TSO = Y +Promiscuous mode = Y +Allmulticast mode = Y +Unicast MAC filter = Y +Multicast MAC filter = Y +Flow control = Y +CRC offload = Y +L3 checksum offload = Y +L4 checksum offload = Y +Packet type parsing = Y +Rx descriptor status = Y +Tx descriptor status = Y +Basic stats = Y +Extended stats = Y +Stats per queue = Y +FW version = Y +Registers dump = Y +Linux = Y +x86-32 = Y +x86-64 = Y diff --git a/doc/guides/nics/r8169.rst b/doc/guides/nics/r8169.rst new file mode 100644 index 0000000000..149276cc91 --- /dev/null +++ b/doc/guides/nics/r8169.rst @@ -0,0 +1,17 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2024 Realtek Corporation. All rights reserved + +R8169 Poll Mode Driver +====================== + +The R8169 PMD provides poll mode driver support for Realtek 2.5 and 5 Gigabit +Ethernet NICs. + +Features +-------- + +Features of the R8169 PMD are: + +* Checksum offload +* TCP segmentation offload +* Jumbo frames supported