From patchwork Tue Oct 29 14:31:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Minggang(Gavin) Li" X-Patchwork-Id: 147598 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58FFF45B4C; Tue, 29 Oct 2024 15:32:11 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E081F42E10; Tue, 29 Oct 2024 15:32:10 +0100 (CET) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2083.outbound.protection.outlook.com [40.107.223.83]) by mails.dpdk.org (Postfix) with ESMTP id 491ED40144 for ; Tue, 29 Oct 2024 15:32:10 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PZ0tXCalDHuL4vehjiMpZM7rnWCLkbK1a0UPIV0+GZqYrWyymRYWYKr6iDunI1cA/g2XuXtEUY5K7XshGttx4FA4VBsAlnYGrcQGnY+ad92JAboeng9EHNvSCUUu3y7rqlTclmLMEyXnG+0Ao2aNUzjS9KWzCoYm3c7EX5SylxyhaTr4Y6VoJvYUduwbmIbsVzYF4i+efu7NWDGyQF+jyfkw4i6lF9IBeB0z8GguArYyUyiwbW49QnROGMG8TzcR9TgoWbMxGlJBCkeFwvs/aUnMSSNuHU64R8Lvw12y6s4T0XhlMCv9e0ugk/7WpJPtEHZoY06/RM/1QHpNpcXdNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RF6SI2HuAWtE4ftK18x6Kfk9w5TiRzuxX8Ksr6AIaJk=; b=WYFRBkEbQxMVljSsAVsFAJ9i3P3a83MsQ2nNoBc8bG+fnXY6i4/fCh0Vf50j7NZqwQUiZEE8Jtk8/JJRP1Xu1vdYeuspNS7aZiSWkElvdKHTXy2JoGvRKSnGOY6DEG+LmmZUa/aXwvj5Idjizl+To6HJ2vCO2ddIaXH18986bbynyYGbIL+XrqsOAkWy8zLPjzucsLkhd1bzQRCQbMFkKy3GDWIGXY+nhWqlfv2Evl2++8G+Sqy72kCW6RpiDae+czkmOe5YdQPQvqgihtZnWuJdLNmpz78usUOeSSWglN3q3wmEuvR5LuUG6RS6APKtD9tufhnO604vnz/xyfzWAA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RF6SI2HuAWtE4ftK18x6Kfk9w5TiRzuxX8Ksr6AIaJk=; b=FrxrfxiKBs+hASVkGBxMCTzZ7zRepMm8zhRddLLeuwoH0lEpNwSpR9Jk3sOYfmv7tqTaWh52tjBtq6Vut0NtU8az00DnsOue5Tp9KRSeXAHZqeXSUP2NeqqPpf5OdtzOfT6Rly0tDfE/jrOWx91OGZkabALHwspxPfUIyfBRLgdqYq9m6RblF4vrtdRgT5zABNW99nZag3X9rpI4ApSfTQcjQWQ98VQxNItPTALTaIByc6bDrL5Jf+iukFdRcvP7HirgCZkOpK+sLrMxUphr1uBJgpPVpXTcLKXkdzORLfK/vv6yiz4cglxhaESurHa3fNfVTt1wKIqVOG8yDO60sg== Received: from CH2PR15CA0005.namprd15.prod.outlook.com (2603:10b6:610:51::15) by DM4PR12MB8521.namprd12.prod.outlook.com (2603:10b6:8:17e::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.27; Tue, 29 Oct 2024 14:32:06 +0000 Received: from CH2PEPF00000144.namprd02.prod.outlook.com (2603:10b6:610:51:cafe::9c) by CH2PR15CA0005.outlook.office365.com (2603:10b6:610:51::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.17 via Frontend Transport; Tue, 29 Oct 2024 14:32:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CH2PEPF00000144.mail.protection.outlook.com (10.167.244.101) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.16 via Frontend Transport; Tue, 29 Oct 2024 14:32:06 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:36 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:33 -0700 From: "Minggang Li(Gavin)" To: , , , CC: , Subject: [PATCH V3 1/7] mailmap: update user name Date: Tue, 29 Oct 2024 16:31:12 +0200 Message-ID: <20241029143118.875214-2-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029143118.875214-1-gavinl@nvidia.com> References: <20241029134256.874767-8-gavinl@nvidia.com> <20241029143118.875214-1-gavinl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000144:EE_|DM4PR12MB8521:EE_ X-MS-Office365-Filtering-Correlation-Id: 9be8438e-28ab-4157-9e24-08dcf82676e9 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?q?FP2VupxHwvVBiKTAThSasiqWVZNYJij?= =?utf-8?q?oQatoP0vs7obMqDCKJtYf6vq8nw3yCv/9VnGlBOBBTQS0nUr8B/sEH1T+7cpqCxTh?= =?utf-8?q?TcUHjtzjd/gnz5+Wr6KF4bhJd/hWTWeK1of57wuyPEbd+J4JZ4GiW3tiT/1MlNzCd?= =?utf-8?q?6QAvYo4XeKP0HaH0wf8Ss3Soq3bH8n2IE8UMJUTd0USdZonKqqNiyxtiA5nPsZoPD?= =?utf-8?q?+nakH5DnLCuXdCMJIen8wgZDe7BWFIxd3vcOw13jbR4lcdz72aJPANEcNohw3oxdN?= =?utf-8?q?HWXsIJlxRxfxnbai/waMOENZKyjdNNf0hGn1bwE6EjQ6NoeUuHM7Ui/wBx4R3Q91o?= =?utf-8?q?9tM5qSbFNigw7kpyIivdRLHnZlyx37cwNGeX77SVwIs2qaPP9nZno3Aif1W9K68jO?= =?utf-8?q?RJJLjjUj582MMeHqrY2Exp0WUh/wu3pCrIprGOh1qXQzLJkX4jcr0/+0vjjXmBsDI?= =?utf-8?q?N3iKbx0t+9ZPkya0CKgX4TsZ+M8IBl0x75Uqy23Tc7gX1CdPXK5DgBjGsNNtbV02m?= =?utf-8?q?llgSJuisjgQL07U1Z383rMajcAUP8yCoaOcfMwI07kCn+pQshTYDdyLHM602UmzdW?= =?utf-8?q?uxahHnxP4d5QSmHAK47PijPmZsUongap3fSBYkzwQvtcQx7/ft/s7JDUxgM4lvIAt?= =?utf-8?q?Af6B394GpeI4sSKXSwkjB/TYCBWhvimngE1PcJM+dAeccN5/DpjVb7MV0OMm+w3R0?= =?utf-8?q?ex1u6rgide6oJL9rv75gFoCGdhbdszmOFWZWQNTpN4LrSVIbT0aFP96qc6TIM4WHP?= =?utf-8?q?SpMEwi5i8W1BYX6fyYz8Mcw6MUYboFtuhk52m/xb55+q28pD6TIOIllvQFXnTrOTE?= =?utf-8?q?am2IXdKpsbuyeqkh/CcxInREvgOfIbVmgKXFplznZZURdJxF+g+yr1bMOUg9nrR7K?= =?utf-8?q?pquf78zMxiHoIEHfh6l/iMBA4bXypYKYSh1RzfLV/vet1etvw+YhfiWM1Hro9gTTJ?= =?utf-8?q?r9LlUEQ71+cp5BnXthKiN2ZR3rfUhKeiGnFM7yY+8jG7jK2fmrIqTl7Yw3X48IN4D?= =?utf-8?q?skgtRnzTKCIT85hvgHelLfMV4mTk9JMe7FmRHa/YcbsGM16Imljk6wDODz9ZmzxSC?= =?utf-8?q?gSFIwVltX758GnfFC9epdEP+8Aue96GVRM4CSI2TXRDvzY9vbkN5LtImCC7HkEHkE?= =?utf-8?q?wOI/a3BaeQ8eeFflIuOXb0LcGkl3/cnOUFhACqGtrSaQ1GikTKVsRic1ePO85DCtV?= =?utf-8?q?SYv3HqrU9d7feDrjEYc0H4e6oW3KbAowVetJWDdZflGRexvUr4E51C0CGNUnRVG1A?= =?utf-8?q?2GnwpIwjxh1hDz+kUU8KSPBdCFArzCGanBO7NCAvsklvXt4TeW032t2uaPvWDk0aj?= =?utf-8?q?fri4ZMjBjFgwY23MLhXrxNz1sVbhaw+mwQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2024 14:32:06.5672 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9be8438e-28ab-4157-9e24-08dcf82676e9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000144.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8521 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Signed-off-by: Minggang Li(Gavin) Signed-off-by: Minggang Li(Gavin) --- .mailmap | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.mailmap b/.mailmap index 504c390f0f..0ce965084c 100644 --- a/.mailmap +++ b/.mailmap @@ -462,7 +462,6 @@ Gary Mussar Gaurav Singh Gautam Dawar Gavin Hu -Gavin Li Geoffrey Le Gourriérec Geoffrey Lv Geoff Thorpe @@ -1024,6 +1023,7 @@ Mike Ximing Chen Milena Olech Min Cao Minghuan Lian +Minggang Li(Gavin) Mingjin Ye Mingshan Zhang Mingxia Liu From patchwork Tue Oct 29 14:31:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Minggang(Gavin) Li" X-Patchwork-Id: 147599 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 308D145B4C; Tue, 29 Oct 2024 15:32:27 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6895542E91; Tue, 29 Oct 2024 15:32:19 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2076.outbound.protection.outlook.com [40.107.94.76]) by mails.dpdk.org (Postfix) with ESMTP id 9F9B842E7C for ; Tue, 29 Oct 2024 15:32:16 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=k41CvWYeAg25ucruJfa0Lm+Q13TtfzO+fcQA9hCKJJQ3QiviQR6hU8ROwCBiLPMYuZYdcqbcaTRWx6E+eO3sCx/7XxtZWwniqJr/hfmGAq/zGTl0mzoqWTtAK1ctv9L/WmNhR8B34CbyRTBao1VL2dUkWtKFb+nhe/t7bt92MsdW6fik2Yc78mOiNwUq7PCwg7iLKiKY82YbfTWpUM8CIkHDThd+i0AZ2ndYVMAL27RjAHABHSxNMx1KQTRSiOAinvHNk1UVWh6EJdauAvLbMFjnRxkdqAO/he3jQPYzC16EioITshgKpcxM0UkLzLxEvQCrl01TSN2jyc3g3rOglg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rlOLpdyx96/VMyaycft1HiV3xVANSLHGFfefQuleZg8=; b=B1+ejhdV++Wd3c1Lp3ZlCZzUFL3Y7r/D+xmYn4DT3uyx3jEMfiqn8rRyblnL5mLgXKlXz82TuQLY46/17PDTkDksarRXmjNjCSkbUG9YcIowDlnPD8k2TG5lmafZir5uN2Z1xhKlFTBlai1khZpjPPW0fk1WAkVNlyeA2z00tj9QBq6/O0Cuxqp1OajnTBLvN0bniGN7JowNYf0C1de4Z04u8F9TXVd95D/GrcCuYzui1AE0wxyzL0ICt3CWJUEqkMZ6mEqjTc05ROjEkTJzz2hiHxNyva4QEoepXmzdV48NofGdJUGTezkmEFPcIj/rIXK6CAZfv20R7ctuWHydYg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rlOLpdyx96/VMyaycft1HiV3xVANSLHGFfefQuleZg8=; b=ZehC+xml7yyuNCUBVMbaeSmL74crxKSaJKhXafct3cxKL3ivh/vtERCgNCSB7mGLqmGUIoohauy8ttzGHdkjRzHRbPQwpameePIJTUOAEAhYSfwgFL9N7xUe4oCPLY6QF0yHcwUPZ9yQnVHz4vuhTjJe7b0vEq48WbkV/wko2glxj+2AwMuppNQxxfvMeuBlQUNKNYuilFSbCpPUy0o6tfBK1yGLQmC5JPoZ1deHpdKK0FK6AmNMU/6YbDSaUADU5srH9dv9/ZY/TS9o0Ora+fSh2BMoUeCAbpm7Ypup5G2dJXklLXkkQwwlRL2pBhskwqW4Nposl1AQGR6hOS6DNQ== Received: from CH2PR17CA0004.namprd17.prod.outlook.com (2603:10b6:610:53::14) by CH3PR12MB7618.namprd12.prod.outlook.com (2603:10b6:610:14c::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.24; Tue, 29 Oct 2024 14:32:11 +0000 Received: from CH2PEPF00000148.namprd02.prod.outlook.com (2603:10b6:610:53:cafe::de) by CH2PR17CA0004.outlook.office365.com (2603:10b6:610:53::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.26 via Frontend Transport; Tue, 29 Oct 2024 14:32:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CH2PEPF00000148.mail.protection.outlook.com (10.167.244.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.16 via Frontend Transport; Tue, 29 Oct 2024 14:32:10 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:39 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:36 -0700 From: "Minggang Li(Gavin)" To: , , , , Dariusz Sosnowski , Bing Zhao , Suanming Mou CC: , , Rongwei Liu Subject: [PATCH V3 2/7] net/mlx5: optimize device probing Date: Tue, 29 Oct 2024 16:31:13 +0200 Message-ID: <20241029143118.875214-3-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029143118.875214-1-gavinl@nvidia.com> References: <20241029134256.874767-8-gavinl@nvidia.com> <20241029143118.875214-1-gavinl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000148:EE_|CH3PR12MB7618:EE_ X-MS-Office365-Filtering-Correlation-Id: 3168ab0d-1648-4ba3-ae2e-08dcf8267961 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|82310400026|4022899009|1800799024; X-Microsoft-Antispam-Message-Info: oai9k7itKNa8Pw+gnFKZNQN/+66hXzWJUMzYJm7dg1MdDL1dhU+JPMHVf/jfRv64hF9y7kvi2yZolBSx0K9hUR88/Jc6pAfl49tsRUJIvsCkYyNSU3+gREWXGrNYIV/+BfAEFhhzBTwnZcUxvoDEE+eYtQsDH3iByI2MhGXy2spM5ABKoI9oJewJX6BLcon30CrTMFERpM0CTakcPWlUEpzjTLuO4spkAsbMPAFBOJB0vEJ/t5plfXUCOXTwukLpmRB1qidut6eryx5kCHRpGUKAKr8uWPVhwDv5UJmk/iw+cwJ5fhT9rJfwhTmn+SOqdRO5VqXJwvOpboRV+2B1RbYdJKxYysKmA29neOZhRYam6BAdlyzGkEUG0wtBOrM5LnMsF6jNcLpCDV8xR2YMJE0UZV2VlQ0y9ftwj7TKVe4ScTQo10oWy36ELh1RXI/lCLwIgp7266BTAU3rlg2B/YZUhsnEQFWGsFVIpobTBtVVNFyd3XOlf4sZ1FIK0gHFrlBz1GEbTuG2hFkfrGAhoJsmzRCz0rhfIL9USZ3108aFcN9ibQ39Ob/02zOlClHf8+/hwEMdivhZMDjK+nbWG8T4trJYQQ6FsW3LVpgklNvOlJGAYnlbbAeLwOJt59M5O+jorDphFbCYTURP6pQeaikAb9vqA06Y0OjZ9JXIUCCxzxNGg3ZxYKcFV4XcDFKFoCRP4RvuAc8ucOlkKg9EyX+opjCIteoP+c44NbJea9V1lfqEY0MeycsJpnrdn3PWke2SPmuhCG24Ik15oeWCvF+q+ZO1lZHFkD8u5kF4wBKS0x3yrS1H81cXErzDZ03LVcxlLnChzXyGkqFoo0K+x/CDvC/1Lbzfk1ILVnMT2dwXeWhrdUgyCfjmMR11uUmecwnZcnKdpEssjjTX+WhbidbEuBx59gh3UjTh1gSSQcGczEjAIvh9RPWLcBoMLz1oTpGOsSkr6UtXTFnC7zlc1rCk1vEnvr5nLc+d1AbZK1SE/TfaM5JXXUtqzBDMAyzphDpodfzj2Cr239Tky90HtCX7dRKrnT7BhidsJxSmv4PHzdPsxKPBCDP19oRhOgKNqHJlDHKEn9dHW+cQzNpGqZtFneAMajgFtGFE6FPPbMqNgudxjVAktvQymf6vlnoIP1HdNphdjV3xzPWV3PwsUsL91rtkvloC6NIwxbyT6Fzhl8hKha4NiuNlm+K/KJDD0uvuciR1e7WjrCltBuFHecLjJb0TLebga3vdFGarAVQrgPRdzsLP9NOZwh1INxOflRRWFczJgINSApTUOu2+26eNQ893aqMrIqemWqe/qmVRHPQqBxARoaXDoo3jTtKRFWDr6WAJOCmBibomQexkObu4CQKCySdqJer2ecMVU06diN4HjFAIDn1herMs0aSslgt7zTuuRbAWruuoyQEmbw== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(4022899009)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2024 14:32:10.6939 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3168ab0d-1648-4ba3-ae2e-08dcf8267961 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000148.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7618 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rongwei Liu Current DPDK probing logic is: 1. Query IB device index and total port number. 2. Query each port information by traversing the port index and get the port's ifindex, name and state information etc. 3. Compare the information with devargs until getting matched. 4. For each probing device, repeat steps 2 and 3. Step 2 will communicate with kernel via netlink and it's time-consuming. There is no need to repeat netlink communication for each probing device, PMD can traverse all ports once and save the information into a caching structure. Introduce the device information caching in the mlx5 common device handle and cache the port number, ibindex, port ifindex. For dynamic interface changing: 1. New VF by toggling switchdev mode should restart dpdk as sriov configuration changed. 2. Changing VF number w/o toggling switchdev mode will trigger RTM_DELLINK and RTM_NEWLINK events. All the caching information is cleared. 3. New SF triggers RTM_NEWLINK event and no port index information in the message. All free entries (ifindex = 0) in the cache are invalidated. 4. Delete SF triggers RTM_DELLINK event. Traverse the cache entries and invalidate the one with the same ifindex. Didn't consider race-condition between probing thread and interrupt thread. Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/linux/mlx5_common_os.h | 6 ++ drivers/common/mlx5/linux/mlx5_nl.c | 94 +++++++++++++---- drivers/common/mlx5/linux/mlx5_nl.h | 8 +- drivers/common/mlx5/mlx5_common.c | 5 + drivers/common/mlx5/mlx5_common.h | 13 +++ drivers/common/mlx5/windows/mlx5_common_os.h | 5 + drivers/net/mlx5/linux/mlx5_ethdev_os.c | 54 ++++++++++ drivers/net/mlx5/linux/mlx5_os.c | 104 ++++++++++++++----- drivers/net/mlx5/linux/mlx5_os.h | 6 -- drivers/net/mlx5/windows/mlx5_os.h | 5 - 10 files changed, 242 insertions(+), 58 deletions(-) diff --git a/drivers/common/mlx5/linux/mlx5_common_os.h b/drivers/common/mlx5/linux/mlx5_common_os.h index e8aa1d46ec..2e2c54f1fa 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.h +++ b/drivers/common/mlx5/linux/mlx5_common_os.h @@ -22,6 +22,12 @@ #include "mlx5_glue.h" #include "mlx5_malloc.h" +/* verb enumerations translations to local enums. */ +enum { + MLX5_FS_NAME_MAX = IBV_SYSFS_NAME_MAX + 1, + MLX5_FS_PATH_MAX = IBV_SYSFS_PATH_MAX + 1 +}; + /** * Get device name. Given an ibv_device pointer - return a * pointer to the corresponding device name. diff --git a/drivers/common/mlx5/linux/mlx5_nl.c b/drivers/common/mlx5/linux/mlx5_nl.c index a5ac4dc543..e98073aafe 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.c +++ b/drivers/common/mlx5/linux/mlx5_nl.c @@ -1073,16 +1073,18 @@ mlx5_nl_port_info(int nl, uint32_t pindex, struct mlx5_nl_port_info *data) uint32_t sn = MLX5_NL_SN_GENERATE; int ret; - ret = mlx5_nl_send(nl, &req.nh, sn); - if (ret < 0) - return ret; - ret = mlx5_nl_recv(nl, sn, mlx5_nl_cmdget_cb, data); - if (ret < 0) - return ret; - if (!(data->flags & MLX5_NL_CMD_GET_IB_NAME) || - !(data->flags & MLX5_NL_CMD_GET_IB_INDEX)) - goto error; - data->flags = 0; + if (data->ibindex == UINT32_MAX) { + ret = mlx5_nl_send(nl, &req.nh, sn); + if (ret < 0) + return ret; + ret = mlx5_nl_recv(nl, sn, mlx5_nl_cmdget_cb, data); + if (ret < 0) + return ret; + if (!(data->flags & MLX5_NL_CMD_GET_IB_NAME) || + !(data->flags & MLX5_NL_CMD_GET_IB_INDEX)) + goto error; + data->flags = 0; + } sn = MLX5_NL_SN_GENERATE; req.nh.nlmsg_type = RDMA_NL_GET_TYPE(RDMA_NL_NLDEV, RDMA_NLDEV_CMD_PORT_GET); @@ -1109,7 +1111,7 @@ mlx5_nl_port_info(int nl, uint32_t pindex, struct mlx5_nl_port_info *data) !(data->flags & MLX5_NL_CMD_GET_NET_INDEX) || !data->ifindex) goto error; - return 1; + return 0; error: rte_errno = ENODEV; return -rte_errno; @@ -1128,21 +1130,48 @@ mlx5_nl_port_info(int nl, uint32_t pindex, struct mlx5_nl_port_info *data) * IB device name. * @param[in] pindex * IB device port index, starting from 1 + * @param[in] dev_info + * Cached mlx5 device information. * @return * A valid (nonzero) interface index on success, 0 otherwise and rte_errno * is set. */ unsigned int -mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex) +mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex, struct mlx5_dev_info *dev_info) { + int ret; + struct mlx5_nl_port_info data = { .ifindex = 0, .name = name, + .ibindex = UINT32_MAX, + .flags = 0, }; - if (mlx5_nl_port_info(nl, pindex, &data) < 0) - return 0; - return data.ifindex; + if (!strcmp(name, dev_info->ibname)) { + if (dev_info->port_info && pindex <= dev_info->port_num && + dev_info->port_info[pindex].valid) { + if (!dev_info->port_info[pindex].ifindex) + rte_errno = ENODEV; + return dev_info->port_info[pindex].ifindex; + } + if (dev_info->port_num) + data.ibindex = dev_info->ibindex; + } + + ret = mlx5_nl_port_info(nl, pindex, &data); + + if (!strcmp(dev_info->ibname, name)) { + if ((!ret || ret == -ENODEV) && dev_info->port_info && + pindex <= dev_info->port_num) { + if (!ret) + dev_info->port_info[pindex].ifindex = data.ifindex; + /* -ENODEV means the pindex is unused but still valid case */ + dev_info->port_info[pindex].valid = 1; + } + } + + return ret ? 0 : data.ifindex; } /** @@ -1157,18 +1186,23 @@ mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex) * IB device name. * @param[in] pindex * IB device port index, starting from 1 + * @param[in] dev_info + * Cached mlx5 device information. * @return * Port state (ibv_port_state) on success, negative on error * and rte_errno is set. */ int -mlx5_nl_port_state(int nl, const char *name, uint32_t pindex) +mlx5_nl_port_state(int nl, const char *name, uint32_t pindex, struct mlx5_dev_info *dev_info) { struct mlx5_nl_port_info data = { .state = 0, .name = name, + .ibindex = UINT32_MAX, }; + if (dev_info && !strcmp(name, dev_info->ibname) && dev_info->port_num) + data.ibindex = dev_info->ibindex; if (mlx5_nl_port_info(nl, pindex, &data) < 0) return -rte_errno; if ((data.flags & MLX5_NL_CMD_GET_PORT_STATE) == 0) { @@ -1185,13 +1219,15 @@ mlx5_nl_port_state(int nl, const char *name, uint32_t pindex) * Netlink socket of the RDMA kind (NETLINK_RDMA). * @param[in] name * IB device name. + * @param[in] dev_info + * Cached mlx5 device info. * * @return * A valid (nonzero) number of ports on success, 0 otherwise * and rte_errno is set. */ unsigned int -mlx5_nl_portnum(int nl, const char *name) +mlx5_nl_portnum(int nl, const char *name, struct mlx5_dev_info *dev_info) { struct mlx5_nl_port_info data = { .flags = 0, @@ -1206,7 +1242,10 @@ mlx5_nl_portnum(int nl, const char *name) .nlmsg_flags = NLM_F_REQUEST | NLM_F_ACK | NLM_F_DUMP, }; uint32_t sn = MLX5_NL_SN_GENERATE; - int ret; + int ret, size; + + if (dev_info->port_num && !strcmp(name, dev_info->ibname)) + return dev_info->port_num; ret = mlx5_nl_send(nl, &req, sn); if (ret < 0) @@ -1220,8 +1259,25 @@ mlx5_nl_portnum(int nl, const char *name) rte_errno = ENODEV; return 0; } - if (!data.portnum) + if (!data.portnum) { rte_errno = EINVAL; + return 0; + } + MLX5_ASSERT(!strlen(dev_info->ibname)); + dev_info->port_num = data.portnum; + dev_info->ibindex = data.ibindex; + snprintf(dev_info->ibname, MLX5_FS_NAME_MAX, "%s", name); + if (data.portnum > 1) { + size = (data.portnum + 1) * sizeof(struct mlx5_port_nl_info); + dev_info->port_info = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, size, + RTE_CACHE_LINE_SIZE, + SOCKET_ID_ANY); + if (dev_info->port_info == NULL) { + memset(dev_info, 0, sizeof(*dev_info)); + rte_errno = ENOMEM; + return 0; + } + } return data.portnum; } diff --git a/drivers/common/mlx5/linux/mlx5_nl.h b/drivers/common/mlx5/linux/mlx5_nl.h index 580de3b769..396ffc98ce 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.h +++ b/drivers/common/mlx5/linux/mlx5_nl.h @@ -11,6 +11,7 @@ #include #include "mlx5_common.h" +#include "mlx5_common_utils.h" typedef void (mlx5_nl_event_cb)(struct nlmsghdr *hdr, void *user_data); @@ -52,11 +53,12 @@ int mlx5_nl_promisc(int nlsk_fd, unsigned int iface_idx, int enable); __rte_internal int mlx5_nl_allmulti(int nlsk_fd, unsigned int iface_idx, int enable); __rte_internal -unsigned int mlx5_nl_portnum(int nl, const char *name); +unsigned int mlx5_nl_portnum(int nl, const char *name, struct mlx5_dev_info *dev_info); __rte_internal -unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex); +unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex, + struct mlx5_dev_info *info); __rte_internal -int mlx5_nl_port_state(int nl, const char *name, uint32_t pindex); +int mlx5_nl_port_state(int nl, const char *name, uint32_t pindex, struct mlx5_dev_info *dev_info); __rte_internal int mlx5_nl_vf_mac_addr_modify(int nlsk_fd, unsigned int iface_idx, struct rte_ether_addr *mac, int vf_index); diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c index ca8543e36e..0aaae91c31 100644 --- a/drivers/common/mlx5/mlx5_common.c +++ b/drivers/common/mlx5/mlx5_common.c @@ -735,6 +735,11 @@ mlx5_common_dev_release(struct mlx5_common_device *cdev) if (TAILQ_EMPTY(&devices_list)) rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", NULL); + if (cdev->dev_info.port_info != NULL) { + mlx5_free(cdev->dev_info.port_info); + cdev->dev_info.port_info = NULL; + } + cdev->dev_info.port_num = 0; mlx5_dev_mempool_unsubscribe(cdev); mlx5_mr_release_cache(&cdev->mr_scache); mlx5_dev_hw_global_release(cdev); diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index 1abd1e8239..6cb40f54dd 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -174,6 +174,18 @@ enum mlx5_nl_phys_port_name_type { MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ }; +struct mlx5_port_nl_info { + uint32_t ifindex; + uint8_t valid; +}; + +struct mlx5_dev_info { + uint32_t port_num; + uint32_t ibindex; + char ibname[MLX5_FS_NAME_MAX]; + struct mlx5_port_nl_info *port_info; +}; + /** Switch information returned by mlx5_nl_switch_info(). */ struct mlx5_switch_info { uint32_t master:1; /**< Master device. */ @@ -525,6 +537,7 @@ struct mlx5_common_device { uint32_t classes_loaded; void *ctx; /* Verbs/DV/DevX context. */ void *pd; /* Protection Domain. */ + struct mlx5_dev_info dev_info; /* Device port info queried via netlink. */ uint32_t pdn; /* Protection Domain Number. */ struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ struct mlx5_common_dev_config config; /* Device configuration. */ diff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h index acee0c987f..65394035de 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.h +++ b/drivers/common/mlx5/windows/mlx5_common_os.h @@ -20,6 +20,11 @@ #define MLX5_BF_OFFSET 0x800 +enum { + MLX5_FS_NAME_MAX = MLX5_DEVX_DEVICE_NAME_SIZE + 1, + MLX5_FS_PATH_MAX = MLX5_DEVX_DEVICE_PNP_SIZE + 1 +}; + /** * This API allocates aligned or non-aligned memory. The free can be on either * aligned or nonaligned memory. To be protected - even though there may be no diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 5d64984022..08ac6dd939 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -673,6 +674,57 @@ mlx5_link_update_bond(struct rte_eth_dev *dev) ((ifr.ifr_flags & IFF_UP) && (ifr.ifr_flags & IFF_RUNNING)); } +static void +mlx5_handle_port_info_update(struct mlx5_dev_info *dev_info, uint32_t if_index, + uint16_t msg_type) +{ + struct mlx5_switch_info info = { + .master = 0, + .representor = 0, + .name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET, + .port_name = 0, + .switch_id = 0, + }; + uint32_t i; + int nl_route; + + if (dev_info->port_num <= 1 || dev_info->port_info == NULL) + return; + + for (i = 1; i <= dev_info->port_num; i++) { + if (!dev_info->port_info[i].valid) + continue; + if (dev_info->port_info[i].ifindex == if_index) + break; + } + if (msg_type == RTM_NEWLINK && i > dev_info->port_num) { + nl_route = mlx5_nl_init(NETLINK_ROUTE, 0); + if (nl_route < 0) + goto flush_all; + + if (mlx5_nl_switch_info(nl_route, if_index, &info)) { + if (mlx5_sysfs_switch_info(if_index, &info)) + goto flush_all; + } + + if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_PFSF || + info.name_type == MLX5_PHYS_PORT_NAME_TYPE_PFVF) + goto flush_all; + close(nl_route); + } else if (msg_type == RTM_DELLINK && i <= dev_info->port_num) { + memset(dev_info->port_info + i, 0, sizeof(struct mlx5_port_nl_info)); + } + + return; +flush_all: + if (nl_route >= 0) + close(nl_route); + for (i = 1; i <= dev_info->port_num; i++) { + if (!dev_info->port_info[i].ifindex) + dev_info->port_info[i].valid = 0; + } +} + static void mlx5_dev_interrupt_nl_cb(struct nlmsghdr *hdr, void *cb_arg) { @@ -682,6 +734,8 @@ mlx5_dev_interrupt_nl_cb(struct nlmsghdr *hdr, void *cb_arg) if (mlx5_nl_parse_link_status_update(hdr, &if_index) < 0) return; + mlx5_handle_port_info_update(&sh->cdev->dev_info, if_index, hdr->nlmsg_type); + for (i = 0; i < sh->max_port; i++) { struct mlx5_dev_shared_port *port = &sh->port[i]; struct rte_eth_dev *dev; diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 69a80b9ddc..8f6e584154 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1268,7 +1268,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, /* IB doesn't allow more than 255 ports, must be Ethernet. */ err = mlx5_nl_port_state(nl_rdma, spawn->phys_dev_name, - spawn->phys_port); + spawn->phys_port, &spawn->cdev->dev_info); if (err < 0) { DRV_LOG(INFO, "Failed to get netlink port state: %s", strerror(rte_errno)); @@ -1897,6 +1897,8 @@ mlx5_dev_spawn_data_cmp(const void *a, const void *b) * Netlink RDMA group socket handle. * @param[in] owner * Representor owner PF index. + * @param[in] dev_info + * Cached mlx5 device information. * @param[out] bond_info * Pointer to bonding information. * @@ -1908,6 +1910,7 @@ static int mlx5_device_bond_pci_match(const char *ibdev_name, const struct rte_pci_addr *pci_dev, int nl_rdma, uint16_t owner, + struct mlx5_dev_info *dev_info, struct mlx5_bond_info *bond_info) { char ifname[IF_NAMESIZE + 1]; @@ -1928,7 +1931,7 @@ mlx5_device_bond_pci_match(const char *ibdev_name, return -1; if (!strstr(ibdev_name, "bond")) return -1; - np = mlx5_nl_portnum(nl_rdma, ibdev_name); + np = mlx5_nl_portnum(nl_rdma, ibdev_name, dev_info); if (!np) return -1; if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0) @@ -1940,7 +1943,7 @@ mlx5_device_bond_pci_match(const char *ibdev_name, */ for (i = 1; i <= np; ++i) { /* Check whether Infiniband port is populated. */ - ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i); + ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i, dev_info); if (!ifindex) continue; if (!if_indextoname(ifindex, ifname)) @@ -1978,9 +1981,13 @@ mlx5_device_bond_pci_match(const char *ibdev_name, if (!file) break; info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; - if (fscanf(file, "%32s", tmp_str) == 1) + if (fscanf(file, "%32s", tmp_str) == 1) { mlx5_translate_port_name(tmp_str, &info); - fclose(file); + fclose(file); + } else { + fclose(file); + break; + } /* Only process PF ports. */ if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) @@ -2003,8 +2010,8 @@ mlx5_device_bond_pci_match(const char *ibdev_name, if (ret != 1) break; /* Save bonding info. */ - strncpy(bond_info->ports[info.port_name].ifname, ifname, - sizeof(bond_info->ports[0].ifname)); + snprintf(bond_info->ports[info.port_name].ifname, + sizeof(bond_info->ports[0].ifname), "%s", ifname); bond_info->ports[info.port_name].pci_addr = pci_addr; bond_info->ports[info.port_name].ifindex = ifindex; bond_info->n_port++; @@ -2033,6 +2040,7 @@ mlx5_device_bond_pci_match(const char *ibdev_name, pci_addr.function == owner))) pf = info.port_name; } + fclose(bond_file); if (pf >= 0) { /* Get bond interface info */ ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, @@ -2084,7 +2092,8 @@ mlx5_nl_esw_multiport_get(struct rte_pci_addr *pci_addr, int *enabled) #define SYSFS_MPESW_PARAM_MAX_LEN 16 static int -mlx5_sysfs_esw_multiport_get(struct ibv_device *ibv, struct rte_pci_addr *pci_addr, int *enabled) +mlx5_sysfs_esw_multiport_get(struct ibv_device *ibv, struct rte_pci_addr *pci_addr, int *enabled, + struct mlx5_dev_info *dev_info) { int nl_rdma; unsigned int n_ports; @@ -2096,7 +2105,7 @@ mlx5_sysfs_esw_multiport_get(struct ibv_device *ibv, struct rte_pci_addr *pci_ad nl_rdma = mlx5_nl_init(NETLINK_RDMA, 0); if (nl_rdma < 0) return nl_rdma; - n_ports = mlx5_nl_portnum(nl_rdma, ibv->name); + n_ports = mlx5_nl_portnum(nl_rdma, ibv->name, dev_info); if (!n_ports) { ret = -rte_errno; goto close_nl_rdma; @@ -2104,12 +2113,12 @@ mlx5_sysfs_esw_multiport_get(struct ibv_device *ibv, struct rte_pci_addr *pci_ad for (i = 1; i <= n_ports; ++i) { unsigned int ifindex; char ifname[IF_NAMESIZE + 1]; - struct rte_pci_addr if_pci_addr; + struct rte_pci_addr if_pci_addr = { 0 }; char mpesw[SYSFS_MPESW_PARAM_MAX_LEN + 1]; FILE *sysfs; int n; - ifindex = mlx5_nl_ifindex(nl_rdma, ibv->name, i); + ifindex = mlx5_nl_ifindex(nl_rdma, ibv->name, i, dev_info); if (!ifindex) continue; if (!if_indextoname(ifindex, ifname)) @@ -2151,7 +2160,8 @@ mlx5_sysfs_esw_multiport_get(struct ibv_device *ibv, struct rte_pci_addr *pci_ad } static int -mlx5_is_mpesw_enabled(struct ibv_device *ibv, struct rte_pci_addr *ibv_pci_addr, int *enabled) +mlx5_is_mpesw_enabled(struct ibv_device *ibv, struct rte_pci_addr *ibv_pci_addr, int *enabled, + struct mlx5_dev_info *dev_info) { /* * Try getting Multiport E-Switch state through netlink interface @@ -2159,7 +2169,7 @@ mlx5_is_mpesw_enabled(struct ibv_device *ibv, struct rte_pci_addr *ibv_pci_addr, * assume that Multiport E-Switch is disabled and return an error. */ if (mlx5_nl_esw_multiport_get(ibv_pci_addr, enabled) >= 0 || - mlx5_sysfs_esw_multiport_get(ibv, ibv_pci_addr, enabled) >= 0) + mlx5_sysfs_esw_multiport_get(ibv, ibv_pci_addr, enabled, dev_info) >= 0) return 0; DRV_LOG(DEBUG, "Unable to check MPESW state for IB device %s " "(PCI: " PCI_PRI_FMT ")", @@ -2173,7 +2183,7 @@ mlx5_is_mpesw_enabled(struct ibv_device *ibv, struct rte_pci_addr *ibv_pci_addr, static int mlx5_device_mpesw_pci_match(struct ibv_device *ibv, const struct rte_pci_addr *owner_pci, - int nl_rdma) + int nl_rdma, struct mlx5_dev_info *dev_info) { struct rte_pci_addr ibdev_pci_addr = { 0 }; char ifname[IF_NAMESIZE + 1] = { 0 }; @@ -2197,24 +2207,24 @@ mlx5_device_mpesw_pci_match(struct ibv_device *ibv, return -1; } /* Check if IB device has MPESW enabled. */ - if (mlx5_is_mpesw_enabled(ibv, &ibdev_pci_addr, &enabled)) + if (mlx5_is_mpesw_enabled(ibv, &ibdev_pci_addr, &enabled, dev_info)) return -1; if (!enabled) return -1; /* Iterate through IB ports to find MPESW master uplink port. */ if (nl_rdma < 0) return -1; - np = mlx5_nl_portnum(nl_rdma, ibv->name); + np = mlx5_nl_portnum(nl_rdma, ibv->name, dev_info); if (!np) return -1; for (i = 1; i <= np; ++i) { - struct rte_pci_addr pci_addr; + struct rte_pci_addr pci_addr = { 0 }; FILE *file; char port_name[IF_NAMESIZE + 1]; struct mlx5_switch_info info; /* Check whether IB port has a corresponding netdev. */ - ifindex = mlx5_nl_ifindex(nl_rdma, ibv->name, i); + ifindex = mlx5_nl_ifindex(nl_rdma, ibv->name, i, dev_info); if (!ifindex) continue; if (!if_indextoname(ifindex, ifname)) @@ -2321,16 +2331,30 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, * matching ones, gathering into the list. */ struct ibv_device *ibv_match[ret + 1]; + struct mlx5_dev_info *info, tmp_info[ret]; int nl_route = mlx5_nl_init(NETLINK_ROUTE, 0); int nl_rdma = mlx5_nl_init(NETLINK_RDMA, 0); unsigned int i; + memset(tmp_info, 0, sizeof(tmp_info)); while (ret-- > 0) { struct rte_pci_addr pci_addr; + if (cdev->dev_info.port_num) { + if (strcmp(ibv_list[ret]->name, cdev->dev_info.ibname)) { + DRV_LOG(INFO, "Unmatched caching device \"%s\" \"%s\"", + cdev->dev_info.ibname, ibv_list[ret]->name); + continue; + } + info = &cdev->dev_info; + } else { + info = &tmp_info[ret]; + } DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name); bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci, - nl_rdma, owner_id, &bond_info); + nl_rdma, owner_id, + info, + &bond_info); if (bd >= 0) { /* * Bonding device detected. Only one match is allowed, @@ -2356,7 +2380,8 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, ibv_match[nd++] = ibv_list[ret]; break; } - mpesw = mlx5_device_mpesw_pci_match(ibv_list[ret], &owner_pci, nl_rdma); + mpesw = mlx5_device_mpesw_pci_match(ibv_list[ret], &owner_pci, nl_rdma, + info); if (mpesw >= 0) { /* * MPESW device detected. Only one matching IB device is allowed, @@ -2380,10 +2405,18 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, } /* Bonding or MPESW device was not found. */ if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, - &pci_addr)) + &pci_addr)) { + if (tmp_info[ret].port_info != NULL) + mlx5_free(tmp_info[ret].port_info); + memset(&tmp_info[ret], 0, sizeof(tmp_info[0])); continue; - if (rte_pci_addr_cmp(&owner_pci, &pci_addr) != 0) + } + if (rte_pci_addr_cmp(&owner_pci, &pci_addr) != 0) { + if (tmp_info[ret].port_info != NULL) + mlx5_free(tmp_info[ret].port_info); + memset(&tmp_info[ret], 0, sizeof(tmp_info[0])); continue; + } DRV_LOG(INFO, "PCI information matches for device \"%s\"", ibv_list[ret]->name); ibv_match[nd++] = ibv_list[ret]; @@ -2401,13 +2434,21 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, goto exit; } if (nd == 1) { + if (!cdev->dev_info.port_num) { + for (i = 0; i < RTE_DIM(tmp_info); i++) { + if (tmp_info[i].port_num) { + cdev->dev_info = tmp_info[i]; + break; + } + } + } /* * Found single matching device may have multiple ports. * Each port may be representor, we have to check the port * number and check the representors existence. */ if (nl_rdma >= 0) - np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); + np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name, &cdev->dev_info); if (!np) DRV_LOG(WARNING, "Cannot get IB device \"%s\" ports number.", @@ -2424,6 +2465,14 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, ret = -rte_errno; goto exit; } + } else { + /* Can't handle one common device with multiple IB devices caching */ + for (i = 0; i < RTE_DIM(tmp_info); i++) { + if (tmp_info[i].port_info != NULL) + mlx5_free(tmp_info[i].port_info); + memset(&tmp_info[i], 0, sizeof(tmp_info[0])); + } + DRV_LOG(INFO, "Cannot handle multiple IB devices info caching in single common device."); } /* Now we can determine the maximal amount of devices to be spawned. */ list = mlx5_malloc(MLX5_MEM_ZERO, @@ -2457,7 +2506,7 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, list[ns].mpesw_port = MLX5_MPESW_PORT_INVALID; list[ns].ifindex = mlx5_nl_ifindex(nl_rdma, ibv_match[0]->name, - i); + i, &cdev->dev_info); if (!list[ns].ifindex) { /* * No network interface index found for the @@ -2588,7 +2637,7 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, list[ns].ifindex = mlx5_nl_ifindex (nl_rdma, ibv_match[i]->name, - 1); + 1, &cdev->dev_info); if (!list[ns].ifindex) { char ifname[IF_NAMESIZE]; @@ -2777,6 +2826,11 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, mlx5_free(list); MLX5_ASSERT(ibv_list); mlx5_glue->free_device_list(ibv_list); + if (ret) { + if (cdev->dev_info.port_info != NULL) + mlx5_free(cdev->dev_info.port_info); + memset(&cdev->dev_info, 0, sizeof(cdev->dev_info)); + } return ret; } diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h index 80c70d713a..4ef0916173 100644 --- a/drivers/net/mlx5/linux/mlx5_os.h +++ b/drivers/net/mlx5/linux/mlx5_os.h @@ -8,12 +8,6 @@ #include -/* verb enumerations translations to local enums. */ -enum { - MLX5_FS_NAME_MAX = IBV_SYSFS_NAME_MAX + 1, - MLX5_FS_PATH_MAX = IBV_SYSFS_PATH_MAX + 1 -}; - /* Maximal data of sendmsg message(in bytes). */ #define MLX5_SENDMSG_MAX 64 diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h index 8b58265687..fb7198c244 100644 --- a/drivers/net/mlx5/windows/mlx5_os.h +++ b/drivers/net/mlx5/windows/mlx5_os.h @@ -7,11 +7,6 @@ #include "mlx5_win_ext.h" -enum { - MLX5_FS_NAME_MAX = MLX5_DEVX_DEVICE_NAME_SIZE + 1, - MLX5_FS_PATH_MAX = MLX5_DEVX_DEVICE_PNP_SIZE + 1 -}; - #define PCI_DRV_FLAGS 0 #define MLX5_NAMESIZE MLX5_FS_NAME_MAX From patchwork Tue Oct 29 14:31:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Minggang(Gavin) Li" X-Patchwork-Id: 147600 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3F8F245B4C; Tue, 29 Oct 2024 15:32:39 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0939F42E87; Tue, 29 Oct 2024 15:32:31 +0100 (CET) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2064.outbound.protection.outlook.com [40.107.244.64]) by mails.dpdk.org (Postfix) with ESMTP id D28A542E98 for ; Tue, 29 Oct 2024 15:32:19 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CAgml57BECvbuyLsDp31Fkm9UGmJALR/+4F5my114WFCwYQrQIR9PjAv6RhqSbFzHJi5vClivgEqpm2uzdVYmQpmRUDX+mceprngLxuOv+PhAjz5ivxVU2Ei6yxS4MzE9nYaxKQBaMIW7hQdWsrlPWLiluX4Rt9OzCweBEg48DvvfsjvuScMGDu1zbVEwcbgMPgF7dkDAzvD+8CAOOjJ/+94Rs9htnzRhg5RxZH7XsymS+EL+WHNLHUacChsmI9V7t0mEDjhCM/UEsUcjoGFx3SQJFXoeJOJJ4p2XoMC0aTaq+oJ5HTy5b5NqJxwTdrjtl+sRobwZZW3a+6FnHPuig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=49O9zv8g7dvC9BXMRP5lRvb/M+RuAlYm6A58LttWoJw=; b=NmmGSRmppo+iVHLCv2Q2LSLjiF5EMyx+0lRshcpSxxeMOC36/q4BrGBEv5SwIkm0/QkcU/oFa0JTdlHySGKcMTrroqhMX4mkTVAWZsu2GRB0VgP7GQBXcH0JyhjFaWFEBAZEpYDsBujHBIfX7O5u8KdBCY2S690WzG9S+LDfQqTh3EmiKNLmK2rIqE1sXM9YS/q2MpUq5H6JQR1HqqFPU1Js5jmYfSeNts/cH0ytJevqRuq7iT495amnt+EdBLj7HMW+ZJAAtePYA4Hnp/KQPFWXXmM8GqIXlNYSRLoS8CAwA5ZmCuGTFNQcdvNrdpC+ZF7g0A/6DexhvYou1lA1sw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=49O9zv8g7dvC9BXMRP5lRvb/M+RuAlYm6A58LttWoJw=; b=QBW3Mjw6ar1UGriq11AYOnJYrnExKwWs4Fv8FEXm7vqglbUVgjJ1QJml7pZsA804dLtSJE8b9LZZH+KKtt3RWGyP+SkePDOFMmziTNot35DQaM3jYCtogRq6W3qNswWwj7gUKMiXXq1XTIH5M9gt+g0DjL96/ndsQfoolo4L/3u3fzmpotGjBAyHYTRbGneqI68VQ7RkEUyNXGemrW5B5wRXWr7FMH6rBhdhwOhsh7+0geyJ0kdGM6ZXiDyi7higMFFspLniJ6YlNyQ2f3fXN6m3BvkZhn8cw9L3vWQnNZ1kF++7bzBOCVbTzIXoRFtfO+fw4QGNqIrOM6cCZSZthg== Received: from CH2PR15CA0015.namprd15.prod.outlook.com (2603:10b6:610:51::25) by PH8PR12MB6987.namprd12.prod.outlook.com (2603:10b6:510:1be::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.24; Tue, 29 Oct 2024 14:32:14 +0000 Received: from CH2PEPF00000144.namprd02.prod.outlook.com (2603:10b6:610:51:cafe::ec) by CH2PR15CA0015.outlook.office365.com (2603:10b6:610:51::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.25 via Frontend Transport; Tue, 29 Oct 2024 14:32:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CH2PEPF00000144.mail.protection.outlook.com (10.167.244.101) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.16 via Frontend Transport; Tue, 29 Oct 2024 14:32:12 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:43 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:39 -0700 From: "Minggang Li(Gavin)" To: , , , , Dariusz Sosnowski , Bing Zhao , Suanming Mou CC: , , Rongwei Liu Subject: [PATCH V3 3/7] net/mlx5: add new devargs to control probe optimization Date: Tue, 29 Oct 2024 16:31:14 +0200 Message-ID: <20241029143118.875214-4-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029143118.875214-1-gavinl@nvidia.com> References: <20241029134256.874767-8-gavinl@nvidia.com> <20241029143118.875214-1-gavinl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000144:EE_|PH8PR12MB6987:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d963e49-a84f-4a39-4e7a-08dcf8267a46 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: BXmp9CfOhvZR7PELryL5vdFoPsK5MTwKrwqMa9zfyO9fNbhAcu3OPIYd1YRieATI/big3EGWtHle3JlkoLZZfsTJV1/3NxgI0BQDhnBlrhLUQ9MVB3kjZBBJ72bu15wOXXxjp2T+UAS47kyiLQq73py9zH8AZTNBOJyv7wSits5xgxbtsOLEPtX0JRVv6Uu3UqlU0ERNwrWQNrIxnpWsC22C6LoHcuiyTffJtxDn7BVU5qPfy/2joPVIDdWKilnudVNMCjpGtEwc3qONmBUxDaVMk7N5KIcSjhGGVcTdlisvq/4gzedOySiApgapsRIL8fiA+J8m1ogruZA2C43AdYgvB4CEBB0kqKKPJll6OghrZWcwJ8eLkMtB5OOsiuZbvEared+U1Y/aThN9gUsmWCj8VyF9VVmsyHc3da+fnQ/T3/AM445vObwKKCd1Oe369h9QsF3FNBJaeqtSLNK7T7heE5L1MrU+0f0nYIWW7+W0BKznuXIRWhr8aQz39nwyo0pmxJq8MFLXDIKqAg8Q8XkM32oJqQDXbRW1ztvTr6vcAWfkn2L/OIU76IL7TIep2A0fDYbIkhBpPMeDlrg08tgiuETdKoxyPV8SO9H90ww8Z8WGFsp78/cYlEaEvNQMflKs9HSivdxFe40ORd6olWfa+klYKm6kdIHcWg2JYBvBJfdWubWWvfza4h4MdwVhQvVUlsjBXpzyy7n/OjmHVslTqELUxNQt2mWnCteecSynNfT8TtBIN/g2fowmWGDXvahmbYb/Gk3n3XVhhXP3g+8mzkxtMHK/lwDwONd7xpMd1zBA/OatYqH9feMQK27X5nrfMQ5eeql5E5hDB6Zc1ZeU6r1sKqf1isH9quxJigSQ70U3evFeIaFHdf9gI7hdIYV6QGa42bj1TiG9Ugx5m8EF4ltdDyGQXV9wYF1jZMZBwpL/ZfjyWDDINO018hnVDxYILDyOL5qNd3BAAZ+iAc7BQFFVhoKLf2xYOvd35m0LVh6ou/+ExwXUBIyKhpEy7Nx/fBMPsdyzdmi8kDt11CCvwBNMwWuaSFgZwfd6bTi9+ukKOQrtEKhitfo6b+9SJc26ZvXXNKUB40c4JdT+NnwUHqKvIgg1pfl0nntMQwSMUETAu97t918PWa+oB6zKvD7FIQnwnqpcvlLQ7bOzWEk4aDdDIWJpJQOUWHA3+rXEUZ9BrdhQFXva7xbQMKJvL6GAOj1YtGoTMoGDGYp2Iqowx9N6qqSdVzK9YzYO2Bj7sCSDLRttVq7e2fJPI+qQF05wOAk8NOMx8zb5XlGO6w7vcWFkCsdY+9kGOxkhN6d9gWM2DMsguMr2Ib1YlFGsLyhjnVjmPMUNskfti+cQENhTJt7ukz9oFqTqdVP+RICQWD45Ynn4gjvS3en5pw6eIrBK1KAZhRA0SZimMcB3XQ== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2024 14:32:12.2078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d963e49-a84f-4a39-4e7a-08dcf8267a46 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000144.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6987 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rongwei Liu Add a new devarg probe_opt_en to control probe optimization in PMD. By default, the value is 0 and no behavior changed. Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 7 +++++++ drivers/common/mlx5/linux/mlx5_nl.c | 12 ++++++++---- drivers/common/mlx5/mlx5_common.c | 15 +++++++++++++++ drivers/common/mlx5/mlx5_common.h | 2 ++ drivers/net/mlx5/linux/mlx5_ethdev_os.c | 5 ++++- drivers/net/mlx5/linux/mlx5_os.c | 2 +- 6 files changed, 37 insertions(+), 6 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index f82e2d75de..981401a9f2 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1436,6 +1436,13 @@ for an additional list of options shared with other mlx5 drivers. By default, the PMD will set this value to 1. +- ``probe_opt_en`` parameter [int] + + A non-zero value optimizes the probe process, especially for large scale. + PMD will hold the IB device information internally and reuse it. + + By default, the PMD will set this value to 0. + - ``lacp_by_user`` parameter [int] A nonzero value enables the control of LACP traffic by the user application. diff --git a/drivers/common/mlx5/linux/mlx5_nl.c b/drivers/common/mlx5/linux/mlx5_nl.c index e98073aafe..745e443f8f 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.c +++ b/drivers/common/mlx5/linux/mlx5_nl.c @@ -1148,7 +1148,7 @@ mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex, struct mlx5_dev_info .flags = 0, }; - if (!strcmp(name, dev_info->ibname)) { + if (dev_info->probe_opt && !strcmp(name, dev_info->ibname)) { if (dev_info->port_info && pindex <= dev_info->port_num && dev_info->port_info[pindex].valid) { if (!dev_info->port_info[pindex].ifindex) @@ -1161,7 +1161,7 @@ mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex, struct mlx5_dev_info ret = mlx5_nl_port_info(nl, pindex, &data); - if (!strcmp(dev_info->ibname, name)) { + if (dev_info->probe_opt && !strcmp(dev_info->ibname, name)) { if ((!ret || ret == -ENODEV) && dev_info->port_info && pindex <= dev_info->port_num) { if (!ret) @@ -1201,7 +1201,8 @@ mlx5_nl_port_state(int nl, const char *name, uint32_t pindex, struct mlx5_dev_in .ibindex = UINT32_MAX, }; - if (dev_info && !strcmp(name, dev_info->ibname) && dev_info->port_num) + if (dev_info && dev_info->probe_opt && + !strcmp(name, dev_info->ibname) && dev_info->port_num) data.ibindex = dev_info->ibindex; if (mlx5_nl_port_info(nl, pindex, &data) < 0) return -rte_errno; @@ -1244,7 +1245,8 @@ mlx5_nl_portnum(int nl, const char *name, struct mlx5_dev_info *dev_info) uint32_t sn = MLX5_NL_SN_GENERATE; int ret, size; - if (dev_info->port_num && !strcmp(name, dev_info->ibname)) + if (dev_info->probe_opt && dev_info->port_num && + !strcmp(name, dev_info->ibname)) return dev_info->port_num; ret = mlx5_nl_send(nl, &req, sn); @@ -1263,6 +1265,8 @@ mlx5_nl_portnum(int nl, const char *name, struct mlx5_dev_info *dev_info) rte_errno = EINVAL; return 0; } + if (!dev_info->probe_opt) + return data.portnum; MLX5_ASSERT(!strlen(dev_info->ibname)); dev_info->port_num = data.portnum; dev_info->ibindex = data.ibindex; diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c index 0aaae91c31..9abae4a374 100644 --- a/drivers/common/mlx5/mlx5_common.c +++ b/drivers/common/mlx5/mlx5_common.c @@ -40,6 +40,9 @@ uint8_t haswell_broadwell_cpu; /* The default memory allocator used in PMD. */ #define MLX5_SYS_MEM_EN "sys_mem_en" +/* Probe optimization in PMD. */ +#define MLX5_PROBE_OPT "probe_opt_en" + /* * Device parameter to force doorbell register mapping * to non-cached region eliminating the extra write memory barrier. @@ -295,6 +298,8 @@ mlx5_common_args_check_handler(const char *key, const char *val, void *opaque) config->device_fd = tmp; } else if (strcmp(key, MLX5_PD_HANDLE) == 0) { config->pd_handle = tmp; + } else if (strcmp(key, MLX5_PROBE_OPT) == 0) { + config->probe_opt = !!tmp; } return 0; } @@ -324,6 +329,7 @@ mlx5_common_config_get(struct mlx5_kvargs_ctrl *mkvlist, MLX5_MR_MEMPOOL_REG_EN, MLX5_DEVICE_FD, MLX5_PD_HANDLE, + MLX5_PROBE_OPT, NULL, }; int ret = 0; @@ -332,6 +338,7 @@ mlx5_common_config_get(struct mlx5_kvargs_ctrl *mkvlist, config->mr_ext_memseg_en = 1; config->mr_mempool_reg_en = 1; config->sys_mem_en = 0; + config->probe_opt = 0; config->dbnc = MLX5_ARG_UNSET; config->device_fd = MLX5_ARG_UNSET; config->pd_handle = MLX5_ARG_UNSET; @@ -351,6 +358,7 @@ mlx5_common_config_get(struct mlx5_kvargs_ctrl *mkvlist, DRV_LOG(DEBUG, "mr_ext_memseg_en is %u.", config->mr_ext_memseg_en); DRV_LOG(DEBUG, "mr_mempool_reg_en is %u.", config->mr_mempool_reg_en); DRV_LOG(DEBUG, "sys_mem_en is %u.", config->sys_mem_en); + DRV_LOG(DEBUG, "probe_opt_en is %u.", config->probe_opt); DRV_LOG(DEBUG, "Send Queue doorbell mapping parameter is %d.", config->dbnc); return ret; @@ -791,6 +799,7 @@ mlx5_common_dev_create(struct rte_device *eal_dev, uint32_t classes, if (TAILQ_EMPTY(&devices_list)) rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", mlx5_mr_mem_event_cb, NULL); + cdev->dev_info.probe_opt = cdev->config.probe_opt; exit: pthread_mutex_lock(&devices_list_lock); TAILQ_INSERT_HEAD(&devices_list, cdev, next); @@ -880,6 +889,12 @@ mlx5_common_probe_again_args_validate(struct mlx5_common_device *cdev, cdev->dev->name); goto error; } + if (cdev->config.probe_opt != config->probe_opt) { + DRV_LOG(ERR, "\"" MLX5_PROBE_OPT"\" " + "configuration mismatch for device %s.", + cdev->dev->name); + goto error; + } if (cdev->config.dbnc != config->dbnc) { DRV_LOG(ERR, "\"" MLX5_SQ_DB_NC "\" " "configuration mismatch for device %s.", diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index 6cb40f54dd..f1b59d6f07 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -183,6 +183,7 @@ struct mlx5_dev_info { uint32_t port_num; uint32_t ibindex; char ibname[MLX5_FS_NAME_MAX]; + uint8_t probe_opt; struct mlx5_port_nl_info *port_info; }; @@ -525,6 +526,7 @@ struct mlx5_common_dev_config { int pd_handle; /* Protection Domain handle for importation. */ unsigned int devx:1; /* Whether devx interface is available or not. */ unsigned int sys_mem_en:1; /* The default memory allocator. */ + unsigned int probe_opt:1; /* Optimize probing . */ unsigned int mr_mempool_reg_en:1; /* Allow/prevent implicit mempool memory registration. */ unsigned int mr_ext_memseg_en:1; diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 08ac6dd939..88d3c57c6e 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -691,6 +691,8 @@ mlx5_handle_port_info_update(struct mlx5_dev_info *dev_info, uint32_t if_index, if (dev_info->port_num <= 1 || dev_info->port_info == NULL) return; + DRV_LOG(DEBUG, "IB device %s ifindex %u received netlink event %u", + dev_info->ibname, if_index, msg_type); for (i = 1; i <= dev_info->port_num; i++) { if (!dev_info->port_info[i].valid) continue; @@ -734,7 +736,8 @@ mlx5_dev_interrupt_nl_cb(struct nlmsghdr *hdr, void *cb_arg) if (mlx5_nl_parse_link_status_update(hdr, &if_index) < 0) return; - mlx5_handle_port_info_update(&sh->cdev->dev_info, if_index, hdr->nlmsg_type); + if (sh->cdev->config.probe_opt && sh->cdev->dev_info.port_num > 1) + mlx5_handle_port_info_update(&sh->cdev->dev_info, if_index, hdr->nlmsg_type); for (i = 0; i < sh->max_port; i++) { struct mlx5_dev_shared_port *port = &sh->port[i]; diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 8f6e584154..695936f634 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -2340,7 +2340,7 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, while (ret-- > 0) { struct rte_pci_addr pci_addr; - if (cdev->dev_info.port_num) { + if (cdev->config.probe_opt && cdev->dev_info.port_num) { if (strcmp(ibv_list[ret]->name, cdev->dev_info.ibname)) { DRV_LOG(INFO, "Unmatched caching device \"%s\" \"%s\"", cdev->dev_info.ibname, ibv_list[ret]->name); From patchwork Tue Oct 29 14:31:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Minggang(Gavin) Li" X-Patchwork-Id: 147601 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6C9AC45B4C; Tue, 29 Oct 2024 15:32:47 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 447E642E9C; Tue, 29 Oct 2024 15:32:32 +0100 (CET) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2084.outbound.protection.outlook.com [40.107.92.84]) by mails.dpdk.org (Postfix) with ESMTP id A8CBF42E80; Tue, 29 Oct 2024 15:32:25 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Z+qy7K5CcqTNgoXCPO8+t2yCKIJloNAlN9S8PEF6aoM6r0HW9KKxG898UUkdh2FUIeROf5xJp/zJ18jLI8MR2d/kuqqHJBKcYzfOc4yLv1jcUtOK7ycM2z9HUiZhHz/RXpCBEcmDAWn213Qqr9XZOsy1lnGVagY4grvhBAs4kg/gOjoQFU3NyWCfeTpR+lCxztFtXYgaPdqMavzezq574Q/4vO1Xyp4a9sEDl2QoPV8JZ7yPoynJHLQFdYcXZUXHt2t/u+zcWsLHmVjQfmtmXI2l2K4njVnqN71dm4eW2q8TYHauS9VS2K4JKcIk2pmnb4gSvMHerBxKk2zTACUvig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=htQ+aK34Jum5czOtPgDnOeUfGDaUEddCTsukZmu1+4U=; b=FSEIMpzz0ZB3Qzh5qnVHYSAf9VBI78RIOocbZxsOndAIbpvWaN66rHo/4Rjfxyi0/3EGoGw9gyLh7X3PHcw0UtHW5+4DNh54Uw2ASVq66pyd0CnlFP1qTaGGzrX1zfvTnbceDcjcrQZctp1YEKA381YytwKLrVGa96dzFNopj/6n/IkLlshuXjO3LjWWD7GdIELcQzqwHCwhFVEn+G0cWF3AEsbDmBt0GzuaU5nq2ZV2JXLjxSrKLB+caqlLKU1uEiLj2gb0adQAJw5JlaWh+JpZCwa3ez673HKepFJpS0FiWPWwpHMnoQ2JNRmzdsDe54LVHRHITmsQVyhv2MbUrA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=htQ+aK34Jum5czOtPgDnOeUfGDaUEddCTsukZmu1+4U=; b=VeswqGlY1IkVJonRs3OapZmEQQWp98K4Nkxqycmm2zYEtdVtGXAhXcvaWuyWhsr+YyBrHikbBh8gjZOAswpRQ7zxMUAdSpkhTi/yce2g4T7BIX5O/P/FJFcf6Qbfzg5WQfkmh4SgLMILCUTSaVlM9vVAJfoDyXicpzqYBHSbxewKjvklhEQOXI5raqurm8kRvBQ2rKpqMNwCAsnI8UlL7Y9Gq7LwtyA9NKU/sqHhcfYzsnrZocHCbQKlx+n7kWpDExzt3VFLYHMeUtfwTLIK5l5A+CAZuWwLmRj1MAHEXsNweHborvBRYDTvodsGZ+pDWvT6xlXWOAZpc5HonYwNEQ== Received: from BN9PR03CA0561.namprd03.prod.outlook.com (2603:10b6:408:138::26) by MN0PR12MB5787.namprd12.prod.outlook.com (2603:10b6:208:376::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.25; Tue, 29 Oct 2024 14:32:19 +0000 Received: from BN3PEPF0000B06F.namprd21.prod.outlook.com (2603:10b6:408:138:cafe::c5) by BN9PR03CA0561.outlook.office365.com (2603:10b6:408:138::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.29 via Frontend Transport; Tue, 29 Oct 2024 14:32:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN3PEPF0000B06F.mail.protection.outlook.com (10.167.243.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.0 via Frontend Transport; Tue, 29 Oct 2024 14:32:18 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:46 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:43 -0700 From: "Minggang Li(Gavin)" To: , , , , Dariusz Sosnowski , Bing Zhao , Suanming Mou , Spike Du CC: , , Subject: [PATCH V3 4/7] common/mlx5: fix Netlink socket leak Date: Tue, 29 Oct 2024 16:31:15 +0200 Message-ID: <20241029143118.875214-5-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029143118.875214-1-gavinl@nvidia.com> References: <20241029134256.874767-8-gavinl@nvidia.com> <20241029143118.875214-1-gavinl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06F:EE_|MN0PR12MB5787:EE_ X-MS-Office365-Filtering-Correlation-Id: 4840c18c-6342-4559-35cc-08dcf8267e24 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: 1Q0jNPuB3oiExNpbvh3jluh3lU6nA0s0LPRtVJqQlPbMyExBr3OVV35MMbV4Qwh7Vw9cqNCGgT4qCPstxkk9ox8P/T6eD/gousk/tH5EcIDtsrs3KoQns2dOnHWfqcl1AO9augUfuffr1r9XJ0kvP3t2VsK0LaPziDBdGZux5VftYsu7hJ+HAgy2/oK6LfGCzhZUPjnZYf5QVknjautjR/TVJmBqIZeg648J9oMUkzhJMp21pZpzs1p1C7awWL9/P+hTZRmevbMmc5g8LQYzJtAaHOXAjn8/kRA1IJ1JLSdLCPnVCvRzZLv7VXXbjdUDHNTPQQdwPtLagS04FKRhDp6ytNQP7fy6tmapRKCUncZIQVAwWtO99oZs649nMLtjnJsC81v93MhHOq13cgHFQWw8PmvVmKa2fzA1WIMtXeKfT2GzeBVjjNGzeqIuGdE9Jf9WXQx5cKmYhJ9djFuPuWc7ojiAlprjV5npzsg0M3wTcOQkq7yvaMXHBKgAqGATsQpaOIh4RCn85BDrORAt8ZNuFUPGYErYBJLcvglltEb2YNoUewLnG0Ghh+li+hXQ418KY+St8DQykGe2N23zwwyiaQ2RWFE6jKr6ecLtJ/VpGgJMSwRRT8Kbo7ixYMBa8inBIYcE04vWgLPQwX44SguOvAJoe4PDj5pDoBE3MPOMl/2UwdjimjIVJUvORyv/PJziC/FS5E7BEPyYTNQyMS18/5k+94ddqn6/U66S23t7w4YFMp7YLSSOJrSBe2BgYRk6FrRJQUJsAG5Sfw/pRno57UR5muyr9jpvRNidk7NfgdixjFN9UFl+Y46/wqHnTAA//3lfdQ3SAJ2/LWQAf4vOjs4gOQVOg17k2KTzZ1iD8f4+aai8FU1KCgKPsZX/jsjb6QZWMCPslfZYKD62x5Q7ZvhFxx0gHRh2aHebFGtX+gabdYVgrHs7Wr/m5g1i3o+DCXmHS7aRVQT8N0dFKmAyxMWkTEkTpR2g7nL3eXBFtyNGFQRnhgHg5tLXK0St9m+X9y6BzEcUq9ppFk1Kg/U8AIzql4uPEQwqlDZzKywGhIAs+Dp+iP1mFxtjarJ8AeNs5p4gk3CdizLy76ndyTBeIb6mAtZihB0MZBhiCGO2XGq1m63lRxVOzlsZU7J0LgQV8Py9arK95G+CHMaisJFMtgKhcauV9ynf/Pez/opiLiOsS982accSsyY4ePRY8MD/CTcsjBvEd67l2Elacap4T4oNdI6+VW75p4cDaviFhMpxYic+MAKYyA3S3lYmcjYISgn92GTrTJZ1GrX8wWlPGVIdWhsYjxuZnqxrVJa5S6OLNITu/smejxG69U5Z+QCFE4XjLEwe3WLPNKW3dxlanKpV+oSrenWmCQwdWWwvYohno8AMg8mzplrPBzYIALwua0lF3AY7/GiDNsJq1Q== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2024 14:32:18.6484 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4840c18c-6342-4559-35cc-08dcf8267e24 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06F.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5787 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fixes: 72d7efe464b1 ("common/mlx5: share interrupt management") Cc: stable@dpdk.org Signed-off-by: Minggang Li(Gavin) Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 695936f634..4537ca0466 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -3071,10 +3071,15 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) { + int fd; + mlx5_os_interrupt_handler_destroy(sh->intr_handle, mlx5_dev_interrupt_handler, sh); + fd = rte_intr_fd_get(sh->intr_handle_nl); mlx5_os_interrupt_handler_destroy(sh->intr_handle_nl, mlx5_dev_interrupt_handler_nl, sh); + if (fd >= 0) + close(fd); #ifdef HAVE_IBV_DEVX_ASYNC mlx5_os_interrupt_handler_destroy(sh->intr_handle_devx, mlx5_dev_interrupt_handler_devx, sh); From patchwork Tue Oct 29 14:31:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Minggang(Gavin) Li" X-Patchwork-Id: 147602 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 65E2945B4C; Tue, 29 Oct 2024 15:32:54 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A00B542EA9; Tue, 29 Oct 2024 15:32:33 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2084.outbound.protection.outlook.com [40.107.94.84]) by mails.dpdk.org (Postfix) with ESMTP id 2CFA542E7D for ; Tue, 29 Oct 2024 15:32:27 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=iQBKTtwcf24ufLqKkXjf2Lyac46bOM7R1E3FAJuBiAlUvTV742JBauLr15zY1KNpsvgyebcvObnxJXW2bdQyGnScw8eHhzc3SkMq2B33V+v321Og9LToRelP798YG5vlrvyr0q79g6OH9mE1tMBSpJ/Qs+x4uDvOAJ5HR8aVy+zh+pEwzm9dgPrMYoE8u72zOZVZkk0wTFS4nO3QYGYOO3ccspMVOFQOdcgNGgHhworR5KpBlh+KSEj1Podu6E5mT4hTDcPlrJk6DQLqu5ZJM9TK+1iM60Z90KSra8p90mzWIksiV+3N4Vvl1Z3OtXabDRM506UubffQqLjkE/oR9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nC9Q8PXdjszOJclvQaIxRRs5+pBVB5WkTiQPxk621Fs=; b=C388FUtGVwNAAt84O1p+EPGSHyD2RhgDXcZyQXtBNNczxK3DJlNiBY9LDVyvNqJgzd+Q37wYeTnS6MXX+8HCAehBwQ45EJPgkoBivDk6OC0S8pg7fA8JJHwH8pxQrtRAy4EiiYvIhZysz7/rayuHkLl2Erg0DeuAsjpVCMs7VxnclOnheUGDFmGMIBlcVX5ZUK3kYSenn3cDvLQqODTZh829DMYFZSx/YcfvHDzQaU2Gc+IAY1LeaqiwyZkG2/1hNnTrL3NBk+zjB360vnC9T9wZuoNoxb7indMRo5/SMH+rpFn3szFwkrJhKOiTCqhpfKzjbo8lztmBCCQDynkhUg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nC9Q8PXdjszOJclvQaIxRRs5+pBVB5WkTiQPxk621Fs=; b=XP1IT/wZdUetIZaLzLilKv8VYgU5sTFRagzN9ZtBBfA4Ki+2QElwZ95JGoo5J85aQZfVkTnQFgxFsiOh7vFZhHWQTh3oCK+Z4iATP/sUsEAVNDYq8VS67NzcqD1g3c7QzETabnefV/yXiasxZLoLwj5sm4Sa2tYRvOQUl37x+gHQ88joVx9HqJ2UjeBJD9RnS/zBh8Avtm0E6Xxfg0LcDB73F30A916MsBaqKfcZ1yaq714K0fbi6ixJFEcGhaMgKUG3nhCDRK3Mo26adG+gW8oGN6RLqI14Jp5kb7Go5+JWZrktHHxKXuXPqGhbClGmENlNqjBRmglggbDJX3tV0g== Received: from BN9PR03CA0561.namprd03.prod.outlook.com (2603:10b6:408:138::26) by SA0PR12MB7092.namprd12.prod.outlook.com (2603:10b6:806:2d5::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.32; Tue, 29 Oct 2024 14:32:22 +0000 Received: from BN3PEPF0000B06F.namprd21.prod.outlook.com (2603:10b6:408:138:cafe::5b) by BN9PR03CA0561.outlook.office365.com (2603:10b6:408:138::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.29 via Frontend Transport; Tue, 29 Oct 2024 14:32:21 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN3PEPF0000B06F.mail.protection.outlook.com (10.167.243.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.0 via Frontend Transport; Tue, 29 Oct 2024 14:32:21 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:49 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:46 -0700 From: "Minggang Li(Gavin)" To: , , , , Dariusz Sosnowski , Bing Zhao , Suanming Mou CC: , Subject: [PATCH V3 5/7] common/mlx5: add RDMA monitor event awareness Date: Tue, 29 Oct 2024 16:31:16 +0200 Message-ID: <20241029143118.875214-6-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029143118.875214-1-gavinl@nvidia.com> References: <20241029134256.874767-8-gavinl@nvidia.com> <20241029143118.875214-1-gavinl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06F:EE_|SA0PR12MB7092:EE_ X-MS-Office365-Filtering-Correlation-Id: 96a5cfd8-6f18-418a-bd7d-08dcf8267ff2 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: aVRgg9jksagOzUpsP62JRDh+Bx3EcoMTs+tDfyhAHtnmpG8yrg48G/1OnIIeIN6uwJDONqLCUtHUi+YZMdRq9stJ5Cuh/1ZIDcum0CPTOcTkjfF/PJp1a4mK1Tm2D3UQ1bNggFoR8fp2l+e8t6ep5BLyVYc57cNVGsNJaNSZ4RHnoZUw0hfOpNJAnDGu7HqjxPgtQ4EgaFCa2RQVcJt5/eTSDHeEvfUEzdBOri2fyQCkOP2Rz8Criwkv+1ZGcoAA45qTae7a6IEWI6F3Jat11DduvDaAyznGNPm/EtGQo1m0O5JlSePw+WwmV+4vujBruG+iZ989RswGipA/L/fENs3MCT9ytAWg8Fk8CgoGUEmY2CFlsC9Z/U7a2M5wGJ+sBSsAHadf7t2PqY0rG0jIHF7OGXWaTiMYWKS6Fv33ASZ4OQB57laA9UTg9vTbTHK1rqFdxuEisjpRxFgDb9vxurVF3DDYgtH7MYyXJWxivOu3b34eIFkFdkCjMAAyjRWeXAdykHUSGwPWZ13wJErtuXiqoQ0lKWwooegK1wOfTb8z7avQyPy932avQA0wPVzNWotVkyFf6ecf7kbZSl8nRirg7TNBsVSiFWP3iK8DWTP9f6sEpf5kNh5h9y1i0+Po5mKtjA2b7yFaz6BfNikhLxKJl9LXBpkvnRP78f1gWDrb9Stx7J7yy50oAWMi3MSdTrm5VmldYV0DKnF9l6W06sVQ0iNmK4xUqAxk0l++7TBVtSCTYhRwKKiTUYTd5Fz0kdupYY2ehb4vcYmdKSfzcHZ+FnZdb/htLtjwdiIcXsa68xrbiOKkAU1kucXo/aB2HZVgZvW5Qfa6yHyJpZHf5F1NCB5Km8aAbWfokT375QF3ZKXwcEOyLMSyS6m+rB8vUwJ8NmQNDEb0OWleL9T4khBuybZuD94l9WA93ztxIEgDRI/lu6hnH7Tqplls+FCnuZNpqVkvTNQfBjiIbwh/asJs5XSDu6jkAdP3tbfuvJ3Wh5rMDKV8CKvtEgBGsmdrN8HKxNnJX9AC86a9UdEw+nIrwMbm6nIxMar4PNbEQYv+azmNu8NT8DenzKNtC7FE0ZZt+RgR54Fe1NQwwzl5C2D0QbKxcyqh4LPpaTuhISDyWfruSE5mZdoPlKxjR5nYrAT/3F6cY8X5Cpz/MdyEirPBbAkHkm+/+35DhH/VmgqEQr0oB5vdCLRLGIMIn+cq4bbGsWVC6guDaG+/zo2PlAVM04/6jut0TmQjpXhvJO0Kh8nejd1Wj/UZiz+eFNvLlFAFuR+eHFHfkZWEVRGT7bPcdO+Wrwp7wUUHiEcYg5D+ug4MXbESxL1XIhNdIk5ZTJPtGpwq9wVs/u2zNf4vQd4gwv3q4dhgQ1GTSBjQw/bWgpODTvpL9c7dVqCHhFs5CKBvLclhrVM1YL6ggFZ66g== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2024 14:32:21.6796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96a5cfd8-6f18-418a-bd7d-08dcf8267ff2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06F.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7092 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org RDMA monitor is a new feature introduced by kernel driver. This commit adds backward compatibility for the kernels do not support it. Signed-off-by: Minggang Li(Gavin) Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/linux/meson.build | 10 ++++++++++ drivers/common/mlx5/linux/mlx5_nl.c | 17 +++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index 82e8046e0c..58d0328c6d 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -170,6 +170,16 @@ has_sym_args = [ 'RDMA_NLDEV_ATTR_PORT_STATE' ], [ 'HAVE_RDMA_NLDEV_ATTR_NDEV_INDEX', 'rdma/rdma_netlink.h', 'RDMA_NLDEV_ATTR_NDEV_INDEX' ], + [ 'HAVE_RDMA_NL_GROUP_NOTIFY', 'rdma/rdma_netlink.h', + 'RDMA_NL_GROUP_NOTIFY' ], + [ 'HAVE_RDMA_NLDEV_CMD_SYS_GET', 'rdma/rdma_netlink.h', + 'RDMA_NLDEV_CMD_SYS_GET' ], + [ 'HAVE_RDMA_NLDEV_SYS_ATTR_MONITOR_MODE', 'rdma/rdma_netlink.h', + 'RDMA_NLDEV_SYS_ATTR_MONITOR_MODE' ], + [ 'HAVE_RDMA_NLDEV_ATTR_EVENT_TYPE', 'rdma/rdma_netlink.h', + 'RDMA_NLDEV_ATTR_EVENT_TYPE' ], + [ 'HAVE_RDMA_NLDEV_CMD_MONITOR', 'rdma/rdma_netlink.h', + 'RDMA_NLDEV_CMD_MONITOR' ], [ 'HAVE_MLX5_DR_FLOW_DUMP', 'infiniband/mlx5dv.h', 'mlx5dv_dump_dr_domain'], [ 'HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE', 'infiniband/mlx5dv.h', diff --git a/drivers/common/mlx5/linux/mlx5_nl.c b/drivers/common/mlx5/linux/mlx5_nl.c index 745e443f8f..e03db4f918 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.c +++ b/drivers/common/mlx5/linux/mlx5_nl.c @@ -84,6 +84,23 @@ #ifndef HAVE_RDMA_NLDEV_ATTR_NDEV_INDEX #define RDMA_NLDEV_ATTR_NDEV_INDEX 50 #endif +#ifndef HAVE_RDMA_NLDEV_ATTR_EVENT_TYPE +#define RDMA_NLDEV_ATTR_EVENT_TYPE 102 +#define RDMA_NETDEV_ATTACH_EVENT 2 +#define RDMA_NETDEV_DETACH_EVENT 3 +#endif +#ifndef HAVE_RDMA_NLDEV_SYS_ATTR_MONITOR_MODE +#define RDMA_NLDEV_SYS_ATTR_MONITOR_MODE 103 +#endif +#ifndef HAVE_RDMA_NLDEV_CMD_MONITOR +#define RDMA_NLDEV_CMD_MONITOR 28 +#endif +#ifndef HAVE_RDMA_NLDEV_CMD_SYS_GET +#define RDMA_NLDEV_CMD_SYS_GET 6 +#endif +#ifndef HAVE_RDMA_NL_GROUP_NOTIFY +#define RDMA_NL_GROUP_NOTIFY 4 +#endif /* These are normally found in linux/if_link.h. */ #ifndef HAVE_IFLA_NUM_VF From patchwork Tue Oct 29 14:31:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Minggang(Gavin) Li" X-Patchwork-Id: 147603 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D367945B4C; Tue, 29 Oct 2024 15:33:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D90BC42EAB; Tue, 29 Oct 2024 15:32:34 +0100 (CET) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2046.outbound.protection.outlook.com [40.107.223.46]) by mails.dpdk.org (Postfix) with ESMTP id C878642E82 for ; Tue, 29 Oct 2024 15:32:28 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Q6Q6Iv+hWcLizlSueNoJ0Z01uRZoi7LXqCne+9APPQlQ7ERPrrYax21DQGdHxTbjVFtqS7CQQzdJ9AdLxtf4ZyP6o8nUk8peSGP9ajbQaDQObQwqzPYBEzleZA2A6Kfc+CmJV+FLUseYGiju8nbiXDCsu3xsnoh9gHOpR+/i6KN97TY0xfQFKprKLvOW4yo9Y8uNMNZQmbMwWklcHEClR6+lSgg3cEppoLzTMYZJpUx4n9Pe5haK9Bry5ZvEIqFB2WEWi49dn3P2bVxPLsCoWdGeNsQdcKgNzw3wOsLJjsXDj0lfnbdO4OTq0IzI577TGWUIVUdNvuuPUr4hrTyTQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=n2Ed5kzt3zzt+7aWbC8VdS1KlFxGVdj9hz/uVXE9BVA=; b=PBXZAfT7bYKlsTr1cvBmVKFAfij7boaSbu3RLYzeNiSDItUj2XLcbhCHpuWiefCd/fusnpKk9E440jwXXtInqPXmrt3xNSiwZc/Yf5tSldB1+yaSzXnhefKgL3EaYZ8ErI/T7JDyiRZeh5yYG7KjvTnolgBvc21+cGCYZ7ZrqS5MgUGUHwV5z+nTxflo86n0twascYpxt8UJGNv8XBXHHr2XLPfnUZn0LJg9ZQSKrx7ETTMOcFfsGd5Sk9T4y9yo/NpuuGAv9Sn5RUGdaGieLUuoBg1Pm5k/Ex3NSj+oQF0sV47RyahSaAYxQR8n+JRUpgjKcgQLmeuFRQBYrrIjmw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=n2Ed5kzt3zzt+7aWbC8VdS1KlFxGVdj9hz/uVXE9BVA=; b=UTLJBAjGxbxHtYzqA/eurPZRf1hsFhpwzyIECbFYndGcwK+++RChKqSfJsEq814DVmPsg9X7ZQoImRqmOCZrTGHt18pOZPNZ7fgVuEPjn8MjfZBRElcX5qJldxKHo2cSnS1y+Z45Lfkq4/aQLrChoOCXwZQlsQKEeiioV6kw5Dnr0i2bPlJUqF8o7L2vQu1ziHROu4dFLMfYzQclIH4tbNQf4a5P1CeLMQr49kiML7dDQN/6iSiX7m5yVwcBQkskzO06+TSritRE2tHy+J56oTNIrVM4ZSZw9R70GwEhW2EMB/M8qoxfhmbfH2kOn2wfqKV0rZrLoMWN0V9vJQw6eQ== Received: from MN2PR05CA0057.namprd05.prod.outlook.com (2603:10b6:208:236::26) by IA1PR12MB7685.namprd12.prod.outlook.com (2603:10b6:208:423::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.27; Tue, 29 Oct 2024 14:32:24 +0000 Received: from BN3PEPF0000B070.namprd21.prod.outlook.com (2603:10b6:208:236:cafe::6f) by MN2PR05CA0057.outlook.office365.com (2603:10b6:208:236::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.17 via Frontend Transport; Tue, 29 Oct 2024 14:32:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN3PEPF0000B070.mail.protection.outlook.com (10.167.243.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.0 via Frontend Transport; Tue, 29 Oct 2024 14:32:23 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:52 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:49 -0700 From: "Minggang Li(Gavin)" To: , , , , Dariusz Sosnowski , Bing Zhao , Suanming Mou CC: , Subject: [PATCH V3 6/7] mlx5: use RDMA Netlink to update port information Date: Tue, 29 Oct 2024 16:31:17 +0200 Message-ID: <20241029143118.875214-7-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029143118.875214-1-gavinl@nvidia.com> References: <20241029134256.874767-8-gavinl@nvidia.com> <20241029143118.875214-1-gavinl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B070:EE_|IA1PR12MB7685:EE_ X-MS-Office365-Filtering-Correlation-Id: 343031b1-f150-495b-6afd-08dcf8268117 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: b42mBmk3dKmJjLUE+1lXysrykQqO3dJ4iOwDIvwWCwxUOyedVWnGb3/C8pjPNAf81tNdexkDYaCCCj2c2lJbsLIdX5mgUCN3JzMgcfpp8mykGWyLyJAIm98YwtS6gPzvplnkxPDg4c4/s7rNClz+jiHbt/ie/8+SxR6Rm/3crRe1R/F1UiEMxefEhiLiR7md2NCbu2+qKUBfc8heRBqlhkgujO95t9JS0IqSuOJE/ZwIJ7uxl5MuJsfd9+VlAIN1AqRB9XK4yV5s7PgERzhnESe3ouF0LNFULNnmH/6dS3XI/WuPiQoJX9LCCmRk/14pK8sLUWp8DSjWotPtxWoLkOeuq+BHq3kvrbBEU2XTjMoQI/Kv1EGJJX07MVUBAx5nKfJbDIdjTKcQf/vjTD4qdCxjw20F2Ri+DGX5ZP5khA9ZFFwXMmM2efPfnUjOl18RX52oKIm7Vxbre1US8Cw5cM1PYNNWb5BHQ5uG4htkb3EhlfK92UTfokY3SXF2c9jQpXAHMnRVLDVoeo1otOiDGd52zBPKYTuoyGUjx9RskL9kN9iofJ017xTtxTJfhC/MmbUrHqmTXQFvO/+LwLrz/sWdkceuIxBza+b6Exnaj8+zcGaylhP2RjxH7vUF0S5m2jzQ0JHoqgmp1BfWdKCLyrzWtvPZwwbXaeJ8LJSvURu2pq/IpwZTRS6x23/8wjoCs37DLfo/8xvDP8mYEc22HHgkBB5/WpBDUtC0f1Kqv0gdHFQngxO/GGL4AV9dnuUesmXSrg2OHMNejWqxxwn2o3ojyyK1dZAKeSegAzyQOir4d4tO/as3SEyILKXJevCyCHYbBdJAytxo7uO43T/4BUuiY+Dtb4oATZ+wRqtDdeg453/KKMFsp1Fmf7l6hJCYHmt4Fsu+u1K7sHgdwvE34H23FKpueGgE3v8mE/s7Pl5kddIflTGxQXxpPs7B0WFE4ongGUJCngdw6u6Us/FCPUBAJqE6WBI8uoEWdqGp+nCe6ZYjap6QNWLJ4dKhDjRY9B7aGN8Voq5I1AJtZYnd5443624cOv/ejJ4qmjlUjrGpLk4M3pOMyQma0UxLGXTKwfCxbr8Cb4gs2cH8x30XKR6bho2uhBz31ZsezbalMPHv+sgR2LpS4p16FS/EHDuqHe5nwWTPQ2qbYSA7QM92//oqmIwGWI1dFXGh7iMqozCcIkvenbwiAvBBsa+Cdkwz6QgOSNQAUPUz9edAfe/uBRy4hmweerghENgRz1bJfCiRpJFR2YEZdgiha1yEtByRU/Vy/tFPyl63SePpXXDjU91GlrhKaKA1jXF632o2vDsrWfuAzFM89KzW2aREISzoG3hwIvfQgxNtdwFd2x+AOIxHKKnJFh8e2IcctuSHVOO06t1+ufgpKVn6uRzxz4K1JneTMAcJlath0IvZ7lQdvQ== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2024 14:32:23.5821 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 343031b1-f150-495b-6afd-08dcf8268117 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B070.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7685 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Previously, port information, such as adding and deleting, is updated via route netlink. And the events used are link up/down, not the exact event for port adding or deleting, which does not performance well. To improve the performance, use RDMA monitor events to track port adding and deleting events and update corresponding port information. Signed-off-by: Minggang Li(Gavin) Acked-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 6 ++ drivers/common/mlx5/linux/mlx5_nl.c | 74 ++++++++++++++++++----- drivers/common/mlx5/linux/mlx5_nl.h | 28 +++++++++ drivers/common/mlx5/version.map | 2 + drivers/net/mlx5/linux/mlx5_ethdev_os.c | 79 +++++++++++++++++++++++++ drivers/net/mlx5/linux/mlx5_os.c | 20 +++++++ drivers/net/mlx5/mlx5.h | 2 + 7 files changed, 195 insertions(+), 16 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 981401a9f2..1a9ec1bd62 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1443,6 +1443,12 @@ for an additional list of options shared with other mlx5 drivers. By default, the PMD will set this value to 0. + .. note:: + + There is a race condition in probing port if probe_opt_en is set to 1. + Port probe may fail with wrong ifindex in cache while the interrupt + thread is updating the cache. Please try again if port probe failed. + - ``lacp_by_user`` parameter [int] A nonzero value enables the control of LACP traffic by the user application. diff --git a/drivers/common/mlx5/linux/mlx5_nl.c b/drivers/common/mlx5/linux/mlx5_nl.c index e03db4f918..ce1c2a8e75 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.c +++ b/drivers/common/mlx5/linux/mlx5_nl.c @@ -101,6 +101,7 @@ #ifndef HAVE_RDMA_NL_GROUP_NOTIFY #define RDMA_NL_GROUP_NOTIFY 4 #endif +#define RDMA_NL_GROUP_NOTIFICATION (1 << (RDMA_NL_GROUP_NOTIFY - 1)) /* These are normally found in linux/if_link.h. */ #ifndef HAVE_IFLA_NUM_VF @@ -176,22 +177,6 @@ struct mlx5_nl_mac_addr { int mac_n; /**< Number of addresses in the array. */ }; -#define MLX5_NL_CMD_GET_IB_NAME (1 << 0) -#define MLX5_NL_CMD_GET_IB_INDEX (1 << 1) -#define MLX5_NL_CMD_GET_NET_INDEX (1 << 2) -#define MLX5_NL_CMD_GET_PORT_INDEX (1 << 3) -#define MLX5_NL_CMD_GET_PORT_STATE (1 << 4) - -/** Data structure used by mlx5_nl_cmdget_cb(). */ -struct mlx5_nl_port_info { - const char *name; /**< IB device name (in). */ - uint32_t flags; /**< found attribute flags (out). */ - uint32_t ibindex; /**< IB device index (out). */ - uint32_t ifindex; /**< Network interface index (out). */ - uint32_t portnum; /**< IB device max port number (out). */ - uint16_t state; /**< IB device port state (out). */ -}; - RTE_ATOMIC(uint32_t) atomic_sn; /* Generate Netlink sequence number. */ @@ -2110,3 +2095,60 @@ mlx5_nl_devlink_esw_multiport_get(int nlsk_fd, int family_id, const char *pci_ad *enable ? "en" : "dis", pci_addr); return ret; } + +int +mlx5_nl_rdma_monitor_init(void) +{ + return mlx5_nl_init(NETLINK_RDMA, RDMA_NL_GROUP_NOTIFICATION); +} + +void +mlx5_nl_rdma_monitor_info_get(struct nlmsghdr *hdr, struct mlx5_nl_port_info *data) +{ + size_t off = NLMSG_HDRLEN; + uint8_t event_type = 0; + + if (hdr->nlmsg_type != RDMA_NL_GET_TYPE(RDMA_NL_NLDEV, RDMA_NLDEV_CMD_MONITOR)) + goto error; + + while (off < hdr->nlmsg_len) { + struct nlattr *na = (void *)((uintptr_t)hdr + off); + void *payload = (void *)((uintptr_t)na + NLA_HDRLEN); + + if (na->nla_len > hdr->nlmsg_len - off) + goto error; + switch (na->nla_type) { + case RDMA_NLDEV_ATTR_EVENT_TYPE: + event_type = *(uint8_t *)payload; + if (event_type == RDMA_NETDEV_ATTACH_EVENT) { + data->flags |= MLX5_NL_CMD_GET_EVENT_TYPE; + data->event_type = MLX5_NL_RDMA_NETDEV_ATTACH_EVENT; + } else if (event_type == RDMA_NETDEV_DETACH_EVENT) { + data->flags |= MLX5_NL_CMD_GET_EVENT_TYPE; + data->event_type = MLX5_NL_RDMA_NETDEV_DETACH_EVENT; + } + break; + case RDMA_NLDEV_ATTR_DEV_INDEX: + data->ibindex = *(uint32_t *)payload; + data->flags |= MLX5_NL_CMD_GET_IB_INDEX; + break; + case RDMA_NLDEV_ATTR_PORT_INDEX: + data->portnum = *(uint32_t *)payload; + data->flags |= MLX5_NL_CMD_GET_PORT_INDEX; + break; + case RDMA_NLDEV_ATTR_NDEV_INDEX: + data->ifindex = *(uint32_t *)payload; + data->flags |= MLX5_NL_CMD_GET_NET_INDEX; + break; + default: + DRV_LOG(DEBUG, "Unknown attribute[%d] found", na->nla_type); + break; + } + off += NLA_ALIGN(na->nla_len); + } + + return; + +error: + rte_errno = EINVAL; +} diff --git a/drivers/common/mlx5/linux/mlx5_nl.h b/drivers/common/mlx5/linux/mlx5_nl.h index 396ffc98ce..e32080fa63 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.h +++ b/drivers/common/mlx5/linux/mlx5_nl.h @@ -32,6 +32,27 @@ struct mlx5_nl_vlan_vmwa_context { struct mlx5_nl_vlan_dev vlan_dev[4096]; }; +#define MLX5_NL_CMD_GET_IB_NAME (1 << 0) +#define MLX5_NL_CMD_GET_IB_INDEX (1 << 1) +#define MLX5_NL_CMD_GET_NET_INDEX (1 << 2) +#define MLX5_NL_CMD_GET_PORT_INDEX (1 << 3) +#define MLX5_NL_CMD_GET_PORT_STATE (1 << 4) +#define MLX5_NL_CMD_GET_EVENT_TYPE (1 << 5) + +/** Data structure used by mlx5_nl_cmdget_cb(). */ +struct mlx5_nl_port_info { + const char *name; /**< IB device name (in). */ + uint32_t flags; /**< found attribute flags (out). */ + uint32_t ibindex; /**< IB device index (out). */ + uint32_t ifindex; /**< Network interface index (out). */ + uint32_t portnum; /**< IB device max port number (out). */ + uint16_t state; /**< IB device port state (out). */ + uint8_t event_type; /**< IB RDMA event type (out). */ +}; + +#define MLX5_NL_RDMA_NETDEV_ATTACH_EVENT (1) +#define MLX5_NL_RDMA_NETDEV_DETACH_EVENT (2) + __rte_internal int mlx5_nl_init(int protocol, int groups); __rte_internal @@ -89,4 +110,11 @@ __rte_internal int mlx5_nl_devlink_esw_multiport_get(int nlsk_fd, int family_id, const char *pci_addr, int *enable); +__rte_internal +int mlx5_nl_rdma_monitor_init(void); +__rte_internal +void mlx5_nl_rdma_monitor_info_get(struct nlmsghdr *hdr, struct mlx5_nl_port_info *data); +__rte_internal +int mlx5_nl_rdma_monitor_cap_get(int nl, uint8_t *cap); + #endif /* RTE_PMD_MLX5_NL_H_ */ diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index a2f72ef46a..5230576006 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -146,6 +146,8 @@ INTERNAL { mlx5_nl_vf_mac_addr_modify; # WINDOWS_NO_EXPORT mlx5_nl_vlan_vmwa_create; # WINDOWS_NO_EXPORT mlx5_nl_vlan_vmwa_delete; # WINDOWS_NO_EXPORT + mlx5_nl_rdma_monitor_init; # WINDOWS_NO_EXPORT + mlx5_nl_rdma_monitor_info_get; # WINDOWS_NO_EXPORT mlx5_os_umem_dereg; mlx5_os_umem_reg; diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 88d3c57c6e..5156d96b3a 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -894,6 +894,85 @@ mlx5_dev_interrupt_handler_devx(void *cb_arg) #endif /* HAVE_IBV_DEVX_ASYNC */ } +static void +mlx5_dev_interrupt_ib_cb(struct nlmsghdr *hdr, void *cb_arg) +{ + mlx5_nl_rdma_monitor_info_get(hdr, (struct mlx5_nl_port_info *)cb_arg); +} + +void +mlx5_dev_interrupt_handler_ib(void *arg) +{ + struct mlx5_dev_ctx_shared *sh = arg; + struct mlx5_nl_port_info data = { + .flags = 0, + .name = "", + .ifindex = 0, + .ibindex = 0, + .portnum = 0, + }; + int nlsk_fd = rte_intr_fd_get(sh->intr_handle_ib); + struct mlx5_dev_info *dev_info; + uint32_t i; + + dev_info = &sh->cdev->dev_info; + DRV_LOG(DEBUG, "IB device %s received RDMA monitor netlink event", dev_info->ibname); + if (dev_info->port_num <= 1 || dev_info->port_info == NULL) + return; + + if (nlsk_fd < 0) + return; + + if (mlx5_nl_read_events(nlsk_fd, mlx5_dev_interrupt_ib_cb, &data) < 0) + DRV_LOG(ERR, "Failed to process Netlink events: %s", + rte_strerror(rte_errno)); + + if (!(data.flags & MLX5_NL_CMD_GET_EVENT_TYPE) || + !(data.flags & MLX5_NL_CMD_GET_PORT_INDEX) || + !(data.flags & MLX5_NL_CMD_GET_IB_INDEX)) + return; + + if (data.ibindex != dev_info->ibindex) + return; + + if (data.event_type != MLX5_NL_RDMA_NETDEV_ATTACH_EVENT && + data.event_type != MLX5_NL_RDMA_NETDEV_DETACH_EVENT) + return; + + if (data.event_type == MLX5_NL_RDMA_NETDEV_ATTACH_EVENT && + !(data.flags & MLX5_NL_CMD_GET_NET_INDEX)) + return; + + DRV_LOG(DEBUG, "Event info: type %d, ibindex %d, ifindex %d, portnum %d,", + data.event_type, data.ibindex, data.ifindex, data.portnum); + + /* Changes found in number of SF/VF ports. All information is likely unreliable. */ + if (data.portnum > dev_info->port_num) { + DRV_LOG(ERR, "Port[%d] exceeds maximum[%d]", data.portnum, dev_info->port_num); + goto flush_all; + } + if (data.event_type == MLX5_NL_RDMA_NETDEV_ATTACH_EVENT) { + if (!dev_info->port_info[data.portnum].ifindex) { + dev_info->port_info[data.portnum].ifindex = data.ifindex; + dev_info->port_info[data.portnum].valid = 1; + } else { + DRV_LOG(WARNING, "Duplicate RDMA event for port[%d] ifindex[%d]", + data.portnum, data.ifindex); + if (data.ifindex != dev_info->port_info[data.portnum].ifindex) + goto flush_all; + } + } else if (data.event_type == MLX5_NL_RDMA_NETDEV_DETACH_EVENT) { + memset(dev_info->port_info + data.portnum, 0, sizeof(struct mlx5_port_nl_info)); + } + return; + +flush_all: + for (i = 1; i <= dev_info->port_num; i++) { + dev_info->port_info[i].ifindex = 0; + dev_info->port_info[i].valid = 0; + } +} + /** * DPDK callback to bring the link DOWN. * diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 4537ca0466..16b275c71e 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -3025,6 +3025,21 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) DRV_LOG(ERR, "Failed to allocate intr_handle."); return; } + if (sh->cdev->config.probe_opt && sh->cdev->dev_info.port_num > 1) { + nlsk_fd = mlx5_nl_rdma_monitor_init(); + if (nlsk_fd < 0) { + DRV_LOG(ERR, "Failed to create a socket for RDMA Netlink events: %s", + rte_strerror(rte_errno)); + return; + } + sh->intr_handle_ib = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + nlsk_fd, mlx5_dev_interrupt_handler_ib, sh); + if (sh->intr_handle_ib == NULL) { + DRV_LOG(ERR, "Fail to allocate intr_handle"); + return; + } + } nlsk_fd = mlx5_nl_init(NETLINK_ROUTE, RTMGRP_LINK); if (nlsk_fd < 0) { DRV_LOG(ERR, "Failed to create a socket for Netlink events: %s", @@ -3086,6 +3101,11 @@ mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) if (sh->devx_comp) mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); #endif + fd = rte_intr_fd_get(sh->intr_handle_ib); + mlx5_os_interrupt_handler_destroy(sh->intr_handle_ib, + mlx5_dev_interrupt_handler_ib, sh); + if (fd >= 0) + close(fd); } /** diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 503366580b..adc21c272b 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1574,6 +1574,7 @@ struct mlx5_dev_ctx_shared { struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */ struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */ struct rte_intr_handle *intr_handle_nl; /* Netlink interrupt handler. */ + struct rte_intr_handle *intr_handle_ib; /* Interrupt handler for IB device. */ void *devx_comp; /* DEVX async comp obj. */ struct mlx5_devx_obj *tis[16]; /* TIS object. */ struct mlx5_devx_obj *td; /* Transport domain. */ @@ -2274,6 +2275,7 @@ int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, void mlx5_dev_interrupt_handler(void *arg); void mlx5_dev_interrupt_handler_devx(void *arg); void mlx5_dev_interrupt_handler_nl(void *arg); +void mlx5_dev_interrupt_handler_ib(void *arg); int mlx5_set_link_down(struct rte_eth_dev *dev); int mlx5_set_link_up(struct rte_eth_dev *dev); int mlx5_is_removed(struct rte_eth_dev *dev); From patchwork Tue Oct 29 14:31:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Minggang(Gavin) Li" X-Patchwork-Id: 147604 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 18F5745B4C; Tue, 29 Oct 2024 15:33:10 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7FC1242EA2; Tue, 29 Oct 2024 15:32:55 +0100 (CET) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2073.outbound.protection.outlook.com [40.107.243.73]) by mails.dpdk.org (Postfix) with ESMTP id E8EE842EAB for ; Tue, 29 Oct 2024 15:32:33 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=TkTW5U0lpN9IobdIuKTDXBdpturbocHlTewu5ZttXkW72v8soY5KbPPHw46+89b3JdXYl8eX+JWHpBysnvPK0sutloBzgCm35JHNvIBI35ppLAIu+Z+HobsKfxS8Qx5Jc3FAoAKNiSYYRaya2SK0yHYzj7JdumdbO9tTTGof+LFsVMh0AN0Y8g7AbyUM8lbUAXmI/42A3JzPdWAxIpqNDd8JuVpE6d010w1G5zLPhh3+6Zm/5fTtziiKytpwghqZ8SVG4e5yMc2JBt+JsU2D/F64COKRcuUA2B8TDR07+BEK6/hlPxfuwlo3KSSUcgMVQ9JKsx1nW5ewt9qsPLFbfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/bGvFRV5M8KjSVLTruAl7i7ZnvWWVyZxnUKLHlRPv2A=; b=QJMypKU6zSskMTKTlv+aL1pUnZBOfhG0gjuez5GJQWlkxUDpEhparWTviVoZ+UJg//DAsAPxILUHrGhR8SWInMLVuThdMkEblZwGcINfKckaB3PJUUPWunciDvtKLVoWFZ62Veywyo1+xRnS/0FbmY0tc+XFq+sXDplYxFqq0GyqknLdoTpLMsFb57bbdduTW6D58P9OGgbEC0O6PL9y3ahZml18+y8fKgWMWpyzDJY2RO1kXsWBzSSMgOHBfLsBUtw2xua1uIe8IwDMFJBx7rsU2YCgrcXjM19pzJj3qLgLXoIvwbxPaJqNvHre627hnWz8+vngIKg6NXH04kdMTg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/bGvFRV5M8KjSVLTruAl7i7ZnvWWVyZxnUKLHlRPv2A=; b=tncFjRD3O1PdddFXXLK9XRNC7cgg59jglIIkMM+9dZvR+SaiAAjF5AZDeHU6XgGTgSTw8yuAb+qW6W5U0ujFbF5Qch0BNVj2jSlgpFFesIStOd/Cb7IRSkwuE3MusgOpVc00wXJmR3hNTtajRSZYlxYhBrZBPdELPtRFVVuRKoE5c+bdNv5v34YkmaZaJR8LiSWYeVDG8OCFzR9jn5h9UYet24hZlTUwSJXLGUFivv0Hzv1ClJ+AgZF5YCX7wmalncwjM4P8Hfh7EtzrgCwqn56HDxXbCDnlFVYu895RSXmo3rWpnVnD78FGBgf+mP+VFAjtaiQITSQwB3FnhodKsA== Received: from CH0PR03CA0182.namprd03.prod.outlook.com (2603:10b6:610:e4::7) by LV3PR12MB9401.namprd12.prod.outlook.com (2603:10b6:408:21c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.32; Tue, 29 Oct 2024 14:32:23 +0000 Received: from CH2PEPF00000145.namprd02.prod.outlook.com (2603:10b6:610:e4:cafe::18) by CH0PR03CA0182.outlook.office365.com (2603:10b6:610:e4::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.26 via Frontend Transport; Tue, 29 Oct 2024 14:32:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CH2PEPF00000145.mail.protection.outlook.com (10.167.244.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.16 via Frontend Transport; Tue, 29 Oct 2024 14:32:23 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:56 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 07:31:53 -0700 From: "Minggang Li(Gavin)" To: , , , , Dariusz Sosnowski , Bing Zhao , Suanming Mou CC: , Subject: [PATCH V3 7/7] mlx5: add backward compatibility for RDMA monitor Date: Tue, 29 Oct 2024 16:31:18 +0200 Message-ID: <20241029143118.875214-8-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029143118.875214-1-gavinl@nvidia.com> References: <20241029134256.874767-8-gavinl@nvidia.com> <20241029143118.875214-1-gavinl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000145:EE_|LV3PR12MB9401:EE_ X-MS-Office365-Filtering-Correlation-Id: 566ff828-f5b7-4ce0-b748-08dcf82680e5 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: rq47o2IJp31rKmnVu5HrldOoaL7UZPsXLFYbkG28q+16KgiAACrFkm+t0jj5NC7b5eNs67NO5VAbJp18rC1+gBusyezTqCI8BQsrt6Q99CMBn7+K0dIPhDOQ/04lE9RXmuf9q/c04D378QZ1lMcszzTGi0yrWN9tGk5ZG+TRuAVf1Y6tUPQklBmCsJBIX6xQo0e3q4gVUGTyLHwBhT2mLrzSEJff1r5By+gR9xKuEdlZpnqpbY31YVrq3yBXqjLBsH7wDNNpW9jD7r2XldM2oCYQauFZoLCdpKURMB0oK5S8WjVTnTLYyghqd/kewuILAcvJH5PrV6a4/jLsqiZXnbWca9ZkZd770q/XsuSIRgN43WddnQw48MZ7ht5gMP7KrqyJlmaArleibtFdymnxgXXEUaR3Xqs06CYm2Vu06Sm9gCFAFhgH/0EBRnqvqOKl3BRTAo8bmGwk+2ZCM1jeod9E32W4u7t1VLI/EAnvqwIARIKwBXpoc09pdz3ue/C5AfvE4OiYMvGrujsPw6DdkxeXGO+mW7vpvZdCspsKeRlD3/iErO6CQ1JnX72L2zfAqvg2IxoMfBirXAr1TsS/7T2Roz/9guY7pN1eDV2o7PTgKCJGUMuAJGDWbWo30WFQlv0uSs4uAKQj2L5VPWN6aFb6F/hGupvRJP+WE8NZU01BlX/qunEhlIAOv4an6G1jGpGlmwwwlUv2agX7+9pH+wweWsHfPRrtG9I2Q5QDEamDLQcn76Bk6xXz0dRZmcDw5Ga9mQYcj+V6Z+v1pplzrMmkL/jxDDs/x5tw0jTONm8Y5Y8YJSpNhR34ULWrCEFJ8oR5Y3SRvUPhKDTcQZh3Lcp5d1DRwwtDT0gJNIobanrTQOpIgwo9bJEm8Fui2hvGV0QJlr39/dacCKQqVvyPBBmjS50q0rIh/gJCT8SF6O+3vUqhctV/Ii16i0JcusVP9Tl6TSLVwAzF8XSjNYP1j9fSNhrOKExG/aGP8zqOyCSsXcEsJsaVJc/4HNRaMFkP43a4rHLvhVFeyzshCd6MNEJhjRUmEnq469YkvTu0oj2wJ9DNBmc1MU5k5humj/fQa9RrBkzNYD7kmrkctH5Y4tBAqI2/MAShdg0SeUdGwLdGMzUi5zh/O8MDeWRVq7eLEmMwNt6PsSbr6L41E4sOwoF1U1HRgESB0XxcsKlMy15TVqBBSrJkc7BR7TLZSDLpBDFcLoCnTAUMU1b1SP3M49ZPWNc6626iReQT+z5wIxEOzQvcXzFL+SC61tcAa6wk27sgNJZfEd5v9q/urIIGxJgiArfKk1k8F0HFuX4Txd/VnMUK0KBBlIQrJ9CSaDm7Ma25LjI87DPsRsETwEmQpz4rNtN7lxHANmonxLEg3BswqVZbbpM5p56kAFI7AUUuThoAw1dYEZ6SWp71yFMD6w== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2024 14:32:23.3189 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 566ff828-f5b7-4ce0-b748-08dcf82680e5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000145.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9401 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fallback to the old way to update port information if the kernel driver does not support RDMA monitor. Signed-off-by: Minggang Li(Gavin) Acked-by: Viacheslav Ovsiienko --- doc/guides/rel_notes/release_24_11.rst | 14 +++++ drivers/common/mlx5/linux/mlx5_nl.c | 73 +++++++++++++++++++++++++ drivers/common/mlx5/version.map | 1 + drivers/net/mlx5/linux/mlx5_ethdev_os.c | 2 +- drivers/net/mlx5/linux/mlx5_os.c | 27 +++++++-- drivers/net/mlx5/mlx5.h | 1 + 6 files changed, 111 insertions(+), 7 deletions(-) diff --git a/doc/guides/rel_notes/release_24_11.rst b/doc/guides/rel_notes/release_24_11.rst index fa4822d928..bc868bb74a 100644 --- a/doc/guides/rel_notes/release_24_11.rst +++ b/doc/guides/rel_notes/release_24_11.rst @@ -247,6 +247,20 @@ New Features Added ability for node to advertise and update multiple xstat counters, that can be retrieved using ``rte_graph_cluster_stats_get``. +* **Updated NVIDIA mlx5 driver.** + + Optimized port probe in large scale. + This feature enhances the efficiency of probing VF/SFs on a large scale + by significantly reducing the probing time. To activate this feature, + set ``probe_opt_en`` to a non-zero value during device probing. It + leverages a capability from the RDMA driver, expected to be released in + the upcoming kernel version 6.12 or its equivalent in OFED 24.10, + specifically the RDMA monitor. For additional details on the limitations + of devargs, refer to "doc/guides/nics/mlx5.rst". + + If there are lots of VFs/SFs to be probed by the application, eg, 300 + VFs/SFs, the option should be enabled to save probing time. + Removed Items ------------- diff --git a/drivers/common/mlx5/linux/mlx5_nl.c b/drivers/common/mlx5/linux/mlx5_nl.c index ce1c2a8e75..12f1a620f3 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.c +++ b/drivers/common/mlx5/linux/mlx5_nl.c @@ -2152,3 +2152,76 @@ mlx5_nl_rdma_monitor_info_get(struct nlmsghdr *hdr, struct mlx5_nl_port_info *da error: rte_errno = EINVAL; } + +static int +mlx5_nl_rdma_monitor_cap_get_cb(struct nlmsghdr *hdr, void *arg) +{ + size_t off = NLMSG_HDRLEN; + uint8_t *cap = arg; + + if (hdr->nlmsg_type != RDMA_NL_GET_TYPE(RDMA_NL_NLDEV, RDMA_NLDEV_CMD_SYS_GET)) + goto error; + + *cap = 0; + while (off < hdr->nlmsg_len) { + struct nlattr *na = (void *)((uintptr_t)hdr + off); + void *payload = (void *)((uintptr_t)na + NLA_HDRLEN); + + if (na->nla_len > hdr->nlmsg_len - off) + goto error; + switch (na->nla_type) { + case RDMA_NLDEV_SYS_ATTR_MONITOR_MODE: + *cap = *(uint8_t *)payload; + return 0; + default: + break; + } + off += NLA_ALIGN(na->nla_len); + } + + return 0; + +error: + return -EINVAL; +} + +/** + * Get RDMA monitor support in driver. + * + * + * @param nl + * Netlink socket of the RDMA kind (NETLINK_RDMA). + * @param[out] cap + * Pointer to port info. + * @return + * 0 on success, negative on error and rte_errno is set. + */ +int +mlx5_nl_rdma_monitor_cap_get(int nl, uint8_t *cap) +{ + union { + struct nlmsghdr nh; + uint8_t buf[NLMSG_HDRLEN]; + } req = { + .nh = { + .nlmsg_len = NLMSG_LENGTH(0), + .nlmsg_type = RDMA_NL_GET_TYPE(RDMA_NL_NLDEV, + RDMA_NLDEV_CMD_SYS_GET), + .nlmsg_flags = NLM_F_REQUEST | NLM_F_ACK, + }, + }; + uint32_t sn = MLX5_NL_SN_GENERATE; + int ret; + + ret = mlx5_nl_send(nl, &req.nh, sn); + if (ret < 0) { + rte_errno = -ret; + return ret; + } + ret = mlx5_nl_recv(nl, sn, mlx5_nl_rdma_monitor_cap_get_cb, cap); + if (ret < 0) { + rte_errno = -ret; + return ret; + } + return 0; +} diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 5230576006..8301485839 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -148,6 +148,7 @@ INTERNAL { mlx5_nl_vlan_vmwa_delete; # WINDOWS_NO_EXPORT mlx5_nl_rdma_monitor_init; # WINDOWS_NO_EXPORT mlx5_nl_rdma_monitor_info_get; # WINDOWS_NO_EXPORT + mlx5_nl_rdma_monitor_cap_get; # WINDOWS_NO_EXPORT mlx5_os_umem_dereg; mlx5_os_umem_reg; diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 5156d96b3a..6b2c25a7c2 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -736,7 +736,7 @@ mlx5_dev_interrupt_nl_cb(struct nlmsghdr *hdr, void *cb_arg) if (mlx5_nl_parse_link_status_update(hdr, &if_index) < 0) return; - if (sh->cdev->config.probe_opt && sh->cdev->dev_info.port_num > 1) + if (sh->cdev->config.probe_opt && sh->cdev->dev_info.port_num > 1 && !sh->rdma_monitor_supp) mlx5_handle_port_info_update(&sh->cdev->dev_info, if_index, hdr->nlmsg_type); for (i = 0; i < sh->max_port; i++) { diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 16b275c71e..d3fd77af58 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -3017,6 +3017,7 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) { struct ibv_context *ctx = sh->cdev->ctx; int nlsk_fd; + uint8_t rdma_monitor_supp = 0; sh->intr_handle = mlx5_os_interrupt_handler_create (RTE_INTR_INSTANCE_F_SHARED, true, @@ -3025,20 +3026,34 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) DRV_LOG(ERR, "Failed to allocate intr_handle."); return; } - if (sh->cdev->config.probe_opt && sh->cdev->dev_info.port_num > 1) { + if (sh->cdev->config.probe_opt && + sh->cdev->dev_info.port_num > 1 && + !sh->rdma_monitor_supp) { nlsk_fd = mlx5_nl_rdma_monitor_init(); if (nlsk_fd < 0) { DRV_LOG(ERR, "Failed to create a socket for RDMA Netlink events: %s", rte_strerror(rte_errno)); return; } - sh->intr_handle_ib = mlx5_os_interrupt_handler_create - (RTE_INTR_INSTANCE_F_SHARED, true, - nlsk_fd, mlx5_dev_interrupt_handler_ib, sh); - if (sh->intr_handle_ib == NULL) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); + if (mlx5_nl_rdma_monitor_cap_get(nlsk_fd, &rdma_monitor_supp)) { + DRV_LOG(ERR, "Failed to query RDMA monitor support: %s", + rte_strerror(rte_errno)); + close(nlsk_fd); return; } + sh->rdma_monitor_supp = rdma_monitor_supp; + if (sh->rdma_monitor_supp) { + sh->intr_handle_ib = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + nlsk_fd, mlx5_dev_interrupt_handler_ib, sh); + if (sh->intr_handle_ib == NULL) { + DRV_LOG(ERR, "Fail to allocate intr_handle"); + close(nlsk_fd); + return; + } + } else { + close(nlsk_fd); + } } nlsk_fd = mlx5_nl_init(NETLINK_ROUTE, RTMGRP_LINK); if (nlsk_fd < 0) { diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index adc21c272b..b6be4646ef 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1517,6 +1517,7 @@ struct mlx5_dev_ctx_shared { uint32_t lag_rx_port_affinity_en:1; /* lag_rx_port_affinity is supported. */ uint32_t hws_max_log_bulk_sz:5; + uint32_t rdma_monitor_supp:1; /* Log of minimal HWS counters created hard coded. */ uint32_t hws_max_nb_counters; /* Maximal number for HWS counters. */ uint32_t max_port; /* Maximal IB device port index. */