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(unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id CB6F43F7051; Thu, 5 Jun 2025 04:42:33 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH 1/6] common/cnxk: support link mode configuration Date: Thu, 5 Jun 2025 17:12:15 +0530 Message-ID: <20250605114231.3036050-1-skori@marvell.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Proofpoint-GUID: 8qXu8rRB1mbAiI0d0V3P3NqEtmuow4QE X-Authority-Analysis: v=2.4 cv=F9hXdrhN c=1 sm=1 tr=0 ts=684182ad cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=6IFa9wvqVegA:10 a=M5GUcnROAAAA:8 a=I4B3QrvN1LbncYpy22gA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA1MDEwMCBTYWx0ZWRfX9u+4HEiTOWQQ SgzD6hEkJNV/UzYMtZB+hsqy8sNqSczt+ycQ6upz3JbqOUVXSQprvl6pXS5Aq43JMwrPVqqAlXj M152IxzQ2UZS+fQTaljxPKij5ivHXcj4186TiXMjs398a3gNuKEOnOc4yxHLRmCHZZTEOUHzsb3 x1Lke4TJVX5/cT3Jsn8PnFF5dVRDw9QM/JOLtUHtGTVFux6N9M4a5fb7Bl/IvdeZCZuMA+bznBD Gdnxprik71aELCE68T45DKT1AoKliC8ySAuw35PhmwSN5yrWiRB8KTzPsE3fTinIacHB2sx47cH HmOtwdDvTLjizgzqs2KGPXBBfzy0TAex3cxirozDCNsJn3+JkmSwAlhCApReThu2rGWWtC4BupI G3ixSJVJlKAyiIs4VZwW/uj1uoxpBfPx7t+rtIbhKTxn6eI5+TU1jmAWV1Dw6O90+8p+vjMI X-Proofpoint-ORIG-GUID: 8qXu8rRB1mbAiI0d0V3P3NqEtmuow4QE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-05_02,2025-06-03_02,2025-03-28_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori CGX MAC can be configured into different modes and speeds as mentioned below: - fixed/autoneg - half/full duplex - 10M/100M/1G/10G etc speeds. Sync mailbox and implement that to configure above mentioned settings. Signed-off-by: Sunil Kumar Kori Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/hw/nix.h | 70 ++++++++++++++ drivers/common/cnxk/roc_mbox.h | 15 ++- drivers/common/cnxk/roc_nix.h | 95 ++++++++++++++++++- drivers/common/cnxk/roc_nix_mac.c | 38 +++++++- drivers/common/cnxk/roc_nix_priv.h | 2 + .../common/cnxk/roc_platform_base_symbols.c | 1 + 6 files changed, 211 insertions(+), 10 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index d16fa3b3ec..f344d4de99 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2681,4 +2681,74 @@ struct nix_lso_format { */ #define NIX_CHAN_CPT_X2P_MASK (0x7ffull) +/* CGX lmac types defined by firmware */ +enum cgx_lmac_type { + CGX_LMAC_TYPE_SGMII = 0, + CGX_LMAC_TYPE_XAUI = 1, + CGX_LMAC_TYPE_RXAUI = 2, + CGX_LMAC_TYPE_10G_R = 3, + CGX_LMAC_TYPE_40G_R = 4, + CGX_LMAC_TYPE_QSGMII = 6, + CGX_LMAC_TYPE_25G_R = 7, + CGX_LMAC_TYPE_50G_R = 8, + CGX_LMAC_TYPE_100G_R = 9, + CGX_LMAC_TYPE_USXGMII = 10, + CGX_LMAC_TYPE_USGMII = 11, + CGX_LMAC_TYPE_MAX, +}; + +/* CGX modes defined by firmware */ +enum cgx_mode { + CGX_MODE_SGMII, + CGX_MODE_1000_BASEX, + CGX_MODE_QSGMII, + CGX_MODE_10G_C2C, + CGX_MODE_10G_C2M, + CGX_MODE_10G_KR, + CGX_MODE_20G_C2C, + CGX_MODE_25G_C2C, + CGX_MODE_25G_C2M, + CGX_MODE_25G_2_C2C, + CGX_MODE_25G_CR, + CGX_MODE_25G_KR, + CGX_MODE_40G_C2C, + CGX_MODE_40G_C2M, + CGX_MODE_40G_CR4, + CGX_MODE_40G_KR4, + CGX_MODE_40GAUI_C2C, + CGX_MODE_50G_C2C, + CGX_MODE_50G_C2M, + CGX_MODE_50G_4_C2C, + CGX_MODE_50G_CR, + CGX_MODE_50G_KR, + CGX_MODE_80GAUI_C2C, + CGX_MODE_100G_C2C, + CGX_MODE_100G_C2M, + CGX_MODE_100G_CR4, + CGX_MODE_100G_KR4, + CGX_MODE_LAUI_2_C2C_BIT, + CGX_MODE_LAUI_2_C2M_BIT, + CGX_MODE_50GBASE_CR2_C_BIT, + CGX_MODE_50GBASE_KR2_C_BIT, /* = 30 */ + CGX_MODE_100GAUI_2_C2C_BIT, + CGX_MODE_100GAUI_2_C2M_BIT, + CGX_MODE_100GBASE_CR2_BIT, + CGX_MODE_100GBASE_KR2_BIT, + CGX_MODE_SFI_1G_BIT, + CGX_MODE_25GBASE_CR_C_BIT, + CGX_MODE_25GBASE_KR_C_BIT, + ETH_MODE_SGMII_10M_BIT, + ETH_MODE_SGMII_100M_BIT, /* = 39 */ + ETH_MODE_2500_BASEX_BIT = 42, /* Mode group 1 */ + ETH_MODE_5000_BASEX_BIT, + ETH_MODE_O_USGMII_BIT, + ETH_MODE_Q_USGMII_BIT, + ETH_MODE_2_5G_USXGMII_BIT, + ETH_MODE_5G_USXGMII_BIT, + ETH_MODE_10G_SXGMII_BIT, + ETH_MODE_10G_DXGMII_BIT, + ETH_MODE_10G_QXGMII_BIT, + CGX_MODE_MAX /* = 51 */ +}; + #endif /* __NIX_HW_H__ */ diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index d2192cb6f9..59287253fe 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -764,13 +764,18 @@ struct cgx_lmac_fwdata_s { uint64_t __io supported_fec; uint64_t __io supported_an; uint64_t __io supported_link_modes; - /* Only applicable if AN is supported */ + /* only applicable if AN is supported */ uint64_t __io advertised_fec; - uint64_t __io advertised_link_modes; + uint64_t __io advertised_link_modes_own : 1; /* CGX_CMD_OWN */ + uint64_t __io advertised_link_modes : 63; /* Only applicable if SFP/QSFP slot is present */ struct sfp_eeprom_s sfp_eeprom; struct phy_s phy; -#define LMAC_FWDATA_RESERVED_MEM 1023 + uint32_t __io lmac_type; + uint32_t __io portm_idx; + uint64_t __io mgmt_port : 1; + uint64_t __io port; +#define LMAC_FWDATA_RESERVED_MEM 1018 uint64_t __io reserved[LMAC_FWDATA_RESERVED_MEM]; }; @@ -798,8 +803,10 @@ struct cgx_set_link_mode_args { uint32_t __io speed; uint8_t __io duplex; uint8_t __io an; - uint8_t __io ports; + uint8_t __io mode_baseidx; + uint8_t __io multimode; uint64_t __io mode; + uint64_t __io advertising; }; struct cgx_set_link_mode_req { diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index a9cdc42617..41334327bb 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -16,6 +16,7 @@ #define ROC_NIX_SQB_THRESH 30U #define ROC_NIX_SQB_SLACK 12U #define ROC_NIX_AURA_THRESH 95U +#define ROC_NIX_LINK_SPEED_ALL 0xFFFFF /* Reserved interface types for BPID allocation */ #define ROC_NIX_INTF_TYPE_CGX 0 @@ -109,6 +110,89 @@ enum roc_nix_bpf_stats { ROC_NIX_BPF_RED_OCTS_F_DROP = BIT_ULL(11), }; +enum roc_nix_link_duplex { + ROC_NIX_LINK_DUPLEX_FULL = 0, + ROC_NIX_LINK_DUPLEX_HALF = 1 +}; + +enum roc_nix_link_speed_bits { + ROC_NIX_LINK_SPEED_NONE_BIT = BIT_ULL(0), + ROC_NIX_LINK_SPEED_10M_HD_BIT = BIT_ULL(1), + ROC_NIX_LINK_SPEED_10M_BIT = BIT_ULL(2), + ROC_NIX_LINK_SPEED_100M_HD_BIT = BIT_ULL(3), + ROC_NIX_LINK_SPEED_100M_BIT = BIT_ULL(4), + ROC_NIX_LINK_SPEED_1G_BIT = BIT_ULL(5), + ROC_NIX_LINK_SPEED_2_5G_BIT = BIT_ULL(6), + ROC_NIX_LINK_SPEED_5G_BIT = BIT_ULL(7), + ROC_NIX_LINK_SPEED_10G_BIT = BIT_ULL(8), + ROC_NIX_LINK_SPEED_20G_BIT = BIT_ULL(9), + ROC_NIX_LINK_SPEED_25G_BIT = BIT_ULL(10), + ROC_NIX_LINK_SPEED_40G_BIT = BIT_ULL(11), + ROC_NIX_LINK_SPEED_50G_BIT = BIT_ULL(12), + ROC_NIX_LINK_SPEED_56G_BIT = BIT_ULL(13), + ROC_NIX_LINK_SPEED_100G_BIT = BIT_ULL(14), + ROC_NIX_LINK_SPEED_200G_BIT = BIT_ULL(15), + ROC_NIX_LINK_SPEED_400G_BIT = BIT_ULL(16), + ROC_NIX_LINK_SPEED_MAX = 17 +}; + +enum roc_nix_link_mode { + ROC_NIX_LINK_MODE_10BASET_HD = BIT_ULL(0), + ROC_NIX_LINK_MODE_10BASET_FD = BIT_ULL(1), + ROC_NIX_LINK_MODE_100BASET_HD = BIT_ULL(2), + ROC_NIX_LINK_MODE_100BASET_FD = BIT_ULL(3), + ROC_NIX_LINK_MODE_1000BASET_HD = BIT_ULL(4), + ROC_NIX_LINK_MODE_1000BASET_FD = BIT_ULL(5), + ROC_NIX_LINK_MODE_AUTONEG = BIT_ULL(6), + ROC_NIX_LINK_MODE_10000BASET_FD = BIT_ULL(12), + ROC_NIX_LINK_MODE_2500BASEX_FD = BIT_ULL(15), + ROC_NIX_LINK_MODE_1000BASEKX_FD = BIT_ULL(17), + ROC_NIX_LINK_MODE_10000BASEKX4_FD = BIT_ULL(18), + ROC_NIX_LINK_MODE_10000BASEKR_FD = BIT_ULL(19), + ROC_NIX_LINK_MODE_10000BASER_FEC = BIT_ULL(20), + ROC_NIX_LINK_MODE_20000BASEMLD2_FD = BIT_ULL(21), + ROC_NIX_LINK_MODE_20000BASEKR2_FD = BIT_ULL(22), + ROC_NIX_LINK_MODE_40000BASEKR4_FD = BIT_ULL(23), + ROC_NIX_LINK_MODE_40000BASECR4_FD = BIT_ULL(24), + ROC_NIX_LINK_MODE_40000BASESR4_FD = BIT_ULL(25), + ROC_NIX_LINK_MODE_40000BASELR4_FD = BIT_ULL(26), + ROC_NIX_LINK_MODE_56000BASEKR4_FD = BIT_ULL(27), + ROC_NIX_LINK_MODE_56000BASECR4_FD = BIT_ULL(28), + ROC_NIX_LINK_MODE_56000BASESR4_FD = BIT_ULL(29), + ROC_NIX_LINK_MODE_56000BASELR4_FD = BIT_ULL(30), + ROC_NIX_LINK_MODE_25000BASECR_FD = BIT_ULL(31), + ROC_NIX_LINK_MODE_25000BASEKR_FD = BIT_ULL(32), + ROC_NIX_LINK_MODE_25000BASESR_FD = BIT_ULL(33), + ROC_NIX_LINK_MODE_50000BASECR2_FD = BIT_ULL(34), + ROC_NIX_LINK_MODE_50000BASEKR2_FD = BIT_ULL(35), + ROC_NIX_LINK_MODE_100000BASEKR4_FD = BIT_ULL(36), + ROC_NIX_LINK_MODE_100000BASESR4_FD = BIT_ULL(37), + ROC_NIX_LINK_MODE_100000BASECR4_FD = BIT_ULL(38), + ROC_NIX_LINK_MODE_100000BASELR4_ER4_FD = BIT_ULL(39), + ROC_NIX_LINK_MODE_50000BASESR2_FD = BIT_ULL(40), + ROC_NIX_LINK_MODE_1000BASEX_FD = BIT_ULL(41), + ROC_NIX_LINK_MODE_10000BASECR_FD = BIT_ULL(42), + ROC_NIX_LINK_MODE_10000BASESR_FD = BIT_ULL(43), + ROC_NIX_LINK_MODE_10000BASELR_FD = BIT_ULL(44), + ROC_NIX_LINK_MODE_10000BASELRM_FD = BIT_ULL(45), + ROC_NIX_LINK_MODE_10000BASEER_FD = BIT_ULL(46), + ROC_NIX_LINK_MODE_2500BASET_FD = BIT_ULL(47), + ROC_NIX_LINK_MODE_5000BASET_FD = BIT_ULL(48), + ROC_NIX_LINK_MODE_FEC_NONE = BIT_ULL(49), + ROC_NIX_LINK_MODE_FEC_RS = BIT_ULL(50), + ROC_NIX_LINK_MODE_FEC_BASER = BIT_ULL(51), + ROC_NIX_LINK_MODE_50000BASEKR_FD = BIT_ULL(52), + ROC_NIX_LINK_MODE_50000BASESR_FD = BIT_ULL(53), + ROC_NIX_LINK_MODE_50000BASECR_FD = BIT_ULL(54), + ROC_NIX_LINK_MODE_50000BASELR_ER_FR_FD = BIT_ULL(55), + ROC_NIX_LINK_MODE_50000BASEDR_FD = BIT_ULL(56), + ROC_NIX_LINK_MODE_100000BASEKR2_FD = BIT_ULL(57), + ROC_NIX_LINK_MODE_100000BASESR2_FD = BIT_ULL(58), + ROC_NIX_LINK_MODE_100000BASECR2_FD = BIT_ULL(59), + ROC_NIX_LINK_MODE_100000BASELR2_ER2_FR2_FD = BIT_ULL(60), + ROC_NIX_LINK_MODE_100000BASEDR2_FD = BIT_ULL(61), +}; + struct roc_nix_bpf_cfg { enum roc_nix_bpf_algo alg; enum roc_nix_bpf_lmode lmode; @@ -413,9 +497,17 @@ struct roc_nix_link_info { uint64_t full_duplex : 1; uint64_t lmac_type_id : 4; uint64_t speed : 20; + uint64_t speed_bitmask : 16; uint64_t autoneg : 1; uint64_t fec : 2; uint64_t port : 8; + uint64_t advertising; +}; + +struct roc_nix_mac_fwdata { + uint64_t advertised_link_modes; + uint64_t supported_link_modes; + uint64_t supported_an; }; /** Maximum name length for extended statistics counters */ @@ -502,7 +594,7 @@ struct roc_nix { bool reass_ena; TAILQ_ENTRY(roc_nix) next; -#define ROC_NIX_MEM_SZ (6 * 1112) +#define ROC_NIX_MEM_SZ (6 * 1131) uint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; @@ -865,6 +957,7 @@ void __roc_api roc_nix_mac_link_info_get_cb_unregister(struct roc_nix *roc_nix); int __roc_api roc_nix_q_err_cb_register(struct roc_nix *roc_nix, q_err_get_t sq_err_handle); void __roc_api roc_nix_q_err_cb_unregister(struct roc_nix *roc_nix); int __roc_api roc_nix_mac_stats_reset(struct roc_nix *roc_nix); +int __roc_api roc_nix_mac_fwdata_get(struct roc_nix *roc_nix, struct roc_nix_mac_fwdata *fwdata); /* Ops */ int __roc_api roc_nix_switch_hdr_set(struct roc_nix *roc_nix, diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c index 54db1adf17..08b4f30810 100644 --- a/drivers/common/cnxk/roc_nix_mac.c +++ b/drivers/common/cnxk/roc_nix_mac.c @@ -267,20 +267,19 @@ roc_nix_mac_link_info_set(struct roc_nix *roc_nix, struct cgx_set_link_mode_req *req; int rc; - rc = roc_nix_mac_link_state_set(roc_nix, link_info->status); - if (rc) - goto exit; - req = mbox_alloc_msg_cgx_set_link_mode(mbox); if (req == NULL) { rc = -ENOSPC; goto exit; } + + req->args.advertising = link_info->advertising; req->args.speed = link_info->speed; req->args.duplex = link_info->full_duplex; req->args.an = link_info->autoneg; - rc = mbox_process(mbox); + /* Link mode changes takes more time. */ + rc = mbox_process_tmo(mbox, mbox->rsp_tmo * 4); exit: mbox_put(mbox); return rc; @@ -412,3 +411,32 @@ roc_nix_mac_link_info_get_cb_unregister(struct roc_nix *roc_nix) dev->ops->link_status_get = NULL; } + +int +roc_nix_mac_fwdata_get(struct roc_nix *roc_nix, struct roc_nix_mac_fwdata *data) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct cgx_fw_data *fw_data; + struct dev *dev = &nix->dev; + struct mbox *mbox; + int rc; + + if (roc_nix_is_sdp(roc_nix)) + return 0; + + mbox = mbox_get(dev->mbox); + + mbox_alloc_msg_cgx_get_aux_link_info(mbox); + rc = mbox_process_msg(mbox, (void *)&fw_data); + if (rc) + goto exit; + + nix->supported_link_modes = fw_data->fwdata.supported_link_modes; + nix->advertised_link_modes = fw_data->fwdata.advertised_link_modes; + data->supported_link_modes = nix->supported_link_modes; + data->advertised_link_modes = nix->advertised_link_modes; + data->supported_an = fw_data->fwdata.supported_an; +exit: + mbox_put(mbox); + return rc; +} diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index dc3450a3d4..c949621196 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -138,6 +138,8 @@ struct nix { uint16_t bpid[NIX_MAX_CHAN]; struct nix_qint *qints_mem; struct nix_qint *cints_mem; + uint64_t supported_link_modes; + uint64_t advertised_link_modes; uint8_t configured_qints; uint8_t configured_cints; uint8_t exact_match_ena; diff --git a/drivers/common/cnxk/roc_platform_base_symbols.c b/drivers/common/cnxk/roc_platform_base_symbols.c index 7f0fe601ad..152798e360 100644 --- a/drivers/common/cnxk/roc_platform_base_symbols.c +++ b/drivers/common/cnxk/roc_platform_base_symbols.c @@ -307,6 +307,7 @@ RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_link_info_set) RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_mtu_set) RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_max_rx_len_set) RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_stats_reset) +RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_fwdata_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_link_cb_register) RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_link_cb_unregister) RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_link_info_get_cb_register) From patchwork Thu Jun 5 11:42:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 154059 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 464314688A; 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(unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 903E43F7051; Thu, 5 Jun 2025 04:42:36 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH 2/6] common/cnxk: provide port type from fwdata Date: Thu, 5 Jun 2025 17:12:16 +0530 Message-ID: <20250605114231.3036050-2-skori@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250605114231.3036050-1-skori@marvell.com> References: <20250605114231.3036050-1-skori@marvell.com> MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=YuQPR5YX c=1 sm=1 tr=0 ts=684182b0 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=6IFa9wvqVegA:10 a=M5GUcnROAAAA:8 a=x9mx7A_yV6r5R7-WvSUA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: EI0ANzxNQJknd5RRKZC1G6CV3elrnI-W X-Proofpoint-ORIG-GUID: EI0ANzxNQJknd5RRKZC1G6CV3elrnI-W X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA1MDEwMCBTYWx0ZWRfX60GMGX5VJ3Tl HQYxOWjT02rARDXojsmtxH3/ASQ8fnupy4DNkNbylfNvdT+QDphdEraIBRZXtosW8GzTAwdGXtP ehTgmjCxrC2Q13Qcy3OCAJCyJLebhYo+7reh+CFT2E+U3MlPGht5iQSpxkyUyQrG9uTidQjQUaT EZhiRvksVvulllj5K++MrM+alsfHKlyYFcvNYLvuIUiE2VyKOwOvyCuEBTo2QwI1+5zDE0v/t1x +SMSZVOL+MEobfQ2l7zr/U46ibeMTa0Oi92opE5QuF76PIBCJN4pQQF9Lh4XHSa1EKs7WCfijc4 LF+RfhZkYuTj1Rvayhzo1bSA1Wg7xw2lLo4TPmQ2EcerN/SCx6JBPBjKVWwEkHl3IpPmWK+IT8B PH8lFu3B6nxUp2cS+6VnuQ0unxbZcsbGphZcfkNF5JoEcs6o4YlVo7NVY8I2C6D+D3Bz9OeG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-05_02,2025-06-03_02,2025-03-28_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Retrieves type of port from firmware data. Signed-off-by: Nithin Dabilpuram Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/hw/nix.h | 12 ++++++++++++ drivers/common/cnxk/roc_mbox.h | 13 +++++++++++-- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_mac.c | 1 + 4 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index f344d4de99..c438f18145 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2751,4 +2751,16 @@ enum cgx_mode { CGX_MODE_MAX /* = 51 */ }; +/* CGX Port types from kernel */ +enum cgx_port_type { + CGX_PORT_TP = 0x0, + CGX_PORT_AUI, + CGX_PORT_MII, + CGX_PORT_FIBRE, + CGX_PORT_BNC, + CGX_PORT_DA, + CGX_PORT_NONE = 0xef, + CGX_PORT_OTHER = 0xff, +}; + #endif /* __NIX_HW_H__ */ diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 59287253fe..c819bd2afe 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -755,8 +755,17 @@ enum fec_type { }; struct phy_s { - uint64_t __io can_change_mod_type : 1; - uint64_t __io mod_type : 1; + struct { + uint64_t __io can_change_mod_type : 1; + uint64_t __io mod_type : 1; + uint64_t __io has_fec_stats : 1; + } misc; + struct fec_stats_s { + uint32_t __io rsfec_corr_cws; + uint32_t __io rsfec_uncorr_cws; + uint32_t __io brfec_corr_blks; + uint32_t __io brfec_uncorr_blks; + } fec_stats; }; struct cgx_lmac_fwdata_s { diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 41334327bb..a62ddf4732 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -507,6 +507,7 @@ struct roc_nix_link_info { struct roc_nix_mac_fwdata { uint64_t advertised_link_modes; uint64_t supported_link_modes; + uint64_t port_type; uint64_t supported_an; }; diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c index 08b4f30810..376ff48522 100644 --- a/drivers/common/cnxk/roc_nix_mac.c +++ b/drivers/common/cnxk/roc_nix_mac.c @@ -436,6 +436,7 @@ roc_nix_mac_fwdata_get(struct roc_nix *roc_nix, struct roc_nix_mac_fwdata *data) data->supported_link_modes = nix->supported_link_modes; data->advertised_link_modes = nix->advertised_link_modes; data->supported_an = fw_data->fwdata.supported_an; + data->port_type = fw_data->fwdata.port; exit: mbox_put(mbox); return rc; From patchwork Thu Jun 5 11:42:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 154060 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A00C34688A; Thu, 5 Jun 2025 13:42:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 660F340662; Thu, 5 Jun 2025 13:42:44 +0200 (CEST) Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4985140656 for ; Thu, 5 Jun 2025 13:42:43 +0200 (CEST) Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5559Zlqd005807 for ; Thu, 5 Jun 2025 04:42:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=q OI3WufL1f6RruyDTzo5IOpATF0zSzOrncf0s6TTfV8=; b=E8QH68NNehApvHbPM ZmIHCjokMGycu9Fbv8ROsZUe8J/W58UzczWcsJmiIn6LTfiwpOPQAqyNbUZhw2Y/ 6d9lSbyN++0hYGWPsdeHaxkRCh158R6fSmV+CdoHa8Wk7ZSGuiOalLbDzXYpSxPh DV+3wp9/ZgCUZaOsLmsnbrf58mVfGT8p+HSkGKuQJSNxNAoczcOZ+4qXnLPr8K59 UTJCUnBRFI8jweIuWDqUpw1XKlwP2YRVAekMWvKMI9u3m3OwcSiJFDnvjTQBh7wL L6T0+b8LsQFVjowjUAV8uXOa7T3YiNXBXw+MlooMN/CCMSQ9D5s4ZNrl/VDpNSqK dQ1kA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 4738r7g782-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 05 Jun 2025 04:42:42 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 5 Jun 2025 04:42:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 5 Jun 2025 04:42:41 -0700 Received: from cavium-3070-BM23.. (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 529DE3F7051; Thu, 5 Jun 2025 04:42:39 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH 3/6] net/cnxk: get speed capability from firmware Date: Thu, 5 Jun 2025 17:12:17 +0530 Message-ID: <20250605114231.3036050-3-skori@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250605114231.3036050-1-skori@marvell.com> References: <20250605114231.3036050-1-skori@marvell.com> MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=UNHdHDfy c=1 sm=1 tr=0 ts=684182b2 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=6IFa9wvqVegA:10 a=M5GUcnROAAAA:8 a=3CMRPe03__idA2T9rPcA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA1MDEwMCBTYWx0ZWRfX4wHbKuOuunKH 9GoyKjqzqsHWldNTlfHva7KrLPQv01I7WTJSA33jK7sEBQJSnhxkp5v7b0pL1R4WrqmF372kTG6 e/Cm4tB80gGze8DtJuAR4pIl7mndaSkfcPfOKGVvXvUuwLogKYQwkkScOEYRQnmsPGmy6cq19qW dYguLkKA5q/k0tHVTAyDsbLpv0x4yfIY7h4V6aQQJ6wVN9cENEDDHlo+kquBAlg4pMwFRQEe/yN QAoLT82Cbt1S7iPkWMWMhZSDHexOOrouoeg1UrOaSH911skUylVwyHeufTkZnVpwDEDN29UgxG+ CGfs3a8fET2F8xQ/AKgZebxlpUDnNi/zwzP9B+8+ExZvxE5HAbYHzXTsY6FoeOpV+6S904vi18W /C0XIfg758hC/dHVmez1R08FqURob9proqjEnMF1lMmsRGCK2+V/kTUx+RDVSW43CTOpD+IB X-Proofpoint-ORIG-GUID: IZ_C0xtv9N-Zs7YpdrFiKksY_oSJArG9 X-Proofpoint-GUID: IZ_C0xtv9N-Zs7YpdrFiKksY_oSJArG9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-05_02,2025-06-03_02,2025-03-28_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Currently speed capability is hardcoded to support defined modes and speeds but MAC can support others modes and speed too. This information is populated by firmware. Hence fetching firmware data to provide actual supported modes and speeds by the port. Signed-off-by: Nithin Dabilpuram Signed-off-by: Sunil Kumar Kori --- drivers/net/cnxk/cnxk_ethdev.c | 75 ++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index fc17841bca..89d304be7e 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -7,6 +7,60 @@ #include #include +static const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { + [CGX_MODE_SGMII] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_1000_BASEX] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_QSGMII] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_10G_C2C] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_10G_C2M] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_10G_KR] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_20G_C2C] = RTE_ETH_LINK_SPEED_20G, + [CGX_MODE_25G_C2C] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_C2M] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_2_C2C] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_CR] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_KR] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_40G_C2C] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_C2M] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_CR4] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_KR4] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40GAUI_C2C] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_50G_C2C] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_C2M] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_4_C2C] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_CR] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_KR] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_80GAUI_C2C] = 0, /* No define for 80G */ + [CGX_MODE_100G_C2C] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_C2M] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_CR4] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_KR4] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_LAUI_2_C2C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_LAUI_2_C2M_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50GBASE_CR2_C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50GBASE_KR2_C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_100GAUI_2_C2C_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GAUI_2_C2M_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GBASE_CR2_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GBASE_KR2_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_SFI_1G_BIT] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_25GBASE_CR_C_BIT] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25GBASE_KR_C_BIT] = RTE_ETH_LINK_SPEED_25G, + [ETH_MODE_SGMII_10M_BIT] = RTE_ETH_LINK_SPEED_10M | RTE_ETH_LINK_SPEED_10M_HD, + [ETH_MODE_SGMII_100M_BIT] = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD, + [40] = 0, + [41] = 0, + [ETH_MODE_2500_BASEX_BIT] = RTE_ETH_LINK_SPEED_2_5G, + [ETH_MODE_5000_BASEX_BIT] = RTE_ETH_LINK_SPEED_5G, + [ETH_MODE_O_USGMII_BIT] = RTE_ETH_LINK_SPEED_100M, + [ETH_MODE_Q_USGMII_BIT] = RTE_ETH_LINK_SPEED_1G, + [ETH_MODE_2_5G_USXGMII_BIT] = RTE_ETH_LINK_SPEED_2_5G, + [ETH_MODE_5G_USXGMII_BIT] = RTE_ETH_LINK_SPEED_5G, + [ETH_MODE_10G_SXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, + [ETH_MODE_10G_DXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, + [ETH_MODE_10G_QXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, +}; + cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb; #define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL) @@ -42,14 +96,29 @@ nix_get_tx_offload_capa(struct cnxk_eth_dev *dev) static inline uint32_t nix_get_speed_capa(struct cnxk_eth_dev *dev) { + struct roc_nix_mac_fwdata fwdata; uint32_t speed_capa; + uint8_t mode; + int rc; /* Auto negotiation disabled */ speed_capa = RTE_ETH_LINK_SPEED_FIXED; if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) { - speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G | - RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G | - RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G; + memset(&fwdata, 0, sizeof(fwdata)); + rc = roc_nix_mac_fwdata_get(&dev->nix, &fwdata); + if (rc) { + plt_err("Failed to get MAC firmware data"); + return 0; + } + + if (fwdata.supported_an) + speed_capa = 0; + + /* Translate advertised modes to speed_capa */ + for (mode = 0; mode < CGX_MODE_MAX; mode++) { + if (fwdata.supported_link_modes & BIT_ULL(mode)) + speed_capa |= cnxk_mac_modes[mode]; + } } return speed_capa; From patchwork Thu Jun 5 11:42:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 154061 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F2E924688A; Thu, 5 Jun 2025 13:42:58 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8C1C940665; Thu, 5 Jun 2025 13:42:47 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 097424066C for ; Thu, 5 Jun 2025 13:42:45 +0200 (CEST) Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 554NaOPP000528 for ; Thu, 5 Jun 2025 04:42:45 -0700 DKIM-Signature: v=1; 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(unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 14A343F7051; Thu, 5 Jun 2025 04:42:41 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH 4/6] net/cnxk: support link mode configuration Date: Thu, 5 Jun 2025 17:12:18 +0530 Message-ID: <20250605114231.3036050-4-skori@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250605114231.3036050-1-skori@marvell.com> References: <20250605114231.3036050-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: pbVHgFZF0Sd0rm7gzAaRyhFx0pkLD0o4 X-Authority-Analysis: v=2.4 cv=F9hXdrhN c=1 sm=1 tr=0 ts=684182b5 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=6IFa9wvqVegA:10 a=M5GUcnROAAAA:8 a=83_Lh2SUWi18qvg5i8YA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA1MDEwMCBTYWx0ZWRfX9KTSqvz+A/nX Z8aR7gOcU2jZB4fbHLwCCWetp8aVlSEj/37Aqz5a4pOGHvbltPPZD4pH4rvhem8pdg6ukRJhP9T CJPKYC9IDD8miBvZc97Mizh/S9lhoq1d6g0yC2QQsDiPSXwHZdC4AHk3NaIU/zgIkOxTlrVC0FL rOXlaWxodXFn+5Djpk6VXz38MZG+FkpcMyLbPeZOfvmZnn5q076z8pHDzZbp6z47/70vmRq6m3N RPJNBK/z90I99kvmBmHS+Mkef0y8+D921YdrPDDBEoHhsbWNi7vvWcdU4HRjfaAzRLvzpAgA72t 5+7Kq508fMiwYxytpjNfv8rWQ0ZFyBDMlXWcyEOiwwDwnz+aX1xvhwg1yTPsdtvWbCbK6ufofzj N7hHSCwKZh60kBrJc9V2OC1Ki9AW8uGADDA04DCcqpeRJaLz9NM7Qs4yK6cKyi8/O6YkGapE X-Proofpoint-ORIG-GUID: pbVHgFZF0Sd0rm7gzAaRyhFx0pkLD0o4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-05_02,2025-06-03_02,2025-03-28_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori As a port can be configured to operate on specific mode and speed via struct rte_eth_conf::link_speeds in rte_eth_dev_configure() API. Implement mentioned configuration passed by user. Signed-off-by: Sunil Kumar Kori Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cnxk_ethdev.c | 6 ++ drivers/net/cnxk/cnxk_ethdev.h | 1 + drivers/net/cnxk/cnxk_link.c | 132 +++++++++++++++++++++++++++++++++ 3 files changed, 139 insertions(+) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 89d304be7e..34f391e755 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -3,6 +3,7 @@ */ #include +#include #include #include #include @@ -1609,6 +1610,11 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) eth_dev->data->port_id, ea_fmt, nb_rxq, nb_txq, dev->rx_offloads, dev->tx_offloads); + /* Configure link parameters */ + rc = cnxk_nix_link_info_configure(eth_dev); + if (rc) + plt_warn("Unable to configure requested link attributes, rc=%d continue...", rc); + /* All good */ dev->configured = 1; dev->nb_rxq = data->nb_rx_queues; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 1ced6dd65e..c11a3e6ce0 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -678,6 +678,7 @@ void cnxk_eth_dev_link_status_cb(struct roc_nix *nix, void cnxk_eth_dev_link_status_get_cb(struct roc_nix *nix, struct roc_nix_link_info *link); void cnxk_eth_dev_q_err_cb(struct roc_nix *nix, void *data); +int cnxk_nix_link_info_configure(struct rte_eth_dev *eth_dev); int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete); int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id, uint8_t stat_idx, uint8_t is_rx); diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c index 903b44de2c..0bc56fbb8c 100644 --- a/drivers/net/cnxk/cnxk_link.c +++ b/drivers/net/cnxk/cnxk_link.c @@ -4,6 +4,74 @@ #include "cnxk_ethdev.h" +const enum roc_nix_link_mode mac_to_ethtool_mode[CGX_LMAC_TYPE_MAX][2] = { + [CGX_LMAC_TYPE_SGMII][ROC_NIX_LINK_DUPLEX_HALF] = ROC_NIX_LINK_MODE_1000BASET_HD, + [CGX_LMAC_TYPE_SGMII][ROC_NIX_LINK_DUPLEX_FULL] = ROC_NIX_LINK_MODE_1000BASET_FD, + [CGX_LMAC_TYPE_10G_R][ROC_NIX_LINK_DUPLEX_FULL] = ROC_NIX_LINK_MODE_10000BASESR_FD, + [CGX_LMAC_TYPE_QSGMII][ROC_NIX_LINK_DUPLEX_HALF] = ROC_NIX_LINK_MODE_1000BASET_HD, + [CGX_LMAC_TYPE_QSGMII][ROC_NIX_LINK_DUPLEX_FULL] = ROC_NIX_LINK_MODE_10000BASET_FD, +}; + +const enum roc_nix_link_mode rte_to_ethtool_mode[ROC_NIX_LINK_SPEED_MAX] = { + 0, + ROC_NIX_LINK_MODE_10BASET_HD, + ROC_NIX_LINK_MODE_10BASET_FD, + ROC_NIX_LINK_MODE_100BASET_HD, + ROC_NIX_LINK_MODE_100BASET_FD, + ROC_NIX_LINK_MODE_1000BASET_FD, + ROC_NIX_LINK_MODE_2500BASEX_FD, + 0, + ROC_NIX_LINK_MODE_10000BASESR_FD, + 0, + ROC_NIX_LINK_MODE_25000BASESR_FD, + ROC_NIX_LINK_MODE_40000BASELR4_FD, + ROC_NIX_LINK_MODE_50000BASELR_ER_FR_FD, + 0, + ROC_NIX_LINK_MODE_100000BASELR4_ER4_FD, + 0, + 0, +}; + +static uint64_t +nix_link_advertising_get(struct cnxk_eth_dev *dev, struct roc_nix_link_info *link_info) +{ + struct roc_nix_mac_fwdata fwdata; + struct roc_nix_link_info linfo; + uint64_t advertise = 0; + int bit, rc; + + memset(&fwdata, 0, sizeof(fwdata)); + rc = roc_nix_mac_fwdata_get(&dev->nix, &fwdata); + if (rc) { + plt_err("Failed to get MAC firmware data"); + goto exit; + } + + memset(&linfo, 0, sizeof(linfo)); + rc = roc_nix_mac_link_info_get(&dev->nix, &linfo); + if (rc) { + plt_err("Failed to get MAC link info"); + goto exit; + } + + if (link_info->autoneg) { + if (!fwdata.supported_an) { + plt_err("Autoneg is not supported"); + goto exit; + } else { + for (bit = 0; bit < ROC_NIX_LINK_SPEED_MAX; bit++) { + if (link_info->speed_bitmask & BIT_ULL(bit)) + advertise |= rte_to_ethtool_mode[bit]; + } + goto exit; + } + } + + advertise |= mac_to_ethtool_mode[linfo.lmac_type_id][link_info->full_duplex]; +exit: + return advertise; +} + void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set) { @@ -146,3 +214,67 @@ cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) return rte_eth_linkstatus_set(eth_dev, &link); } + +int +cnxk_nix_link_info_configure(struct rte_eth_dev *eth_dev) +{ + uint32_t speed_map[] = { + RTE_ETH_SPEED_NUM_NONE, RTE_ETH_SPEED_NUM_10M, RTE_ETH_SPEED_NUM_10M, + RTE_ETH_SPEED_NUM_100M, RTE_ETH_SPEED_NUM_100M, RTE_ETH_SPEED_NUM_1G, + RTE_ETH_SPEED_NUM_2_5G, RTE_ETH_SPEED_NUM_5G, RTE_ETH_SPEED_NUM_10G, + RTE_ETH_SPEED_NUM_20G, RTE_ETH_SPEED_NUM_25G, RTE_ETH_SPEED_NUM_40G, + RTE_ETH_SPEED_NUM_50G, RTE_ETH_SPEED_NUM_56G, RTE_ETH_SPEED_NUM_100G, + RTE_ETH_SPEED_NUM_200G, RTE_ETH_SPEED_NUM_400G + }; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct rte_eth_dev_data *data = eth_dev->data; + struct rte_eth_conf *conf = &data->dev_conf; + uint32_t link_speeds = conf->link_speeds; + struct roc_nix_link_info link_info = {0}; + struct roc_nix *nix = &dev->nix; + uint32_t speed = link_speeds; + bool fixed; + + plt_info("User passed link configuration: %x", link_speeds); + + if (!roc_nix_is_pf(nix) || link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) + return 0; + + fixed = link_speeds & RTE_ETH_LINK_SPEED_FIXED ? true : false; + if (fixed) { + if (rte_popcount32(link_speeds) == 1) { + plt_err("Desired speed is not specified in FIXED mode"); + return -EINVAL; + } + + if (rte_popcount32(link_speeds) > 2) { + plt_err("Multiple speeds can't be configured in FIXED mode"); + return -EINVAL; + } + + link_info.autoneg = 0; + } else { + link_info.autoneg = 1; + } + + speed >>= 1; + link_info.speed = speed_map[rte_bsf32(speed) + 1]; + link_info.speed_bitmask = link_speeds & ~RTE_ETH_LINK_SPEED_FIXED; + link_info.full_duplex = ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || + (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) ? + ROC_NIX_LINK_DUPLEX_HALF : + ROC_NIX_LINK_DUPLEX_FULL; + link_info.advertising = nix_link_advertising_get(dev, &link_info); + if (link_info.advertising == 0) { + plt_err("advertising bitmap is not set"); + return -EINVAL; + } + + plt_info("Following link settings are sent to firmware:"); + plt_info("Advertised modes: %lx", link_info.advertising); + plt_info("speed: %u", link_info.speed); + plt_info("duplex: %s", link_info.full_duplex == ROC_NIX_LINK_DUPLEX_HALF ? + "half-duplex" : "full-duplex"); + plt_info("autoneg: %s", link_info.autoneg ? "enabled" : "disabled"); + return roc_nix_mac_link_info_set(nix, &link_info); +} From patchwork Thu Jun 5 11:42:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 154062 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4F064688A; Thu, 5 Jun 2025 13:43:04 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9A7EC4065E; Thu, 5 Jun 2025 13:42:50 +0200 (CEST) Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 623F140656 for ; Thu, 5 Jun 2025 13:42:49 +0200 (CEST) Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5559Zlqf005807 for ; Thu, 5 Jun 2025 04:42:48 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=9 0lJGda3e7UPWdajvW6elHCS9CTYqwlh9RarTUreqro=; b=BEDJPPIVUIe53kIWJ X5z03XmNgvimsg5UEEtU1CjO1ETpjMG6w9GKKLW7Plq9y+3zeTXv+3DToMhOe77S Gtv7/ukh5EO9w+bzrIt6UCQdpSvyfiKVXTRkmZPdooWqWLL/rhPYqXOulVOPK3Nf aKz5cxxNVDe2Wy4/oW5RwwIJOqsoWHynjStlC7i8P/qDyHE7v26Ky1QOF3bcbij/ PYasn6m3vqyed17IyCk7wlA40smFgQeCw0ssajJZIrWErYgCs5DMpi9yup999mqi LcKpocRB1Efi17hWpaCDZ9W5NHCcx6IzCgYls3MpKRW1k3GwsD3AdczqAoCKcubz old1w== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 4738r7g78b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 05 Jun 2025 04:42:48 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 5 Jun 2025 04:42:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 5 Jun 2025 04:42:47 -0700 Received: from cavium-3070-BM23.. (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id D7FBE3F7051; Thu, 5 Jun 2025 04:42:44 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH 5/6] net/cnxk: report link type and status Date: Thu, 5 Jun 2025 17:12:19 +0530 Message-ID: <20250605114231.3036050-5-skori@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250605114231.3036050-1-skori@marvell.com> References: <20250605114231.3036050-1-skori@marvell.com> MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=UNHdHDfy c=1 sm=1 tr=0 ts=684182b8 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=6IFa9wvqVegA:10 a=M5GUcnROAAAA:8 a=Ax6jqZJi9XUBVAB8cagA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA1MDEwMCBTYWx0ZWRfX4CAL2h45WOwK eq2FcW/v3yJjy40scSOCwLDx1lgYxs/V85I1kl+DDbF4M9mptIfsI1mdNzuRWcmZFPiH6CKEjpl DvtZA7DjXLKZmA6Ra47bVvmCNt7rLyOASrZ0x9t8q6O+jeDVL3/7LU6gCsmRSgviuzuJiCI2Ecg AMmSL6Noq9bsUZDtnaUKydFz3vCgxXjEQK+mGfkF+eD9WdCVb6ow+pMAPvlZnOUiEUqRwd3ug3/ I6PyY6fR1MJnSSzGDmwGixAGMZD3AJflKkLJ+pZy0DkewsuCsVJZ8aeBYa6uoDc6P9eD55seUQz /44ffK6Xsrl/WRc0SmSjCcvoOpO6oWAN8baD1F0FazhTYXoIWZee5iJeevv8mhqBK/VbVUs+xGS 68hjSgNdLSmPZodEroSVS3+WXx+UWqSbyzT4MAwD7dZfm6C8cGVCTZY2UleTk6tlUyVHcXMs X-Proofpoint-ORIG-GUID: JzVKHu5sCC1oy9LT1VUOwpmnSynlF3nL X-Proofpoint-GUID: JzVKHu5sCC1oy9LT1VUOwpmnSynlF3nL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-05_02,2025-06-03_02,2025-03-28_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Retrieves type of port i.e. twisted pair, fibre etc from firmware and reports the same to user. Signed-off-by: Nithin Dabilpuram Signed-off-by: Sunil Kumar Kori --- drivers/net/cnxk/cnxk_ethdev.c | 19 +++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev.h | 1 + drivers/net/cnxk/cnxk_link.c | 10 +++++++--- 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 34f391e755..d5df73cc91 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -62,6 +62,17 @@ static const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { [ETH_MODE_10G_QXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, }; +static const uint8_t cnxk_port_type[] = { + [CGX_PORT_TP] = RTE_ETH_LINK_TYPE_TP, + [CGX_PORT_AUI] = RTE_ETH_LINK_TYPE_AUI, + [CGX_PORT_MII] = RTE_ETH_LINK_TYPE_MII, + [CGX_PORT_FIBRE] = RTE_ETH_LINK_TYPE_FIBRE, + [CGX_PORT_BNC] = RTE_ETH_LINK_TYPE_BNC, + [CGX_PORT_DA] = RTE_ETH_LINK_TYPE_DA, + [CGX_PORT_NONE] = RTE_ETH_LINK_TYPE_NONE, + [CGX_PORT_OTHER] = RTE_ETH_LINK_TYPE_OTHER, +}; + cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb; #define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL) @@ -98,6 +109,7 @@ static inline uint32_t nix_get_speed_capa(struct cnxk_eth_dev *dev) { struct roc_nix_mac_fwdata fwdata; + struct rte_eth_link link; uint32_t speed_capa; uint8_t mode; int rc; @@ -120,6 +132,12 @@ nix_get_speed_capa(struct cnxk_eth_dev *dev) if (fwdata.supported_link_modes & BIT_ULL(mode)) speed_capa |= cnxk_mac_modes[mode]; } + dev->link_type = cnxk_port_type[(uint8_t)fwdata.port_type]; + + /* Set link type at init */ + memset(&link, 0, sizeof(link)); + link.link_type = dev->link_type; + rte_eth_linkstatus_set(dev->eth_dev, &link); } return speed_capa; @@ -1784,6 +1802,7 @@ cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev) /* Bring down link status internally */ memset(&link, 0, sizeof(link)); + link.link_type = dev->link_type; rte_eth_linkstatus_set(eth_dev, &link); return 0; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index c11a3e6ce0..17734b806b 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -370,6 +370,7 @@ struct cnxk_eth_dev { uint64_t rx_offload_capa; uint64_t tx_offload_capa; uint32_t speed_capa; + uint8_t link_type; /* Configured Rx and Tx offloads */ uint64_t rx_offloads; uint64_t tx_offloads; diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c index 0bc56fbb8c..a074f6f65e 100644 --- a/drivers/net/cnxk/cnxk_link.c +++ b/drivers/net/cnxk/cnxk_link.c @@ -115,14 +115,16 @@ static void nix_link_status_print(struct rte_eth_dev *eth_dev, struct rte_eth_link *link) { if (link && link->link_status) - plt_info("Port %d: Link Up - speed %u Mbps - %s", + plt_info("Port %d: Link Up - speed %u Mbps - %s - %s", (int)(eth_dev->data->port_id), (uint32_t)link->link_speed, link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX ? "full-duplex" - : "half-duplex"); + : "half-duplex", + rte_eth_link_type_to_str(link->link_type)); else - plt_info("Port %d: Link Down", (int)(eth_dev->data->port_id)); + plt_info("Port %d: Link Down - %s", (int)(eth_dev->data->port_id), + rte_eth_link_type_to_str(link->link_type)); } void @@ -171,6 +173,7 @@ cnxk_eth_dev_link_status_cb(struct roc_nix *nix, struct roc_nix_link_info *link) eth_link.link_speed = link->speed; eth_link.link_autoneg = RTE_ETH_LINK_AUTONEG; eth_link.link_duplex = link->full_duplex; + eth_link.link_type = dev->link_type; /* Print link info */ nix_link_status_print(eth_dev, ð_link); @@ -210,6 +213,7 @@ cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) link.link_autoneg = RTE_ETH_LINK_AUTONEG; if (info.full_duplex) link.link_duplex = info.full_duplex; + link.link_type = dev->link_type; } return rte_eth_linkstatus_set(eth_dev, &link); From patchwork Thu Jun 5 11:42:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 154063 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3E2E84688A; Thu, 5 Jun 2025 13:43:13 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3614940670; Thu, 5 Jun 2025 13:42:53 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D716F4067B for ; Thu, 5 Jun 2025 13:42:51 +0200 (CEST) Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 554NaOPQ000528 for ; Thu, 5 Jun 2025 04:42:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=E RnQZw10KJykvycrz1FfCO4FR4XYjoPXfDeP+XELlL8=; b=OKJg1tDZD7y3gAQSX iFveiBikgC5zHpt+6u8Jw0v5q6rLE3HOKjP/Jy/R/qyCYn9HFD4JD61M+gwYpcFX w2ArHS5PTgYgXnmN2diVPwtjDRDAfvdqPj0LQvyqgbG+VF3NpubiwAtGoJecRIAx iNY6ul+YLPSxfrgP3cOw8qjqc/bSG8Suwp4gFNI+RolOGPXs5HzTd+RfAZ9srz2/ DBX6uqIW+03Aaq8RJjwv0DAJkRiryfcOwA05+4NEsDOqUsj7hrpwCyHftjehQNIn E8o1MFJAY//rpDX+zDMQl6rtsXLPYkxGh5Hq00dcuFRnhNEOE50SLnslw9uABKj1 fWehA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 472yyb9a42-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 05 Jun 2025 04:42:51 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 5 Jun 2025 04:42:49 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 5 Jun 2025 04:42:49 -0700 Received: from cavium-3070-BM23.. (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id A4B073F7051; Thu, 5 Jun 2025 04:42:47 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH 6/6] net/cnxk: report link mode Date: Thu, 5 Jun 2025 17:12:20 +0530 Message-ID: <20250605114231.3036050-6-skori@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250605114231.3036050-1-skori@marvell.com> References: <20250605114231.3036050-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 2vMV3rkDkN9r4gJxaeQOsgITDclw7Za7 X-Authority-Analysis: v=2.4 cv=F9hXdrhN c=1 sm=1 tr=0 ts=684182bb cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=6IFa9wvqVegA:10 a=M5GUcnROAAAA:8 a=koTAqf3Ast2ZiasxKz8A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA1MDEwMCBTYWx0ZWRfX6kno6h0kcmfk jCPoTxiHo9YZwTmcqNBbRFDYX+wy4vW69648OGCy5cFg/3LS8z8/rfRZV5IUKtNgvt/vkPeud3N mbhh3romypOdv81DylJVvQU1oP678dS3BgphuoDMAX1Ujr4OL3PZens7XZVhX3ND1CzSTQU5Y2l Bv3YkhTIF+OiIWBJsAR1XND9V4humZa/Liaw0PUGhZpgP6wTqzN7xnxYkXnggaRy0zAbUEP8eRB jdUt0dLA4LH8Gj4eqSuL/N6x2E/ERJNyQsruHlNuaO9cat7HVnYXS0fG6BOSRnKcG2OAYPngZA6 JnKooaxDOqDTI8suTWhC0mLlwuMZW8/psn359sULrdNCmYRMDxZ8gJBm7zk8i56IZf83opWeVmH 9aXHRf+ZwxteKfqgsqhItgEe4BuVI9ZRU45JDQJZ2jIEoKhqcKUbEAu4UMYzYlkUnZCW8KcR X-Proofpoint-ORIG-GUID: 2vMV3rkDkN9r4gJxaeQOsgITDclw7Za7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-05_02,2025-06-03_02,2025-03-28_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Reports link mode whether fixed or autonegotiation Depends-on: patch-35378 ("ethdev: add support to provide link type") Signed-off-by: Nithin Dabilpuram Signed-off-by: Sunil Kumar Kori --- drivers/net/cnxk/cnxk_link.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c index a074f6f65e..d2b2372871 100644 --- a/drivers/net/cnxk/cnxk_link.c +++ b/drivers/net/cnxk/cnxk_link.c @@ -171,7 +171,7 @@ cnxk_eth_dev_link_status_cb(struct roc_nix *nix, struct roc_nix_link_info *link) eth_link.link_status = link->status; eth_link.link_speed = link->speed; - eth_link.link_autoneg = RTE_ETH_LINK_AUTONEG; + eth_link.link_autoneg = link->autoneg ? RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED; eth_link.link_duplex = link->full_duplex; eth_link.link_type = dev->link_type; @@ -210,7 +210,7 @@ cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) return rc; link.link_status = info.status; link.link_speed = info.speed; - link.link_autoneg = RTE_ETH_LINK_AUTONEG; + link.link_autoneg = info.autoneg ? RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED; if (info.full_duplex) link.link_duplex = info.full_duplex; link.link_type = dev->link_type;