From patchwork Sat Apr 6 14:27:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob X-Patchwork-Id: 52368 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9DAFA3576; Sat, 6 Apr 2019 16:28:25 +0200 (CEST) Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) by dpdk.org (Postfix) with ESMTP id 392BD34F3 for ; Sat, 6 Apr 2019 16:28:24 +0200 (CEST) Received: by mail-pf1-f195.google.com with SMTP id w25so3454008pfi.9 for ; Sat, 06 Apr 2019 07:28:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5+XZ9MpJ57nnOoZqvrcM9a7WTriq2hN1jRkmPvgLpd0=; b=BjnuTRMIN318k+8c6YJnHIbpITZUqbC8v2S7+VpqeCgqQ2kAA/PFqbFjtEa6z6BIny tCXDnjIo2o0yQ7JDUO9AOKMwu2EauCzMpMYxlr4Bszbm6PRenpPEn0Sy4jG2m8OupMiu RYjlc6TNDtMTfwCdw9G59kWXDVYDojDtuQnWlFCERQoYyji012QanttSlzp4LKwliDnc Oe4LpjMAQk99dHlc5MFErei28TfX9Edy6QZuBLOROLSahTV9dyQlB+jkrZr7ut6pkpor YrdpAKwMcaxDqcguE4BpIfivs9W1Ee8FB4D2Yr1JLm+63rIWlmhjg2x/vW6pf7qD9FH+ 38Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5+XZ9MpJ57nnOoZqvrcM9a7WTriq2hN1jRkmPvgLpd0=; b=mdqsUgfQG1Xt33uZZnpqUXCfV0p9R/0Z2RC+z6T2x7KIml1Pzv3oEKe3rXEkEiu9Rw V+fi2OoMTwhgPDCLXpO4IOTfuTNFvriv9YVANWp1uEegDQ1l0OYT3tEfyYRFPSGQp3tn GrZrFhqMtVf5JUAWGgWgGS9nXhOrSeaLnnfPS+70jIz/aRrqr5Da+fO3uqeiPeCIwDzo voltgsNaljXx4M5ln3qc/iHUldRB9PMx3Z9er0x7he/MdCHzeaZTcfz00mAaFZvCU+eZ PxJy44dXbTdXe/tKKEyCzjjTL+rQbodmLNPErfQlRub5qif7tOjShZd5TF5lSLAtyFGi ULbw== X-Gm-Message-State: APjAAAXWg9PmMs/+/ItHArtRb10XWU6FiBKtLJgnCiO0dKrlHyCU/0Ye oEsykek9YGGzniXP2gHCDOHBgR3BND8= X-Google-Smtp-Source: APXvYqxxY/cFZL5LvxKEAhJ43Oj937Llhpg8xdvzohS0uFITUa3jYvmeIvd9+/LjN7PPlQuw3cPbTg== X-Received: by 2002:aa7:9a89:: with SMTP id w9mr11546360pfi.213.1554560903178; Sat, 06 Apr 2019 07:28:23 -0700 (PDT) Received: from jerin.caveonetworks.com ([223.226.40.87]) by smtp.gmail.com with ESMTPSA id o5sm84199008pfa.135.2019.04.06.07.28.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 06 Apr 2019 07:28:22 -0700 (PDT) From: jerinjacobk@gmail.com X-Google-Original-From: jerinj@marvell.com To: Thomas Monjalon Cc: dev@dpdk.org, Jerin Jacob , Pavan Nikhilesh Date: Sat, 6 Apr 2019 19:57:34 +0530 Message-Id: <20190406142737.20091-1-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190318164949.2357-1-jerinj@marvell.com> References: <20190318164949.2357-1-jerinj@marvell.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 1/4] mk: introduce helper to check valid compiler argument X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Introduce rte_cc_has_argument() Makefile helper to check a given argument is support by the compiler. Example Usage: include $(RTE_SDK)/mk/rte.helper.mk MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2) This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS if it is only supported by the compiler. The use case for such scheme is to enable the mcpu optimization if the compiler supports else it needs to compile the source code without any errors. This patch also moves inclusion of toolchain's rte.vars.mk to before the machine's rte.vars.mk inclusion to make correct CC available for the cross compile case. Signed-off-by: Jerin Jacob Signed-off-by: Pavan Nikhilesh --- Change history of this series: v7 Changes: - Updated cross compile config files align with "build: improve pcap dependency handling" changeset to fix build issue with meson - Some compiler needs the following depended patch to compile with meson http://patches.dpdk.org/patch/52367/ v6 Changes: - Rework to change the config files to sync with "mk: use linux and freebsd in config names" - Fix the following error with latest gcc by fixing the mcpu type cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch v5 Changes: - Fix incorrect meson flag parsing(Phil Yang) - Squash meson cross build patch(5/5) into configuration update patches for thunderx2(3/5) and octeontx2(4/5)(Thomas) - Changed octeontx2's march as armv8-a and added the extension required instead of armv8-2a(Phil Yang) - Improved rte_cc_has_argument() implementaion by removing the temp file(Thomas) v4 Changes: - Fix incorrect signoff marrvell -> marvell. v3 Changes: - Squash meson build support into config support for thunderx2/octeontx2. v2 Changes: - Add meson build support. --- mk/rte.helper.mk | 10 ++++++++++ mk/target/generic/rte.vars.mk | 22 +++++++++++----------- 2 files changed, 21 insertions(+), 11 deletions(-) create mode 100644 mk/rte.helper.mk diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk new file mode 100644 index 000000000..6e7fd03d7 --- /dev/null +++ b/mk/rte.helper.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Marvell International Ltd + +# rte_cc_has_argument +# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f) +# Return the argument if the argument is supported by the compiler. +# +define rte_cc_has_argument + $(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1)) +endef diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk index dd149acc9..25a578ad7 100644 --- a/mk/target/generic/rte.vars.mk +++ b/mk/target/generic/rte.vars.mk @@ -7,6 +7,17 @@ # executive environment. # +# +# toolchain: +# +# - define CC, LD, AR, AS, ... +# - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value) +# - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value) +# - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value) +# - may override any previously defined variable +# +include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk + # # machine: # @@ -45,17 +56,6 @@ endif # include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk -# -# toolchain: -# -# - define CC, LD, AR, AS, ... -# - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value) -# - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value) -# - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value) -# - may override any previously defined variable -# -include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk - # # exec-env: # From patchwork Sat Apr 6 14:27:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob X-Patchwork-Id: 52369 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 061074C96; Sat, 6 Apr 2019 16:28:31 +0200 (CEST) Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by dpdk.org (Postfix) with ESMTP id B5DA34C96 for ; Sat, 6 Apr 2019 16:28:29 +0200 (CEST) Received: by mail-pf1-f194.google.com with SMTP id y13so4899676pfm.11 for ; Sat, 06 Apr 2019 07:28:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Eafi/uPL5ecY/xhRQYiAdpY6E8uOqNwAjaF3LQtbfc=; b=IxD7Ws02/PgrcSk/FtVDZUGPCQzr4zSB4ZqG20bpoiizzStLFwT5GgRSzM4xpSN1ee LQZphLrDcXdBjSicRn0JpUT7T2HbVE93QJy65oZaE5YSRr+a9YiYYjsqKzbPcdYV5UG/ lnqsoDKGl8KmZpWdoaRCHyd1NEWOqnkdwPBjowmeD5uUTycDPoGquzoh9wzA7xB90lru kdWSf0xtGbYR0vvB4GNebEonDsyTXRBu+Qp44dCt27w7Q+ZS52MxuexINMbZPsIlVcTy OE7H3Wfah5oS0LEN3enl3zXpb3ls9cPOOGpRqU5DuhSPVcsaaL6HjhM0tBbykzHv2MKB ejnw== X-Google-DKIM-Signature: v=1; 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Sat, 06 Apr 2019 07:28:28 -0700 (PDT) From: jerinjacobk@gmail.com X-Google-Original-From: jerinj@marvell.com To: Thomas Monjalon Cc: dev@dpdk.org, Pavan Nikhilesh , Jerin Jacob Date: Sat, 6 Apr 2019 19:57:35 +0530 Message-Id: <20190406142737.20091-2-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190406142737.20091-1-jerinj@marvell.com> References: <20190318164949.2357-1-jerinj@marvell.com> <20190406142737.20091-1-jerinj@marvell.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Currently, RTE_* flags are set based on the implementer ID but there might be some micro arch specific differences from the same vendor eg. CACHE_LINESIZE. Add support to set micro arch specific flags. Signed-off-by: Pavan Nikhilesh Signed-off-by: Jerin Jacob --- config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 170a4981a..8de3f3e3a 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -52,12 +52,10 @@ flags_generic = [ ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] flags_cavium = [ - ['RTE_MACHINE', '"thunderx"'], ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_USE_C11_MEM_MODEL', false]] + ['RTE_MAX_VFIO_GROUPS', 128]] flags_dpaa = [ ['RTE_MACHINE', '"dpaa"'], ['RTE_USE_C11_MEM_MODEL', true], @@ -71,6 +69,27 @@ flags_dpaa2 = [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] +flags_default_extra = [] +flags_thunderx_extra = [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_USE_C11_MEM_MODEL', false]] + +machine_args_generic = [ + ['default', ['-march=armv8-a+crc+crypto']], + ['native', ['-march=native']], + ['0xd03', ['-mcpu=cortex-a53']], + ['0xd04', ['-mcpu=cortex-a35']], + ['0xd07', ['-mcpu=cortex-a57']], + ['0xd08', ['-mcpu=cortex-a72']], + ['0xd09', ['-mcpu=cortex-a73']], + ['0xd0a', ['-mcpu=cortex-a75']]] + +machine_args_cavium = [ + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], + ['native', ['-march=native']], + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] @@ -157,8 +176,16 @@ else endif foreach marg: machine[2] if marg[0] == impl_pn - foreach f: marg[1] - machine_args += f + foreach flag: marg[1] + if cc.has_argument(flag) + machine_args += flag + endif + endforeach + # Apply any extra machine specific flags. + foreach flag: marg.get(2, flags_default_extra) + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif endforeach endif endforeach From patchwork Sat Apr 6 14:27:36 2019 Content-Type: text/plain; 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Sat, 06 Apr 2019 07:28:32 -0700 (PDT) From: jerinjacobk@gmail.com X-Google-Original-From: jerinj@marvell.com To: Thomas Monjalon Cc: dev@dpdk.org, Jerin Jacob , Pavan Nikhilesh , Gavin Hu Date: Sat, 6 Apr 2019 19:57:36 +0530 Message-Id: <20190406142737.20091-3-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190406142737.20091-1-jerinj@marvell.com> References: <20190318164949.2357-1-jerinj@marvell.com> <20190406142737.20091-1-jerinj@marvell.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 3/4] config: add thunderx2 machine config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Optimized configuration for Marvell thunderx2 SoC. Updated meson build to support Marvell thunderx2 SoC. Added meson cross compile target. Product details are here: https://www.marvell.com/server-processors/thunderx2-arm-processors/ Signed-off-by: Jerin Jacob Signed-off-by: Pavan Nikhilesh Reviewed-by: Gavin Hu --- config/arm/arm64_thunderx2_linux_gcc | 16 +++++++++ config/arm/meson.build | 9 ++++- config/defconfig_arm64-thunderx2-linux-gcc | 1 + config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++ mk/machine/thunderx2/rte.vars.mk | 34 +++++++++++++++++++ 5 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 config/arm/arm64_thunderx2_linux_gcc create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc create mode 100644 mk/machine/thunderx2/rte.vars.mk diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc new file mode 100644 index 000000000..0dc275644 --- /dev/null +++ b/config/arm/arm64_thunderx2_linux_gcc @@ -0,0 +1,16 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' +strip = 'aarch64-linux-gnu-strip' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = '0x43' +implementor_pn = '0xaf' diff --git a/config/arm/meson.build b/config/arm/meson.build index 8de3f3e3a..9282bbf33 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -73,6 +73,12 @@ flags_default_extra = [] flags_thunderx_extra = [ ['RTE_MACHINE', '"thunderx"'], ['RTE_USE_C11_MEM_MODEL', false]] +flags_thunderx2_extra = [ + ['RTE_MACHINE', '"thunderx2"'], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_NUMA_NODES', 2], + ['RTE_MAX_LCORE', 256], + ['RTE_USE_C11_MEM_MODEL', true]] machine_args_generic = [ ['default', ['-march=armv8-a+crc+crypto']], @@ -89,7 +95,8 @@ machine_args_cavium = [ ['native', ['-march=native']], ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], - ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra], + ['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc new file mode 120000 index 000000000..b40a760b1 --- /dev/null +++ b/config/defconfig_arm64-thunderx2-linux-gcc @@ -0,0 +1 @@ +defconfig_arm64-thunderx2-linuxapp-gcc \ No newline at end of file diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc new file mode 100644 index 000000000..cc5c64ba0 --- /dev/null +++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Marvell International Ltd +# + +#include "defconfig_arm64-armv8a-linux-gcc" + +CONFIG_RTE_MACHINE="thunderx2" + +CONFIG_RTE_CACHE_LINE_SIZE=64 +CONFIG_RTE_MAX_NUMA_NODES=2 +CONFIG_RTE_MAX_LCORE=256 diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk new file mode 100644 index 000000000..b80dc8680 --- /dev/null +++ b/mk/machine/thunderx2/rte.vars.mk @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Marvell International Ltd +# + +# +# machine: +# +# - can define ARCH variable (overridden by cmdline value) +# - can define CROSS variable (overridden by cmdline value) +# - define MACHINE_CFLAGS variable (overridden by cmdline value) +# - define MACHINE_LDFLAGS variable (overridden by cmdline value) +# - define MACHINE_ASFLAGS variable (overridden by cmdline value) +# - can define CPU_CFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - can define CPU_LDFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - can define CPU_ASFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - may override any previously defined variable +# + +# ARCH = +# CROSS = +# MACHINE_CFLAGS = +# MACHINE_LDFLAGS = +# MACHINE_ASFLAGS = +# CPU_CFLAGS = +# CPU_LDFLAGS = +# CPU_ASFLAGS = + +include $(RTE_SDK)/mk/rte.helper.mk + +MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto) +MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99) From patchwork Sat Apr 6 14:27:37 2019 Content-Type: text/plain; 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Sat, 06 Apr 2019 07:28:36 -0700 (PDT) From: jerinjacobk@gmail.com X-Google-Original-From: jerinj@marvell.com To: Thomas Monjalon Cc: dev@dpdk.org, Jerin Jacob , Pavan Nikhilesh , Gavin Hu Date: Sat, 6 Apr 2019 19:57:37 +0530 Message-Id: <20190406142737.20091-4-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190406142737.20091-1-jerinj@marvell.com> References: <20190318164949.2357-1-jerinj@marvell.com> <20190406142737.20091-1-jerinj@marvell.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 4/4] config: add octeontx2 machine config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Optimized configuration for Marvell octeontx2 SoC. Updated meson build to support Marvell octeontx2 SoC. Added meson cross build target for octeontx2. Signed-off-by: Jerin Jacob Signed-off-by: Pavan Nikhilesh Reviewed-by: Gavin Hu --- config/arm/arm64_octeontx2_linux_gcc | 16 +++++++++ config/arm/meson.build | 9 ++++- config/defconfig_arm64-octeontx2-linux-gcc | 1 + config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++ mk/machine/octeontx2/rte.vars.mk | 34 +++++++++++++++++++ 5 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 config/arm/arm64_octeontx2_linux_gcc create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc create mode 100644 mk/machine/octeontx2/rte.vars.mk diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc new file mode 100644 index 000000000..e2c0b8f72 --- /dev/null +++ b/config/arm/arm64_octeontx2_linux_gcc @@ -0,0 +1,16 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' +strip = 'aarch64-linux-gnu-strip' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = '0x43' +implementor_pn = '0xb2' diff --git a/config/arm/meson.build b/config/arm/meson.build index 9282bbf33..0d76b2554 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -79,6 +79,12 @@ flags_thunderx2_extra = [ ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 256], ['RTE_USE_C11_MEM_MODEL', true]] +flags_octeontx2_extra = [ + ['RTE_MACHINE', '"octeontx2"'], + ['RTE_MAX_NUMA_NODES', 1], + ['RTE_MAX_LCORE', 24], + ['RTE_EAL_IGB_UIO', false], + ['RTE_USE_C11_MEM_MODEL', true]] machine_args_generic = [ ['default', ['-march=armv8-a+crc+crypto']], @@ -96,7 +102,8 @@ machine_args_cavium = [ ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra], - ['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]] + ['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra], + ['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc new file mode 120000 index 000000000..e25150531 --- /dev/null +++ b/config/defconfig_arm64-octeontx2-linux-gcc @@ -0,0 +1 @@ +defconfig_arm64-octeontx2-linuxapp-gcc \ No newline at end of file diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc new file mode 100644 index 000000000..9eae84538 --- /dev/null +++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Marvell International Ltd +# + +#include "defconfig_arm64-armv8a-linux-gcc" + +CONFIG_RTE_MACHINE="octeontx2" + +CONFIG_RTE_CACHE_LINE_SIZE=128 +CONFIG_RTE_MAX_NUMA_NODES=1 +CONFIG_RTE_MAX_LCORE=24 + +# Doesn't support NUMA +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n +CONFIG_RTE_LIBRTE_VHOST_NUMA=n + +# Recommend to use VFIO as co-processors needs SMMU/IOMMU +CONFIG_RTE_EAL_IGB_UIO=n diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk new file mode 100644 index 000000000..cbec7f14d --- /dev/null +++ b/mk/machine/octeontx2/rte.vars.mk @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Marvell International Ltd +# + +# +# machine: +# +# - can define ARCH variable (overridden by cmdline value) +# - can define CROSS variable (overridden by cmdline value) +# - define MACHINE_CFLAGS variable (overridden by cmdline value) +# - define MACHINE_LDFLAGS variable (overridden by cmdline value) +# - define MACHINE_ASFLAGS variable (overridden by cmdline value) +# - can define CPU_CFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - can define CPU_LDFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - can define CPU_ASFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - may override any previously defined variable +# + +# ARCH = +# CROSS = +# MACHINE_CFLAGS = +# MACHINE_LDFLAGS = +# MACHINE_ASFLAGS = +# CPU_CFLAGS = +# CPU_LDFLAGS = +# CPU_ASFLAGS = + +include $(RTE_SDK)/mk/rte.helper.mk + +MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse) +MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)