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GET /api/1.0/patches/10658/?format=api
{ "id": 10658, "url": "http://patchwork.dpdk.org/api/1.0/patches/10658/?format=api", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/1.0/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk" }, "msgid": "<1455806076-18497-30-git-send-email-helin.zhang@intel.com>", "date": "2016-02-18T14:34:35", "name": "[dpdk-dev,v3,29/30] i40e: use rx control function for rx control registers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c298eb9b5f7c68f43b86e8815da3c7ea3ed60ab4", "submitter": { "id": 14, "url": "http://patchwork.dpdk.org/api/1.0/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": { "id": 10, "url": "http://patchwork.dpdk.org/api/1.0/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1455806076-18497-30-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/10658/checks/", "tags": {}, "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id B56D2C512;\n\tThu, 18 Feb 2016 15:35:47 +0100 (CET)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id E40F9C510\n\tfor <dev@dpdk.org>; Thu, 18 Feb 2016 15:35:45 +0100 (CET)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga101.fm.intel.com with ESMTP; 18 Feb 2016 06:35:45 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 18 Feb 2016 06:35:44 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id u1IEZhDK020299;\n\tThu, 18 Feb 2016 22:35:43 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid u1IEZePV018742; Thu, 18 Feb 2016 22:35:42 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u1IEZeXG018738; \n\tThu, 18 Feb 2016 22:35:40 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.22,465,1449561600\"; d=\"scan'208\";a=\"655038871\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 18 Feb 2016 22:34:35 +0800", "Message-Id": "<1455806076-18497-30-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1455806076-18497-1-git-send-email-helin.zhang@intel.com>", "References": "<1455776683-11790-1-git-send-email-helin.zhang@intel.com>\n\t<1455806076-18497-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 29/30] i40e: use rx control function for rx\n\tcontrol registers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "As required, rx control registers have to be read/written by\nrx control functions, otherwise if may fail to read/write\nwhen under stress small traffic.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 66 ++++++++++++++++++++-------------------\n drivers/net/i40e/i40e_ethdev_vf.c | 28 ++++++++---------\n drivers/net/i40e/i40e_fdir.c | 13 ++++----\n drivers/net/i40e/i40e_pf.c | 6 ++--\n 4 files changed, 58 insertions(+), 55 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 614bd5b..6241bfc 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -5632,11 +5632,11 @@ i40e_pf_disable_rss(struct i40e_pf *pf)\n \tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n \tuint64_t hena;\n \n-\thena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));\n-\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;\n+\thena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));\n+\thena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;\n \thena &= ~I40E_RSS_HENA_ALL;\n-\tI40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);\n-\tI40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));\n \tI40E_WRITE_FLUSH(hw);\n }\n \n@@ -5669,7 +5669,7 @@ i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)\n \t\tuint16_t i;\n \n \t\tfor (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)\n-\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);\n+\t\t\ti40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);\n \t\tI40E_WRITE_FLUSH(hw);\n \t}\n \n@@ -5698,7 +5698,7 @@ i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)\n \t\tuint16_t i;\n \n \t\tfor (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)\n-\t\t\tkey_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));\n+\t\t\tkey_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));\n \t}\n \t*key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);\n \n@@ -5719,12 +5719,12 @@ i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)\n \t\treturn ret;\n \n \trss_hf = rss_conf->rss_hf;\n-\thena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));\n-\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;\n+\thena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));\n+\thena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;\n \thena &= ~I40E_RSS_HENA_ALL;\n \thena |= i40e_config_hena(rss_hf);\n-\tI40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);\n-\tI40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));\n \tI40E_WRITE_FLUSH(hw);\n \n \treturn 0;\n@@ -5739,8 +5739,8 @@ i40e_dev_rss_hash_update(struct rte_eth_dev *dev,\n \tuint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;\n \tuint64_t hena;\n \n-\thena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));\n-\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;\n+\thena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));\n+\thena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;\n \tif (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */\n \t\tif (rss_hf != 0) /* Enable RSS */\n \t\t\treturn -EINVAL;\n@@ -5764,8 +5764,8 @@ i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n \ti40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,\n \t\t\t &rss_conf->rss_key_len);\n \n-\thena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));\n-\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;\n+\thena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));\n+\thena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;\n \trss_conf->rss_hf = i40e_parse_hena(hena);\n \n \treturn 0;\n@@ -6266,7 +6266,7 @@ i40e_pf_config_mq_rx(struct i40e_pf *pf)\n static void\n i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)\n {\n-\tuint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);\n+\tuint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);\n \n \t*enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;\n }\n@@ -6275,7 +6275,7 @@ i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)\n static void\n i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)\n {\n-\tuint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);\n+\tuint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);\n \n \tif (enable > 0) {\n \t\tif (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {\n@@ -6292,7 +6292,7 @@ i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)\n \t\t}\n \t\treg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;\n \t}\n-\tI40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);\n+\ti40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);\n \tI40E_WRITE_FLUSH(hw);\n }\n \n@@ -6310,7 +6310,7 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw,\n \tenum i40e_filter_pctype pctype;\n \n \tmemset(g_cfg, 0, sizeof(*g_cfg));\n-\treg = I40E_READ_REG(hw, I40E_GLQF_CTL);\n+\treg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);\n \tif (reg & I40E_GLQF_CTL_HTOEP_MASK)\n \t\tg_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;\n \telse\n@@ -6325,7 +6325,7 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw,\n \t\t/* Bit set indicats the coresponding flow type is supported */\n \t\tg_cfg->valid_bit_mask[0] |= (1UL << i);\n \t\tpctype = i40e_flowtype_to_pctype(i);\n-\t\treg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));\n+\t\treg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));\n \t\tif (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)\n \t\t\tg_cfg->sym_hash_enable_mask[0] |= (1UL << i);\n \t}\n@@ -6398,10 +6398,10 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\tpctype = i40e_flowtype_to_pctype(i);\n \t\treg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?\n \t\t\t\tI40E_GLQF_HSYM_SYMH_ENA_MASK : 0;\n-\t\tI40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);\n+\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);\n \t}\n \n-\treg = I40E_READ_REG(hw, I40E_GLQF_CTL);\n+\treg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);\n \tif (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {\n \t\t/* Toeplitz */\n \t\tif (reg & I40E_GLQF_CTL_HTOEP_MASK) {\n@@ -6422,7 +6422,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t/* Use the default, and keep it as it is */\n \t\tgoto out;\n \n-\tI40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);\n+\ti40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);\n \n out:\n \tI40E_WRITE_FLUSH(hw);\n@@ -6845,13 +6845,13 @@ i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,\n \tuint64_t reg = 0;\n \n \tif (filter == RTE_ETH_FILTER_HASH) {\n-\t\treg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));\n+\t\treg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));\n \t\treg <<= I40E_32_BIT_WIDTH;\n-\t\treg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));\n+\t\treg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));\n \t} else if (filter == RTE_ETH_FILTER_FDIR) {\n-\t\treg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));\n+\t\treg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));\n \t\treg <<= I40E_32_BIT_WIDTH;\n-\t\treg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));\n+\t\treg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));\n \t}\n \n \treturn reg;\n@@ -6860,13 +6860,13 @@ i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,\n static void\n i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)\n {\n-\tuint32_t reg = I40E_READ_REG(hw, addr);\n+\tuint32_t reg = i40e_read_rx_ctl(hw, addr);\n \n \tPMD_DRV_LOG(DEBUG, \"[0x%08x] original: 0x%08x\\n\", addr, reg);\n \tif (reg != val)\n-\t\tI40E_WRITE_REG(hw, addr, val);\n+\t\ti40e_write_rx_ctl(hw, addr, val);\n \tPMD_DRV_LOG(DEBUG, \"[0x%08x] after: 0x%08x\\n\", addr,\n-\t\t (uint32_t)I40E_READ_REG(hw, addr));\n+\t\t (uint32_t)i40e_read_rx_ctl(hw, addr));\n }\n \n static int\n@@ -6895,7 +6895,8 @@ i40e_set_hash_inset_mask(struct i40e_hw *hw,\n \t\tuint8_t j, count = 0;\n \n \t\tfor (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {\n-\t\t\treg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));\n+\t\t\treg = i40e_read_rx_ctl(hw,\n+\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype));\n \t\t\tif (reg & I40E_GLQF_HASH_MSK_MASK_MASK)\n \t\t\t\tcount++;\n \t\t}\n@@ -6936,7 +6937,8 @@ i40e_set_fd_inset_mask(struct i40e_hw *hw,\n \t\tuint8_t j, count = 0;\n \n \t\tfor (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {\n-\t\t\treg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));\n+\t\t\treg = i40e_read_rx_ctl(hw,\n+\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype));\n \t\t\tif (reg & I40E_GLQF_FD_MSK_MASK_MASK)\n \t\t\t\tcount++;\n \t\t}\n@@ -7263,7 +7265,7 @@ static void\n i40e_hw_init(struct i40e_hw *hw)\n {\n \t/* clear the PF Queue Filter control register */\n-\tI40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);\n \n \t/* Disable symmetric hash per port */\n \ti40e_set_symmetric_hash_enable_per_port(hw, 0);\ndiff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c\nindex 13c5b3d..bd5c091 100644\n--- a/drivers/net/i40e/i40e_ethdev_vf.c\n+++ b/drivers/net/i40e/i40e_ethdev_vf.c\n@@ -2229,7 +2229,7 @@ i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)\n \t\tuint16_t i;\n \n \t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n-\t\t\tI40E_WRITE_REG(hw, I40E_VFQF_HKEY(i), hash_key[i]);\n+\t\t\ti40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);\n \t\tI40EVF_WRITE_FLUSH(hw);\n \t}\n \n@@ -2258,7 +2258,7 @@ i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)\n \t\tuint16_t i;\n \n \t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n-\t\t\tkey_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HKEY(i));\n+\t\t\tkey_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));\n \t}\n \t*key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);\n \n@@ -2278,12 +2278,12 @@ i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)\n \t\treturn ret;\n \n \trss_hf = rss_conf->rss_hf;\n-\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n-\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n+\thena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));\n+\thena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;\n \thena &= ~I40E_RSS_HENA_ALL;\n \thena |= i40e_config_hena(rss_hf);\n-\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena);\n-\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));\n+\ti40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);\n+\ti40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));\n \tI40EVF_WRITE_FLUSH(hw);\n \n \treturn 0;\n@@ -2295,11 +2295,11 @@ i40evf_disable_rss(struct i40e_vf *vf)\n \tstruct i40e_hw *hw = I40E_VF_TO_HW(vf);\n \tuint64_t hena;\n \n-\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n-\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n+\thena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));\n+\thena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;\n \thena &= ~I40E_RSS_HENA_ALL;\n-\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena);\n-\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));\n+\ti40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);\n+\ti40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));\n \tI40EVF_WRITE_FLUSH(hw);\n }\n \n@@ -2356,8 +2356,8 @@ i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,\n \tuint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;\n \tuint64_t hena;\n \n-\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n-\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n+\thena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));\n+\thena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;\n \tif (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */\n \t\tif (rss_hf != 0) /* Enable RSS */\n \t\t\treturn -EINVAL;\n@@ -2382,8 +2382,8 @@ i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n \ti40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,\n \t\t\t &rss_conf->rss_key_len);\n \n-\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n-\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n+\thena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));\n+\thena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;\n \trss_conf->rss_hf = i40e_parse_hena(hena);\n \n \treturn 0;\ndiff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c\nindex 9ad6981..14c51ce 100644\n--- a/drivers/net/i40e/i40e_fdir.c\n+++ b/drivers/net/i40e/i40e_fdir.c\n@@ -52,6 +52,7 @@\n \n #include \"i40e_logs.h\"\n #include \"base/i40e_type.h\"\n+#include \"base/i40e_prototype.h\"\n #include \"i40e_ethdev.h\"\n #include \"i40e_rxtx.h\"\n \n@@ -369,11 +370,11 @@ i40e_init_flx_pld(struct i40e_pf *pf)\n \t\tif (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)pctype))\n \t\t\tcontinue;\n \t\tpf->fdir.flex_mask[pctype].word_mask = 0;\n-\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);\n+\t\ti40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);\n \t\tfor (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {\n \t\t\tpf->fdir.flex_mask[pctype].bitmask[i].offset = 0;\n \t\t\tpf->fdir.flex_mask[pctype].bitmask[i].mask = 0;\n-\t\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);\n+\t\t\ti40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);\n \t\t}\n \t}\n }\n@@ -618,7 +619,7 @@ i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,\n \tflxinset = (flex_mask->word_mask <<\n \t\tI40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &\n \t\tI40E_PRTQF_FD_FLXINSET_INSET_MASK;\n-\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);\n+\ti40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);\n \n \tfor (i = 0; i < nb_bitmask; i++) {\n \t\tfd_mask = (flex_mask->bitmask[i].mask <<\n@@ -628,7 +629,7 @@ i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,\n \t\t\tI40E_FLX_OFFSET_IN_FIELD_VECTOR) <<\n \t\t\tI40E_PRTQF_FD_MSK_OFFSET_SHIFT) &\n \t\t\tI40E_PRTQF_FD_MSK_OFFSET_MASK;\n-\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);\n+\t\ti40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);\n \t}\n }\n \n@@ -660,9 +661,9 @@ i40e_fdir_configure(struct rte_eth_dev *dev)\n \t}\n \n \t/* enable FDIR filter */\n-\tval = I40E_READ_REG(hw, I40E_PFQF_CTL_0);\n+\tval = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);\n \tval |= I40E_PFQF_CTL_0_FD_ENA_MASK;\n-\tI40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);\n \n \ti40e_init_flx_pld(pf); /* set flex config to default value */\n \ndiff --git a/drivers/net/i40e/i40e_pf.c b/drivers/net/i40e/i40e_pf.c\nindex cbf4e5b..51ae1e7 100644\n--- a/drivers/net/i40e/i40e_pf.c\n+++ b/drivers/net/i40e/i40e_pf.c\n@@ -82,8 +82,8 @@ i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)\n \t * VF should use scatter range queues. So, it needn't\n \t * to set QBASE in this register.\n \t */\n-\tI40E_WRITE_REG(hw, I40E_VSILAN_QBASE(vsi_id),\n-\t I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);\n+\ti40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vsi_id),\n+\t\t\t I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);\n \n \t/* Set to enable VFLAN_QTABLE[] registers valid */\n \tI40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),\n@@ -108,7 +108,7 @@ i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)\n \t\t\tq2 = qbase + 2 * i + 1;\n \n \t\tval = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;\n-\t\tI40E_WRITE_REG(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);\n+\t\ti40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);\n \t}\n \tI40E_WRITE_FLUSH(hw);\n \n", "prefixes": [ "dpdk-dev", "v3", "29/30" ] }