Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/12616/?format=api
{ "id": 12616, "url": "http://patchwork.dpdk.org/api/1.0/patches/12616/?format=api", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/1.0/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk" }, "msgid": "<1462634198-2289-9-git-send-email-jerin.jacob@caviumnetworks.com>", "date": "2016-05-07T15:16:26", "name": "[dpdk-dev,08/20] thunderx/nicvf: add tx_queue_setup/release support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a3fe39404e28b37bc938c4e5ef43244a430d995d", "submitter": { "id": 305, "url": "http://patchwork.dpdk.org/api/1.0/people/305/?format=api", "name": "Jerin Jacob", "email": "jerin.jacob@caviumnetworks.com" }, "delegate": { "id": 10, "url": "http://patchwork.dpdk.org/api/1.0/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1462634198-2289-9-git-send-email-jerin.jacob@caviumnetworks.com/mbox/", "series": [], "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/12616/checks/", "tags": {}, "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 6C4815A83;\n\tSat, 7 May 2016 17:18:22 +0200 (CEST)", "from na01-by2-obe.outbound.protection.outlook.com\n\t(mail-by2on0054.outbound.protection.outlook.com [207.46.100.54])\n\tby dpdk.org (Postfix) with ESMTP id 1CD9C5A79\n\tfor <dev@dpdk.org>; Sat, 7 May 2016 17:18:21 +0200 (CEST)", "from localhost.localdomain.localdomain (122.167.10.92) by\n\tBN3PR0701MB1718.namprd07.prod.outlook.com (10.163.39.17) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.1.492.11; Sat, 7 May 2016 15:18:14 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:To:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=gY7whyw04CFZioJqdfv0gc9BvpqDy+fjw4YM+B6RWhE=;\n\tb=K1haDziPaIA8q+aOZjJa0gflDjfgxXm6w3YrZcf7uMe/GlR+Ip7vDpbujBAMeRGlwY+E+2ZkM8gE4tfeDl9QPGM95hdhecJ5Y8mqMgtE+wIrt26kVapNt3QIxDiqpLDO9LvhwMbcZSFXgMqQjmjZUQniNb7qwYWvsCp7B/a5pn4=", "Authentication-Results": "dpdk.org; dkim=none (message not signed)\n\theader.d=none;dpdk.org; dmarc=none action=none\n\theader.from=caviumnetworks.com;", "From": "Jerin Jacob <jerin.jacob@caviumnetworks.com>", "To": "<dev@dpdk.org>", "CC": "<thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>, Jerin Jacob\n\t<jerin.jacob@caviumnetworks.com>, Maciej Czekaj\n\t<maciej.czekaj@caviumnetworks.com>, Kamil Rytarowski\n\t<Kamil.Rytarowski@caviumnetworks.com>,\n\tZyta Szpak <zyta.szpak@semihalf.com>, \n\tSlawomir Rosek <slawomir.rosek@semihalf.com>, Radoslaw Biernacki\n\t<rad@semihalf.com>", "Date": "Sat, 7 May 2016 20:46:26 +0530", "Message-ID": "<1462634198-2289-9-git-send-email-jerin.jacob@caviumnetworks.com>", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1462634198-2289-1-git-send-email-jerin.jacob@caviumnetworks.com>", "References": "<1462634198-2289-1-git-send-email-jerin.jacob@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[122.167.10.92]", "X-ClientProxiedBy": "PN1PR01CA0050.INDPRD01.PROD.OUTLOOK.COM (10.164.136.150)\n\tTo\n\tBN3PR0701MB1718.namprd07.prod.outlook.com (10.163.39.17)", "X-MS-Office365-Filtering-Correlation-Id": "a47d0303-d802-42dc-e0a4-08d3768ad286", "X-Microsoft-Exchange-Diagnostics": [ "1; BN3PR0701MB1718;\n\t2:tT3fhm41hmuK6eefN01uBceGpmSOL+lr9dD3OldW99u7+FMKtibtcX5X+j061dMzqM2NdQo1RfAChIKPuK0uBGUA46xXLIYQ5K8UJKuGszjUZr/2uUUkvyVmz7I45xIlFUwxgmVzSPYBGqCwHKTeFYmNCAzdtUzNsXTyQ7kKa4qNtQrlvT/dMzeTJM2SHJVh;\n\t3:kc9jt9Yd0bEE05H/d2vXq6+bZ2XDNpaU0Lb1HtvHEWCLsvRDS+pSKKFbeh/5alN9GUtAFKbuRVRgiplFaW9pCboKOc/lVhRP+wMPZblUjt1n7en1NmLOPqsqXTHtf5gJ", "1; BN3PR0701MB1718;\n\t25:1AZUPZyQ+S+f8zodwrNpl+4nPAat8nTyKSJENElFywt8pM/IWrPe3IksBM/Way+o4PxNHdmMzf/QNX3nF6njhcpvN8e613jcotCDtxYto/JP10Kgbe0q69+8ofqTmOLQ/kCeSODhqX4jIxWISlK94OqqhgGQjRdtO88cIB1gSDW3mq6MKMmyIgUZnKakApFM8GSzPQPtq9vnhEQio6Kp/q/CWmvMdGKVWNHIfS3bXRdB4pTJ55iHPGdSZkRudiDf0JH8vorHr4PPdWZGuhaBSIi800MB3jsR2ARPEvCyDkE0fTpyHkgSohNBgrvV0q6fWw6w2lX+mekPnooyPKSdIYd7MROY8e07DXgF5xjrEt8Lr3GjAvYPfD1T+j13mT2oZNiDDYh8hrgtEmkt33QzRB5YofD+V2JojEb+gMSSuYtq075pCBujqD62H6X79svOCtkKUjKPK9xrpNkJOSj3x2rcO4wfE4vdIKp4kaW6V/CorqY/gib1vdNyskMm6LXBx6yMwDqNj4H0Lsz8MV5Ia3nD4ayHYzeVgTkl6QCkHGc94dCixvQVn5jf/wMwEh1ubHzrUVHthiFLygc0vDtdlsaJHUgCphKwFvY4Hu+wufKS5l99XnMzp0iockDuOyQY4ymm7djBdn7hd5YBTV0+Ygsi1IN3zPJgqbDdyO9m2MBA2W6Mh/9fgJIq5WbCk/dQLKuD7IX1wG0v4+gtrH5CQ2NdaYt+X0vzVIaUJGXu+HQ=", "1; BN3PR0701MB1718;\n\t20:C/4x9F+om4jdxMCsWYDzETEYT0vGOAGovJw90iKsZcrGvoOwLlRSAZpYPj5oAVxWaAaHKWbch1DCw01hWVjh/irXJeExXJeubLtxonwPRs4FX/H7j6WoS5P51uLIWWnc+B3D2Dfg3OtXdjYEnqim+0Gt0rPVqhpwZxGbvgFaVOQwVUleK/7+Ewg18UgS2zBIsImH8Ew8IfbbicmTp/aT7RdlzDe9kIaYu5wT1MnUieXrHzkY/Lp27ECQlelRcHjbG6hLqCcn77KQLxvghOexobYX+OdkEjL8w9WpQODE+iKtT1e+WpzA0E60qMIeDb8O98ObtOSY1orrUA91eUZDimmKMcRlIaE1vvG4GGcbH/O+HBH4qRD64XFLvTLUoHx+9FOFneuEwyEjng56OyGEhhF001tX7O/ti+W/j4Yb04r7FVlPwTjNaRyj15hNQPhb9v4dgtMMN4F6PPVEIrmnYRj/GP6Rk8+OACFrsBw8f9GMmhLhYR7Kc3tQSHt93nqUzaWKMngUDhx7jlxWPPtRT1B5Xy/TfBVttvlvPvWa16Q3Dj09ze5TkyHPlJany8fxfDOUnIesBN3jfaBO7HO61+EpSaMqJ1rWxifZ7PYhldc=", "1; BN3PR0701MB1718;\n\t4:DaLC5femUbF201A6eXOBMTYx9FmAR0biOXO/V/cxaliqQWE/GvMUMBtOdT8xxVQfPQ7hA1584EgdELv5kglkbBHih0L+vsnxS/OXNp1Y14pGbLdcHa5Ukm8Q1bYoKUkpkKCt9awL/E3Q7v7ZDGgxTIQzk9EUn1FLQuzwVx573Y5Pmiq+UDyDFGWurIkSaXZL+4EXlQtdYIARYf8d8MFAtKZa98VXZyLYcsfLQz6Sdp+IfdiL9anpUz8x8radlO1LCAfUhCXIOL440ne4aDl/Pqdgig04Pm3r+OXkM4JUNHWdloKbEhtCjmZV1b4gp5hzTwDbmUnFXRuoh0albhLr9L2SiBrNaQs8YHm8N6w9hr1X9po4ZFLMWQXZ+sJrMNDp", "1; BN3PR0701MB1718;\n\t23:BCX4Kvy3PgQNyiebInVkVu1J5KoO/VO17hl/6vcEFyi0wwoglFhiKLX/FyjYiVdoO7KpzfFnPGqdFGdB6Jh4JQhQu8gFC9s3NDG+LY0sXpR9FHb8CyE9xJQDJmW+gKL61seS0jyo8L2fcmDNCHQcZlujpNWxG09nnJXpsoBMAqvJD3VPrhKUpbXYWIMe3Xgo52i4/ToLyI/Y4mH3LGoqtCCYI4E/zAEEFSsZKZBxu93Ecv8rKbu0Gs7ma5URKKHiChUbLB9+FGbUYIEf9yv2LmYfwgM8kZeF1wOHI8ka5kkALAGfPx8oLBJpQwdGGGhKMRBvATwk07x7kBjpZqL/5WRUrrPM42x3rNE/tIDP03gNSGOwzVcFAO1F14MeIUk0iPLimj5hBARayqKo1Kck8uRp5x32V3xWz3yjlfQpdhgPNzpUEEq6Bsv3zI0VPPaJBiLrTBT0aXTtDxdPgiiK8tzcjlga31Yf2oPKoWsns3LZCoX1+mGdwxLNWf1gJ0ws0j3DgiE28K8TrWr9T0i9DLC3gJ0t4ID5Oxorv4T37ByO5+lNdZNMk5/cvAU9iphObfq9d6bSnGOCnVHblxFgLPESxzKAUzTQhkQh4KnAwBBJj4L7MPTubl/vc4cArD3yDwVCJMGfCOJ8tDjVV88VUoHtjoJkJYZvevmbFLgBUC+IYRX2WFURuHGqHOR2SgCxq1RSIWqzLFQCKN9yxue+9GdgYd+wkzgfhvLcRdF2GTxUk+K2QOC6jJdcVXnhByjoVyP4MUWQR+uQVUHRK5w41VLAu5ks0EAT6d+WXyJLryFVmrvxBs+qOM3ow8zahuOIzAFp/hnOJUy69bF4yfYFEDmTZKRD9A8AkpCXJhaHc8eEpdmLE20FmCTeQfyaeXt8", "1; BN3PR0701MB1718;\n\t5:10aJNDA0gJNu/a7ZFJlfRTkdGC4t1Msev1n2G2ja09OulEJhBaEFFSchdgKWu7VDv47fQElIIA1Hqgn9XPtmay5RRkhN5G0qQS4cfKv9PmTUrsfpWwHC1phl/IATn4CGl/IDdiLFfHHhC6AiXcPEpw==;\n\t24:VUeqfoMSJ0REqM2aljU2TBqDMYYQziIOvdf6Ftvk5Cf90F8jWHsd31J92YC47LwJ5roxCDnOFAxqQ1wBL9i+YHY+6j2o18ImGNV3VZrQIs8=;\n\t7:YMM08Tu7G572LFIo+YwQattM9uirakf30Qs0tdXrPHUSeCNSa5DsU2VTQu4B19z7ak1COePQw8sbPZfFA6NsAP75yXLSkER/fKVeH29dOzjVcGR+eT8UcAuMwMQcSo3qxSl6NvDPW1o8xCBibWHiHBcDNlKv158LjaPQiY0oJ2kGAA/vg98vG78oScpk3Sup" ], "X-Microsoft-Antispam": "UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR0701MB1718;", "X-Microsoft-Antispam-PRVS": "<BN3PR0701MB171894AAE05DA8BCCEDD42DF817E0@BN3PR0701MB1718.namprd07.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046); \n\tSRVR:BN3PR0701MB1718; BCL:0; PCL:0; RULEID:; SRVR:BN3PR0701MB1718; ", "X-Forefront-PRVS": "09352FD734", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(4630300001)(6009001)(6069001)(50226002)(77096005)(2950100001)(48376002)(81166005)(50466002)(66066001)(47776003)(92566002)(5003940100001)(4326007)(2906002)(110136002)(50986999)(2351001)(33646002)(586003)(3846002)(6116002)(229853001)(5004730100002)(76176999)(19580395003)(19580405001)(189998001)(5008740100001)(42186005)(36756003)(7099028);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BN3PR0701MB1718;\n\tH:localhost.localdomain.localdomain; FPR:; SPF:None; MLV:sfv; LANG:en;", "SpamDiagnosticOutput": "1:23", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 May 2016 15:18:14.8364\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN3PR0701MB1718", "Subject": "[dpdk-dev] [PATCH 08/20] thunderx/nicvf: add tx_queue_setup/release\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>\nSigned-off-by: Maciej Czekaj <maciej.czekaj@caviumnetworks.com>\nSigned-off-by: Kamil Rytarowski <Kamil.Rytarowski@caviumnetworks.com>\nSigned-off-by: Zyta Szpak <zyta.szpak@semihalf.com>\nSigned-off-by: Slawomir Rosek <slawomir.rosek@semihalf.com>\nSigned-off-by: Radoslaw Biernacki <rad@semihalf.com>\n---\n drivers/net/thunderx/nicvf_ethdev.c | 179 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 179 insertions(+)", "diff": "diff --git a/drivers/net/thunderx/nicvf_ethdev.c b/drivers/net/thunderx/nicvf_ethdev.c\nindex 3b94168..b99b4bb 100644\n--- a/drivers/net/thunderx/nicvf_ethdev.c\n+++ b/drivers/net/thunderx/nicvf_ethdev.c\n@@ -78,6 +78,10 @@ static int nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,\n \t\t\t\t const struct rte_eth_rxconf *rx_conf,\n \t\t\t\t struct rte_mempool *mp);\n static void nicvf_dev_rx_queue_release(void *rx_queue);\n+static int nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,\n+\t\t\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t\t\t const struct rte_eth_txconf *tx_conf);\n+static void nicvf_dev_tx_queue_release(void *sq);\n static int nicvf_dev_get_reg_length(struct rte_eth_dev *dev);\n static int nicvf_dev_get_regs(struct rte_eth_dev *dev,\n \t\t\t struct rte_dev_reg_info *regs);\n@@ -226,6 +230,179 @@ nicvf_qset_cq_alloc(struct nicvf *nic, struct nicvf_rxq *rxq, uint16_t qidx,\n \treturn 0;\n }\n \n+static int\n+nicvf_qset_sq_alloc(struct nicvf *nic, struct nicvf_txq *sq, uint16_t qidx,\n+\t\t uint32_t desc_cnt)\n+{\n+\tconst struct rte_memzone *rz;\n+\tuint32_t ring_size = desc_cnt * sizeof(union sq_entry_t);\n+\n+\trz = rte_eth_dma_zone_reserve(nic->eth_dev, \"sq\", qidx, ring_size,\n+\t\t\t\t NICVF_SQ_BASE_ALIGN_BYTES, nic->node);\n+\tif (rz == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed allocate mem for sq hw ring\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tmemset(rz->addr, 0, ring_size);\n+\n+\tsq->phys = rz->phys_addr;\n+\tsq->desc = rz->addr;\n+\tsq->qlen_mask = desc_cnt - 1;\n+\n+\treturn 0;\n+}\n+\n+static inline void\n+nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)\n+{\n+\tuint32_t head;\n+\n+\thead = txq->head;\n+\twhile (head != txq->tail) {\n+\t\tif (txq->txbuffs[head]) {\n+\t\t\trte_pktmbuf_free_seg(txq->txbuffs[head]);\n+\t\t\ttxq->txbuffs[head] = NULL;\n+\t\t}\n+\t\thead++;\n+\t\thead = head & txq->qlen_mask;\n+\t}\n+}\n+\n+static void\n+nicvf_tx_queue_reset(struct nicvf_txq *txq)\n+{\n+\tuint32_t txq_desc_cnt = txq->qlen_mask + 1;\n+\n+\tmemset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);\n+\tmemset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);\n+\ttxq->tail = 0;\n+\ttxq->head = 0;\n+\ttxq->xmit_bufs = 0;\n+}\n+\n+static void\n+nicvf_dev_tx_queue_release(void *sq)\n+{\n+\tstruct nicvf_txq *txq;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttxq = (struct nicvf_txq *)sq;\n+\tif (txq) {\n+\t\tif (txq->txbuffs != NULL) {\n+\t\t\tnicvf_tx_queue_release_mbufs(txq);\n+\t\t\trte_free(txq->txbuffs);\n+\t\t\ttxq->txbuffs = NULL;\n+\t\t}\n+\t\trte_free(txq);\n+\t}\n+}\n+\n+static int\n+nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,\n+\t\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t\t const struct rte_eth_txconf *tx_conf)\n+{\n+\tuint16_t tx_free_thresh;\n+\tstruct nicvf_txq *txq;\n+\tstruct nicvf *nic = nicvf_pmd_priv(dev);\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Socked id check */\n+\tif (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)\n+\t\tPMD_DRV_LOG(WARNING, \"socket_id expected %d, configured %d\",\n+\t\t\t socket_id, nic->node);\n+\n+\t/* Tx deferred start is not supported */\n+\tif (tx_conf->tx_deferred_start) {\n+\t\tPMD_INIT_LOG(ERR, \"Tx deferred start not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Roundup nb_desc to avilable qsize and validate max number of desc */\n+\tnb_desc = nicvf_qsize_sq_roundup(nb_desc);\n+\tif (nb_desc == 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Value of nb_desc beyond available sq qsize\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Validate tx_free_thresh */\n+\ttx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?\n+\t\t\t\t tx_conf->tx_free_thresh :\n+\t\t\t\t DEFAULT_TX_FREE_THRESH);\n+\n+\tif (tx_free_thresh > (nb_desc) || tx_free_thresh > MAX_TX_FREE_THRESH) {\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\"tx_free_thresh must be less than the number of TX \"\n+\t\t\t\"descriptors. (tx_free_thresh=%u port=%d \"\n+\t\t\t\"queue=%d)\", (unsigned int)tx_free_thresh,\n+\t\t\t(int)dev->data->port_id, (int)qidx);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Free memory prior to re-allocation if needed. */\n+\tif (dev->data->tx_queues[qidx] != NULL) {\n+\t\tPMD_TX_LOG(DEBUG, \"Freeing memory prior to re-allocation %d\",\n+\t\t\t qidx);\n+\t\tnicvf_dev_tx_queue_release(dev->data->tx_queues[qidx]);\n+\t\tdev->data->tx_queues[qidx] = NULL;\n+\t}\n+\n+\t/* Allocating tx queue data structure */\n+\ttxq = rte_zmalloc_socket(\"ethdev TX queue\", sizeof(struct nicvf_txq),\n+\t\t\t\t RTE_CACHE_LINE_SIZE, nic->node);\n+\tif (txq == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate txq=%d\", qidx);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ttxq->nic = nic;\n+\ttxq->queue_id = qidx;\n+\ttxq->tx_free_thresh = tx_free_thresh;\n+\ttxq->txq_flags = tx_conf->txq_flags;\n+\ttxq->port_id = dev->data->port_id;\n+\ttxq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;\n+\ttxq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;\n+\ttxq->is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&\n+\t\t\t\ttxq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);\n+\n+\t/* Choose optimum free threshold value for multipool case */\n+\tif (!txq->is_single_pool)\n+\t\ttxq->tx_free_thresh =\n+\t\t(uint16_t)(tx_conf->tx_free_thresh == DEFAULT_TX_FREE_THRESH ?\n+\t\t\t\tDEFAULT_TX_FREE_MPOOL_THRESH :\n+\t\t\t\ttx_conf->tx_free_thresh);\n+\ttxq->tail = 0;\n+\ttxq->head = 0;\n+\n+\t/* Allocate software ring */\n+\ttxq->txbuffs = rte_zmalloc_socket(\"txq->txbuffs\",\n+\t\t\t\tnb_desc * sizeof(struct rte_mbuf *),\n+\t\t\t\tRTE_CACHE_LINE_SIZE, nic->node);\n+\n+\tif (txq->txbuffs == NULL) {\n+\t\tnicvf_dev_tx_queue_release(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (nicvf_qset_sq_alloc(nic, txq, qidx, nb_desc)) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate mem for sq %d\", qidx);\n+\t\tnicvf_dev_tx_queue_release(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tnicvf_tx_queue_reset(txq);\n+\n+\tPMD_TX_LOG(DEBUG, \"[%d] txq=%p nb_desc=%d desc=%p phys=0x%\" PRIx64,\n+\t\t qidx, txq, nb_desc, txq->desc, txq->phys);\n+\n+\tdev->data->tx_queues[qidx] = txq;\n+\tdev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\treturn 0;\n+}\n+\n static void\n nicvf_rx_queue_reset(struct nicvf_rxq *rxq)\n {\n@@ -465,6 +642,8 @@ static const struct eth_dev_ops nicvf_eth_dev_ops = {\n \t.dev_infos_get = nicvf_dev_info_get,\n \t.rx_queue_setup = nicvf_dev_rx_queue_setup,\n \t.rx_queue_release = nicvf_dev_rx_queue_release,\n+\t.tx_queue_setup = nicvf_dev_tx_queue_setup,\n+\t.tx_queue_release = nicvf_dev_tx_queue_release,\n \t.get_reg_length = nicvf_dev_get_reg_length,\n \t.get_reg = nicvf_dev_get_regs,\n };\n", "prefixes": [ "dpdk-dev", "08/20" ] }