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GET /api/1.0/patches/59361/?format=api
{ "id": 59361, "url": "http://patchwork.dpdk.org/api/1.0/patches/59361/?format=api", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/1.0/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk" }, "msgid": "<1568881185-89233-1-git-send-email-andy.pei@intel.com>", "date": "2019-09-19T08:19:28", "name": "[v5,00/17] Add PCIe AER disable and IRQ support for ipn3ke", "commit_ref": null, "pull_url": null, "state": null, "archived": false, "hash": null, "submitter": { "id": 1185, "url": "http://patchwork.dpdk.org/api/1.0/people/1185/?format=api", "name": "Pei, Andy", "email": "andy.pei@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1568881185-89233-1-git-send-email-andy.pei@intel.com/mbox/", "series": [], "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/59361/checks/", "tags": {}, "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EF90D1E974;\n\tThu, 19 Sep 2019 10:34:04 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 12B761E973\n\tfor <dev@dpdk.org>; Thu, 19 Sep 2019 10:34:02 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2019 01:34:01 -0700", "from dpdk-dipei.sh.intel.com ([10.67.110.224])\n\tby fmsmga005.fm.intel.com with ESMTP; 19 Sep 2019 01:33:59 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,522,1559545200\"; d=\"scan'208\";a=\"387196764\"", "From": "Andy Pei <andy.pei@intel.com>", "To": "dev@dpdk.org", "Cc": "rosen.xu@intel.com, tianfei.zhang@intel.com, xiaolong.ye@intel.com,\n\tqi.z.zhang@intel.com, david.lomartire@intel.com, ferruh.yigit@intel.com", "Date": "Thu, 19 Sep 2019 16:19:28 +0800", "Message-Id": "<1568881185-89233-1-git-send-email-andy.pei@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1567652381-124289-2-git-send-email-andy.pei@intel.com>", "References": "<1567652381-124289-2-git-send-email-andy.pei@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 00/17] Add PCIe AER disable and IRQ support\n\tfor ipn3ke", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "s patch set adds PCIe AER disable and IRQ support for ipn3ke.\nDisable PCIe AER is very useful when FPGA reload. IRQ is used very\nwidely in interrupt process.\n\nFor ipn3ke is connect to CPU with PCIe switch, driver needs to scan\nall PCIe devices of ipn3ke, it also can get all i40e of card, so\nipn3ke driver doesn't need to take some configuration of i40e.\n\nv5 update:\n=========\n- add lightweight fpga image support. in lightweight fpga image mode, ipn3ke \n representor will not be probed.\n\nv4 updates:\n==========\n- align with new naming standard.\n\nv3 updates:\n===========\n- Add FPGA network side port MTU configuration\n\nv2 updates:\n===========\n- Add AUX feature support\n\n\nAndy Pei (13):\n net/i40e: i40e support ipn3ke FPGA port bonding\n raw/ifpga/base: add irq support\n raw/ifpga/base: clear pending bit\n raw/ifpga/base: add SEU error support\n raw/ifpga/base: add device tree support\n raw/ifpga/base: align the send buffer for SPI\n raw/ifpga/base: add sensor support\n raw/ifpga/base: introducing sensor APIs\n raw/ifpga/base: update SEU register definition\n raw/ifpga: add SEU error handler\n raw/ifpga: add PCIe BDF devices tree scan\n net/ipn3ke: remove configuration for i40e port bonding\n raw/ifpga: add lightweight fpga image support\n\nTianfei Zhang (2):\n raw/ifpga/base: configure FEC mode\n raw/ifpga/base: clean fme errors\n\nTianfei zhang (2):\n raw/ifpga/base: add secure support\n raw/ifpga/base: add new API get board info\n\n drivers/net/i40e/base/i40e_type.h | 3 +\n drivers/net/i40e/i40e_ethdev.c | 20 +\n drivers/net/i40e/rte_pmd_i40e.h | 4 +\n drivers/net/ipn3ke/Makefile | 2 +\n drivers/net/ipn3ke/ipn3ke_ethdev.c | 289 ++-------\n drivers/net/ipn3ke/ipn3ke_representor.c | 7 +-\n drivers/raw/ifpga/base/ifpga_api.c | 21 +\n drivers/raw/ifpga/base/ifpga_defines.h | 75 ++-\n drivers/raw/ifpga/base/ifpga_feature_dev.c | 60 ++\n drivers/raw/ifpga/base/ifpga_feature_dev.h | 3 +\n drivers/raw/ifpga/base/ifpga_fme.c | 138 ++++-\n drivers/raw/ifpga/base/ifpga_fme_error.c | 89 ++-\n drivers/raw/ifpga/base/ifpga_hw.h | 2 +-\n drivers/raw/ifpga/base/ifpga_port.c | 20 +\n drivers/raw/ifpga/base/ifpga_port_error.c | 21 +\n drivers/raw/ifpga/base/opae_hw_api.c | 135 ++++\n drivers/raw/ifpga/base/opae_hw_api.h | 21 +\n drivers/raw/ifpga/base/opae_ifpga_hw_api.h | 2 +\n drivers/raw/ifpga/base/opae_intel_max10.c | 568 ++++++++++++++++-\n drivers/raw/ifpga/base/opae_intel_max10.h | 146 ++++-\n drivers/raw/ifpga/base/opae_osdep.h | 7 +-\n drivers/raw/ifpga/base/opae_spi.h | 23 +-\n drivers/raw/ifpga/base/opae_spi_transaction.c | 40 +-\n drivers/raw/ifpga/ifpga_rawdev.c | 851 +++++++++++++++++++++++++-\n drivers/raw/ifpga/ifpga_rawdev.h | 16 +\n mk/rte.app.mk | 2 +-\n 26 files changed, 2187 insertions(+), 378 deletions(-)", "diff": null, "prefixes": [ "v5", "00/17" ] }