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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<gakhil@marvell.com>", "CC": "<rasland@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH v4 0/9] crypto/mlx5: support AES-GCM", "Date": "Tue, 20 Jun 2023 17:11:06 +0300", "Message-ID": "<20230620141115.841226-1-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230418092325.2578712-1-suanmingm@nvidia.com>", "References": "<20230418092325.2578712-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT037:EE_|SJ2PR12MB8830:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ad04ad46-b800-4a51-4b21-08db71984902", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n FbfHg/iJIOUaGAOwkyMROp7qU/aZ9YLTntsKHGBvJdFyu1sHQ6sTeC5rExXz4jISUfBvMj0A68xmWmTLq8OUSpHqhHODkFg1eS0BznjRgcBsuazeYUli08z4OgJXKuU7FivE1BgGQuGPBXG0FsPhpoHkHRS2XXSMI6CG2EuG6P6RH620rkBaMqmQJL2L5QEK7iw3q1Y2l2SIbqkJxrfNUL1GbEfezppG2WK22P9nNBHgILrK6hX7uo/MYABtbRqQ6SMP5oXxuoh3v6ph5LDqsHrA44BnI0ZU3bWfklCWAjN/x+EUmqbdWs098sacVJd6VPNEZZxMPn8WIu532A0xymZrxmdXUgbyLDC53cSe/Na7gAUAvZfM+xPHBmC3WC9uokuDj3vBoH5CXBVn551ZgCGi8ZTwrxtx20NL+H8+KZXCOeoOGRykKnV50VTpiyLm4HF838G0hF6/8CSOeHB/uwh27dzJ9A+RzK6HqPcYSBWhjt54KvpFovKz6O3T1aLUzXdPXHveWsEIvU7g2+FuwS0S1KchB3lG/byDQaOl7PvvI4daQOlglxP5WBQgphBdIv1ODLqEiC9ELr858C3P3dlgEyyYoZCtguCznxngIIfFes3zkFAk47bCCTXKWUSr6L7NexkTeR6IwTDZ/rwVKFvXBNzWEtO2yti0B438nDHVIoJF8RkXjVkD1Pj+78FKz9bSMRBZYOR/avMQmVAA9nM0TB0+cuJ7rzGmFEYMKwkXhaDvQIw/Fo6tuHySz/GT", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(396003)(346002)(136003)(39860400002)(376002)(451199021)(46966006)(36840700001)(40470700004)(2906002)(41300700001)(40460700003)(5660300002)(8936002)(8676002)(82310400005)(36756003)(55016003)(40480700001)(86362001)(478600001)(26005)(1076003)(54906003)(186003)(16526019)(6286002)(7696005)(6666004)(70586007)(70206006)(36860700001)(47076005)(7636003)(4326008)(356005)(6916009)(316002)(426003)(2616005)(336012)(82740400003)(83380400001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jun 2023 14:11:47.5505 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ad04ad46-b800-4a51-4b21-08db71984902", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT037.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ2PR12MB8830", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "AES-GCM provides both authenticated encryption and the ability to check\nthe integrity and authentication of additional authenticated data (AAD)\nthat is sent in the clear.\n\nThe crypto operations are performed with crypto WQE. If the input\nbuffers(AAD, mbuf, digest) are not contiguous and there is no enough\nheadroom or tailroom for AAD or digest, as the requirement from FW, an\nUMR WQE is needed to generate contiguous address space for crypto WQE.\nThe UMR WQE and crypto WQE are handled in two different QPs.\n\nThe QP for UMR operation contains two types of WQE, UMR and SEND_EN\nWQE. The WQEs are built dynamically according to the crypto operation \nbuffer address. Crypto operation with non-contiguous buffers will\nhave its own UMR WQE, while the operation with contiguous buffers \ndoesn't need the UMR WQE. Once the all the operations WQE in the\nenqueue burst built finishes, if any UMR WQEs are built, additional\nSEND_EN WQE will be as the final WQE of the burst in the UMR QP.\nThe purpose of that SEND_EN WQE is to trigger the crypto QP processing\nwith the UMR ready input memory address space buffers.\n\nThe QP for crypto operations contains only the crypto WQE and the QP\nWQEs are built as fixed in QP setup. The QP processing is triggered\nby doorbell ring or the SEND_EN WQE from UMR QP.\n\nv2:\n - split XTS and GCM code to different file.\n - add headroom and tailroom optimize.\n\nv3:\n - fix AES-GCM 128b key creation.\n\nv4:\n - add missing feature cap in mlx5.ini \n\nSuanming Mou (9):\n common/mlx5: export memory region lookup by address\n crypto/mlx5: split AES-XTS\n crypto/mlx5: add AES-GCM query and initialization\n crypto/mlx5: add AES-GCM encryption key\n crypto/mlx5: add AES-GCM session configure\n common/mlx5: add WQE-based QP synchronous basics\n crypto/mlx5: add queue pair setup for GCM\n crypto/mlx5: add enqueue and dequeue operations\n crypto/mlx5: enable AES-GCM capability\n\n doc/guides/cryptodevs/features/mlx5.ini | 2 +\n doc/guides/cryptodevs/mlx5.rst | 48 +-\n doc/guides/rel_notes/release_23_07.rst | 1 +\n drivers/common/mlx5/mlx5_common_mr.c | 2 +-\n drivers/common/mlx5/mlx5_common_mr.h | 5 +\n drivers/common/mlx5/mlx5_devx_cmds.c | 21 +\n drivers/common/mlx5/mlx5_devx_cmds.h | 16 +\n drivers/common/mlx5/mlx5_prm.h | 65 +-\n drivers/common/mlx5/version.map | 3 +\n drivers/crypto/mlx5/meson.build | 2 +\n drivers/crypto/mlx5/mlx5_crypto.c | 673 ++--------------\n drivers/crypto/mlx5/mlx5_crypto.h | 101 ++-\n drivers/crypto/mlx5/mlx5_crypto_dek.c | 102 ++-\n drivers/crypto/mlx5/mlx5_crypto_gcm.c | 997 ++++++++++++++++++++++++\n drivers/crypto/mlx5/mlx5_crypto_xts.c | 645 +++++++++++++++\n 15 files changed, 2018 insertions(+), 665 deletions(-)\n create mode 100644 drivers/crypto/mlx5/mlx5_crypto_gcm.c\n create mode 100644 drivers/crypto/mlx5/mlx5_crypto_xts.c" }