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{
    "id": 56359,
    "url": "http://patchwork.dpdk.org/api/covers/56359/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/cover/20190712030923.37832-1-ruifeng.wang@arm.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190712030923.37832-1-ruifeng.wang@arm.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190712030923.37832-1-ruifeng.wang@arm.com",
    "date": "2019-07-12T03:09:17",
    "name": "[v5,0/6] LPM4 memory ordering changes",
    "submitter": {
        "id": 1198,
        "url": "http://patchwork.dpdk.org/api/people/1198/?format=api",
        "name": "Ruifeng Wang",
        "email": "ruifeng.wang@arm.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/cover/20190712030923.37832-1-ruifeng.wang@arm.com/mbox/",
    "series": [
        {
            "id": 5462,
            "url": "http://patchwork.dpdk.org/api/series/5462/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=5462",
            "date": "2019-07-12T03:09:17",
            "name": "LPM4 memory ordering changes",
            "version": 5,
            "mbox": "http://patchwork.dpdk.org/series/5462/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/covers/56359/comments/",
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1FBC21DBE;\n\tFri, 12 Jul 2019 05:09:53 +0200 (CEST)",
            "from foss.arm.com (foss.arm.com [217.140.110.172])\n\tby dpdk.org (Postfix) with ESMTP id 9D3821D7\n\tfor <dev@dpdk.org>; Fri, 12 Jul 2019 05:09:51 +0200 (CEST)",
            "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E64A82B;\n\tThu, 11 Jul 2019 20:09:50 -0700 (PDT)",
            "from net-arm-c2400-02.shanghai.arm.com\n\t(net-arm-c2400-02.shanghai.arm.com [10.169.40.42])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t5265D3F246; Thu, 11 Jul 2019 20:09:49 -0700 (PDT)"
        ],
        "From": "Ruifeng Wang <ruifeng.wang@arm.com>",
        "To": "vladimir.medvedkin@intel.com,\n\tbruce.richardson@intel.com",
        "Cc": "dev@dpdk.org, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, nd@arm.com,\n\tRuifeng Wang <ruifeng.wang@arm.com>",
        "Date": "Fri, 12 Jul 2019 11:09:17 +0800",
        "Message-Id": "<20190712030923.37832-1-ruifeng.wang@arm.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20190605055451.30473-1-ruifeng.wang@arm.com>",
        "References": "<20190605055451.30473-1-ruifeng.wang@arm.com>",
        "Subject": "[dpdk-dev] [PATCH v5 0/6] LPM4 memory ordering changes",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "LPM4 uses DIR24-8 method of routing info data organization.\nRouting rule with prefix longer than 24 bits will be stored\nin a tbl24 entry together with an associated tbl8 group.\n\nWhen a tbl8 group is getting attached to a tbl24 entry, lookup\nmight fail even though the entry is configured in the table.\n\nFor ex: consider a LPM table configured with 10.10.10.1/24.\nWhen a new entry 10.10.10.32/28 is being added, a new tbl8\ngroup is allocated and tbl24 entry is changed to point to\nthe tbl8 group. If the tbl24 entry is written without the tbl8\ngroup entries updated, a lookup on 10.10.10.9 will return\nfailure.\n\nCorrect memory orderings are required to ensure that the\nstore to tbl24 does not happen before the stores to tbl8 group\nentries complete.\n\nWhen memory orderings are imposed, API performance could drop.\nHowever, a patch to de-inline unnecessary functions is added,\nand this helps to keep API performance.\n\nOn Arm A72 platform, the whole patch series in general have no\nnotable performance impact.\n\nOn x86 E5-2640 platform, the whole patch series showed 2.6%\nperformance improvement on add, and no impact on lookup or\ndelete.\n\n\nv5:\nFixed typo in commit message.\nRemove all other inlines.\nChange to use atomic_store in tbl8_alloc / tbl8_free.\nMerge multiple sigle field updates into one atomic store.\nv4:\nChanged alignment attribute parameter.\nUse atomic store to avoid partial update.\nv3:\nUse __rte_noinline to force no inline.\nv2:\nFixed clang building issue by supplying alignment attribute.\n\nRuifeng Wang (6):\n  lib/lpm: not inline unnecessary functions\n  lib/lpm: memory orderings to avoid race conditions for v1604\n  lib/lpm: memory orderings to avoid race conditions for v20\n  lib/lpm: use atomic store to avoid partial update\n  lib/lpm: data update optimization for v1604\n  lib/lpm: data update optimization for v20\n\n lib/librte_lpm/rte_lpm.c | 248 ++++++++++++++++++++++++++++-----------\n lib/librte_lpm/rte_lpm.h |   8 +-\n 2 files changed, 183 insertions(+), 73 deletions(-)"
}