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{
    "id": 103721,
    "url": "http://patchwork.dpdk.org/api/patches/103721/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211104103457.20264-5-kai.ji@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211104103457.20264-5-kai.ji@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211104103457.20264-5-kai.ji@intel.com",
    "date": "2021-11-04T10:34:52",
    "name": "[v8,4/9] common/qat: add gen specific queue implementation",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "330fb072991ac467d37f9692a217800c48fe6e9e",
    "submitter": {
        "id": 2202,
        "url": "http://patchwork.dpdk.org/api/people/2202/?format=api",
        "name": "Ji, Kai",
        "email": "kai.ji@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patchwork.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211104103457.20264-5-kai.ji@intel.com/mbox/",
    "series": [
        {
            "id": 20302,
            "url": "http://patchwork.dpdk.org/api/series/20302/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20302",
            "date": "2021-11-04T10:34:48",
            "name": "drivers/qat: isolate implementations of qat generations",
            "version": 8,
            "mbox": "http://patchwork.dpdk.org/series/20302/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/103721/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/103721/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7A098A0548;\n\tThu,  4 Nov 2021 11:35:31 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DB822426D3;\n\tThu,  4 Nov 2021 11:35:12 +0100 (CET)",
            "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id EFF4D411A4\n for <dev@dpdk.org>; Thu,  4 Nov 2021 11:35:09 +0100 (CET)",
            "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 04 Nov 2021 03:35:09 -0700",
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        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10157\"; a=\"212426612\"",
            "E=Sophos;i=\"5.87,208,1631602800\"; d=\"scan'208\";a=\"212426612\"",
            "E=Sophos;i=\"5.87,208,1631602800\"; d=\"scan'208\";a=\"542020247\""
        ],
        "X-ExtLoop1": "1",
        "From": "Kai Ji <kai.ji@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "gakhil@marvell.com, Fan Zhang <roy.fan.zhang@intel.com>,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>, Kai Ji <kai.ji@intel.com>",
        "Date": "Thu,  4 Nov 2021 10:34:52 +0000",
        "Message-Id": "<20211104103457.20264-5-kai.ji@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20211104103457.20264-1-kai.ji@intel.com>",
        "References": "<20211027155055.32264-1-kai.ji@intel.com>\n <20211104103457.20264-1-kai.ji@intel.com>",
        "Subject": "[dpdk-dev] [dpdk-dev v8 4/9] common/qat: add gen specific queue\n implementation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Fan Zhang <roy.fan.zhang@intel.com>\n\nThis patch replaces the mixed QAT queue pair configuration\nimplementation by separate files with shared or individual\nimplementation for specific QAT generation.\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\nSigned-off-by: Fan Zhang <roy.fan.zhang@intel.com>\nSigned-off-by: Kai Ji <kai.ji@intel.com>\nAcked-by: Ciara Power <ciara.power@intel.com>\n---\n drivers/common/qat/dev/qat_dev_gen1.c         | 190 +++++\n drivers/common/qat/dev/qat_dev_gen2.c         |  14 +\n drivers/common/qat/dev/qat_dev_gen3.c         |  60 ++\n drivers/common/qat/dev/qat_dev_gen4.c         | 161 ++++-\n drivers/common/qat/dev/qat_dev_gens.h         |  37 +-\n .../qat/qat_adf/adf_transport_access_macros.h |   2 +\n drivers/common/qat/qat_device.h               |   3 -\n drivers/common/qat/qat_qp.c                   | 677 +++++++-----------\n drivers/common/qat/qat_qp.h                   |  24 +-\n drivers/crypto/qat/qat_sym_pmd.c              |  32 +-\n 10 files changed, 723 insertions(+), 477 deletions(-)\n\n--\n2.17.1",
    "diff": "diff --git a/drivers/common/qat/dev/qat_dev_gen1.c b/drivers/common/qat/dev/qat_dev_gen1.c\nindex 9972280e06..38757e6e40 100644\n--- a/drivers/common/qat/dev/qat_dev_gen1.c\n+++ b/drivers/common/qat/dev/qat_dev_gen1.c\n@@ -3,6 +3,7 @@\n  */\n\n #include \"qat_device.h\"\n+#include \"qat_qp.h\"\n #include \"adf_transport_access_macros.h\"\n #include \"qat_dev_gens.h\"\n\n@@ -10,6 +11,194 @@\n\n #define ADF_ARB_REG_SLOT\t\t\t0x1000\n\n+#define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \\\n+\tADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \\\n+\t(ADF_ARB_REG_SLOT * index), value)\n+\n+__extension__\n+const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]\n+\t\t\t\t\t [ADF_MAX_QPS_ON_ANY_SERVICE] = {\n+\t/* queue pairs which provide an asymmetric crypto service */\n+\t[QAT_SERVICE_ASYMMETRIC] = {\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_ASYMMETRIC,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 0,\n+\t\t\t.rx_ring_num = 8,\n+\t\t\t.tx_msg_size = 64,\n+\t\t\t.rx_msg_size = 32,\n+\n+\t\t}, {\n+\t\t\t.service_type = QAT_SERVICE_ASYMMETRIC,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 1,\n+\t\t\t.rx_ring_num = 9,\n+\t\t\t.tx_msg_size = 64,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}\n+\t},\n+\t/* queue pairs which provide a symmetric crypto service */\n+\t[QAT_SERVICE_SYMMETRIC] = {\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_SYMMETRIC,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 2,\n+\t\t\t.rx_ring_num = 10,\n+\t\t\t.tx_msg_size = 128,\n+\t\t\t.rx_msg_size = 32,\n+\t\t},\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_SYMMETRIC,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 3,\n+\t\t\t.rx_ring_num = 11,\n+\t\t\t.tx_msg_size = 128,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}\n+\t},\n+\t/* queue pairs which provide a compression service */\n+\t[QAT_SERVICE_COMPRESSION] = {\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_COMPRESSION,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 6,\n+\t\t\t.rx_ring_num = 14,\n+\t\t\t.tx_msg_size = 128,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}, {\n+\t\t\t.service_type = QAT_SERVICE_COMPRESSION,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 7,\n+\t\t\t.rx_ring_num = 15,\n+\t\t\t.tx_msg_size = 128,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}\n+\t}\n+};\n+\n+const struct qat_qp_hw_data *\n+qat_qp_get_hw_data_gen1(struct qat_pci_device *dev __rte_unused,\n+\t\tenum qat_service_type service_type, uint16_t qp_id)\n+{\n+\treturn qat_gen1_qps[service_type] + qp_id;\n+}\n+\n+int\n+qat_qp_rings_per_service_gen1(struct qat_pci_device *qat_dev,\n+\t\tenum qat_service_type service)\n+{\n+\tint i = 0, count = 0;\n+\n+\tfor (i = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++) {\n+\t\tconst struct qat_qp_hw_data *hw_qps =\n+\t\t\t\tqat_qp_get_hw_data(qat_dev, service, i);\n+\t\tif (hw_qps->service_type == service)\n+\t\t\tcount++;\n+\t}\n+\n+\treturn count;\n+}\n+\n+void\n+qat_qp_csr_build_ring_base_gen1(void *io_addr,\n+\t\t\tstruct qat_queue *queue)\n+{\n+\tuint64_t queue_base;\n+\n+\tqueue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,\n+\t\t\tqueue->queue_size);\n+\tWRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,\n+\t\tqueue->hw_queue_number, queue_base);\n+}\n+\n+void\n+qat_qp_adf_arb_enable_gen1(const struct qat_queue *txq,\n+\t\t\tvoid *base_addr, rte_spinlock_t *lock)\n+{\n+\tuint32_t arb_csr_offset = 0, value;\n+\n+\trte_spinlock_lock(lock);\n+\tarb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +\n+\t\t\t(ADF_ARB_REG_SLOT *\n+\t\t\ttxq->hw_bundle_number);\n+\tvalue = ADF_CSR_RD(base_addr,\n+\t\t\tarb_csr_offset);\n+\tvalue |= (0x01 << txq->hw_queue_number);\n+\tADF_CSR_WR(base_addr, arb_csr_offset, value);\n+\trte_spinlock_unlock(lock);\n+}\n+\n+void\n+qat_qp_adf_arb_disable_gen1(const struct qat_queue *txq,\n+\t\t\tvoid *base_addr, rte_spinlock_t *lock)\n+{\n+\tuint32_t arb_csr_offset =  ADF_ARB_RINGSRVARBEN_OFFSET +\n+\t\t\t\t(ADF_ARB_REG_SLOT * txq->hw_bundle_number);\n+\tuint32_t value;\n+\n+\trte_spinlock_lock(lock);\n+\tvalue = ADF_CSR_RD(base_addr, arb_csr_offset);\n+\tvalue &= ~(0x01 << txq->hw_queue_number);\n+\tADF_CSR_WR(base_addr, arb_csr_offset, value);\n+\trte_spinlock_unlock(lock);\n+}\n+\n+void\n+qat_qp_adf_configure_queues_gen1(struct qat_qp *qp)\n+{\n+\tuint32_t q_tx_config, q_resp_config;\n+\tstruct qat_queue *q_tx = &qp->tx_q, *q_rx = &qp->rx_q;\n+\n+\tq_tx_config = BUILD_RING_CONFIG(q_tx->queue_size);\n+\tq_resp_config = BUILD_RESP_RING_CONFIG(q_rx->queue_size,\n+\t\t\tADF_RING_NEAR_WATERMARK_512,\n+\t\t\tADF_RING_NEAR_WATERMARK_0);\n+\tWRITE_CSR_RING_CONFIG(qp->mmap_bar_addr,\n+\t\tq_tx->hw_bundle_number,\tq_tx->hw_queue_number,\n+\t\tq_tx_config);\n+\tWRITE_CSR_RING_CONFIG(qp->mmap_bar_addr,\n+\t\tq_rx->hw_bundle_number,\tq_rx->hw_queue_number,\n+\t\tq_resp_config);\n+}\n+\n+void\n+qat_qp_csr_write_tail_gen1(struct qat_qp *qp, struct qat_queue *q)\n+{\n+\tWRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,\n+\t\tq->hw_queue_number, q->tail);\n+}\n+\n+void\n+qat_qp_csr_write_head_gen1(struct qat_qp *qp, struct qat_queue *q,\n+\t\t\tuint32_t new_head)\n+{\n+\tWRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,\n+\t\t\tq->hw_queue_number, new_head);\n+}\n+\n+void\n+qat_qp_csr_setup_gen1(struct qat_pci_device *qat_dev,\n+\t\t\tvoid *io_addr, struct qat_qp *qp)\n+{\n+\tqat_qp_csr_build_ring_base_gen1(io_addr, &qp->tx_q);\n+\tqat_qp_csr_build_ring_base_gen1(io_addr, &qp->rx_q);\n+\tqat_qp_adf_configure_queues_gen1(qp);\n+\tqat_qp_adf_arb_enable_gen1(&qp->tx_q, qp->mmap_bar_addr,\n+\t\t\t\t\t&qat_dev->arb_csr_lock);\n+}\n+\n+static struct qat_qp_hw_spec_funcs qat_qp_hw_spec_gen1 = {\n+\t.qat_qp_rings_per_service = qat_qp_rings_per_service_gen1,\n+\t.qat_qp_build_ring_base = qat_qp_csr_build_ring_base_gen1,\n+\t.qat_qp_adf_arb_enable = qat_qp_adf_arb_enable_gen1,\n+\t.qat_qp_adf_arb_disable = qat_qp_adf_arb_disable_gen1,\n+\t.qat_qp_adf_configure_queues = qat_qp_adf_configure_queues_gen1,\n+\t.qat_qp_csr_write_tail = qat_qp_csr_write_tail_gen1,\n+\t.qat_qp_csr_write_head = qat_qp_csr_write_head_gen1,\n+\t.qat_qp_csr_setup = qat_qp_csr_setup_gen1,\n+\t.qat_qp_get_hw_data = qat_qp_get_hw_data_gen1,\n+};\n+\n int\n qat_reset_ring_pairs_gen1(struct qat_pci_device *qat_pci_dev __rte_unused)\n {\n@@ -59,6 +248,7 @@ static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen1 = {\n\n RTE_INIT(qat_dev_gen_gen1_init)\n {\n+\tqat_qp_hw_spec[QAT_GEN1] = &qat_qp_hw_spec_gen1;\n \tqat_dev_hw_spec[QAT_GEN1] = &qat_dev_hw_spec_gen1;\n \tqat_gen_config[QAT_GEN1].dev_gen = QAT_GEN1;\n }\ndiff --git a/drivers/common/qat/dev/qat_dev_gen2.c b/drivers/common/qat/dev/qat_dev_gen2.c\nindex d3470ed6b8..f077fe9eef 100644\n--- a/drivers/common/qat/dev/qat_dev_gen2.c\n+++ b/drivers/common/qat/dev/qat_dev_gen2.c\n@@ -3,11 +3,24 @@\n  */\n\n #include \"qat_device.h\"\n+#include \"qat_qp.h\"\n #include \"adf_transport_access_macros.h\"\n #include \"qat_dev_gens.h\"\n\n #include <stdint.h>\n\n+static struct qat_qp_hw_spec_funcs qat_qp_hw_spec_gen2 = {\n+\t.qat_qp_rings_per_service = qat_qp_rings_per_service_gen1,\n+\t.qat_qp_build_ring_base = qat_qp_csr_build_ring_base_gen1,\n+\t.qat_qp_adf_arb_enable = qat_qp_adf_arb_enable_gen1,\n+\t.qat_qp_adf_arb_disable = qat_qp_adf_arb_disable_gen1,\n+\t.qat_qp_adf_configure_queues = qat_qp_adf_configure_queues_gen1,\n+\t.qat_qp_csr_write_tail = qat_qp_csr_write_tail_gen1,\n+\t.qat_qp_csr_write_head = qat_qp_csr_write_head_gen1,\n+\t.qat_qp_csr_setup = qat_qp_csr_setup_gen1,\n+\t.qat_qp_get_hw_data = qat_qp_get_hw_data_gen1,\n+};\n+\n static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen2 = {\n \t.qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,\n \t.qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,\n@@ -18,6 +31,7 @@ static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen2 = {\n\n RTE_INIT(qat_dev_gen_gen2_init)\n {\n+\tqat_qp_hw_spec[QAT_GEN2] = &qat_qp_hw_spec_gen2;\n \tqat_dev_hw_spec[QAT_GEN2] = &qat_dev_hw_spec_gen2;\n \tqat_gen_config[QAT_GEN2].dev_gen = QAT_GEN2;\n }\ndiff --git a/drivers/common/qat/dev/qat_dev_gen3.c b/drivers/common/qat/dev/qat_dev_gen3.c\nindex e4a66869d2..de3fa17fa9 100644\n--- a/drivers/common/qat/dev/qat_dev_gen3.c\n+++ b/drivers/common/qat/dev/qat_dev_gen3.c\n@@ -3,11 +3,70 @@\n  */\n\n #include \"qat_device.h\"\n+#include \"qat_qp.h\"\n #include \"adf_transport_access_macros.h\"\n #include \"qat_dev_gens.h\"\n\n #include <stdint.h>\n\n+__extension__\n+const struct qat_qp_hw_data qat_gen3_qps[QAT_MAX_SERVICES]\n+\t\t\t\t\t [ADF_MAX_QPS_ON_ANY_SERVICE] = {\n+\t/* queue pairs which provide an asymmetric crypto service */\n+\t[QAT_SERVICE_ASYMMETRIC] = {\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_ASYMMETRIC,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 0,\n+\t\t\t.rx_ring_num = 4,\n+\t\t\t.tx_msg_size = 64,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}\n+\t},\n+\t/* queue pairs which provide a symmetric crypto service */\n+\t[QAT_SERVICE_SYMMETRIC] = {\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_SYMMETRIC,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 1,\n+\t\t\t.rx_ring_num = 5,\n+\t\t\t.tx_msg_size = 128,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}\n+\t},\n+\t/* queue pairs which provide a compression service */\n+\t[QAT_SERVICE_COMPRESSION] = {\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_COMPRESSION,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 3,\n+\t\t\t.rx_ring_num = 7,\n+\t\t\t.tx_msg_size = 128,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}\n+\t}\n+};\n+\n+\n+static const struct qat_qp_hw_data *\n+qat_qp_get_hw_data_gen3(struct qat_pci_device *dev __rte_unused,\n+\t\tenum qat_service_type service_type, uint16_t qp_id)\n+{\n+\treturn qat_gen3_qps[service_type] + qp_id;\n+}\n+\n+static struct qat_qp_hw_spec_funcs qat_qp_hw_spec_gen3 = {\n+\t.qat_qp_rings_per_service  = qat_qp_rings_per_service_gen1,\n+\t.qat_qp_build_ring_base = qat_qp_csr_build_ring_base_gen1,\n+\t.qat_qp_adf_arb_enable = qat_qp_adf_arb_enable_gen1,\n+\t.qat_qp_adf_arb_disable = qat_qp_adf_arb_disable_gen1,\n+\t.qat_qp_adf_configure_queues = qat_qp_adf_configure_queues_gen1,\n+\t.qat_qp_csr_write_tail = qat_qp_csr_write_tail_gen1,\n+\t.qat_qp_csr_write_head = qat_qp_csr_write_head_gen1,\n+\t.qat_qp_csr_setup = qat_qp_csr_setup_gen1,\n+\t.qat_qp_get_hw_data = qat_qp_get_hw_data_gen3\n+};\n+\n static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen3 = {\n \t.qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,\n \t.qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,\n@@ -18,6 +77,7 @@ static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen3 = {\n\n RTE_INIT(qat_dev_gen_gen3_init)\n {\n+\tqat_qp_hw_spec[QAT_GEN3] = &qat_qp_hw_spec_gen3;\n \tqat_dev_hw_spec[QAT_GEN3] = &qat_dev_hw_spec_gen3;\n \tqat_gen_config[QAT_GEN3].dev_gen = QAT_GEN3;\n }\ndiff --git a/drivers/common/qat/dev/qat_dev_gen4.c b/drivers/common/qat/dev/qat_dev_gen4.c\nindex 5e5423ebfa..7ffde5f4c8 100644\n--- a/drivers/common/qat/dev/qat_dev_gen4.c\n+++ b/drivers/common/qat/dev/qat_dev_gen4.c\n@@ -10,10 +10,13 @@\n #include \"adf_transport_access_macros_gen4vf.h\"\n #include \"adf_pf2vf_msg.h\"\n #include \"qat_pf2vf.h\"\n-#include \"qat_dev_gens.h\"\n\n #include <stdint.h>\n\n+/* QAT GEN 4 specific macros */\n+#define QAT_GEN4_BUNDLE_NUM             4\n+#define QAT_GEN4_QPS_PER_BUNDLE_NUM     1\n+\n struct qat_dev_gen4_extra {\n \tstruct qat_qp_hw_data qp_gen4_data[QAT_GEN4_BUNDLE_NUM]\n \t\t[QAT_GEN4_QPS_PER_BUNDLE_NUM];\n@@ -28,7 +31,7 @@ static struct qat_pf2vf_dev qat_pf2vf_gen4 = {\n \t.pf2vf_data_mask = ADF_PFVF_2X_MSGDATA_MASK,\n };\n\n-int\n+static int\n qat_query_svc_gen4(struct qat_pci_device *qat_dev, uint8_t *val)\n {\n \tstruct qat_pf2vf_msg pf2vf_msg;\n@@ -39,6 +42,52 @@ qat_query_svc_gen4(struct qat_pci_device *qat_dev, uint8_t *val)\n \treturn qat_pf2vf_exch_msg(qat_dev, pf2vf_msg, 2, val);\n }\n\n+static int\n+qat_select_valid_queue_gen4(struct qat_pci_device *qat_dev, int qp_id,\n+\t\t\tenum qat_service_type service_type)\n+{\n+\tint i = 0, valid_qps = 0;\n+\tstruct qat_dev_gen4_extra *dev_extra = qat_dev->dev_private;\n+\n+\tfor (; i < QAT_GEN4_BUNDLE_NUM; i++) {\n+\t\tif (dev_extra->qp_gen4_data[i][0].service_type ==\n+\t\t\tservice_type) {\n+\t\t\tif (valid_qps == qp_id)\n+\t\t\t\treturn i;\n+\t\t\t++valid_qps;\n+\t\t}\n+\t}\n+\treturn -1;\n+}\n+\n+static const struct qat_qp_hw_data *\n+qat_qp_get_hw_data_gen4(struct qat_pci_device *qat_dev,\n+\t\tenum qat_service_type service_type, uint16_t qp_id)\n+{\n+\tstruct qat_dev_gen4_extra *dev_extra = qat_dev->dev_private;\n+\tint ring_pair = qat_select_valid_queue_gen4(qat_dev, qp_id,\n+\t\t\tservice_type);\n+\n+\tif (ring_pair < 0)\n+\t\treturn NULL;\n+\n+\treturn &dev_extra->qp_gen4_data[ring_pair][0];\n+}\n+\n+static int\n+qat_qp_rings_per_service_gen4(struct qat_pci_device *qat_dev,\n+\t\tenum qat_service_type service)\n+{\n+\tint i = 0, count = 0, max_ops_per_srv = 0;\n+\tstruct qat_dev_gen4_extra *dev_extra = qat_dev->dev_private;\n+\n+\tmax_ops_per_srv = QAT_GEN4_BUNDLE_NUM;\n+\tfor (i = 0, count = 0; i < max_ops_per_srv; i++)\n+\t\tif (dev_extra->qp_gen4_data[i][0].service_type == service)\n+\t\t\tcount++;\n+\treturn count;\n+}\n+\n static enum qat_service_type\n gen4_pick_service(uint8_t hw_service)\n {\n@@ -94,6 +143,109 @@ qat_dev_read_config_gen4(struct qat_pci_device *qat_dev)\n \treturn 0;\n }\n\n+static void\n+qat_qp_build_ring_base_gen4(void *io_addr,\n+\t\t\tstruct qat_queue *queue)\n+{\n+\tuint64_t queue_base;\n+\n+\tqueue_base = BUILD_RING_BASE_ADDR_GEN4(queue->base_phys_addr,\n+\t\t\tqueue->queue_size);\n+\tWRITE_CSR_RING_BASE_GEN4VF(io_addr, queue->hw_bundle_number,\n+\t\tqueue->hw_queue_number, queue_base);\n+}\n+\n+static void\n+qat_qp_adf_arb_enable_gen4(const struct qat_queue *txq,\n+\t\t\tvoid *base_addr, rte_spinlock_t *lock)\n+{\n+\tuint32_t arb_csr_offset = 0, value;\n+\n+\trte_spinlock_lock(lock);\n+\tarb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +\n+\t\t\t(ADF_RING_BUNDLE_SIZE_GEN4 *\n+\t\t\ttxq->hw_bundle_number);\n+\tvalue = ADF_CSR_RD(base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4VF,\n+\t\t\tarb_csr_offset);\n+\tvalue |= (0x01 << txq->hw_queue_number);\n+\tADF_CSR_WR(base_addr, arb_csr_offset, value);\n+\trte_spinlock_unlock(lock);\n+}\n+\n+static void\n+qat_qp_adf_arb_disable_gen4(const struct qat_queue *txq,\n+\t\t\tvoid *base_addr, rte_spinlock_t *lock)\n+{\n+\tuint32_t arb_csr_offset = 0, value;\n+\n+\trte_spinlock_lock(lock);\n+\tarb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +\n+\t\t\t(ADF_RING_BUNDLE_SIZE_GEN4 *\n+\t\t\ttxq->hw_bundle_number);\n+\tvalue = ADF_CSR_RD(base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4VF,\n+\t\t\tarb_csr_offset);\n+\tvalue &= ~(0x01 << txq->hw_queue_number);\n+\tADF_CSR_WR(base_addr, arb_csr_offset, value);\n+\trte_spinlock_unlock(lock);\n+}\n+\n+static void\n+qat_qp_adf_configure_queues_gen4(struct qat_qp *qp)\n+{\n+\tuint32_t q_tx_config, q_resp_config;\n+\tstruct qat_queue *q_tx = &qp->tx_q, *q_rx = &qp->rx_q;\n+\n+\tq_tx_config = BUILD_RING_CONFIG(q_tx->queue_size);\n+\tq_resp_config = BUILD_RESP_RING_CONFIG(q_rx->queue_size,\n+\t\t\tADF_RING_NEAR_WATERMARK_512,\n+\t\t\tADF_RING_NEAR_WATERMARK_0);\n+\n+\tWRITE_CSR_RING_CONFIG_GEN4VF(qp->mmap_bar_addr,\n+\t\tq_tx->hw_bundle_number,\tq_tx->hw_queue_number,\n+\t\tq_tx_config);\n+\tWRITE_CSR_RING_CONFIG_GEN4VF(qp->mmap_bar_addr,\n+\t\tq_rx->hw_bundle_number,\tq_rx->hw_queue_number,\n+\t\tq_resp_config);\n+}\n+\n+static void\n+qat_qp_csr_write_tail_gen4(struct qat_qp *qp, struct qat_queue *q)\n+{\n+\tWRITE_CSR_RING_TAIL_GEN4VF(qp->mmap_bar_addr,\n+\t\tq->hw_bundle_number, q->hw_queue_number, q->tail);\n+}\n+\n+static void\n+qat_qp_csr_write_head_gen4(struct qat_qp *qp, struct qat_queue *q,\n+\t\t\tuint32_t new_head)\n+{\n+\tWRITE_CSR_RING_HEAD_GEN4VF(qp->mmap_bar_addr,\n+\t\t\tq->hw_bundle_number, q->hw_queue_number, new_head);\n+}\n+\n+static void\n+qat_qp_csr_setup_gen4(struct qat_pci_device *qat_dev,\n+\t\t\tvoid *io_addr, struct qat_qp *qp)\n+{\n+\tqat_qp_build_ring_base_gen4(io_addr, &qp->tx_q);\n+\tqat_qp_build_ring_base_gen4(io_addr, &qp->rx_q);\n+\tqat_qp_adf_configure_queues_gen4(qp);\n+\tqat_qp_adf_arb_enable_gen4(&qp->tx_q, qp->mmap_bar_addr,\n+\t\t\t\t\t&qat_dev->arb_csr_lock);\n+}\n+\n+static struct qat_qp_hw_spec_funcs qat_qp_hw_spec_gen4 = {\n+\t.qat_qp_rings_per_service = qat_qp_rings_per_service_gen4,\n+\t.qat_qp_build_ring_base = qat_qp_build_ring_base_gen4,\n+\t.qat_qp_adf_arb_enable = qat_qp_adf_arb_enable_gen4,\n+\t.qat_qp_adf_arb_disable = qat_qp_adf_arb_disable_gen4,\n+\t.qat_qp_adf_configure_queues = qat_qp_adf_configure_queues_gen4,\n+\t.qat_qp_csr_write_tail = qat_qp_csr_write_tail_gen4,\n+\t.qat_qp_csr_write_head = qat_qp_csr_write_head_gen4,\n+\t.qat_qp_csr_setup = qat_qp_csr_setup_gen4,\n+\t.qat_qp_get_hw_data = qat_qp_get_hw_data_gen4,\n+};\n+\n static int\n qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev)\n {\n@@ -116,8 +268,8 @@ qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev)\n \treturn 0;\n }\n\n-static const struct\n-rte_mem_resource *qat_dev_get_transport_bar_gen4(struct rte_pci_device *pci_dev)\n+static const struct rte_mem_resource *\n+qat_dev_get_transport_bar_gen4(struct rte_pci_device *pci_dev)\n {\n \treturn &pci_dev->mem_resource[0];\n }\n@@ -146,6 +298,7 @@ static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen4 = {\n\n RTE_INIT(qat_dev_gen_4_init)\n {\n+\tqat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4;\n \tqat_dev_hw_spec[QAT_GEN4] = &qat_dev_hw_spec_gen4;\n \tqat_gen_config[QAT_GEN4].dev_gen = QAT_GEN4;\n \tqat_gen_config[QAT_GEN4].pf2vf_dev = &qat_pf2vf_gen4;\ndiff --git a/drivers/common/qat/dev/qat_dev_gens.h b/drivers/common/qat/dev/qat_dev_gens.h\nindex 4ad0ffa728..7c92f1938c 100644\n--- a/drivers/common/qat/dev/qat_dev_gens.h\n+++ b/drivers/common/qat/dev/qat_dev_gens.h\n@@ -16,6 +16,40 @@ extern const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]\n int\n qat_dev_get_extra_size_gen1(void);\n\n+const struct qat_qp_hw_data *\n+qat_qp_get_hw_data_gen1(struct qat_pci_device *dev,\n+\t\tenum qat_service_type service_type, uint16_t qp_id);\n+\n+int\n+qat_qp_rings_per_service_gen1(struct qat_pci_device *qat_dev,\n+\t\tenum qat_service_type service);\n+\n+void\n+qat_qp_csr_build_ring_base_gen1(void *io_addr,\n+\t\tstruct qat_queue *queue);\n+\n+void\n+qat_qp_adf_arb_enable_gen1(const struct qat_queue *txq,\n+\t\tvoid *base_addr, rte_spinlock_t *lock);\n+\n+void\n+qat_qp_adf_arb_disable_gen1(const struct qat_queue *txq,\n+\t\tvoid *base_addr, rte_spinlock_t *lock);\n+\n+void\n+qat_qp_adf_configure_queues_gen1(struct qat_qp *qp);\n+\n+void\n+qat_qp_csr_write_tail_gen1(struct qat_qp *qp, struct qat_queue *q);\n+\n+void\n+qat_qp_csr_write_head_gen1(struct qat_qp *qp, struct qat_queue *q,\n+\t\tuint32_t new_head);\n+\n+void\n+qat_qp_csr_setup_gen1(struct qat_pci_device *qat_dev,\n+\t\tvoid *io_addr, struct qat_qp *qp);\n+\n int\n qat_reset_ring_pairs_gen1(\n \t\tstruct qat_pci_device *qat_pci_dev);\n@@ -28,7 +62,4 @@ qat_dev_get_misc_bar_gen1(struct rte_mem_resource **mem_resource,\n int\n qat_dev_read_config_gen1(struct qat_pci_device *qat_dev);\n\n-int\n-qat_query_svc_gen4(struct qat_pci_device *qat_dev, uint8_t *val);\n-\n #endif\ndiff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h\nindex 504ffb7236..f98bbb5001 100644\n--- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h\n+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h\n@@ -51,6 +51,8 @@\n #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128\n #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M\n #define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K\n+/* ARB CSR offset */\n+#define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C\n\n /* Maximum number of qps on a device for any service type */\n #define ADF_MAX_QPS_ON_ANY_SERVICE\t2\ndiff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h\nindex 8b69206df5..8233cc045d 100644\n--- a/drivers/common/qat/qat_device.h\n+++ b/drivers/common/qat/qat_device.h\n@@ -128,9 +128,6 @@ struct qat_pci_device {\n \t/* Data relating to compression service */\n \tstruct qat_comp_dev_private *comp_dev;\n \t/**< link back to compressdev private data */\n-\tstruct qat_qp_hw_data qp_gen4_data[QAT_GEN4_BUNDLE_NUM]\n-\t\t[QAT_GEN4_QPS_PER_BUNDLE_NUM];\n-\t/**< Data of ring configuration on gen4 */\n \tvoid *misc_bar_io_addr;\n \t/**< Address of misc bar */\n \tvoid *dev_private;\ndiff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c\nindex 27994036b8..cde421eb77 100644\n--- a/drivers/common/qat/qat_qp.c\n+++ b/drivers/common/qat/qat_qp.c\n@@ -18,124 +18,15 @@\n #include \"qat_sym.h\"\n #include \"qat_asym.h\"\n #include \"qat_comp.h\"\n-#include \"adf_transport_access_macros.h\"\n-#include \"adf_transport_access_macros_gen4vf.h\"\n-#include \"dev/qat_dev_gens.h\"\n\n #define QAT_CQ_MAX_DEQ_RETRIES 10\n\n #define ADF_MAX_DESC\t\t\t\t4096\n #define ADF_MIN_DESC\t\t\t\t128\n\n-#define ADF_ARB_REG_SLOT\t\t\t0x1000\n-#define ADF_ARB_RINGSRVARBEN_OFFSET\t\t0x19C\n-\n-#define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \\\n-\tADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \\\n-\t(ADF_ARB_REG_SLOT * index), value)\n-\n struct qat_qp_hw_spec_funcs*\n \tqat_qp_hw_spec[QAT_N_GENS];\n\n-__extension__\n-const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]\n-\t\t\t\t\t [ADF_MAX_QPS_ON_ANY_SERVICE] = {\n-\t/* queue pairs which provide an asymmetric crypto service */\n-\t[QAT_SERVICE_ASYMMETRIC] = {\n-\t\t{\n-\t\t\t.service_type = QAT_SERVICE_ASYMMETRIC,\n-\t\t\t.hw_bundle_num = 0,\n-\t\t\t.tx_ring_num = 0,\n-\t\t\t.rx_ring_num = 8,\n-\t\t\t.tx_msg_size = 64,\n-\t\t\t.rx_msg_size = 32,\n-\n-\t\t}, {\n-\t\t\t.service_type = QAT_SERVICE_ASYMMETRIC,\n-\t\t\t.hw_bundle_num = 0,\n-\t\t\t.tx_ring_num = 1,\n-\t\t\t.rx_ring_num = 9,\n-\t\t\t.tx_msg_size = 64,\n-\t\t\t.rx_msg_size = 32,\n-\t\t}\n-\t},\n-\t/* queue pairs which provide a symmetric crypto service */\n-\t[QAT_SERVICE_SYMMETRIC] = {\n-\t\t{\n-\t\t\t.service_type = QAT_SERVICE_SYMMETRIC,\n-\t\t\t.hw_bundle_num = 0,\n-\t\t\t.tx_ring_num = 2,\n-\t\t\t.rx_ring_num = 10,\n-\t\t\t.tx_msg_size = 128,\n-\t\t\t.rx_msg_size = 32,\n-\t\t},\n-\t\t{\n-\t\t\t.service_type = QAT_SERVICE_SYMMETRIC,\n-\t\t\t.hw_bundle_num = 0,\n-\t\t\t.tx_ring_num = 3,\n-\t\t\t.rx_ring_num = 11,\n-\t\t\t.tx_msg_size = 128,\n-\t\t\t.rx_msg_size = 32,\n-\t\t}\n-\t},\n-\t/* queue pairs which provide a compression service */\n-\t[QAT_SERVICE_COMPRESSION] = {\n-\t\t{\n-\t\t\t.service_type = QAT_SERVICE_COMPRESSION,\n-\t\t\t.hw_bundle_num = 0,\n-\t\t\t.tx_ring_num = 6,\n-\t\t\t.rx_ring_num = 14,\n-\t\t\t.tx_msg_size = 128,\n-\t\t\t.rx_msg_size = 32,\n-\t\t}, {\n-\t\t\t.service_type = QAT_SERVICE_COMPRESSION,\n-\t\t\t.hw_bundle_num = 0,\n-\t\t\t.tx_ring_num = 7,\n-\t\t\t.rx_ring_num = 15,\n-\t\t\t.tx_msg_size = 128,\n-\t\t\t.rx_msg_size = 32,\n-\t\t}\n-\t}\n-};\n-\n-__extension__\n-const struct qat_qp_hw_data qat_gen3_qps[QAT_MAX_SERVICES]\n-\t\t\t\t\t [ADF_MAX_QPS_ON_ANY_SERVICE] = {\n-\t/* queue pairs which provide an asymmetric crypto service */\n-\t[QAT_SERVICE_ASYMMETRIC] = {\n-\t\t{\n-\t\t\t.service_type = QAT_SERVICE_ASYMMETRIC,\n-\t\t\t.hw_bundle_num = 0,\n-\t\t\t.tx_ring_num = 0,\n-\t\t\t.rx_ring_num = 4,\n-\t\t\t.tx_msg_size = 64,\n-\t\t\t.rx_msg_size = 32,\n-\t\t}\n-\t},\n-\t/* queue pairs which provide a symmetric crypto service */\n-\t[QAT_SERVICE_SYMMETRIC] = {\n-\t\t{\n-\t\t\t.service_type = QAT_SERVICE_SYMMETRIC,\n-\t\t\t.hw_bundle_num = 0,\n-\t\t\t.tx_ring_num = 1,\n-\t\t\t.rx_ring_num = 5,\n-\t\t\t.tx_msg_size = 128,\n-\t\t\t.rx_msg_size = 32,\n-\t\t}\n-\t},\n-\t/* queue pairs which provide a compression service */\n-\t[QAT_SERVICE_COMPRESSION] = {\n-\t\t{\n-\t\t\t.service_type = QAT_SERVICE_COMPRESSION,\n-\t\t\t.hw_bundle_num = 0,\n-\t\t\t.tx_ring_num = 3,\n-\t\t\t.rx_ring_num = 7,\n-\t\t\t.tx_msg_size = 128,\n-\t\t\t.rx_msg_size = 32,\n-\t\t}\n-\t}\n-};\n-\n static int qat_qp_check_queue_alignment(uint64_t phys_addr,\n \tuint32_t queue_size_bytes);\n static void qat_queue_delete(struct qat_queue *queue);\n@@ -143,77 +34,32 @@ static int qat_queue_create(struct qat_pci_device *qat_dev,\n \tstruct qat_queue *queue, struct qat_qp_config *, uint8_t dir);\n static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,\n \tuint32_t *queue_size_for_csr);\n-static void adf_configure_queues(struct qat_qp *queue,\n+static int adf_configure_queues(struct qat_qp *queue,\n \tenum qat_device_gen qat_dev_gen);\n-static void adf_queue_arb_enable(enum qat_device_gen qat_dev_gen,\n+static int adf_queue_arb_enable(struct qat_pci_device *qat_dev,\n \tstruct qat_queue *txq, void *base_addr, rte_spinlock_t *lock);\n-static void adf_queue_arb_disable(enum qat_device_gen qat_dev_gen,\n+static int adf_queue_arb_disable(enum qat_device_gen qat_dev_gen,\n \tstruct qat_queue *txq, void *base_addr, rte_spinlock_t *lock);\n+static int qat_qp_build_ring_base(struct qat_pci_device *qat_dev,\n+\tvoid *io_addr, struct qat_queue *queue);\n+static const struct rte_memzone *queue_dma_zone_reserve(const char *queue_name,\n+\tuint32_t queue_size, int socket_id);\n+static int qat_qp_csr_setup(struct qat_pci_device *qat_dev, void *io_addr,\n+\tstruct qat_qp *qp);\n\n-int qat_qps_per_service(struct qat_pci_device *qat_dev,\n-\t\tenum qat_service_type service)\n-{\n-\tint i = 0, count = 0, max_ops_per_srv = 0;\n-\n-\tif (qat_dev->qat_dev_gen == QAT_GEN4) {\n-\t\tmax_ops_per_srv = QAT_GEN4_BUNDLE_NUM;\n-\t\tfor (i = 0, count = 0; i < max_ops_per_srv; i++)\n-\t\t\tif (qat_dev->qp_gen4_data[i][0].service_type == service)\n-\t\t\t\tcount++;\n-\t} else {\n-\t\tconst struct qat_qp_hw_data *sym_hw_qps =\n-\t\t\t\tqat_gen_config[qat_dev->qat_dev_gen]\n-\t\t\t\t.qp_hw_data[service];\n-\n-\t\tmax_ops_per_srv = ADF_MAX_QPS_ON_ANY_SERVICE;\n-\t\tfor (i = 0, count = 0; i < max_ops_per_srv; i++)\n-\t\t\tif (sym_hw_qps[i].service_type == service)\n-\t\t\t\tcount++;\n-\t}\n-\n-\treturn count;\n-}\n-\n-static const struct rte_memzone *\n-queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,\n-\t\t\tint socket_id)\n-{\n-\tconst struct rte_memzone *mz;\n-\n-\tmz = rte_memzone_lookup(queue_name);\n-\tif (mz != 0) {\n-\t\tif (((size_t)queue_size <= mz->len) &&\n-\t\t\t\t((socket_id == SOCKET_ID_ANY) ||\n-\t\t\t\t\t(socket_id == mz->socket_id))) {\n-\t\t\tQAT_LOG(DEBUG, \"re-use memzone already \"\n-\t\t\t\t\t\"allocated for %s\", queue_name);\n-\t\t\treturn mz;\n-\t\t}\n-\n-\t\tQAT_LOG(ERR, \"Incompatible memzone already \"\n-\t\t\t\t\"allocated %s, size %u, socket %d. \"\n-\t\t\t\t\"Requested size %u, socket %u\",\n-\t\t\t\tqueue_name, (uint32_t)mz->len,\n-\t\t\t\tmz->socket_id, queue_size, socket_id);\n-\t\treturn NULL;\n-\t}\n-\n-\tQAT_LOG(DEBUG, \"Allocate memzone for %s, size %u on socket %u\",\n-\t\t\t\t\tqueue_name, queue_size, socket_id);\n-\treturn rte_memzone_reserve_aligned(queue_name, queue_size,\n-\t\tsocket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);\n-}\n-\n-int qat_qp_setup(struct qat_pci_device *qat_dev,\n+int\n+qat_qp_setup(struct qat_pci_device *qat_dev,\n \t\tstruct qat_qp **qp_addr,\n \t\tuint16_t queue_pair_id,\n \t\tstruct qat_qp_config *qat_qp_conf)\n {\n-\tstruct qat_qp *qp;\n+\tstruct qat_qp *qp = NULL;\n \tstruct rte_pci_device *pci_dev =\n \t\t\tqat_pci_devs[qat_dev->qat_dev_id].pci_dev;\n \tchar op_cookie_pool_name[RTE_RING_NAMESIZE];\n-\tenum qat_device_gen qat_dev_gen = qat_dev->qat_dev_gen;\n+\tstruct qat_dev_hw_spec_funcs *ops_hw =\n+\t\tqat_dev_hw_spec[qat_dev->qat_dev_gen];\n+\tvoid *io_addr;\n \tuint32_t i;\n\n \tQAT_LOG(DEBUG, \"Setup qp %u on qat pci device %d gen %d\",\n@@ -226,7 +72,15 @@ int qat_qp_setup(struct qat_pci_device *qat_dev,\n \t\treturn -EINVAL;\n \t}\n\n-\tif (pci_dev->mem_resource[0].addr == NULL) {\n+\tif (ops_hw->qat_dev_get_transport_bar == NULL)\t{\n+\t\tQAT_LOG(ERR,\n+\t\t\t\"QAT Internal Error: qat_dev_get_transport_bar not set for gen %d\",\n+\t\t\tqat_dev->qat_dev_gen);\n+\t\tgoto create_err;\n+\t}\n+\n+\tio_addr = ops_hw->qat_dev_get_transport_bar(pci_dev)->addr;\n+\tif (io_addr == NULL) {\n \t\tQAT_LOG(ERR, \"Could not find VF config space \"\n \t\t\t\t\"(UIO driver attached?).\");\n \t\treturn -EINVAL;\n@@ -250,7 +104,7 @@ int qat_qp_setup(struct qat_pci_device *qat_dev,\n \t\treturn -ENOMEM;\n \t}\n\n-\tqp->mmap_bar_addr = pci_dev->mem_resource[0].addr;\n+\tqp->mmap_bar_addr = io_addr;\n \tqp->enqueued = qp->dequeued = 0;\n\n \tif (qat_queue_create(qat_dev, &(qp->tx_q), qat_qp_conf,\n@@ -277,10 +131,6 @@ int qat_qp_setup(struct qat_pci_device *qat_dev,\n \t\tgoto create_err;\n \t}\n\n-\tadf_configure_queues(qp, qat_dev_gen);\n-\tadf_queue_arb_enable(qat_dev_gen, &qp->tx_q, qp->mmap_bar_addr,\n-\t\t\t\t\t&qat_dev->arb_csr_lock);\n-\n \tsnprintf(op_cookie_pool_name, RTE_RING_NAMESIZE,\n \t\t\t\t\t\"%s%d_cookies_%s_qp%hu\",\n \t\tpci_dev->driver->driver.name, qat_dev->qat_dev_id,\n@@ -298,6 +148,8 @@ int qat_qp_setup(struct qat_pci_device *qat_dev,\n \tif (!qp->op_cookie_pool) {\n \t\tQAT_LOG(ERR, \"QAT PMD Cannot create\"\n \t\t\t\t\" op mempool\");\n+\t\tqat_queue_delete(&(qp->tx_q));\n+\t\tqat_queue_delete(&(qp->rx_q));\n \t\tgoto create_err;\n \t}\n\n@@ -316,91 +168,32 @@ int qat_qp_setup(struct qat_pci_device *qat_dev,\n \tQAT_LOG(DEBUG, \"QP setup complete: id: %d, cookiepool: %s\",\n \t\t\tqueue_pair_id, op_cookie_pool_name);\n\n+\tqat_qp_csr_setup(qat_dev, io_addr, qp);\n+\n \t*qp_addr = qp;\n \treturn 0;\n\n create_err:\n-\tif (qp->op_cookie_pool)\n-\t\trte_mempool_free(qp->op_cookie_pool);\n-\trte_free(qp->op_cookies);\n-\trte_free(qp);\n-\treturn -EFAULT;\n-}\n-\n-\n-int qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr)\n-{\n-\tstruct qat_qp *qp = *qp_addr;\n-\tuint32_t i;\n-\n-\tif (qp == NULL) {\n-\t\tQAT_LOG(DEBUG, \"qp already freed\");\n-\t\treturn 0;\n-\t}\n+\tif (qp) {\n+\t\tif (qp->op_cookie_pool)\n+\t\t\trte_mempool_free(qp->op_cookie_pool);\n\n-\tQAT_LOG(DEBUG, \"Free qp on qat_pci device %d\",\n-\t\t\t\tqp->qat_dev->qat_dev_id);\n-\n-\t/* Don't free memory if there are still responses to be processed */\n-\tif ((qp->enqueued - qp->dequeued) == 0) {\n-\t\tqat_queue_delete(&(qp->tx_q));\n-\t\tqat_queue_delete(&(qp->rx_q));\n-\t} else {\n-\t\treturn -EAGAIN;\n-\t}\n+\t\tif (qp->op_cookies)\n+\t\t\trte_free(qp->op_cookies);\n\n-\tadf_queue_arb_disable(qat_dev_gen, &(qp->tx_q), qp->mmap_bar_addr,\n-\t\t\t\t&qp->qat_dev->arb_csr_lock);\n-\n-\tfor (i = 0; i < qp->nb_descriptors; i++)\n-\t\trte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);\n-\n-\tif (qp->op_cookie_pool)\n-\t\trte_mempool_free(qp->op_cookie_pool);\n-\n-\trte_free(qp->op_cookies);\n-\trte_free(qp);\n-\t*qp_addr = NULL;\n-\treturn 0;\n-}\n-\n-\n-static void qat_queue_delete(struct qat_queue *queue)\n-{\n-\tconst struct rte_memzone *mz;\n-\tint status = 0;\n-\n-\tif (queue == NULL) {\n-\t\tQAT_LOG(DEBUG, \"Invalid queue\");\n-\t\treturn;\n+\t\trte_free(qp);\n \t}\n-\tQAT_LOG(DEBUG, \"Free ring %d, memzone: %s\",\n-\t\t\tqueue->hw_queue_number, queue->memz_name);\n\n-\tmz = rte_memzone_lookup(queue->memz_name);\n-\tif (mz != NULL)\t{\n-\t\t/* Write an unused pattern to the queue memory. */\n-\t\tmemset(queue->base_addr, 0x7F, queue->queue_size);\n-\t\tstatus = rte_memzone_free(mz);\n-\t\tif (status != 0)\n-\t\t\tQAT_LOG(ERR, \"Error %d on freeing queue %s\",\n-\t\t\t\t\tstatus, queue->memz_name);\n-\t} else {\n-\t\tQAT_LOG(DEBUG, \"queue %s doesn't exist\",\n-\t\t\t\tqueue->memz_name);\n-\t}\n+\treturn -EFAULT;\n }\n\n static int\n qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,\n \t\tstruct qat_qp_config *qp_conf, uint8_t dir)\n {\n-\tuint64_t queue_base;\n-\tvoid *io_addr;\n \tconst struct rte_memzone *qp_mz;\n \tstruct rte_pci_device *pci_dev =\n \t\t\tqat_pci_devs[qat_dev->qat_dev_id].pci_dev;\n-\tenum qat_device_gen qat_dev_gen = qat_dev->qat_dev_gen;\n \tint ret = 0;\n \tuint16_t desc_size = (dir == ADF_RING_DIR_TX ?\n \t\t\tqp_conf->hw->tx_msg_size : qp_conf->hw->rx_msg_size);\n@@ -460,19 +253,6 @@ qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,\n \t * Write an unused pattern to the queue memory.\n \t */\n \tmemset(queue->base_addr, 0x7F, queue_size_bytes);\n-\tio_addr = pci_dev->mem_resource[0].addr;\n-\n-\tif (qat_dev_gen == QAT_GEN4) {\n-\t\tqueue_base = BUILD_RING_BASE_ADDR_GEN4(queue->base_phys_addr,\n-\t\t\t\t\tqueue->queue_size);\n-\t\tWRITE_CSR_RING_BASE_GEN4VF(io_addr, queue->hw_bundle_number,\n-\t\t\tqueue->hw_queue_number, queue_base);\n-\t} else {\n-\t\tqueue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,\n-\t\t\t\tqueue->queue_size);\n-\t\tWRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,\n-\t\t\tqueue->hw_queue_number, queue_base);\n-\t}\n\n \tQAT_LOG(DEBUG, \"RING: Name:%s, size in CSR: %u, in bytes %u,\"\n \t\t\" nb msgs %u, msg_size %u, modulo mask %u\",\n@@ -488,202 +268,231 @@ qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,\n \treturn ret;\n }\n\n-int\n-qat_select_valid_queue(struct qat_pci_device *qat_dev, int qp_id,\n-\t\t\tenum qat_service_type service_type)\n+static const struct rte_memzone *\n+queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,\n+\t\tint socket_id)\n {\n-\tif (qat_dev->qat_dev_gen == QAT_GEN4) {\n-\t\tint i = 0, valid_qps = 0;\n-\n-\t\tfor (; i < QAT_GEN4_BUNDLE_NUM; i++) {\n-\t\t\tif (qat_dev->qp_gen4_data[i][0].service_type ==\n-\t\t\t\tservice_type) {\n-\t\t\t\tif (valid_qps == qp_id)\n-\t\t\t\t\treturn i;\n-\t\t\t\t++valid_qps;\n-\t\t\t}\n+\tconst struct rte_memzone *mz;\n+\n+\tmz = rte_memzone_lookup(queue_name);\n+\tif (mz != 0) {\n+\t\tif (((size_t)queue_size <= mz->len) &&\n+\t\t\t\t((socket_id == SOCKET_ID_ANY) ||\n+\t\t\t\t\t(socket_id == mz->socket_id))) {\n+\t\t\tQAT_LOG(DEBUG, \"re-use memzone already \"\n+\t\t\t\t\t\"allocated for %s\", queue_name);\n+\t\t\treturn mz;\n \t\t}\n+\n+\t\tQAT_LOG(ERR, \"Incompatible memzone already \"\n+\t\t\t\t\"allocated %s, size %u, socket %d. \"\n+\t\t\t\t\"Requested size %u, socket %u\",\n+\t\t\t\tqueue_name, (uint32_t)mz->len,\n+\t\t\t\tmz->socket_id, queue_size, socket_id);\n+\t\treturn NULL;\n \t}\n-\treturn -1;\n+\n+\tQAT_LOG(DEBUG, \"Allocate memzone for %s, size %u on socket %u\",\n+\t\t\t\t\tqueue_name, queue_size, socket_id);\n+\treturn rte_memzone_reserve_aligned(queue_name, queue_size,\n+\t\tsocket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);\n }\n\n int\n-qat_read_qp_config(struct qat_pci_device *qat_dev)\n+qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr)\n {\n-\tint i = 0;\n-\tenum qat_device_gen qat_dev_gen = qat_dev->qat_dev_gen;\n-\n-\tif (qat_dev_gen == QAT_GEN4) {\n-\t\tuint16_t svc = 0;\n-\n-\t\tif (qat_query_svc_gen4(qat_dev, (uint8_t *)&svc))\n-\t\t\treturn -(EFAULT);\n-\t\tfor (; i < QAT_GEN4_BUNDLE_NUM; i++) {\n-\t\t\tstruct qat_qp_hw_data *hw_data =\n-\t\t\t\t&qat_dev->qp_gen4_data[i][0];\n-\t\t\tuint8_t svc1 = (svc >> (3 * i)) & 0x7;\n-\t\t\tenum qat_service_type service_type = QAT_SERVICE_INVALID;\n-\n-\t\t\tif (svc1 == QAT_SVC_SYM) {\n-\t\t\t\tservice_type = QAT_SERVICE_SYMMETRIC;\n-\t\t\t\tQAT_LOG(DEBUG,\n-\t\t\t\t\t\"Discovered SYMMETRIC service on bundle %d\",\n-\t\t\t\t\ti);\n-\t\t\t} else if (svc1 == QAT_SVC_COMPRESSION) {\n-\t\t\t\tservice_type = QAT_SERVICE_COMPRESSION;\n-\t\t\t\tQAT_LOG(DEBUG,\n-\t\t\t\t\t\"Discovered COPRESSION service on bundle %d\",\n-\t\t\t\t\ti);\n-\t\t\t} else if (svc1 == QAT_SVC_ASYM) {\n-\t\t\t\tservice_type = QAT_SERVICE_ASYMMETRIC;\n-\t\t\t\tQAT_LOG(DEBUG,\n-\t\t\t\t\t\"Discovered ASYMMETRIC service on bundle %d\",\n-\t\t\t\t\ti);\n-\t\t\t} else {\n-\t\t\t\tQAT_LOG(ERR,\n-\t\t\t\t\t\"Unrecognized service on bundle %d\",\n-\t\t\t\t\ti);\n-\t\t\t\treturn -(EFAULT);\n-\t\t\t}\n+\tint ret;\n+\tstruct qat_qp *qp = *qp_addr;\n+\tuint32_t i;\n\n-\t\t\tmemset(hw_data, 0, sizeof(*hw_data));\n-\t\t\thw_data->service_type = service_type;\n-\t\t\tif (service_type == QAT_SERVICE_ASYMMETRIC) {\n-\t\t\t\thw_data->tx_msg_size = 64;\n-\t\t\t\thw_data->rx_msg_size = 32;\n-\t\t\t} else if (service_type == QAT_SERVICE_SYMMETRIC ||\n-\t\t\t\t\tservice_type ==\n-\t\t\t\t\t\tQAT_SERVICE_COMPRESSION) {\n-\t\t\t\thw_data->tx_msg_size = 128;\n-\t\t\t\thw_data->rx_msg_size = 32;\n-\t\t\t}\n-\t\t\thw_data->tx_ring_num = 0;\n-\t\t\thw_data->rx_ring_num = 1;\n-\t\t\thw_data->hw_bundle_num = i;\n-\t\t}\n+\tif (qp == NULL) {\n+\t\tQAT_LOG(DEBUG, \"qp already freed\");\n \t\treturn 0;\n \t}\n-\treturn -(EINVAL);\n+\n+\tQAT_LOG(DEBUG, \"Free qp on qat_pci device %d\",\n+\t\t\t\tqp->qat_dev->qat_dev_id);\n+\n+\t/* Don't free memory if there are still responses to be processed */\n+\tif ((qp->enqueued - qp->dequeued) == 0) {\n+\t\tqat_queue_delete(&(qp->tx_q));\n+\t\tqat_queue_delete(&(qp->rx_q));\n+\t} else {\n+\t\treturn -EAGAIN;\n+\t}\n+\n+\tret = adf_queue_arb_disable(qat_dev_gen, &(qp->tx_q),\n+\t\t\tqp->mmap_bar_addr, &qp->qat_dev->arb_csr_lock);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0; i < qp->nb_descriptors; i++)\n+\t\trte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);\n+\n+\tif (qp->op_cookie_pool)\n+\t\trte_mempool_free(qp->op_cookie_pool);\n+\n+\trte_free(qp->op_cookies);\n+\trte_free(qp);\n+\t*qp_addr = NULL;\n+\treturn 0;\n }\n\n-static int qat_qp_check_queue_alignment(uint64_t phys_addr,\n-\t\t\t\t\tuint32_t queue_size_bytes)\n+\n+static void\n+qat_queue_delete(struct qat_queue *queue)\n {\n-\tif (((queue_size_bytes - 1) & phys_addr) != 0)\n-\t\treturn -EINVAL;\n+\tconst struct rte_memzone *mz;\n+\tint status = 0;\n+\n+\tif (queue == NULL) {\n+\t\tQAT_LOG(DEBUG, \"Invalid queue\");\n+\t\treturn;\n+\t}\n+\tQAT_LOG(DEBUG, \"Free ring %d, memzone: %s\",\n+\t\t\tqueue->hw_queue_number, queue->memz_name);\n+\n+\tmz = rte_memzone_lookup(queue->memz_name);\n+\tif (mz != NULL)\t{\n+\t\t/* Write an unused pattern to the queue memory. */\n+\t\tmemset(queue->base_addr, 0x7F, queue->queue_size);\n+\t\tstatus = rte_memzone_free(mz);\n+\t\tif (status != 0)\n+\t\t\tQAT_LOG(ERR, \"Error %d on freeing queue %s\",\n+\t\t\t\t\tstatus, queue->memz_name);\n+\t} else {\n+\t\tQAT_LOG(DEBUG, \"queue %s doesn't exist\",\n+\t\t\t\tqueue->memz_name);\n+\t}\n+}\n+\n+static int __rte_unused\n+adf_queue_arb_enable(struct qat_pci_device *qat_dev, struct qat_queue *txq,\n+\t\tvoid *base_addr, rte_spinlock_t *lock)\n+{\n+\tstruct qat_qp_hw_spec_funcs *ops =\n+\t\tqat_qp_hw_spec[qat_dev->qat_dev_gen];\n+\n+\tRTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_adf_arb_enable,\n+\t\t\t-ENOTSUP);\n+\tops->qat_qp_adf_arb_enable(txq, base_addr, lock);\n \treturn 0;\n }\n\n-static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,\n-\tuint32_t *p_queue_size_for_csr)\n+static int\n+adf_queue_arb_disable(enum qat_device_gen qat_dev_gen, struct qat_queue *txq,\n+\t\tvoid *base_addr, rte_spinlock_t *lock)\n {\n-\tuint8_t i = ADF_MIN_RING_SIZE;\n+\tstruct qat_qp_hw_spec_funcs *ops =\n+\t\tqat_qp_hw_spec[qat_dev_gen];\n\n-\tfor (; i <= ADF_MAX_RING_SIZE; i++)\n-\t\tif ((msg_size * msg_num) ==\n-\t\t\t\t(uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {\n-\t\t\t*p_queue_size_for_csr = i;\n-\t\t\treturn 0;\n-\t\t}\n-\tQAT_LOG(ERR, \"Invalid ring size %d\", msg_size * msg_num);\n-\treturn -EINVAL;\n+\tRTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_adf_arb_disable,\n+\t\t\t-ENOTSUP);\n+\tops->qat_qp_adf_arb_disable(txq, base_addr, lock);\n+\treturn 0;\n }\n\n-static void\n-adf_queue_arb_enable(enum qat_device_gen qat_dev_gen, struct qat_queue *txq,\n-\t\t\tvoid *base_addr, rte_spinlock_t *lock)\n+static int __rte_unused\n+qat_qp_build_ring_base(struct qat_pci_device *qat_dev, void *io_addr,\n+\t\tstruct qat_queue *queue)\n {\n-\tuint32_t arb_csr_offset = 0, value;\n-\n-\trte_spinlock_lock(lock);\n-\tif (qat_dev_gen == QAT_GEN4) {\n-\t\tarb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +\n-\t\t\t\t(ADF_RING_BUNDLE_SIZE_GEN4 *\n-\t\t\t\ttxq->hw_bundle_number);\n-\t\tvalue = ADF_CSR_RD(base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4VF,\n-\t\t\t\tarb_csr_offset);\n-\t} else {\n-\t\tarb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +\n-\t\t\t\t(ADF_ARB_REG_SLOT *\n-\t\t\t\ttxq->hw_bundle_number);\n-\t\tvalue = ADF_CSR_RD(base_addr,\n-\t\t\t\tarb_csr_offset);\n-\t}\n-\tvalue |= (0x01 << txq->hw_queue_number);\n-\tADF_CSR_WR(base_addr, arb_csr_offset, value);\n-\trte_spinlock_unlock(lock);\n+\tstruct qat_qp_hw_spec_funcs *ops =\n+\t\tqat_qp_hw_spec[qat_dev->qat_dev_gen];\n+\n+\tRTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_build_ring_base,\n+\t\t\t-ENOTSUP);\n+\tops->qat_qp_build_ring_base(io_addr, queue);\n+\treturn 0;\n }\n\n-static void adf_queue_arb_disable(enum qat_device_gen qat_dev_gen,\n-\t\tstruct qat_queue *txq, void *base_addr, rte_spinlock_t *lock)\n+int\n+qat_qps_per_service(struct qat_pci_device *qat_dev,\n+\t\tenum qat_service_type service)\n {\n-\tuint32_t arb_csr_offset = 0, value;\n-\n-\trte_spinlock_lock(lock);\n-\tif (qat_dev_gen == QAT_GEN4) {\n-\t\tarb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +\n-\t\t\t\t(ADF_RING_BUNDLE_SIZE_GEN4 *\n-\t\t\t\ttxq->hw_bundle_number);\n-\t\tvalue = ADF_CSR_RD(base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4VF,\n-\t\t\t\tarb_csr_offset);\n-\t} else {\n-\t\tarb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +\n-\t\t\t\t(ADF_ARB_REG_SLOT *\n-\t\t\t\ttxq->hw_bundle_number);\n-\t\tvalue = ADF_CSR_RD(base_addr,\n-\t\t\t\tarb_csr_offset);\n-\t}\n-\tvalue &= ~(0x01 << txq->hw_queue_number);\n-\tADF_CSR_WR(base_addr, arb_csr_offset, value);\n-\trte_spinlock_unlock(lock);\n+\tstruct qat_qp_hw_spec_funcs *ops =\n+\t\tqat_qp_hw_spec[qat_dev->qat_dev_gen];\n+\n+\tRTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_rings_per_service,\n+\t\t\t-ENOTSUP);\n+\treturn ops->qat_qp_rings_per_service(qat_dev, service);\n }\n\n-static void adf_configure_queues(struct qat_qp *qp,\n-\t\tenum qat_device_gen qat_dev_gen)\n+const struct qat_qp_hw_data *\n+qat_qp_get_hw_data(struct qat_pci_device *qat_dev,\n+\t\tenum qat_service_type service, uint16_t qp_id)\n {\n-\tuint32_t q_tx_config, q_resp_config;\n-\tstruct qat_queue *q_tx = &qp->tx_q, *q_rx = &qp->rx_q;\n-\n-\tq_tx_config = BUILD_RING_CONFIG(q_tx->queue_size);\n-\tq_resp_config = BUILD_RESP_RING_CONFIG(q_rx->queue_size,\n-\t\t\tADF_RING_NEAR_WATERMARK_512,\n-\t\t\tADF_RING_NEAR_WATERMARK_0);\n-\n-\tif (qat_dev_gen == QAT_GEN4) {\n-\t\tWRITE_CSR_RING_CONFIG_GEN4VF(qp->mmap_bar_addr,\n-\t\t\tq_tx->hw_bundle_number,\tq_tx->hw_queue_number,\n-\t\t\tq_tx_config);\n-\t\tWRITE_CSR_RING_CONFIG_GEN4VF(qp->mmap_bar_addr,\n-\t\t\tq_rx->hw_bundle_number,\tq_rx->hw_queue_number,\n-\t\t\tq_resp_config);\n-\t} else {\n-\t\tWRITE_CSR_RING_CONFIG(qp->mmap_bar_addr,\n-\t\t\tq_tx->hw_bundle_number,\tq_tx->hw_queue_number,\n-\t\t\tq_tx_config);\n-\t\tWRITE_CSR_RING_CONFIG(qp->mmap_bar_addr,\n-\t\t\tq_rx->hw_bundle_number,\tq_rx->hw_queue_number,\n-\t\t\tq_resp_config);\n-\t}\n+\tstruct qat_qp_hw_spec_funcs *ops =\n+\t\tqat_qp_hw_spec[qat_dev->qat_dev_gen];\n+\n+\tRTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_get_hw_data, NULL);\n+\treturn ops->qat_qp_get_hw_data(qat_dev, service, qp_id);\n }\n\n-static inline uint32_t adf_modulo(uint32_t data, uint32_t modulo_mask)\n+int\n+qat_read_qp_config(struct qat_pci_device *qat_dev)\n {\n-\treturn data & modulo_mask;\n+\tstruct qat_dev_hw_spec_funcs *ops_hw =\n+\t\tqat_dev_hw_spec[qat_dev->qat_dev_gen];\n+\n+\tRTE_FUNC_PTR_OR_ERR_RET(ops_hw->qat_dev_read_config,\n+\t\t\t-ENOTSUP);\n+\treturn ops_hw->qat_dev_read_config(qat_dev);\n+}\n+\n+static int __rte_unused\n+adf_configure_queues(struct qat_qp *qp, enum qat_device_gen qat_dev_gen)\n+{\n+\tstruct qat_qp_hw_spec_funcs *ops =\n+\t\tqat_qp_hw_spec[qat_dev_gen];\n+\n+\tRTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_adf_configure_queues,\n+\t\t\t-ENOTSUP);\n+\tops->qat_qp_adf_configure_queues(qp);\n+\treturn 0;\n }\n\n static inline void\n txq_write_tail(enum qat_device_gen qat_dev_gen,\n-\t\tstruct qat_qp *qp, struct qat_queue *q) {\n+\t\tstruct qat_qp *qp, struct qat_queue *q)\n+{\n+\tstruct qat_qp_hw_spec_funcs *ops =\n+\t\tqat_qp_hw_spec[qat_dev_gen];\n\n-\tif (qat_dev_gen == QAT_GEN4) {\n-\t\tWRITE_CSR_RING_TAIL_GEN4VF(qp->mmap_bar_addr,\n-\t\t\tq->hw_bundle_number, q->hw_queue_number, q->tail);\n-\t} else {\n-\t\tWRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,\n-\t\t\tq->hw_queue_number, q->tail);\n-\t}\n+\t/*\n+\t * Pointer check should be done during\n+\t * initialization\n+\t */\n+\tops->qat_qp_csr_write_tail(qp, q);\n }\n\n+static inline void\n+qat_qp_csr_write_head(enum qat_device_gen qat_dev_gen, struct qat_qp *qp,\n+\t\t\tstruct qat_queue *q, uint32_t new_head)\n+{\n+\tstruct qat_qp_hw_spec_funcs *ops =\n+\t\tqat_qp_hw_spec[qat_dev_gen];\n+\n+\t/*\n+\t * Pointer check should be done during\n+\t * initialization\n+\t */\n+\tops->qat_qp_csr_write_head(qp, q, new_head);\n+}\n+\n+static int\n+qat_qp_csr_setup(struct qat_pci_device *qat_dev,\n+\t\tvoid *io_addr, struct qat_qp *qp)\n+{\n+\tstruct qat_qp_hw_spec_funcs *ops =\n+\t\tqat_qp_hw_spec[qat_dev->qat_dev_gen];\n+\n+\tRTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_csr_setup,\n+\t\t\t-ENOTSUP);\n+\tops->qat_qp_csr_setup(qat_dev, io_addr, qp);\n+\treturn 0;\n+}\n+\n+\n static inline\n void rxq_free_desc(enum qat_device_gen qat_dev_gen, struct qat_qp *qp,\n \t\t\t\tstruct qat_queue *q)\n@@ -707,15 +516,37 @@ void rxq_free_desc(enum qat_device_gen qat_dev_gen, struct qat_qp *qp,\n \tq->nb_processed_responses = 0;\n \tq->csr_head = new_head;\n\n-\t/* write current head to CSR */\n-\tif (qat_dev_gen == QAT_GEN4) {\n-\t\tWRITE_CSR_RING_HEAD_GEN4VF(qp->mmap_bar_addr,\n-\t\t\tq->hw_bundle_number, q->hw_queue_number, new_head);\n-\t} else {\n-\t\tWRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,\n-\t\t\t\tq->hw_queue_number, new_head);\n-\t}\n+\tqat_qp_csr_write_head(qat_dev_gen, qp, q, new_head);\n+}\n+\n+static int\n+qat_qp_check_queue_alignment(uint64_t phys_addr, uint32_t queue_size_bytes)\n+{\n+\tif (((queue_size_bytes - 1) & phys_addr) != 0)\n+\t\treturn -EINVAL;\n+\treturn 0;\n+}\n+\n+static int\n+adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,\n+\t\tuint32_t *p_queue_size_for_csr)\n+{\n+\tuint8_t i = ADF_MIN_RING_SIZE;\n+\n+\tfor (; i <= ADF_MAX_RING_SIZE; i++)\n+\t\tif ((msg_size * msg_num) ==\n+\t\t\t\t(uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {\n+\t\t\t*p_queue_size_for_csr = i;\n+\t\t\treturn 0;\n+\t\t}\n+\tQAT_LOG(ERR, \"Invalid ring size %d\", msg_size * msg_num);\n+\treturn -EINVAL;\n+}\n\n+static inline uint32_t\n+adf_modulo(uint32_t data, uint32_t modulo_mask)\n+{\n+\treturn data & modulo_mask;\n }\n\n uint16_t\ndiff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h\nindex 726cd2ef61..deafb407b3 100644\n--- a/drivers/common/qat/qat_qp.h\n+++ b/drivers/common/qat/qat_qp.h\n@@ -12,16 +12,6 @@\n\n #define QAT_QP_MIN_INFL_THRESHOLD\t256\n\n-/* Default qp configuration for GEN4 devices */\n-#define QAT_GEN4_QP_DEFCON\t(QAT_SERVICE_SYMMETRIC |\t\\\n-\t\t\t\tQAT_SERVICE_SYMMETRIC << 8 |\t\\\n-\t\t\t\tQAT_SERVICE_SYMMETRIC << 16 |\t\\\n-\t\t\t\tQAT_SERVICE_SYMMETRIC << 24)\n-\n-/* QAT GEN 4 specific macros */\n-#define QAT_GEN4_BUNDLE_NUM             4\n-#define QAT_GEN4_QPS_PER_BUNDLE_NUM     1\n-\n struct qat_pci_device;\n\n /**\n@@ -106,7 +96,11 @@ qat_qp_setup(struct qat_pci_device *qat_dev,\n\n int\n qat_qps_per_service(struct qat_pci_device *qat_dev,\n-\t\t\tenum qat_service_type service);\n+\t\tenum qat_service_type service);\n+\n+const struct qat_qp_hw_data *\n+qat_qp_get_hw_data(struct qat_pci_device *qat_dev,\n+\t\tenum qat_service_type service, uint16_t qp_id);\n\n int\n qat_cq_get_fw_version(struct qat_qp *qp);\n@@ -116,11 +110,6 @@ int\n qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,\n \t\t\t  void *op_cookie __rte_unused,\n \t\t\t  uint64_t *dequeue_err_count __rte_unused);\n-\n-int\n-qat_select_valid_queue(struct qat_pci_device *qat_dev, int qp_id,\n-\t\t\tenum qat_service_type service_type);\n-\n int\n qat_read_qp_config(struct qat_pci_device *qat_dev);\n\n@@ -166,7 +155,4 @@ struct qat_qp_hw_spec_funcs {\n\n extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];\n\n-extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];\n-extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];\n-\n #endif /* _QAT_QP_H_ */\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c\nindex d4f087733f..5b8ee4bee6 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.c\n+++ b/drivers/crypto/qat/qat_sym_pmd.c\n@@ -164,35 +164,11 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tint ret = 0;\n \tuint32_t i;\n \tstruct qat_qp_config qat_qp_conf;\n-\tconst struct qat_qp_hw_data *sym_hw_qps = NULL;\n-\tconst struct qat_qp_hw_data *qp_hw_data = NULL;\n-\n \tstruct qat_qp **qp_addr =\n \t\t\t(struct qat_qp **)&(dev->data->queue_pairs[qp_id]);\n \tstruct qat_sym_dev_private *qat_private = dev->data->dev_private;\n \tstruct qat_pci_device *qat_dev = qat_private->qat_dev;\n\n-\tif (qat_dev->qat_dev_gen == QAT_GEN4) {\n-\t\tint ring_pair =\n-\t\t\tqat_select_valid_queue(qat_dev, qp_id,\n-\t\t\t\tQAT_SERVICE_SYMMETRIC);\n-\n-\t\tif (ring_pair < 0) {\n-\t\t\tQAT_LOG(ERR,\n-\t\t\t\t\"qp_id %u invalid for this device, no enough services allocated for GEN4 device\",\n-\t\t\t\tqp_id);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tsym_hw_qps =\n-\t\t\t&qat_dev->qp_gen4_data[0][0];\n-\t\tqp_hw_data =\n-\t\t\t&qat_dev->qp_gen4_data[ring_pair][0];\n-\t} else {\n-\t\tsym_hw_qps = qat_gen_config[qat_dev->qat_dev_gen]\n-\t\t\t\t.qp_hw_data[QAT_SERVICE_SYMMETRIC];\n-\t\tqp_hw_data = sym_hw_qps + qp_id;\n-\t}\n-\n \t/* If qp is already in use free ring memory and qp metadata. */\n \tif (*qp_addr != NULL) {\n \t\tret = qat_sym_qp_release(dev, qp_id);\n@@ -204,7 +180,13 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\treturn -EINVAL;\n \t}\n\n-\tqat_qp_conf.hw = qp_hw_data;\n+\tqat_qp_conf.hw = qat_qp_get_hw_data(qat_dev, QAT_SERVICE_SYMMETRIC,\n+\t\t\tqp_id);\n+\tif (qat_qp_conf.hw == NULL) {\n+\t\tQAT_LOG(ERR, \"qp_id %u invalid for this device\", qp_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n \tqat_qp_conf.cookie_size = sizeof(struct qat_sym_op_cookie);\n \tqat_qp_conf.nb_descriptors = qp_conf->nb_descriptors;\n \tqat_qp_conf.socket_id = socket_id;\n",
    "prefixes": [
        "v8",
        "4/9"
    ]
}