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GET /api/patches/104461/?format=api
{ "id": 104461, "url": "http://patchwork.dpdk.org/api/patches/104461/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211117105709.2059941-1-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211117105709.2059941-1-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211117105709.2059941-1-michaelba@nvidia.com", "date": "2021-11-17T10:57:09", "name": "common/mlx5: fix user mode register access attribute", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "abc3c5fbbb93f2e0227b7ec36d74d6872a0f943d", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211117105709.2059941-1-michaelba@nvidia.com/mbox/", "series": [ { "id": 20615, "url": "http://patchwork.dpdk.org/api/series/20615/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20615", "date": "2021-11-17T10:57:09", "name": "common/mlx5: fix user mode register access attribute", "version": 1, "mbox": "http://patchwork.dpdk.org/series/20615/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104461/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/104461/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 32F5EA0C41;\n\tWed, 17 Nov 2021 11:57:47 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 254E0411AB;\n\tWed, 17 Nov 2021 11:57:47 +0100 (CET)", "from NAM04-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam08on2072.outbound.protection.outlook.com [40.107.101.72])\n by mails.dpdk.org (Postfix) with ESMTP id C95BE41199;\n Wed, 17 Nov 2021 11:57:45 +0100 (CET)", "from MW4PR04CA0190.namprd04.prod.outlook.com (2603:10b6:303:86::15)\n by CY4PR12MB1719.namprd12.prod.outlook.com (2603:10b6:903:125::17)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4690.18; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "<michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Michael Baum\n <michaelba@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH] common/mlx5: fix user mode register access attribute", "Date": "Wed, 17 Nov 2021 12:57:09 +0200", "Message-ID": "<20211117105709.2059941-1-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "5c93dce1-8c0d-4237-b69d-08d9a9b914a2", "X-MS-TrafficTypeDiagnostic": "CY4PR12MB1719:", "X-Microsoft-Antispam-PRVS": "\n <CY4PR12MB171940257040EB40414378C4CC9A9@CY4PR12MB1719.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6430;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n TmQ2nzu7A7iWfTk4f/UkQokjwXRrgwVAySSOqU/piZ6a1AFNnzswEjipbEuc88j1U6ra4LXROYfxtuBbPf8Z8eh/d2UZgVGUVEUWxKuckobG1E/3510zuDMAVXuGM91h1Ba++SE+O4DiZNl2/w5VdNluvkTHQxf5JzydeBtILA0vNGufJdhi5oh5HNnS6x+gZqUEWtOethB/shQ8VlUZm6UT5ezv4Mlzv8x8dc0ZT8Gd/4TV/jWza6cYIVCjh3fdQdwXQ75zhVErA+Cfcil2THHkp2hkql8TCkeJ/nJzf+/+lhpfWlL8Gp3rvGRu9iOz504a8JS3C3HBoInT+U8eHesbT04QdbrcxEusG9O5GTgv5FTbrY+UtPyiO/c1V4uIwSseEZ2AavYC4P85581ejIma0n23iMl1838MHl7r+45K5l/rBG1w13LUjYfN6pwFgH9v8/96DzaIiENRpNNrst8KSxM5hK69tUZOkh7AfdrJSL+ShtGle4MP0IEFrFBCoe2+PIN4hOuFCL8N1ClgpR0b/mKLaD1FqSA3DFD9rba1AT4vUZkmczk7UHrLG2l41vQ0y/dHNm9pz/cIF/h/F9pcDeMMtfDW35V8Da50gjYyI9PWD4h0IruH01Ev2zVohixfYUpCDInKO8PFTZ8SNa4Q67PP8eZG9pQ1FeXX6hKyRbLAe06+KadCqua4Jyfgz2IZPaLJXESRt4i/S4N17Q==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(508600001)(36860700001)(82310400003)(6286002)(55016002)(2906002)(450100002)(8936002)(316002)(4326008)(2616005)(7696005)(47076005)(36756003)(70206006)(8676002)(6916009)(186003)(6666004)(1076003)(426003)(26005)(86362001)(16526019)(356005)(36906005)(7636003)(5660300002)(2876002)(336012)(70586007)(54906003)(83380400001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Nov 2021 10:57:42.8848 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5c93dce1-8c0d-4237-b69d-08d9a9b914a2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT051.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1719", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Michael Baum <michaelba@nvidia.com>\n\nTo detect the timestamp mode configured on the NIC the mlx5 PMD uses the\nfirmware command ACCESS_REGISTER_USER.\nThe HCA capability command has an attribute flag checking whether\nfirmware supports the command.\n\nHowever, the HCA capability query command read the flag from wrong place\nin PRM structure.\n\nThis patch move the plag to correct place.\n\nFixes: 972a1bf8120d (\"common/mlx5: fix user mode register access command\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 7 ++++---\n 1 file changed, 4 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 13959575e3..2ded67e85e 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1370,13 +1370,14 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 reserved_at_bc[0x4];\n \tu8 reserved_at_c0[0x8];\n \tu8 log_max_cq_sz[0x8];\n-\tu8 reserved_at_d0[0xb];\n+\tu8 reserved_at_d0[0x2];\n+\tu8 access_register_user[0x1];\n+\tu8 reserved_at_d3[0x8];\n \tu8 log_max_cq[0x5];\n \tu8 log_max_eq_sz[0x8];\n \tu8 relaxed_ordering_write[0x1];\n \tu8 relaxed_ordering_read[0x1];\n-\tu8 access_register_user[0x1];\n-\tu8 log_max_mkey[0x5];\n+\tu8 log_max_mkey[0x6];\n \tu8 reserved_at_f0[0x8];\n \tu8 dump_fill_mkey[0x1];\n \tu8 reserved_at_f9[0x3];\n", "prefixes": [] }