Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/104541/?format=api
{ "id": 104541, "url": "http://patchwork.dpdk.org/api/patches/104541/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211121081846.10674-1-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211121081846.10674-1-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211121081846.10674-1-getelson@nvidia.com", "date": "2021-11-21T08:18:46", "name": "[v2] doc: add flex item API examples", "commit_ref": null, "pull_url": null, "state": "rejected", "archived": true, "hash": "3cceb734728688a5751cad1036303e0caa4c5707", "submitter": { "id": 1882, "url": "http://patchwork.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211121081846.10674-1-getelson@nvidia.com/mbox/", "series": [ { "id": 20668, "url": "http://patchwork.dpdk.org/api/series/20668/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20668", "date": "2021-11-21T08:18:46", "name": "[v2] doc: add flex item API examples", "version": 2, "mbox": "http://patchwork.dpdk.org/series/20668/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104541/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/104541/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B7E78A0C4C;\n\tSun, 21 Nov 2021 09:19:08 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3DBE64014E;\n\tSun, 21 Nov 2021 09:19:08 +0100 (CET)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam07on2066.outbound.protection.outlook.com [40.107.212.66])\n by mails.dpdk.org (Postfix) with ESMTP id 5023F40143\n for <dev@dpdk.org>; Sun, 21 Nov 2021 09:19:07 +0100 (CET)", "from MW4PR04CA0156.namprd04.prod.outlook.com (2603:10b6:303:85::11)\n by BL0PR12MB4738.namprd12.prod.outlook.com (2603:10b6:208:8e::13)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; Sun, 21 Nov\n 2021 08:19:04 +0000", "from CO1NAM11FT023.eop-nam11.prod.protection.outlook.com\n (2603:10b6:303:85:cafe::59) by MW4PR04CA0156.outlook.office365.com\n (2603:10b6:303:85::11) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.22 via Frontend\n Transport; Sun, 21 Nov 2021 08:19:04 +0000", "from mail.nvidia.com (216.228.112.34) by\n CO1NAM11FT023.mail.protection.outlook.com (10.13.175.35) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4713.20 via Frontend Transport; Sun, 21 Nov 2021 08:19:03 +0000", "from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 21 Nov\n 2021 08:19:00 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=TqD0+GmhtuXcc+pgnh92pAUyAtCh8x2eeuOl8GdKPzuo61DoynZANLhvu8osyDiRcDTfsF3fEFrmQt3H0BdBwruxGiHB5lVoKa3ue7fwFp6GCvtmF1tXT1ptHSUG614PcuqWmrMwwZyfYw8UB3LFlLnA4H+4RhAZaJ56iFrpT6bXJGQuTSIYlQRv7Q+/QUcIAqsPQJyeUYnWM95amNq9BmsKsCns5qXCrzTZfLDrCeJtS4WdEZvdXlrVodb7Oeq5tQchuMNw9MOjcuAhe50MNI3XaYg5m0VwPzVA4W15yfp0tWV0V035OtsaYq8xqkzqlJGpTMcgBxxshaItW++ezw==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=lYTqce8sfFm3fM+PB99itjiBO15KFinCTqQydVeWn6U=;\n b=oah1dwDKRAdFDAx9QdcbkRMjNhE1sRovcKXnyr71vxwVGUg29KWDXJgB3I0LYuYfyoiRcx0uKIiAN0yXTE+LW2mKUatL9N4ENAnXGv8MC/V5EEFrQB9jiCwmfb0+bFJtHq/nLY+t6/0yOhkNRnWuHvPWAOzpelJpq2IcgovaCpVPomurcEBhCE7d925n+CF0077L1cP4mMVxNehs1VGzdGrgUc5iIkdfYmSNoKPfpg6d7bbCxzz3uaRpM/Egxv92EeL3kpLyD1NTxS9YYKfd/2tuSokgdE82660PprKeWPy9eag2dUU/R+3JvDaf5MOeEIAknb1yUhFeoqEAodbiWA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=quarantine pct=100) action=none\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=lYTqce8sfFm3fM+PB99itjiBO15KFinCTqQydVeWn6U=;\n b=nQe9ZkQmUH88lcHwPHGa3NGxTYaFfrNCpbefCDdIUlEPYMnEMFgpBvxms2ERGj2IbVzmonGQJHzEWGJ7ftvd6LudrRPZd653T4UiGLZKPkNdacMEu62wx9PLeYwIglIWfaNDXCtEBTqGkJX0y8MGzwBmvqF+r+CdyD8viyjm0asGyxQrJ0Nc+bXZkZSi7Z0D1O+E4mQlSY1xA8U+rX0g3KnY5p9D9kmPfw+8zZlXysLJveiLc0jnY5u3HRIM0i3uunjw3BDnb3rSbsDE/rfIACuEwR7sVh6rVyd5dJGO7A60Iv1p9lubwWEjlTEGEeqC11CKC25paayj3+835ejljg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>, <getelson@nvidia.com>", "CC": "<rasland@nvidia.com>, <thomas@monjalon.net>, Ferruh Yigit\n <ferruh.yigit@intel.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Subject": "[PATCH v2] doc: add flex item API examples", "Date": "Sun, 21 Nov 2021 10:18:46 +0200", "Message-ID": "<20211121081846.10674-1-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.34.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "1399ef36-b2d1-4c9b-29e2-08d9acc79474", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB4738:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB4738F683FAAEC7FAC15DF21FA59E9@BL0PR12MB4738.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8882;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n RdpoAKyWCKfSrLIrQhZbEsSStgbAiTrc9Vcw66SWgU3G13eI+HCjmYOvzGjLhpIL+4J1/06eymle6X4W8jiEt3DQpmwS4jnZ4M2PL0OONfIXYMavb2xzrM9KskBr/OctMrk4WNQnCptYK0S750imzxM8xVRxy5s4h0zbhFktXXWrrjBZ9FR/wmXgHB8PdkNF+5szQ84JGHiLLfIIxblKoYCN2nkyT1j3GIRmSkYSyeOu0rqV+BHSMRekdrhOpmet3LlDi7lPOU/JXICJzFpPFZ4cdk+Jon+R296a2dNx9YNSa33EBtDmdJKy8SzsTdkwoBtmdTA7qAfjUlE5I1k/NlVF38z34PRG7FqvP8pJaAj6GZw3avHw4sZbj08dCOEPOGkcx6Jd0Zie5YZUPNV2dt4rTaCzpmOoBn1pPnuZlI3HhowQIM8xmt88Q+kiH8jILpe1ktdPM2kXewi7ebvvnoxeZQqiX2RGKZSGCZoMjCuYhCNJ10BahsY5ZfUd2bflYkz8NO2Nrl2nsleCF5QFjA/nxAO0waRK9ZlvOqJRka9ozQcRNHszbNKwY+K2eqav1qr5cZoLckBjv7R9jM7tcoHaztdy9+vsvxLW2c7yd0B+JBipGMMJkWkWzEmg98WNX77unoqZfNWUwY5huscs9hQCwJwiYt27JfGLsBM05OOHqCHBqJAaNjA4kAU/YItqUHaCg0KA+CvQLNdwzYopVQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(36860700001)(26005)(5660300002)(2616005)(86362001)(336012)(55016002)(16526019)(186003)(7696005)(30864003)(508600001)(82310400003)(426003)(47076005)(7636003)(356005)(7049001)(6666004)(36906005)(1076003)(110136005)(70586007)(36756003)(70206006)(54906003)(2906002)(8676002)(4326008)(107886003)(83380400001)(6286002)(8936002)(316002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Nov 2021 08:19:03.7566 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1399ef36-b2d1-4c9b-29e2-08d9acc79474", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT023.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB4738", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Demonstrate flex item API usage on known network protocols.\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nReviewed-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\nv2: Fix spelling error.\n---\n doc/guides/howto/flex_item.rst | 618 +++++++++++++++++++++++++++++++++\n doc/guides/howto/index.rst | 1 +\n 2 files changed, 619 insertions(+)\n create mode 100644 doc/guides/howto/flex_item.rst", "diff": "diff --git a/doc/guides/howto/flex_item.rst b/doc/guides/howto/flex_item.rst\nnew file mode 100644\nindex 0000000000..db828e3dc8\n--- /dev/null\n+++ b/doc/guides/howto/flex_item.rst\n@@ -0,0 +1,618 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright (c) 2021 NVIDIA Corporation & Affiliates\n+\n+\n+Flex item API - examples\n+========================\n+\n+The document uses known network protocols to demonstrate flex item API\n+programming examples.\n+\n+eCPRI protocol\n+--------------\n+\n+This example demonstrates basic flex item API usage.\n+\n+Header structure\n+~~~~~~~~~~~~~~~~\n+\n+::\n+\n+ 0 1 2 3 4 5 6 7\n+ +----+----+----+----+----+----+----+----+\n+ | protocol version | reserved | C | +0\n+ +----+----+----+----+----+----+----+----+\n+ | message type | +1\n+ +----+----+----+----+----+----+----+----+\n+ | | +2\n+ +---- payload size ----+\n+ | | +3\n+ +----+----+----+----+----+----+----+----+\n+\n+Flex item configuration\n+~~~~~~~~~~~~~~~~~~~~~~~\n+\n+.. code-block:: c\n+ :linenos:\n+\n+ #include <rte_flow.h>\n+\n+ const struct rte_flow_item_flex_conf ecpri_flex_conf = {\n+ /* single eCPRI header in a packet. Can be ether inner or outer */\n+ .tunnel = FLEX_TUNNEL_MODE_SINGLE,\n+\n+ /* eCPRI header size description */\n+ .next_header = {\n+ .field_mode = FIELD_MODE_FIXED, /* fixed-size header */\n+ .field_size = 4 * sizeof(char) * CHAR_BIT;\n+ },\n+\n+ /* eCPRI header is followed by a payload */\n+ .next_protocol = {},\n+\n+ /* single sample that covers entire eCPRI header */\n+ .sample_data = {\n+ {\n+ .field_mode = FIELD_MODE_FIXED,\n+ .field_size = 4 * sizeof(char) * CHAR_BIT,\n+ .field_base = 0\n+ }\n+ },\n+ .nb_samples = 1,\n+\n+ /* eCPRI protocol follows ether Ethernet or UDP headers */\n+ .input_link = {\n+ {\n+ .item = {\n+ .type = RTE_FLOW_ITEM_TYPE_ETH,\n+ .spec = &(struct rte_flow_item_eth) {\n+ .type = rte_cpu_to_be_16(0xAEFE),\n+ },\n+ }\n+ },\n+ {\n+ .item = {\n+ .type = RTE_FLOW_ITEM_TYPE_UDP,\n+ .spec = &(struct rte_flow_item_udp) {\n+ .hdr.dst_port = rte_cpu_to_be_16(0xAEFE)\n+ },\n+ }\n+ },\n+ },\n+ .nb_inputs = 2,\n+\n+ /* no network protocol follows eCPRI header */\n+ .nb_outputs = 0;\n+ };\n+\n+ struct rte_flow_item_flex_handle *ecpri_flex_handle;\n+ ecpri_flex_handle = rte_flow_flex_item_create(port_id, ecpri_flex_conf, error);\n+\n+Flex flow item\n+~~~~~~~~~~~~~~\n+\n+Application defined structure to match eCPRI header:\n+\n+.. code-block:: c\n+ :linenos:\n+\n+ struct ecpri_hdr {\n+ unsigned char version:4;\n+ unsigned char reserved:3;\n+ unsigned char c:1;\n+ unsigned char msg_type;\n+ unsigned short payload_size;\n+ } __rte_packed;\n+\n+\n+* Match all but last eCPRI PDUs:\n+\n+ .. code-block:: c\n+ :linenos:\n+\n+ const struct ecpri_hdr ecpri_not_last_spec = {\n+ .version = 1,\n+ .c = 1\n+ };\n+ const struct ecpri_hdr ecpri_not_last_mask = {\n+ .version = 0xf,\n+ .c = 1\n+ };\n+\n+ const struct rte_flow_item_flex ecpri_not_last_flex_spec = {\n+ .handle = ecpri_flex_handle,\n+ .length = sizeof(ecpri_not_last_spec),\n+ .pattern = &ecpri_not_last_spec\n+ };\n+\n+ const struct rte_flow_item_flex ecpri_not_last_flex_mask = {\n+ .handle = ecpri_flex_handle,\n+ .length = sizeof(ecpri_not_last_mask),\n+ .pattern = &ecpri_not_last_mask\n+ };\n+\n+ const struct rte_flow_item ecpri_not_last_flow_item = {\n+ .type = RTE_FLOW_ITEM_TYPE_FLEX,\n+ .spec = (const void *)&ecpri_not_last_flex_spec,\n+ .mask = (const void *)&ecpri_not_last_flex_mask,\n+ };\n+\n+* Match ``Generic Data Transfer`` type eCPRI PDUs:\n+\n+ .. code-block:: c\n+ :linenos:\n+\n+ const struct ecpri_hdr ecpri_data_transfer_spec = {\n+ .version = 1,\n+ .msg_type = 3\n+ };\n+ const struct ecpri_hdr ecpri_data_transfer_mask = {\n+ .version = 0xf,\n+ .msg_type = 0xff\n+ };\n+\n+ const struct rte_flow_item_flex ecpri_data_transfer_flex_spec = {\n+ .handle = ecpri_flex_handle,\n+ .length = sizeof(ecpri_data_transfer_spec),\n+ .pattern = &ecpri_data_transfer_spec\n+ };\n+\n+ const struct rte_flow_item_flex ecpri_data_transfer_flex_mask = {\n+ .handle = ecpri_flex_handle,\n+ .length = sizeof(ecpri_data_transfer_mask),\n+ .pattern = &ecpri_data_transfer_mask\n+ };\n+\n+ const struct rte_flow_item ecpri_data_transfer_flow_item = {\n+ .type = RTE_FLOW_ITEM_TYPE_FLEX,\n+ .spec = (const void *)&ecpri_data_transfer_flex_spec,\n+ .mask = (const void *)&ecpri_data_transfer_flex_mask,\n+ };\n+\n+Geneve protocol\n+---------------\n+\n+Demonstrate flex item API usage with variable length network header.\n+Protocol header is built from a fixed size section that is followed by\n+variable size section.\n+\n+\n+Header Structure\n+~~~~~~~~~~~~~~~~\n+\n+Geneve header format:\n+\n+::\n+\n+ 1 2 3\n+ 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ |Ver| Opt Len |O|C| Rsvd. | Protocol Type |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ | Virtual Network Identifier (VNI) | Reserved |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ | |\n+ ~ Variable-Length Options ~\n+ | |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+\n+Geneve option format:\n+\n+::\n+\n+ 0 1 2 3\n+ 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ | Option Class | Type |R|R|R| Length |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ | |\n+ ~ Variable-Length Option Data ~\n+ | |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+\n+Flex item configuration\n+~~~~~~~~~~~~~~~~~~~~~~~\n+\n+.. code-block:: c\n+ :linenos:\n+\n+ #include <rte_flow.h>\n+\n+ const struct rte_flow_item_flex_conf geneve_flex_conf = {\n+ /* Geneve is tunnel protocol */\n+ .tunnel = FLEX_TUNNEL_MODE_TUNNEL,\n+\n+ /*\n+ * Geneve header size description\n+ * Header size calculation: field_size + ([Length] & offset_mask) << offset_shift\n+ */\n+ .next_header = {\n+ .field_mode = FIELD_MODE_OFFSET, /* variable header length */\n+ .field_size = 2 * sizeof(int) * CHAR_BIT, /* minimal header size */\n+ .offset_base = 2, /* length extension location in the header */\n+ .offset_mask = 0x3f, /* length extension mask */\n+ .offset_shift = 3, /* length extension scale factor */\n+ },\n+\n+ /* next protocol location in Geneve header */\n+ .next_protocol = {\n+ .field_base = 16,\n+ .field_size = 16,\n+ },\n+\n+ /* Samples for flow matches */\n+ .sample_data = {\n+ /* sample first 2 double words */\n+ {\n+ .field_mode = FIELD_MODE_FIXED,\n+ .field_size = 64,\n+ .field_base = 0,\n+ },\n+ /* sample 6 optional double words */\n+ {\n+ .field_mode = FIELD_MODE_FIXED,\n+ .field_size = 192,\n+ .field_base = 64,\n+ },\n+ },\n+ .nb_samples = 2,\n+\n+ /* Geneve follows UDP header */\n+ .input_link = {\n+ {\n+ .item = {\n+ .type = RTE_FLOW_ITEM_TYPE_UDP,\n+ .spec = &(struct rte_flow_item_udp) {\n+ .hdr.dst_port = rte_cpu_to_be_16(6081)\n+ }\n+ }\n+ }\n+ },\n+ .nb_inputs = 1,\n+\n+ .output_link = {\n+ {\n+ .item = { .type = RTE_FLOW_ITEM_TYPE_ETH },\n+ .next = rte_cpu_to_be_16(0x6558)\n+ },\n+ {\n+ .item = { .type = RTE_FLOW_ITEM_TYPE_IPv4 },\n+ .next = rte_cpu_to_be_16(0x0800)\n+ },\n+ {\n+ .item = { .type = RTE_FLOW_ITEM_TYPE_IPv6 },\n+ .next = rte_cpu_to_be_16(0x86dd)\n+ },\n+ },\n+ .nb_output = 3\n+ };\n+\n+ struct rte_flow_item_flex_handle *geneve_flex_handle;\n+ geneve_flex_handle = rte_flow_flex_item_create(port_id, geneve_flex_conf, error);\n+\n+Flex flow item\n+~~~~~~~~~~~~~~\n+\n+Application defined structure for Geneve header:\n+\n+.. code-block:: c\n+ :linenos:\n+\n+ struct geneve_hdr {\n+ unsigned int ver:2;\n+ unsigned int opt_len:6;\n+ unsigned int o:1;\n+ unsigned int c:1;\n+ unsigned int reserved1:6;\n+ unsigned int next_protocol:16;\n+ unsigned int vni:24;\n+ unsigned int reserved2:8;\n+ unsigned long options[];\n+ } __rte_packed;\n+\n+ struct geneve_option_hdr {\n+ unsigned int class:16;\n+ unsigned int type:8;\n+ unsigned int flags:3;\n+ unsigned int length:5;\n+ unsigned int data[];\n+ } __rte_packed;\n+\n+* Match Geneve basic header\n+\n+ .. code-block:: c\n+ :linenos:\n+\n+ const struct geneve_hdr geneve_basic_header_spec = {\n+ .ver = 0,\n+ .opt_len = 0,\n+ };\n+ const struct geneve_hdr geneve_basic_header_mask = {\n+ .ver = 3,\n+ .opt_len = 0x3f,\n+ };\n+\n+ const struct rte_flow_item_flex geneve_basic_header_flex_spec = {\n+ .handle = geneve_flex_handle,\n+ .length = sizeof(geneve_basic_header_spec),\n+ .pattern = &geneve_basic_header_spec\n+ };\n+\n+ const struct rte_flow_item_flex geneve_basic_header_flex_mask = {\n+ .handle = geneve_flex_handle,\n+ .length = sizeof(geneve_basic_header_mask),\n+ .pattern = &geneve_basic_header_mask\n+ };\n+\n+ const struct rte_flow_item geneve_basic_header_flow_item = {\n+ .type = RTE_FLOW_ITEM_TYPE_FLEX,\n+ .spec = (const void *)&geneve_basic_header_flex_spec,\n+ .mask = (const void *)&geneve_basic_header_flex_mask,\n+ };\n+\n+* Match if the first option class is Open vSwitch\n+\n+ .. code-block:: c\n+ :linenos:\n+\n+ const struct geneve_option_hdr geneve_ovs_opt_spec = {\n+ .class = rte_cpu_to_be16(0x0101),\n+ };\n+\n+ const struct geneve_option_hdr geneve_ovs_opt_mask = {\n+ .class = 0xffff,\n+ };\n+\n+ const struct geneve_hdr geneve_hdr_with_ovs_spec = {\n+ .ver = 0,\n+ .options = (const unsigned long *)&geneve_ovs_opt_spec\n+ };\n+\n+ const struct geneve_hdr geneve_hdr_with_ovs_mask = {\n+ .ver = 3,\n+ .options = (const unsigned long *)&geneve_ovs_opt_mask\n+ };\n+\n+ const struct rte_flow_item_flex geneve_flex_spec = {\n+ .handle = geneve_flex_handle,\n+ .length = sizeof(geneve_hdr_with_ovs_spec) + sizeof(geneve_ovs_opt_spec),\n+ .pattern = &geneve_hdr_with_ovs_spec\n+ };\n+\n+ const struct rte_flow_item_flex geneve_flex_mask = {\n+ .handle = geneve_flex_handle,\n+ .length = sizeof(geneve_hdr_with_ovs_mask) + sizeof(geneve_ovs_opt_mask),\n+ .pattern = &geneve_hdr_with_ovs_mask\n+ };\n+\n+ const struct rte_flow_item geneve_vni_flow_item = {\n+ .type = RTE_FLOW_ITEM_TYPE_FLEX,\n+ .spec = (const void *)&geneve_flex_spec,\n+ .mask = (const void *)&geneve_flex_mask,\n+ };\n+\n+Extended GRE packet header (RFC 2890)\n+-------------------------------------\n+\n+This example shows how to configure flex item if protocol header length\n+depends on a bitmask.\n+\n+Header structure\n+~~~~~~~~~~~~~~~~\n+\n+::\n+\n+ 1 2 3\n+ 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ |C| |K|S| Reserved0 | Ver | Protocol Type |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ | Checksum (optional) | Reserved1 (Optional) |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ | Key (optional) |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ | Sequence Number (Optional) |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+\n+\n+Flex item configuration\n+~~~~~~~~~~~~~~~~~~~~~~~\n+\n+.. code-block:: c\n+ :linenos:\n+\n+ #include <rte_flow.h>\n+\n+ const struct rte_flow_item_flex_conf egre_flex_conf = {\n+ /* eGRE is tunnel protocol */\n+ .tunnel = FLEX_TUNNEL_MODE_TUNNEL,\n+\n+ /*\n+ * Header size description.\n+ * Header calculation field_size + (bitcount([C|K|S]) & offset_mask) << offset_shift\n+ */\n+ .next_header = {\n+ .field_mode = FIELD_MODE_BITMASK,\n+ .field_size = sizeof(int) * CHAR_BIT,\n+ .offset_base = 0,\n+ .offset_mask = 3,\n+ .offset_shift = 2\n+ },\n+\n+ /*\n+ * Samples for flow match.\n+ * Adjust samples for maximal header length.\n+ */\n+ .sample_data = {\n+ {\n+ .field_mode = FIELD_MODE_FIXED,\n+ .filed_size = 4 * sizeof(int) * CHAR_BIT,\n+ .field_base = 0\n+ }\n+ }\n+ .nb_samples = 1,\n+\n+ /* eGRE follows IPv4 or IPv6 */\n+ .input_link = {\n+ {\n+ .item = {\n+ .type = RTE_FLOW_ITEM_TYPE_IPV4,\n+ .spec = &(struct rte_flow_item_ipv4) {\n+ .hdr.next_proto_id = 47\n+ }\n+ }\n+ },\n+ {\n+ .item = {\n+ .type = RTE_FLOW_ITEM_TYPE_IPV6,\n+ .spec = &(struct rte_flow_item_ipv6) {\n+ .hdr.proto = 47\n+ }\n+ }\n+ }\n+ },\n+ .nb_inputs = 2,\n+\n+ .output_link = {\n+ {\n+ .item = { .type = RTE_FLOW_ITEM_TYPE_ETH },\n+ .next = rte_cpu_to_be_16(0x6558)\n+ },\n+ {\n+ .item = { .type = RTE_FLOW_ITEM_TYPE_IPv4 },\n+ .next = rte_cpu_to_be_16(0x0800)\n+ },\n+ {\n+ .item = { .type = RTE_FLOW_ITEM_TYPE_IPv6 },\n+ .next = rte_cpu_to_be_16(0x86dd)\n+ },\n+ },\n+ .nb_output = 3\n+ };\n+\n+ struct rte_flow_item_flex_handle *egre_flex_handle;\n+ egre_flex_handle = rte_flow_flex_item_create(port_id, egre_flex_conf, error);\n+\n+Flex flow item\n+~~~~~~~~~~~~~~\n+\n+Application defined eGRE header structure:\n+\n+.. code-block:: c\n+ :linenos:\n+\n+ struct egre_hdr {\n+ unsigned int c:1;\n+ unsigned int reserved_bit:1;\n+ unsigned int k:1;\n+ unsigned int s:1;\n+ unsigned int reserved0:9;\n+ unsigned int ver:3;\n+ unsigned int protocol:16;\n+ unsigned int optional_cks[];\n+ };\n+\n+* Match eGRE header\n+\n+.. code-block:: c\n+ :linenos:\n+\n+ const struct egre_hdr egre_hdr_spec = {\n+ .version = 0\n+ };\n+\n+ const struct egre_hdr egre_hdr_mask = {\n+ .version = 7\n+ };\n+\n+ const struct rte_flow_item_flex egre_flex_item_spec = {\n+ .handle = egre_flex_handle,\n+ .length = sizeof(egre_hdr_spec),\n+ .pattern = &egre_hdr_spec\n+ };\n+\n+ const struct rte_flow_item_flex egre_flex_item_mask = {\n+ .handle = egre_flex_handle,\n+ .length = sizeof(egre_hdr_mask),\n+ .pattern = &egre_hdr_mask\n+ };\n+\n+ const struct rte_flow_item egre_item_spec = {\n+ .type = RTE_FLOW_ITEM_TYPE_FLEX,\n+ .spec = (const void *)&egre_flex_item_spec,\n+ .mask = (const void *)&egre_flex_item_mask\n+ };\n+\n+* Match key value\n+\n+That example needs 2 flow rules - one flow rule to match eGRE header with both\n+C and K flags on and the second flow rule to match eGRE header with K flag only.\n+\n+.. code-block:: c\n+ :linenos:\n+\n+ unsigned int key_val;\n+\n+ /* eGRE header with both C and K flags set */\n+ const struct egre_hdr_ck_spec = {\n+ .c = 1,\n+ .k = 1,\n+ .version = 0,\n+ .optional_cks[1] = ky_val;\n+ };\n+\n+ const struct egre_hdr_ck_mask = {\n+ .c = 1,\n+ .k = 1,\n+ .version = 7,\n+ .optional_cks[1] = 0xffffffff;\n+ };\n+\n+ /* eGRE header with K flag set only */\n+ const struct egre_hdr_k_spec = {\n+ .k = 1,\n+ .version = 0,\n+ .optional_cks[0] = ky_val;\n+ };\n+\n+ const struct egre_hdr_k_mask = {\n+ .k = 1,\n+ .version = 7,\n+ .optional_cks[0] = 0xffffffff;\n+ };\n+\n+ const struct rte_flow_item_flex egre_ck_flex_item_spec = {\n+ .handle = egre_hdr_ck_spec,\n+ .length = sizeof(egre_hdr_ck_spec) + 2 * sizeof(int),\n+ .pattern = &egre_hdr_ck_spec\n+ };\n+\n+ const struct rte_flow_item_flex egre_ck_flex_item_mask = {\n+ .handle = egre_hdr_ck_spec,\n+ .length = sizeof(egre_hdr_ck_spec) + 2 * sizeof(int),\n+ .pattern = &egre_hdr_ck_mask\n+ };\n+\n+ const struct rte_flow_item_flex egre_k_flex_item_spec = {\n+ .handle = egre_hdr_k_spec,\n+ .length = sizeof(egre_hdr_k_spec) + sizeof(int),\n+ .pattern = &egre_hdr_k_spec\n+ };\n+\n+ const struct rte_flow_item_flex egre_k_flex_item_mask = {\n+ .handle = egre_hdr_k_spec,\n+ .length = sizeof(egre_hdr_k_spec) + sizeof(int),\n+ .pattern = &egre_hdr_k_mask\n+ };\n+\n+ const struct rte_flow_item egre_ck_item_spec = {\n+ .type = RTE_FLOW_ITEM_TYPE_FLEX,\n+ .spec = (const void *)&egre_ck_flex_item_spec,\n+ .mask = (const void *)&egre_ck_flex_item_mask\n+ };\n+\n+ const struct rte_flow_item egre_k_item_spec = {\n+ .type = RTE_FLOW_ITEM_TYPE_FLEX,\n+ .spec = (const void *)&egre_k_flex_item_spec,\n+ .mask = (const void *)&egre_k_flex_item_mask\n+ };\ndiff --git a/doc/guides/howto/index.rst b/doc/guides/howto/index.rst\nindex c2a2c60ddb..7232f4d504 100644\n--- a/doc/guides/howto/index.rst\n+++ b/doc/guides/howto/index.rst\n@@ -21,3 +21,4 @@ HowTo Guides\n debug_troubleshoot\n openwrt\n avx512\n+ flex_item\n", "prefixes": [ "v2" ] }