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GET /api/patches/104613/?format=api
{ "id": 104613, "url": "http://patchwork.dpdk.org/api/patches/104613/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211123135741.178491-1-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211123135741.178491-1-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211123135741.178491-1-dsosnowski@nvidia.com", "date": "2021-11-23T13:57:40", "name": "[v2] net/mlx5: fix multi segment packet wraparound", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "588db41783c6fd2be217641935133b589453d5d1", "submitter": { "id": 2386, "url": "http://patchwork.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211123135741.178491-1-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 20710, "url": "http://patchwork.dpdk.org/api/series/20710/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20710", "date": "2021-11-23T13:57:40", "name": "[v2] net/mlx5: fix multi segment packet wraparound", "version": 2, "mbox": "http://patchwork.dpdk.org/series/20710/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104613/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/104613/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 698DEA0C4C;\n\tTue, 23 Nov 2021 14:58:31 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 32B5840688;\n\tTue, 23 Nov 2021 14:58:31 +0100 (CET)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2085.outbound.protection.outlook.com [40.107.93.85])\n by mails.dpdk.org (Postfix) with ESMTP id 1417340040;\n Tue, 23 Nov 2021 14:58:29 +0100 (CET)", "from MW4PR04CA0119.namprd04.prod.outlook.com (2603:10b6:303:83::34)\n by SA0PR12MB4592.namprd12.prod.outlook.com (2603:10b6:806:9b::16)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.22; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>, Raslan Darawsheh <rasland@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH v2] net/mlx5: fix multi segment packet wraparound", "Date": "Tue, 23 Nov 2021 15:57:40 +0200", "Message-ID": "<20211123135741.178491-1-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211119181110.232000-1-dsosnowski@nvidia.com>", "References": "<20211119181110.232000-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "190a2d5a-0472-45ed-6a49-08d9ae8952ac", "X-MS-TrafficTypeDiagnostic": "SA0PR12MB4592:", "X-Microsoft-Antispam-PRVS": "\n <SA0PR12MB4592911C36D90C083305FA16A4609@SA0PR12MB4592.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7691;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n AgUFb4Y7NzMOS6+kEliem0oRI2KFGAhl7dCoOZpMRJuBABUkXZUkyqhY0xfFy0skiR72zxZg+mu7qUeA5Z9bsLV/78E7va6TNVkoqHtfJG9ykIsC+LeTRARkTVL/v2kU2Ksk2fIgCobjuueXQsUNH1xmu/t8vsg1M2AbI0uAZRsHyoOeLQ+oi/Zqdrpn9rZtttmQFDF+tdd9Wr7yqJhWdck8Mc/eR8vYk8L6Mw/ALcSX62PkcBJUOOONbpNmECUoY/1n1jBkgzG0zDiINGfMv5OYqxQ5gniKvPxZxoJJzPcnsrJJk5+ntgGi0HhCAKKGFccC3vexJkz/yCfbqyA55DhxzZNChOVjRc4oxc5ZrjiUqt9cfU0xaaQouZeioHA76RDvmyIdnLcjmw75ehhYr3DNRD1Vn2dx+ypC9+CJp8Pejps3nviVrmSYh1+mxBSP6qFLE3TNI0ilUjEtMN3qNmm26cAn+9GPQqnpQyMuAc+/ILMiLTy8m0k1cRM3RXSKQiqw1OumNQRRmrjpnzASsRo629haMh58qLaEl3ezpGR6eh9UfORGUHGxiRwbOimmxfEyh5qBFM9egkK3xeIPgLUurt4HTyL5N5C6iUGOHBJpX9L94TScR0dJl9GkymGd3u1UYRrA8XODsmvUDaHRcpje08yeIZhcnpgSVsuyF8+q0iSqs7c/dXLH10c3CbPrbhxLhUsXciIfXCBLpxUvhA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(336012)(450100002)(1076003)(426003)(36756003)(5660300002)(82310400004)(70586007)(7696005)(6636002)(316002)(36906005)(508600001)(83380400001)(8676002)(86362001)(6286002)(186003)(47076005)(7636003)(70206006)(36860700001)(16526019)(54906003)(110136005)(8936002)(2906002)(26005)(6666004)(4326008)(356005)(2616005)(55016003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Nov 2021 13:58:26.9350 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 190a2d5a-0472-45ed-6a49-08d9ae8952ac", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT018.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA0PR12MB4592", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch fixes the assertion failure triggered when the user\nconfigured minimum inline length requirements and the application\ntransmitted multi segment packets. Failure was triggered when space left\nin TX queue was not enough to cover this requirement.\n\nThis patch limits the length of data to be copied to the available space\nin TX queue.\n\nFixes: cacb44a09962 (\"net/mlx5: add no-inline Tx flag\")\nCc: viacheslavo@nvidia.com\nCc: stable@dpdk.org\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_tx.h | 7 ++++---\n 1 file changed, 4 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h\nindex bc629983fa..099e72935a 100644\n--- a/drivers/net/mlx5/mlx5_tx.h\n+++ b/drivers/net/mlx5/mlx5_tx.h\n@@ -1071,7 +1071,6 @@ mlx5_tx_mseg_memcpy(uint8_t *pdst,\n \tuint8_t *psrc;\n \n \tMLX5_ASSERT(len);\n-\tMLX5_ASSERT(must <= len);\n \tdo {\n \t\t/* Allow zero length packets, must check first. */\n \t\tdlen = rte_pktmbuf_data_len(loc->mbuf);\n@@ -1098,9 +1097,11 @@ mlx5_tx_mseg_memcpy(uint8_t *pdst,\n \t\t\t\tif (diff <= rte_pktmbuf_data_len(loc->mbuf)) {\n \t\t\t\t\t/*\n \t\t\t\t\t * Copy only the minimal required\n-\t\t\t\t\t * part of the data buffer.\n+\t\t\t\t\t * part of the data buffer. Limit amount\n+\t\t\t\t\t * of data to be copied to the length of\n+\t\t\t\t\t * available space.\n \t\t\t\t\t */\n-\t\t\t\t\tlen = diff;\n+\t\t\t\t\tlen = RTE_MIN(len, diff);\n \t\t\t\t}\n \t\t\t}\n \t\t\tcontinue;\n", "prefixes": [ "v2" ] }