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GET /api/patches/104624/?format=api
http://patchwork.dpdk.org/api/patches/104624/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211123183805.2905792-3-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211123183805.2905792-3-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211123183805.2905792-3-michaelba@nvidia.com", "date": "2021-11-23T18:38:04", "name": "[2/3] net/mlx5: improve stride parameter names", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "bda15ca6e5c22d389507882e6d6dec46c003b62b", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211123183805.2905792-3-michaelba@nvidia.com/mbox/", "series": [ { "id": 20719, "url": "http://patchwork.dpdk.org/api/series/20719/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20719", "date": "2021-11-23T18:38:02", "name": "fix MPRQ prepare", "version": 1, "mbox": "http://patchwork.dpdk.org/series/20719/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104624/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/104624/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B4DFFA0C4C;\n\tTue, 23 Nov 2021 19:38:47 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BDD4E41154;\n\tTue, 23 Nov 2021 19:38:36 +0100 (CET)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2049.outbound.protection.outlook.com [40.107.92.49])\n by mails.dpdk.org (Postfix) with ESMTP id BA4454113D;\n Tue, 23 Nov 2021 19:38:34 +0100 (CET)", "from DM5PR1401CA0019.namprd14.prod.outlook.com (2603:10b6:4:4a::29)\n by BL0PR12MB4737.namprd12.prod.outlook.com (2603:10b6:208:8d::21)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "<michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Michael Baum\n <michaelba@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH 2/3] net/mlx5: improve stride parameter names", "Date": "Tue, 23 Nov 2021 20:38:04 +0200", "Message-ID": "<20211123183805.2905792-3-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211123183805.2905792-1-michaelba@nvidia.com>", "References": "<20211123183805.2905792-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "cab7da8e-c1a4-42ed-3549-08d9aeb07382", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB4737:", "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB47379CACAE26364B30C41DC1CC609@BL0PR12MB4737.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2201;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n LPpWifYppWwgpnM1q5LdtHI3+jG+uspGKjuhZBllYABzl6o6sSwjMOArZ8arM8nAng9+gQJLSgK3o+WCGR+qHWGZaQgwvlgGEOgTqAwpEDauEdcfRgG3/zz8wQM+eMwZ75Gg+LX3Psr9M7P5pHSTEYxOSnqBjF1ePhrjjWhek/X7zjXNK7t/DTnh7pnK1pjz5i9VRZhSzkBzYpv+HSCtuQTlRq/Y3ispjcWsCp+SRP3dHJT99PDx8PHopyTC5SVOIuBqK2cNxKDvwlTIV7tQ/x3uRyTHpib939EQAzvMDEJ3KjF+vYdJoLe/wVzAYhS05xiqgpjpuNfnK/adxlMTLB9slo4AWz4DSakd44H5XQFG0WsTVOxiqPmYI+vuw75YQgtM1Gjz9VGfseTgrM3Sh4A1oiXtmhV9MiJst+8EhB5ULMmL0GidDAnadsphtVWQErXZh3BfSgaR5QZpqH5yRZo+IrPhtRVCUqiQVHwHrn2/QiMhyw7GvJlaQsA3Azk5iz8MosjNim8SLy9LxRgcd0tSDQxJKWv/Sqi3vYBTl4V50F5hpjIJPW1rvb1Vef10zxljejQQRkEduVW/I/RMDN/Ycxp9fVkOJMuzS4Sx/alqlqjS04yb+a6pypl/Kq4NUcVPKNJjvGdmymjrwkAT+97nwvLqFMjHj7tVGwweupYkfpf0hY4n8DMtfOO1Or3HbEBg9wgcqPMO+rINDLl/G5YhSVsne5920NhYAWKqrdA=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(316002)(508600001)(8936002)(1076003)(2616005)(30864003)(47076005)(82310400004)(7696005)(36860700001)(54906003)(70586007)(70206006)(86362001)(36756003)(8676002)(26005)(6916009)(186003)(16526019)(426003)(2876002)(356005)(2906002)(4326008)(7636003)(6286002)(5660300002)(55016003)(83380400001)(6666004)(336012)(450100002)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Nov 2021 18:38:32.3926 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n cab7da8e-c1a4-42ed-3549-08d9aeb07382", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT013.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB4737", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Michael Baum <michaelba@nvidia.com>\n\nIn the striding RQ management there are two important parameters, the\nsize of the single stride in bytes and the number of strides.\n\nBoth the data-path structure and config structure keep the log of the\nabove parameters. However, in their names there is no mention that the\nvalue is a log which may be misleading as if the fields represent the\nvalues themselves.\n\nThis patch updates their names describing the values more accurately.\n\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 38 +++++------\n drivers/net/mlx5/linux/mlx5_verbs.c | 4 +-\n drivers/net/mlx5/mlx5.c | 4 +-\n drivers/net/mlx5/mlx5.h | 8 +--\n drivers/net/mlx5/mlx5_defs.h | 4 +-\n drivers/net/mlx5/mlx5_devx.c | 4 +-\n drivers/net/mlx5/mlx5_rx.c | 22 +++---\n drivers/net/mlx5/mlx5_rx.h | 12 ++--\n drivers/net/mlx5/mlx5_rxq.c | 102 +++++++++++++++-------------\n drivers/net/mlx5/mlx5_rxtx_vec.c | 8 +--\n 10 files changed, 106 insertions(+), 100 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex c29fe3d92b..70472efc29 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1549,34 +1549,34 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tDRV_LOG(DEBUG, \"FCS stripping configuration is %ssupported\",\n \t\t(config->hw_fcs_strip ? \"\" : \"not \"));\n \tif (config->mprq.enabled && mprq) {\n-\t\tif (config->mprq.stride_num_n &&\n-\t\t (config->mprq.stride_num_n > mprq_max_stride_num_n ||\n-\t\t config->mprq.stride_num_n < mprq_min_stride_num_n)) {\n-\t\t\tconfig->mprq.stride_num_n =\n-\t\t\t\tRTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,\n-\t\t\t\t\t\tmprq_min_stride_num_n),\n-\t\t\t\t\tmprq_max_stride_num_n);\n+\t\tif (config->mprq.log_stride_num &&\n+\t\t (config->mprq.log_stride_num > mprq_max_stride_num_n ||\n+\t\t config->mprq.log_stride_num < mprq_min_stride_num_n)) {\n+\t\t\tconfig->mprq.log_stride_num =\n+\t\t\t RTE_MIN(RTE_MAX(MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM,\n+\t\t\t\t\t mprq_min_stride_num_n),\n+\t\t\t\t mprq_max_stride_num_n);\n \t\t\tDRV_LOG(WARNING,\n \t\t\t\t\"the number of strides\"\n \t\t\t\t\" for Multi-Packet RQ is out of range,\"\n \t\t\t\t\" setting default value (%u)\",\n-\t\t\t\t1 << config->mprq.stride_num_n);\n-\t\t}\n-\t\tif (config->mprq.stride_size_n &&\n-\t\t (config->mprq.stride_size_n > mprq_max_stride_size_n ||\n-\t\t config->mprq.stride_size_n < mprq_min_stride_size_n)) {\n-\t\t\tconfig->mprq.stride_size_n =\n-\t\t\t\tRTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,\n-\t\t\t\t\t\tmprq_min_stride_size_n),\n-\t\t\t\t\tmprq_max_stride_size_n);\n+\t\t\t\t1 << config->mprq.log_stride_num);\n+\t\t}\n+\t\tif (config->mprq.log_stride_size &&\n+\t\t (config->mprq.log_stride_size > mprq_max_stride_size_n ||\n+\t\t config->mprq.log_stride_size < mprq_min_stride_size_n)) {\n+\t\t\tconfig->mprq.log_stride_size =\n+\t\t\t RTE_MIN(RTE_MAX(MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE,\n+\t\t\t\t\t mprq_min_stride_size_n),\n+\t\t\t\t mprq_max_stride_size_n);\n \t\t\tDRV_LOG(WARNING,\n \t\t\t\t\"the size of a stride\"\n \t\t\t\t\" for Multi-Packet RQ is out of range,\"\n \t\t\t\t\" setting default value (%u)\",\n-\t\t\t\t1 << config->mprq.stride_size_n);\n+\t\t\t\t1 << config->mprq.log_stride_size);\n \t\t}\n-\t\tconfig->mprq.min_stride_size_n = mprq_min_stride_size_n;\n-\t\tconfig->mprq.max_stride_size_n = mprq_max_stride_size_n;\n+\t\tconfig->mprq.log_min_stride_size = mprq_min_stride_size_n;\n+\t\tconfig->mprq.log_max_stride_size = mprq_max_stride_size_n;\n \t} else if (config->mprq.enabled && !mprq) {\n \t\tDRV_LOG(WARNING, \"Multi-Packet RQ isn't supported\");\n \t\tconfig->mprq.enabled = 0;\ndiff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex 58556d2bf0..2b6eef44a7 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -272,8 +272,8 @@ mlx5_rxq_ibv_wq_create(struct mlx5_rxq_priv *rxq)\n \n \t\twq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;\n \t\t*mprq_attr = (struct mlx5dv_striding_rq_init_attr){\n-\t\t\t.single_stride_log_num_of_bytes = rxq_data->strd_sz_n,\n-\t\t\t.single_wqe_log_num_of_strides = rxq_data->strd_num_n,\n+\t\t\t.single_stride_log_num_of_bytes = rxq_data->log_strd_sz,\n+\t\t\t.single_wqe_log_num_of_strides = rxq_data->log_strd_num,\n \t\t\t.two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,\n \t\t};\n \t}\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 4e04817d11..8c654045c6 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1884,9 +1884,9 @@ mlx5_args_check(const char *key, const char *val, void *opaque)\n \t} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {\n \t\tconfig->mprq.enabled = !!tmp;\n \t} else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {\n-\t\tconfig->mprq.stride_num_n = tmp;\n+\t\tconfig->mprq.log_stride_num = tmp;\n \t} else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {\n-\t\tconfig->mprq.stride_size_n = tmp;\n+\t\tconfig->mprq.log_stride_size = tmp;\n \t} else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {\n \t\tconfig->mprq.max_memcpy_len = tmp;\n \t} else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 8466531060..4ba90db816 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -275,10 +275,10 @@ struct mlx5_dev_config {\n \tunsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */\n \tstruct {\n \t\tunsigned int enabled:1; /* Whether MPRQ is enabled. */\n-\t\tunsigned int stride_num_n; /* Number of strides. */\n-\t\tunsigned int stride_size_n; /* Size of a stride. */\n-\t\tunsigned int min_stride_size_n; /* Min size of a stride. */\n-\t\tunsigned int max_stride_size_n; /* Max size of a stride. */\n+\t\tunsigned int log_stride_num; /* Log number of strides. */\n+\t\tunsigned int log_stride_size; /* Log size of a stride. */\n+\t\tunsigned int log_min_stride_size; /* Log min size of a stride.*/\n+\t\tunsigned int log_max_stride_size; /* Log max size of a stride.*/\n \t\tunsigned int max_memcpy_len;\n \t\t/* Maximum packet size to memcpy Rx packets. */\n \t\tunsigned int min_rxqs_num;\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 258475ed2c..36b384fa08 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -113,10 +113,10 @@\n #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1)\n \n /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */\n-#define MLX5_MPRQ_STRIDE_NUM_N 6U\n+#define MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM 6U\n \n /* Log 2 of the default size of a stride per WQE for Multi-Packet RQ. */\n-#define MLX5_MPRQ_STRIDE_SIZE_N 11U\n+#define MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE 11U\n \n /* Two-byte shift is disabled for Multi-Packet RQ. */\n #define MLX5_MPRQ_TWO_BYTE_SHIFT 0\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 105c3d67f0..91243f684f 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -257,11 +257,11 @@ mlx5_rxq_create_devx_rq_resources(struct mlx5_rxq_priv *rxq)\n \t\t * 512*2^single_wqe_log_num_of_strides.\n \t\t */\n \t\trq_attr.wq_attr.single_wqe_log_num_of_strides =\n-\t\t\t\trxq_data->strd_num_n -\n+\t\t\t\trxq_data->log_strd_num -\n \t\t\t\tMLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;\n \t\t/* Stride size = (2^single_stride_log_num_of_bytes)*64B. */\n \t\trq_attr.wq_attr.single_stride_log_num_of_bytes =\n-\t\t\t\trxq_data->strd_sz_n -\n+\t\t\t\trxq_data->log_strd_sz -\n \t\t\t\tMLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;\n \t\twqe_size = sizeof(struct mlx5_wqe_mprq);\n \t} else {\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex e8215f7381..6b169b33c9 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -73,7 +73,7 @@ rx_queue_count(struct mlx5_rxq_data *rxq)\n \tconst unsigned int cqe_n = (1 << rxq->cqe_n);\n \tconst unsigned int sges_n = (1 << rxq->sges_n);\n \tconst unsigned int elts_n = (1 << rxq->elts_n);\n-\tconst unsigned int strd_n = (1 << rxq->strd_num_n);\n+\tconst unsigned int strd_n = RTE_BIT32(rxq->log_strd_num);\n \tconst unsigned int cqe_cnt = cqe_n - 1;\n \tunsigned int cq_ci, used;\n \n@@ -167,8 +167,8 @@ mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n \tqinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;\n \tqinfo->scattered_rx = dev->data->scattered_rx;\n \tqinfo->nb_desc = mlx5_rxq_mprq_enabled(rxq) ?\n-\t\t(1 << rxq->elts_n) * (1 << rxq->strd_num_n) :\n-\t\t(1 << rxq->elts_n);\n+\t\tRTE_BIT32(rxq->elts_n) * RTE_BIT32(rxq->log_strd_num) :\n+\t\tRTE_BIT32(rxq->elts_n);\n }\n \n /**\n@@ -354,10 +354,10 @@ mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)\n \n \t\t\tscat = &((volatile struct mlx5_wqe_mprq *)\n \t\t\t\trxq->wqes)[i].dseg;\n-\t\t\taddr = (uintptr_t)mlx5_mprq_buf_addr(buf,\n-\t\t\t\t\t\t\t 1 << rxq->strd_num_n);\n-\t\t\tbyte_count = (1 << rxq->strd_sz_n) *\n-\t\t\t\t\t(1 << rxq->strd_num_n);\n+\t\t\taddr = (uintptr_t)mlx5_mprq_buf_addr\n+\t\t\t\t\t(buf, RTE_BIT32(rxq->log_strd_num));\n+\t\t\tbyte_count = RTE_BIT32(rxq->log_strd_sz) *\n+\t\t\t\t RTE_BIT32(rxq->log_strd_num);\n \t\t\tlkey = mlx5_rx_addr2mr(rxq, addr);\n \t\t} else {\n \t\t\tstruct rte_mbuf *buf = (*rxq->elts)[i];\n@@ -383,7 +383,7 @@ mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)\n \t\t.ai = 0,\n \t};\n \trxq->elts_ci = mlx5_rxq_mprq_enabled(rxq) ?\n-\t\t(wqe_n >> rxq->sges_n) * (1 << rxq->strd_num_n) : 0;\n+\t\t(wqe_n >> rxq->sges_n) * RTE_BIT32(rxq->log_strd_num) : 0;\n \t/* Update doorbell counter. */\n \trxq->rq_ci = wqe_n >> rxq->sges_n;\n \trte_io_wmb();\n@@ -412,7 +412,7 @@ mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)\n \tconst uint16_t cqe_n = 1 << rxq->cqe_n;\n \tconst uint16_t cqe_mask = cqe_n - 1;\n \tconst uint16_t wqe_n = 1 << rxq->elts_n;\n-\tconst uint16_t strd_n = 1 << rxq->strd_num_n;\n+\tconst uint16_t strd_n = RTE_BIT32(rxq->log_strd_num);\n \tstruct mlx5_rxq_ctrl *rxq_ctrl =\n \t\t\tcontainer_of(rxq, struct mlx5_rxq_ctrl, rxq);\n \tunion {\n@@ -1045,8 +1045,8 @@ uint16_t\n mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n {\n \tstruct mlx5_rxq_data *rxq = dpdk_rxq;\n-\tconst uint32_t strd_n = 1 << rxq->strd_num_n;\n-\tconst uint32_t strd_sz = 1 << rxq->strd_sz_n;\n+\tconst uint32_t strd_n = RTE_BIT32(rxq->log_strd_num);\n+\tconst uint32_t strd_sz = RTE_BIT32(rxq->log_strd_sz);\n \tconst uint32_t cq_mask = (1 << rxq->cqe_n) - 1;\n \tconst uint32_t wq_mask = (1 << rxq->elts_n) - 1;\n \tvolatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex 9cc1a2703b..4651826a1d 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -88,8 +88,8 @@ struct mlx5_rxq_data {\n \tunsigned int elts_n:4; /* Log 2 of Mbufs. */\n \tunsigned int rss_hash:1; /* RSS hash result is enabled. */\n \tunsigned int mark:1; /* Marked flow available on the queue. */\n-\tunsigned int strd_num_n:5; /* Log 2 of the number of stride. */\n-\tunsigned int strd_sz_n:4; /* Log 2 of stride size. */\n+\tunsigned int log_strd_num:5; /* Log 2 of the number of stride. */\n+\tunsigned int log_strd_sz:4; /* Log 2 of stride size. */\n \tunsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */\n \tunsigned int err_state:2; /* enum mlx5_rxq_err_state. */\n \tunsigned int strd_scatter_en:1; /* Scattered packets from a stride. */\n@@ -395,7 +395,7 @@ mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset,\n static __rte_always_inline void\n mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)\n {\n-\tconst uint32_t strd_n = 1 << rxq->strd_num_n;\n+\tconst uint32_t strd_n = RTE_BIT32(rxq->log_strd_num);\n \tstruct mlx5_mprq_buf *rep = rxq->mprq_repl;\n \tvolatile struct mlx5_wqe_data_seg *wqe =\n \t\t&((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;\n@@ -453,8 +453,8 @@ static __rte_always_inline enum mlx5_rqx_code\n mprq_buf_to_pkt(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, uint32_t len,\n \t\tstruct mlx5_mprq_buf *buf, uint16_t strd_idx, uint16_t strd_cnt)\n {\n-\tconst uint32_t strd_n = 1 << rxq->strd_num_n;\n-\tconst uint16_t strd_sz = 1 << rxq->strd_sz_n;\n+\tconst uint32_t strd_n = RTE_BIT32(rxq->log_strd_num);\n+\tconst uint16_t strd_sz = RTE_BIT32(rxq->log_strd_sz);\n \tconst uint16_t strd_shift =\n \t\tMLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;\n \tconst int32_t hdrm_overlap =\n@@ -599,7 +599,7 @@ mlx5_check_mprq_support(struct rte_eth_dev *dev)\n static __rte_always_inline int\n mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)\n {\n-\treturn rxq->strd_num_n > 0;\n+\treturn rxq->log_strd_num > 0;\n }\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex e406779faf..e76bfaa000 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -67,7 +67,7 @@ mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data)\n \tunsigned int wqe_n = 1 << rxq_data->elts_n;\n \n \tif (mlx5_rxq_mprq_enabled(rxq_data))\n-\t\tcqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;\n+\t\tcqe_n = wqe_n * RTE_BIT32(rxq_data->log_strd_num) - 1;\n \telse\n \t\tcqe_n = wqe_n - 1;\n \treturn cqe_n;\n@@ -137,8 +137,9 @@ rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)\n {\n \tconst unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;\n \tunsigned int elts_n = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?\n-\t\t(1 << rxq_ctrl->rxq.elts_n) * (1 << rxq_ctrl->rxq.strd_num_n) :\n-\t\t(1 << rxq_ctrl->rxq.elts_n);\n+\t\t\t RTE_BIT32(rxq_ctrl->rxq.elts_n) *\n+\t\t\t RTE_BIT32(rxq_ctrl->rxq.log_strd_num) :\n+\t\t\t RTE_BIT32(rxq_ctrl->rxq.elts_n);\n \tunsigned int i;\n \tint err;\n \n@@ -293,8 +294,8 @@ rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)\n {\n \tstruct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;\n \tconst uint16_t q_n = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?\n-\t\t(1 << rxq->elts_n) * (1 << rxq->strd_num_n) :\n-\t\t(1 << rxq->elts_n);\n+\t\tRTE_BIT32(rxq->elts_n) * RTE_BIT32(rxq->log_strd_num) :\n+\t\tRTE_BIT32(rxq->elts_n);\n \tconst uint16_t q_mask = q_n - 1;\n \tuint16_t elts_ci = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?\n \t\trxq->elts_ci : rxq->rq_ci;\n@@ -1373,8 +1374,8 @@ mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)\n \tunsigned int buf_len;\n \tunsigned int obj_num;\n \tunsigned int obj_size;\n-\tunsigned int strd_num_n = 0;\n-\tunsigned int strd_sz_n = 0;\n+\tunsigned int log_strd_num = 0;\n+\tunsigned int log_strd_sz = 0;\n \tunsigned int i;\n \tunsigned int n_ibv = 0;\n \tint ret;\n@@ -1393,16 +1394,18 @@ mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)\n \t\tn_ibv++;\n \t\tdesc += 1 << rxq->elts_n;\n \t\t/* Get the max number of strides. */\n-\t\tif (strd_num_n < rxq->strd_num_n)\n-\t\t\tstrd_num_n = rxq->strd_num_n;\n+\t\tif (log_strd_num < rxq->log_strd_num)\n+\t\t\tlog_strd_num = rxq->log_strd_num;\n \t\t/* Get the max size of a stride. */\n-\t\tif (strd_sz_n < rxq->strd_sz_n)\n-\t\t\tstrd_sz_n = rxq->strd_sz_n;\n-\t}\n-\tMLX5_ASSERT(strd_num_n && strd_sz_n);\n-\tbuf_len = (1 << strd_num_n) * (1 << strd_sz_n);\n-\tobj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *\n-\t\tsizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;\n+\t\tif (log_strd_sz < rxq->log_strd_sz)\n+\t\t\tlog_strd_sz = rxq->log_strd_sz;\n+\t}\n+\tMLX5_ASSERT(log_strd_num && log_strd_sz);\n+\tbuf_len = RTE_BIT32(log_strd_num) * RTE_BIT32(log_strd_sz);\n+\tobj_size = sizeof(struct mlx5_mprq_buf) + buf_len +\n+\t\t RTE_BIT32(log_strd_num) *\n+\t\t sizeof(struct rte_mbuf_ext_shared_info) +\n+\t\t RTE_PKTMBUF_HEADROOM;\n \t/*\n \t * Received packets can be either memcpy'd or externally referenced. In\n \t * case that the packet is attached to an mbuf as an external buffer, as\n@@ -1448,7 +1451,7 @@ mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)\n \tsnprintf(name, sizeof(name), \"port-%u-mprq\", dev->data->port_id);\n \tmp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,\n \t\t\t\t0, NULL, NULL, mlx5_mprq_buf_init,\n-\t\t\t\t(void *)((uintptr_t)1 << strd_num_n),\n+\t\t\t\t(void *)((uintptr_t)1 << log_strd_num),\n \t\t\t\tdev->device->numa_node, 0);\n \tif (mp == NULL) {\n \t\tDRV_LOG(ERR,\n@@ -1564,15 +1567,18 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \tunsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;\n \tconst int mprq_en = mlx5_check_mprq_support(dev) > 0 && n_seg == 1 &&\n \t\t\t !rx_seg[0].offset && !rx_seg[0].length;\n-\tunsigned int mprq_stride_nums = config->mprq.stride_num_n ?\n-\t\tconfig->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;\n-\tunsigned int mprq_stride_size = non_scatter_min_mbuf_size <=\n-\t\t(1U << config->mprq.max_stride_size_n) ?\n-\t\tlog2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;\n-\tunsigned int mprq_stride_cap = (config->mprq.stride_num_n ?\n-\t\t(1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *\n-\t\t(config->mprq.stride_size_n ?\n-\t\t(1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));\n+\tunsigned int log_mprq_stride_nums = config->mprq.log_stride_num ?\n+\t\tconfig->mprq.log_stride_num : MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;\n+\tunsigned int log_mprq_stride_size = non_scatter_min_mbuf_size <=\n+\t\tRTE_BIT32(config->mprq.log_max_stride_size) ?\n+\t\tlog2above(non_scatter_min_mbuf_size) :\n+\t\tMLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE;\n+\tunsigned int mprq_stride_cap = (config->mprq.log_stride_num ?\n+\t\t\t\t\tRTE_BIT32(config->mprq.log_stride_num) :\n+\t\t\t\t\tRTE_BIT32(log_mprq_stride_nums)) *\n+\t\t\t\t (config->mprq.log_stride_size ?\n+\t\t\t\t RTE_BIT32(config->mprq.log_stride_size) :\n+\t\t\t\t\tRTE_BIT32(log_mprq_stride_size));\n \t/*\n \t * Always allocate extra slots, even if eventually\n \t * the vector Rx will not be used.\n@@ -1584,7 +1590,7 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \ttmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n \t\tsizeof(*tmpl) + desc_n * sizeof(struct rte_mbuf *) +\n \t\t(!!mprq_en) *\n-\t\t(desc >> mprq_stride_nums) * sizeof(struct mlx5_mprq_buf *),\n+\t\t(desc >> log_mprq_stride_nums) * sizeof(struct mlx5_mprq_buf *),\n \t\t0, socket);\n \tif (!tmpl) {\n \t\trte_errno = ENOMEM;\n@@ -1689,37 +1695,37 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \t * - MPRQ is enabled.\n \t * - The number of descs is more than the number of strides.\n \t * - max_rx_pktlen plus overhead is less than the max size\n-\t * of a stride or mprq_stride_size is specified by a user.\n+\t * of a stride or log_mprq_stride_size is specified by a user.\n \t * Need to make sure that there are enough strides to encap\n-\t * the maximum packet size in case mprq_stride_size is set.\n+\t * the maximum packet size in case log_mprq_stride_size is set.\n \t * Otherwise, enable Rx scatter if necessary.\n \t */\n-\tif (mprq_en && desc > (1U << mprq_stride_nums) &&\n+\tif (mprq_en && desc > RTE_BIT32(log_mprq_stride_nums) &&\n \t (non_scatter_min_mbuf_size <=\n-\t (1U << config->mprq.max_stride_size_n) ||\n-\t (config->mprq.stride_size_n &&\n+\t RTE_BIT32(config->mprq.log_max_stride_size) ||\n+\t (config->mprq.log_stride_size &&\n \t non_scatter_min_mbuf_size <= mprq_stride_cap))) {\n \t\t/* TODO: Rx scatter isn't supported yet. */\n \t\ttmpl->rxq.sges_n = 0;\n \t\t/* Trim the number of descs needed. */\n-\t\tdesc >>= mprq_stride_nums;\n-\t\ttmpl->rxq.strd_num_n = config->mprq.stride_num_n ?\n-\t\t\tconfig->mprq.stride_num_n : mprq_stride_nums;\n-\t\ttmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?\n-\t\t\tconfig->mprq.stride_size_n : mprq_stride_size;\n+\t\tdesc >>= log_mprq_stride_nums;\n+\t\ttmpl->rxq.log_strd_num = config->mprq.log_stride_num ?\n+\t\t\tconfig->mprq.log_stride_num : log_mprq_stride_nums;\n+\t\ttmpl->rxq.log_strd_sz = config->mprq.log_stride_size ?\n+\t\t\tconfig->mprq.log_stride_size : log_mprq_stride_size;\n \t\ttmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;\n \t\ttmpl->rxq.strd_scatter_en =\n \t\t\t\t!!(offloads & RTE_ETH_RX_OFFLOAD_SCATTER);\n \t\ttmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,\n \t\t\t\tconfig->mprq.max_memcpy_len);\n \t\tmax_lro_size = RTE_MIN(max_rx_pktlen,\n-\t\t\t\t (1u << tmpl->rxq.strd_num_n) *\n-\t\t\t\t (1u << tmpl->rxq.strd_sz_n));\n+\t\t\t\t RTE_BIT32(tmpl->rxq.log_strd_num) *\n+\t\t\t\t RTE_BIT32(tmpl->rxq.log_strd_sz));\n \t\tDRV_LOG(DEBUG,\n \t\t\t\"port %u Rx queue %u: Multi-Packet RQ is enabled\"\n \t\t\t\" strd_num_n = %u, strd_sz_n = %u\",\n \t\t\tdev->data->port_id, idx,\n-\t\t\ttmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);\n+\t\t\ttmpl->rxq.log_strd_num, tmpl->rxq.log_strd_sz);\n \t} else if (tmpl->rxq.rxseg_n == 1) {\n \t\tMLX5_ASSERT(max_rx_pktlen <= first_mb_free_size);\n \t\ttmpl->rxq.sges_n = 0;\n@@ -1762,15 +1768,15 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \t\t\t\" min_stride_sz = %u, max_stride_sz = %u).\",\n \t\t\tdev->data->port_id, non_scatter_min_mbuf_size,\n \t\t\tdesc, priv->rxqs_n,\n-\t\t\tconfig->mprq.stride_size_n ?\n-\t\t\t\t(1U << config->mprq.stride_size_n) :\n-\t\t\t\t(1U << mprq_stride_size),\n-\t\t\tconfig->mprq.stride_num_n ?\n-\t\t\t\t(1U << config->mprq.stride_num_n) :\n-\t\t\t\t(1U << mprq_stride_nums),\n+\t\t\tconfig->mprq.log_stride_size ?\n+\t\t\t\tRTE_BIT32(config->mprq.log_stride_size) :\n+\t\t\t\tRTE_BIT32(log_mprq_stride_size),\n+\t\t\tconfig->mprq.log_stride_num ?\n+\t\t\t\tRTE_BIT32(config->mprq.log_stride_num) :\n+\t\t\t\tRTE_BIT32(log_mprq_stride_nums),\n \t\t\tconfig->mprq.min_rxqs_num,\n-\t\t\t(1U << config->mprq.min_stride_size_n),\n-\t\t\t(1U << config->mprq.max_stride_size_n));\n+\t\t\tRTE_BIT32(config->mprq.log_min_stride_size),\n+\t\t\tRTE_BIT32(config->mprq.log_max_stride_size));\n \tDRV_LOG(DEBUG, \"port %u maximum number of segments per packet: %u\",\n \t\tdev->data->port_id, 1 << tmpl->rxq.sges_n);\n \tif (desc % (1 << tmpl->rxq.sges_n)) {\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c\nindex 6212ce8247..0e2eab068a 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec.c\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec.c\n@@ -148,7 +148,7 @@ static inline void\n mlx5_rx_mprq_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq)\n {\n \tconst uint16_t wqe_n = 1 << rxq->elts_n;\n-\tconst uint32_t strd_n = 1 << rxq->strd_num_n;\n+\tconst uint32_t strd_n = RTE_BIT32(rxq->log_strd_num);\n \tconst uint32_t elts_n = wqe_n * strd_n;\n \tconst uint32_t wqe_mask = elts_n - 1;\n \tuint32_t n = elts_n - (rxq->elts_ci - rxq->rq_pi);\n@@ -197,8 +197,8 @@ rxq_copy_mprq_mbuf_v(struct mlx5_rxq_data *rxq,\n {\n \tconst uint16_t wqe_n = 1 << rxq->elts_n;\n \tconst uint16_t wqe_mask = wqe_n - 1;\n-\tconst uint16_t strd_sz = 1 << rxq->strd_sz_n;\n-\tconst uint32_t strd_n = 1 << rxq->strd_num_n;\n+\tconst uint16_t strd_sz = RTE_BIT32(rxq->log_strd_sz);\n+\tconst uint32_t strd_n = RTE_BIT32(rxq->log_strd_num);\n \tconst uint32_t elts_n = wqe_n * strd_n;\n \tconst uint32_t elts_mask = elts_n - 1;\n \tuint32_t elts_idx = rxq->rq_pi & elts_mask;\n@@ -428,7 +428,7 @@ rxq_burst_mprq_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts,\n \tconst uint16_t q_n = 1 << rxq->cqe_n;\n \tconst uint16_t q_mask = q_n - 1;\n \tconst uint16_t wqe_n = 1 << rxq->elts_n;\n-\tconst uint32_t strd_n = 1 << rxq->strd_num_n;\n+\tconst uint32_t strd_n = RTE_BIT32(rxq->log_strd_num);\n \tconst uint32_t elts_n = wqe_n * strd_n;\n \tconst uint32_t elts_mask = elts_n - 1;\n \tvolatile struct mlx5_cqe *cq;\n", "prefixes": [ "2/3" ] }{ "id": 104624, "url": "