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GET /api/patches/104996/?format=api
{ "id": 104996, "url": "http://patchwork.dpdk.org/api/patches/104996/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211207183143.27145-4-lironh@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211207183143.27145-4-lironh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211207183143.27145-4-lironh@marvell.com", "date": "2021-12-07T18:31:42", "name": "[v4,3/4] common/cnxk: add REE support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9f2bf402a1eac0b1a3d5635575044e41cbfc938d", "submitter": { "id": 996, "url": "http://patchwork.dpdk.org/api/people/996/?format=api", "name": "Liron Himi", "email": "lironh@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211207183143.27145-4-lironh@marvell.com/mbox/", "series": [ { "id": 20887, "url": "http://patchwork.dpdk.org/api/series/20887/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20887", "date": "2021-12-07T18:31:39", "name": "regex/cn9k: use cnxk infrastructure", "version": 4, "mbox": "http://patchwork.dpdk.org/series/20887/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104996/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/104996/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B71FFA0093;\n\tTue, 7 Dec 2021 19:32:15 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0BF44426DA;\n\tTue, 7 Dec 2021 19:32:01 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 2BEB041152\n for <dev@dpdk.org>; Tue, 7 Dec 2021 19:32:00 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1B7IVuxc024844\n for <dev@dpdk.org>; Tue, 7 Dec 2021 10:31:59 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ct5hfj14u-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 07 Dec 2021 10:31:59 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 7 Dec 2021 10:31:57 -0800", "from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 7 Dec 2021 10:31:56 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=ojvw1ZhGalJQwZHW/2yw9odJjtiiClRVfT+sIfQbyuk=;\n b=ENXG+SylHWM8YegIVKU0GuSLwb3pLx+Qw+psPiBxaGp+7Dj3z8A7Wp1UCAGM9igTIDzS\n RYXKEU5u07W6HrfFj4l7G53J0C9uBFSPuN+WpFRS5oebys2Q6TiHagpkE1zqTsaI5w4K\n O8XUmskXxtViiv5mi3Vz9k9QlsEcx5tMCbG9KBjTwc6VYzgZveBq5erpIOlU4PgcXcMU\n 1zvUarLzh+hrkIck+7A7ovSk5lQ3fpjxEG3GC7YrVxE8ZN++8NjbW+qxxPdM2Q9WELQJ\n VVkneoSgVkQHoR49Q9vbnuLpRNtbpt4/WV6mowUnIRXC/SZlCmEg9GVerepBlNgfuqeG xg==", "From": "<lironh@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Liron Himi <lironh@marvell.com>", "Subject": "[PATCH v4 3/4] common/cnxk: add REE support", "Date": "Tue, 7 Dec 2021 20:31:42 +0200", "Message-ID": "<20211207183143.27145-4-lironh@marvell.com>", "X-Mailer": "git-send-email 2.28.0", "In-Reply-To": "<20211207183143.27145-1-lironh@marvell.com>", "References": "<20211129194736.14518-3-lironh@marvell.com>\n <20211207183143.27145-1-lironh@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "ki2wTUQUaKvmtRVfcl0QJusQ6jaDwSxr", "X-Proofpoint-ORIG-GUID": "ki2wTUQUaKvmtRVfcl0QJusQ6jaDwSxr", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-07_07,2021-12-06_02,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Liron Himi <lironh@marvell.com>\n\nextend cnxk infrastructure to support REE\n\nSigned-off-by: Liron Himi <lironh@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 4 +\n drivers/common/cnxk/roc_constants.h | 2 +\n drivers/common/cnxk/roc_platform.c | 1 +\n drivers/common/cnxk/roc_platform.h | 2 +\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/roc_ree.c | 647 ++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_ree.h | 137 ++++++\n drivers/common/cnxk/roc_ree_priv.h | 18 +\n drivers/common/cnxk/version.map | 18 +-\n 10 files changed, 832 insertions(+), 1 deletion(-)\n create mode 100644 drivers/common/cnxk/roc_ree.c\n create mode 100644 drivers/common/cnxk/roc_ree.h\n create mode 100644 drivers/common/cnxk/roc_ree_priv.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 4928f7e549..7e27b3cc0a 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -61,6 +61,7 @@ sources = files(\n 'roc_tim.c',\n 'roc_tim_irq.c',\n 'roc_utils.c',\n+ 'roc_ree.c',\n )\n \n # Security common code\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex e7aaa07563..1b46c21f7f 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -37,6 +37,7 @@\n #include \"hw/nix.h\"\n #include \"hw/npa.h\"\n #include \"hw/npc.h\"\n+#include \"hw/ree.h\"\n #include \"hw/rvu.h\"\n #include \"hw/sdp.h\"\n #include \"hw/sso.h\"\n@@ -90,6 +91,9 @@\n /* DPI */\n #include \"roc_dpi.h\"\n \n+/* REE */\n+#include \"roc_ree.h\"\n+\n /* HASH computation */\n #include \"roc_hash.h\"\n \ndiff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h\nindex ac7335061c..5f78823642 100644\n--- a/drivers/common/cnxk/roc_constants.h\n+++ b/drivers/common/cnxk/roc_constants.h\n@@ -37,6 +37,8 @@\n #define PCI_DEVID_CNXK_BPHY\t 0xA089\n #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0\n #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1\n+#define PCI_DEVID_CNXK_RVU_REE_PF 0xA0f4\n+#define PCI_DEVID_CNXK_RVU_REE_VF 0xA0f5\n \n #define PCI_DEVID_CN9K_CGX 0xA059\n #define PCI_DEVID_CN10K_RPM 0xA060\ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex 74dbdeceb9..ebb6225f4d 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -65,3 +65,4 @@ RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);\n+RTE_LOG_REGISTER_DEFAULT(cnxk_logtype_ree, NOTICE);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 61d4781209..85aa6dcebc 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -197,6 +197,7 @@ extern int cnxk_logtype_npc;\n extern int cnxk_logtype_sso;\n extern int cnxk_logtype_tim;\n extern int cnxk_logtype_tm;\n+extern int cnxk_logtype_ree;\n \n #define plt_err(fmt, args...) \\\n \tRTE_LOG(ERR, PMD, \"%s():%u \" fmt \"\\n\", __func__, __LINE__, ##args)\n@@ -222,6 +223,7 @@ extern int cnxk_logtype_tm;\n #define plt_sso_dbg(fmt, ...)\tplt_dbg(sso, fmt, ##__VA_ARGS__)\n #define plt_tim_dbg(fmt, ...)\tplt_dbg(tim, fmt, ##__VA_ARGS__)\n #define plt_tm_dbg(fmt, ...)\tplt_dbg(tm, fmt, ##__VA_ARGS__)\n+#define plt_ree_dbg(fmt, ...)\tplt_dbg(ree, fmt, ##__VA_ARGS__)\n \n /* Datapath logs */\n #define plt_dp_err(fmt, args...) \\\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex 782b90cf8d..122d411fe7 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -44,4 +44,7 @@\n /* DPI */\n #include \"roc_dpi_priv.h\"\n \n+/* REE */\n+#include \"roc_ree_priv.h\"\n+\n #endif /* _ROC_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c\nnew file mode 100644\nindex 0000000000..1eb2ae7272\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_ree.c\n@@ -0,0 +1,647 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+#define REE0_PF 19\n+#define REE1_PF 20\n+\n+static int\n+roc_ree_available_queues_get(struct roc_ree_vf *vf, uint16_t *nb_queues)\n+{\n+\tstruct free_rsrcs_rsp *rsp;\n+\tstruct dev *dev = vf->dev;\n+\tint ret;\n+\n+\tmbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n+\n+\tret = mbox_process_msg(dev->mbox, (void *)&rsp);\n+\tif (ret)\n+\t\treturn -EIO;\n+\n+\tif (vf->block_address == RVU_BLOCK_ADDR_REE0)\n+\t\t*nb_queues = rsp->ree0;\n+\telse\n+\t\t*nb_queues = rsp->ree1;\n+\treturn 0;\n+}\n+\n+static int\n+roc_ree_max_matches_get(struct roc_ree_vf *vf, uint8_t *max_matches)\n+{\n+\tuint64_t val;\n+\tint ret;\n+\n+\tret = roc_ree_af_reg_read(vf, REE_AF_REEXM_MAX_MATCH, &val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*max_matches = val;\n+\treturn 0;\n+}\n+\n+int\n+roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues)\n+{\n+\tstruct rsrc_attach_req *req;\n+\tstruct mbox *mbox;\n+\n+\tmbox = vf->dev->mbox;\n+\t/* Ask AF to attach required LFs */\n+\treq = mbox_alloc_msg_attach_resources(mbox);\n+\tif (req == NULL) {\n+\t\tplt_err(\"Could not allocate mailbox message\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/* 1 LF = 1 queue */\n+\treq->reelfs = nb_queues;\n+\treq->ree_blkaddr = vf->block_address;\n+\n+\tif (mbox_process(mbox) < 0)\n+\t\treturn -EIO;\n+\n+\t/* Update number of attached queues */\n+\tvf->nb_queues = nb_queues;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_ree_queues_detach(struct roc_ree_vf *vf)\n+{\n+\tstruct rsrc_detach_req *req;\n+\tstruct mbox *mbox;\n+\n+\tmbox = vf->dev->mbox;\n+\treq = mbox_alloc_msg_detach_resources(mbox);\n+\tif (req == NULL) {\n+\t\tplt_err(\"Could not allocate mailbox message\");\n+\t\treturn -EFAULT;\n+\t}\n+\treq->reelfs = true;\n+\treq->partial = true;\n+\tif (mbox_process(mbox) < 0)\n+\t\treturn -EIO;\n+\n+\t/* Queues have been detached */\n+\tvf->nb_queues = 0;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_ree_msix_offsets_get(struct roc_ree_vf *vf)\n+{\n+\tstruct msix_offset_rsp *rsp;\n+\tstruct mbox *mbox;\n+\tuint32_t i, ret;\n+\n+\t/* Get REE MSI-X vector offsets */\n+\tmbox = vf->dev->mbox;\n+\tmbox_alloc_msg_msix_offset(mbox);\n+\n+\tret = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0; i < vf->nb_queues; i++) {\n+\t\tif (vf->block_address == RVU_BLOCK_ADDR_REE0)\n+\t\t\tvf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];\n+\t\telse\n+\t\t\tvf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];\n+\t\tplt_ree_dbg(\"lf_msixoff[%d] 0x%x\", i, vf->lf_msixoff[i]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+ree_send_mbox_msg(struct roc_ree_vf *vf)\n+{\n+\tstruct mbox *mbox = vf->dev->mbox;\n+\tint ret;\n+\n+\tmbox_msg_send(mbox, 0);\n+\n+\tret = mbox_wait_for_rsp(mbox, 0);\n+\tif (ret < 0) {\n+\t\tplt_err(\"Could not get mailbox response\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri, uint32_t size)\n+{\n+\tstruct ree_lf_req_msg *req;\n+\tstruct mbox *mbox;\n+\tint ret;\n+\n+\tmbox = vf->dev->mbox;\n+\treq = mbox_alloc_msg_ree_config_lf(mbox);\n+\tif (req == NULL) {\n+\t\tplt_err(\"Could not allocate mailbox message\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treq->lf = lf;\n+\treq->pri = pri ? 1 : 0;\n+\treq->size = size;\n+\treq->blkaddr = vf->block_address;\n+\n+\tret = mbox_process(mbox);\n+\tif (ret < 0) {\n+\t\tplt_err(\"Could not get mailbox response\");\n+\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg, uint64_t *val)\n+{\n+\tstruct ree_rd_wr_reg_msg *msg;\n+\tstruct mbox_dev *mdev;\n+\tstruct mbox *mbox;\n+\tint ret, off;\n+\n+\tmbox = vf->dev->mbox;\n+\tmdev = &mbox->dev[0];\n+\tmsg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(\n+\t\tmbox, 0, sizeof(*msg), sizeof(*msg));\n+\tif (msg == NULL) {\n+\t\tplt_err(\"Could not allocate mailbox message\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tmsg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;\n+\tmsg->hdr.sig = MBOX_REQ_SIG;\n+\tmsg->hdr.pcifunc = vf->dev->pf_func;\n+\tmsg->is_write = 0;\n+\tmsg->reg_offset = reg;\n+\tmsg->ret_val = val;\n+\tmsg->blkaddr = vf->block_address;\n+\n+\tret = ree_send_mbox_msg(vf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\toff = mbox->rx_start +\n+\t RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+\tmsg = (struct ree_rd_wr_reg_msg *)((uintptr_t)mdev->mbase + off);\n+\n+\t*val = msg->val;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg, uint64_t val)\n+{\n+\tstruct ree_rd_wr_reg_msg *msg;\n+\tstruct mbox *mbox;\n+\n+\tmbox = vf->dev->mbox;\n+\tmsg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(\n+\t\tmbox, 0, sizeof(*msg), sizeof(*msg));\n+\tif (msg == NULL) {\n+\t\tplt_err(\"Could not allocate mailbox message\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tmsg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;\n+\tmsg->hdr.sig = MBOX_REQ_SIG;\n+\tmsg->hdr.pcifunc = vf->dev->pf_func;\n+\tmsg->is_write = 1;\n+\tmsg->reg_offset = reg;\n+\tmsg->val = val;\n+\tmsg->blkaddr = vf->block_address;\n+\n+\treturn ree_send_mbox_msg(vf);\n+}\n+\n+int\n+roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db, uint32_t rule_db_len,\n+\t\t char *rule_dbi, uint32_t rule_dbi_len)\n+{\n+\tstruct ree_rule_db_get_req_msg *req;\n+\tstruct ree_rule_db_get_rsp_msg *rsp;\n+\tchar *rule_db_ptr = (char *)rule_db;\n+\tstruct mbox *mbox;\n+\tint ret, last = 0;\n+\tuint32_t len = 0;\n+\n+\tmbox = vf->dev->mbox;\n+\tif (!rule_db) {\n+\t\tplt_err(\"Couldn't return rule db due to NULL pointer\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\twhile (!last) {\n+\t\treq = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(\n+\t\t\tmbox, 0, sizeof(*req), sizeof(*rsp));\n+\t\tif (!req) {\n+\t\t\tplt_err(\"Could not allocate mailbox message\");\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\n+\t\treq->hdr.id = MBOX_MSG_REE_RULE_DB_GET;\n+\t\treq->hdr.sig = MBOX_REQ_SIG;\n+\t\treq->hdr.pcifunc = vf->dev->pf_func;\n+\t\treq->blkaddr = vf->block_address;\n+\t\treq->is_dbi = 0;\n+\t\treq->offset = len;\n+\t\tret = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tif (rule_db_len < len + rsp->len) {\n+\t\t\tplt_err(\"Rule db size is too small\");\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t\tmbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);\n+\t\tlen += rsp->len;\n+\t\trule_db_ptr = rule_db_ptr + rsp->len;\n+\t\tlast = rsp->is_last;\n+\t}\n+\n+\tif (rule_dbi) {\n+\t\treq = (struct ree_rule_db_get_req_msg *)mbox_alloc_msg_rsp(\n+\t\t\tmbox, 0, sizeof(*req), sizeof(*rsp));\n+\t\tif (!req) {\n+\t\t\tplt_err(\"Could not allocate mailbox message\");\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\n+\t\treq->hdr.id = MBOX_MSG_REE_RULE_DB_GET;\n+\t\treq->hdr.sig = MBOX_REQ_SIG;\n+\t\treq->hdr.pcifunc = vf->dev->pf_func;\n+\t\treq->blkaddr = vf->block_address;\n+\t\treq->is_dbi = 1;\n+\t\treq->offset = 0;\n+\n+\t\tret = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tif (rule_dbi_len < rsp->len) {\n+\t\t\tplt_err(\"Rule dbi size is too small\");\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t\tmbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+roc_ree_rule_db_len_get(struct roc_ree_vf *vf, uint32_t *rule_db_len,\n+\t\t\tuint32_t *rule_dbi_len)\n+{\n+\tstruct ree_rule_db_len_rsp_msg *rsp;\n+\tstruct ree_req_msg *req;\n+\tstruct mbox *mbox;\n+\tint ret;\n+\n+\tmbox = vf->dev->mbox;\n+\treq = (struct ree_req_msg *)mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),\n+\t\t\t\t\t\t sizeof(*rsp));\n+\tif (!req) {\n+\t\tplt_err(\"Could not allocate mailbox message\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treq->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;\n+\treq->hdr.sig = MBOX_REQ_SIG;\n+\treq->hdr.pcifunc = vf->dev->pf_func;\n+\treq->blkaddr = vf->block_address;\n+\tret = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (ret)\n+\t\treturn ret;\n+\tif (rule_db_len != NULL)\n+\t\t*rule_db_len = rsp->len;\n+\tif (rule_dbi_len != NULL)\n+\t\t*rule_dbi_len = rsp->inc_len;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ree_db_msg(struct roc_ree_vf *vf, const char *db, uint32_t db_len, int inc,\n+\t int dbi)\n+{\n+\tuint32_t len_left = db_len, offset = 0;\n+\tstruct ree_rule_db_prog_req_msg *req;\n+\tconst char *rule_db_ptr = db;\n+\tstruct mbox *mbox;\n+\tstruct msg_rsp *rsp;\n+\tint ret;\n+\n+\tmbox = vf->dev->mbox;\n+\twhile (len_left) {\n+\t\treq = (struct ree_rule_db_prog_req_msg *)mbox_alloc_msg_rsp(\n+\t\t\tmbox, 0, sizeof(*req), sizeof(*rsp));\n+\t\tif (!req) {\n+\t\t\tplt_err(\"Could not allocate mailbox message\");\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t\treq->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;\n+\t\treq->hdr.sig = MBOX_REQ_SIG;\n+\t\treq->hdr.pcifunc = vf->dev->pf_func;\n+\t\treq->offset = offset;\n+\t\treq->total_len = db_len;\n+\t\treq->len = REE_RULE_DB_REQ_BLOCK_SIZE;\n+\t\treq->is_incremental = inc;\n+\t\treq->is_dbi = dbi;\n+\t\treq->blkaddr = vf->block_address;\n+\n+\t\tif (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {\n+\t\t\treq->is_last = true;\n+\t\t\treq->len = len_left;\n+\t\t}\n+\t\tmbox_memcpy(req->rule_db, rule_db_ptr, req->len);\n+\t\tret = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (ret) {\n+\t\t\tplt_err(\"Programming mailbox processing failed\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tlen_left -= req->len;\n+\t\toffset += req->len;\n+\t\trule_db_ptr = rule_db_ptr + req->len;\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,\n+\t\t uint32_t rule_db_len, const char *rule_dbi,\n+\t\t uint32_t rule_dbi_len)\n+{\n+\tint inc, ret;\n+\n+\tif (rule_db_len == 0) {\n+\t\tplt_err(\"Couldn't program empty rule db\");\n+\t\treturn -EFAULT;\n+\t}\n+\tinc = (rule_dbi_len != 0);\n+\tif ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {\n+\t\tplt_err(\"Couldn't program NULL rule db\");\n+\t\treturn -EFAULT;\n+\t}\n+\tif (inc) {\n+\t\tret = ree_db_msg(vf, rule_dbi, rule_dbi_len, inc, 1);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\treturn ree_db_msg(vf, rule_db, rule_db_len, inc, 0);\n+}\n+\n+static int\n+ree_get_blkaddr(struct dev *dev)\n+{\n+\tint pf;\n+\n+\tpf = dev_get_pf(dev->pf_func);\n+\tif (pf == REE0_PF)\n+\t\treturn RVU_BLOCK_ADDR_REE0;\n+\telse if (pf == REE1_PF)\n+\t\treturn RVU_BLOCK_ADDR_REE1;\n+\telse\n+\t\treturn 0;\n+}\n+\n+uintptr_t\n+roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id)\n+{\n+\treturn REE_LF_BAR2(vf, qp_id);\n+}\n+\n+static void\n+roc_ree_lf_err_intr_handler(void *param)\n+{\n+\tuintptr_t base = (uintptr_t)param;\n+\tuint8_t lf_id;\n+\tuint64_t intr;\n+\n+\tlf_id = (base >> 12) & 0xFF;\n+\n+\tintr = plt_read64(base + REE_LF_MISC_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_ree_dbg(\"LF %d MISC_INT: 0x%\" PRIx64 \"\", lf_id, intr);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, base + REE_LF_MISC_INT);\n+}\n+\n+static void\n+roc_ree_lf_err_intr_unregister(struct roc_ree_vf *vf, uint16_t msix_off,\n+\t\t\t uintptr_t base)\n+{\n+\tstruct rte_pci_device *pci_dev = vf->pci_dev;\n+\n+\t/* Disable error interrupts */\n+\tplt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);\n+\n+\tdev_irq_unregister(pci_dev->intr_handle,\n+\t\t\t roc_ree_lf_err_intr_handler, (void *)base, msix_off);\n+}\n+\n+void\n+roc_ree_err_intr_unregister(struct roc_ree_vf *vf)\n+{\n+\tuintptr_t base;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < vf->nb_queues; i++) {\n+\t\tbase = REE_LF_BAR2(vf, i);\n+\t\troc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[i], base);\n+\t}\n+\n+\tvf->err_intr_registered = 0;\n+}\n+\n+static int\n+roc_ree_lf_err_intr_register(struct roc_ree_vf *vf, uint16_t msix_off,\n+\t\t\t uintptr_t base)\n+{\n+\tstruct rte_pci_device *pci_dev = vf->pci_dev;\n+\tint ret;\n+\n+\t/* Disable error interrupts */\n+\tplt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C);\n+\n+\t/* Register error interrupt handler */\n+\tret = dev_irq_register(pci_dev->intr_handle,\n+\t\t\t roc_ree_lf_err_intr_handler, (void *)base,\n+\t\t\t msix_off);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Enable error interrupts */\n+\tplt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1S);\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_ree_err_intr_register(struct roc_ree_vf *vf)\n+{\n+\tuint32_t i, j, ret;\n+\tuintptr_t base;\n+\n+\tfor (i = 0; i < vf->nb_queues; i++) {\n+\t\tif (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {\n+\t\t\tplt_err(\"Invalid REE LF MSI-X offset: 0x%x\",\n+\t\t\t\tvf->lf_msixoff[i]);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < vf->nb_queues; i++) {\n+\t\tbase = REE_LF_BAR2(vf, i);\n+\t\tret = roc_ree_lf_err_intr_register(vf, vf->lf_msixoff[i], base);\n+\t\tif (ret)\n+\t\t\tgoto intr_unregister;\n+\t}\n+\n+\tvf->err_intr_registered = 1;\n+\treturn 0;\n+\n+intr_unregister:\n+\t/* Unregister the ones already registered */\n+\tfor (j = 0; j < i; j++) {\n+\t\tbase = REE_LF_BAR2(vf, j);\n+\t\troc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[j], base);\n+\t}\n+\treturn ret;\n+}\n+\n+int\n+roc_ree_iq_enable(struct roc_ree_vf *vf, const struct roc_ree_qp *qp,\n+\t\t uint8_t pri, uint32_t size_div2)\n+{\n+\tuint64_t val;\n+\n+\t/* Set instruction queue size and priority */\n+\troc_ree_config_lf(vf, qp->id, pri, size_div2);\n+\n+\t/* Set instruction queue base address */\n+\t/* Should be written after SBUF_CTL and before LF_ENA */\n+\n+\tval = plt_read64(qp->base + REE_LF_SBUF_ADDR);\n+\tval &= ~REE_LF_SBUF_ADDR_PTR_MASK;\n+\tval |= FIELD_PREP(REE_LF_SBUF_ADDR_PTR_MASK, qp->iq_dma_addr >> 7);\n+\tplt_write64(val, qp->base + REE_LF_SBUF_ADDR);\n+\n+\t/* Enable instruction queue */\n+\n+\tval = plt_read64(qp->base + REE_LF_ENA);\n+\tval &= ~REE_LF_ENA_ENA_MASK;\n+\tval |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 1);\n+\tplt_write64(val, qp->base + REE_LF_ENA);\n+\n+\treturn 0;\n+}\n+\n+void\n+roc_ree_iq_disable(struct roc_ree_qp *qp)\n+{\n+\tuint64_t val;\n+\n+\t/* Stop instruction execution */\n+\tval = plt_read64(qp->base + REE_LF_ENA);\n+\tval &= ~REE_LF_ENA_ENA_MASK;\n+\tval |= FIELD_PREP(REE_LF_ENA_ENA_MASK, 0);\n+\tplt_write64(val, qp->base + REE_LF_ENA);\n+}\n+\n+int\n+roc_ree_dev_init(struct roc_ree_vf *vf)\n+{\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct ree *ree;\n+\tstruct dev *dev;\n+\tuint8_t max_matches = 0;\n+\tuint16_t nb_queues = 0;\n+\tint rc;\n+\n+\tif (vf == NULL || vf->pci_dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\tPLT_STATIC_ASSERT(sizeof(struct ree) <= ROC_REE_MEM_SZ);\n+\n+\tree = roc_ree_to_ree_priv(vf);\n+\tmemset(ree, 0, sizeof(*ree));\n+\tvf->dev = &ree->dev;\n+\n+\tpci_dev = vf->pci_dev;\n+\tdev = vf->dev;\n+\n+\t/* Initialize device */\n+\trc = dev_init(dev, pci_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init roc device\");\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Get REE block address */\n+\tvf->block_address = ree_get_blkaddr(dev);\n+\tif (!vf->block_address) {\n+\t\tplt_err(\"Could not determine block PF number\");\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Get number of queues available on the device */\n+\trc = roc_ree_available_queues_get(vf, &nb_queues);\n+\tif (rc) {\n+\t\tplt_err(\"Could not determine the number of queues available\");\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Don't exceed the limits set per VF */\n+\tnb_queues = RTE_MIN(nb_queues, REE_MAX_QUEUES_PER_VF);\n+\n+\tif (nb_queues == 0) {\n+\t\tplt_err(\"No free queues available on the device\");\n+\t\tgoto fail;\n+\t}\n+\n+\tvf->max_queues = nb_queues;\n+\n+\tplt_ree_dbg(\"Max queues supported by device: %d\", vf->max_queues);\n+\n+\t/* Get number of maximum matches supported on the device */\n+\trc = roc_ree_max_matches_get(vf, &max_matches);\n+\tif (rc) {\n+\t\tplt_err(\"Could not determine the maximum matches supported\");\n+\t\tgoto fail;\n+\t}\n+\t/* Don't exceed the limits set per VF */\n+\tmax_matches = RTE_MIN(max_matches, REE_MAX_MATCHES_PER_VF);\n+\tif (max_matches == 0) {\n+\t\tplt_err(\"Could not determine the maximum matches supported\");\n+\t\tgoto fail;\n+\t}\n+\n+\tvf->max_matches = max_matches;\n+\n+\tplt_ree_dbg(\"Max matches supported by device: %d\", vf->max_matches);\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+roc_ree_dev_fini(struct roc_ree_vf *vf)\n+{\n+\tif (vf == NULL)\n+\t\treturn -EINVAL;\n+\n+\tvf->max_matches = 0;\n+\tvf->max_queues = 0;\n+\n+\treturn dev_fini(vf->dev, vf->pci_dev);\n+}\ndiff --git a/drivers/common/cnxk/roc_ree.h b/drivers/common/cnxk/roc_ree.h\nnew file mode 100644\nindex 0000000000..e138e4de66\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_ree.h\n@@ -0,0 +1,137 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_REE_H_\n+#define _ROC_REE_H_\n+\n+#include \"roc_api.h\"\n+\n+#define REE_MAX_LFS\t 36\n+#define REE_MAX_QUEUES_PER_VF 36\n+#define REE_MAX_MATCHES_PER_VF 254\n+\n+#define REE_MAX_PAYLOAD_SIZE (1 << 14)\n+\n+#define REE_NON_INC_PROG 0\n+#define REE_INC_PROG\t 1\n+\n+#define REE_MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++)\n+\n+/**\n+ * Device vf data\n+ */\n+struct roc_ree_vf {\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct dev *dev;\n+\t/**< Base class */\n+\tuint16_t max_queues;\n+\t/**< Max queues supported */\n+\tuint8_t nb_queues;\n+\t/**< Number of regex queues attached */\n+\tuint16_t max_matches;\n+\t/**< Max matches supported*/\n+\tuint16_t lf_msixoff[REE_MAX_LFS];\n+\t/**< MSI-X offsets */\n+\tuint8_t block_address;\n+\t/**< REE Block Address */\n+\tuint8_t err_intr_registered : 1;\n+\t/**< Are error interrupts registered? */\n+\n+#define ROC_REE_MEM_SZ (6 * 1024)\n+\tuint8_t reserved[ROC_REE_MEM_SZ] __plt_cache_aligned;\n+} __plt_cache_aligned;\n+\n+struct roc_ree_rid {\n+\tuintptr_t rid;\n+\t/** Request id of a ree operation */\n+\tuint64_t user_id;\n+\t/* Client data */\n+\t/**< IOVA address of the pattern to be matched. */\n+};\n+\n+struct roc_ree_pending_queue {\n+\tuint64_t pending_count;\n+\t/** Pending requests count */\n+\tstruct roc_ree_rid *rid_queue;\n+\t/** Array of pending requests */\n+\tuint16_t enq_tail;\n+\t/** Tail of queue to be used for enqueue */\n+\tuint16_t deq_head;\n+\t/** Head of queue to be used for dequeue */\n+};\n+\n+struct roc_ree_qp {\n+\tuint32_t id;\n+\t/**< Queue pair id */\n+\tuintptr_t base;\n+\t/**< Base address where BAR is mapped */\n+\tstruct roc_ree_pending_queue pend_q;\n+\t/**< Pending queue */\n+\trte_iova_t iq_dma_addr;\n+\t/**< Instruction queue address */\n+\tuint32_t roc_regexdev_jobid;\n+\t/**< Job ID */\n+\tuint32_t write_offset;\n+\t/**< write offset */\n+};\n+\n+union roc_ree_inst {\n+\tuint64_t u[8];\n+\tstruct {\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t reserved_1_3 : 3;\n+\t\tuint64_t dg : 1;\n+\t\tuint64_t reserved_5_7 : 3;\n+\t\tuint64_t ooj : 1;\n+\t\tuint64_t reserved_9_15 : 7;\n+\t\tuint64_t reserved_16_63 : 48;\n+\t\tuint64_t inp_ptr_addr : 64;\n+\t\tuint64_t inp_ptr_ctl : 64;\n+\t\tuint64_t res_ptr_addr : 64;\n+\t\tuint64_t wq_ptr : 64;\n+\t\tuint64_t tag : 32;\n+\t\tuint64_t tt : 2;\n+\t\tuint64_t ggrp : 10;\n+\t\tuint64_t reserved_364_383 : 20;\n+\t\tuint64_t reserved_384_391 : 8;\n+\t\tuint64_t ree_job_id : 24;\n+\t\tuint64_t ree_job_ctrl : 16;\n+\t\tuint64_t ree_job_length : 15;\n+\t\tuint64_t reserved_447_447 : 1;\n+\t\tuint64_t ree_job_subset_id_0 : 16;\n+\t\tuint64_t ree_job_subset_id_1 : 16;\n+\t\tuint64_t ree_job_subset_id_2 : 16;\n+\t\tuint64_t ree_job_subset_id_3 : 16;\n+\t} cn98xx;\n+};\n+\n+int __roc_api roc_ree_dev_init(struct roc_ree_vf *vf);\n+int __roc_api roc_ree_dev_fini(struct roc_ree_vf *vf);\n+int __roc_api roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues);\n+int __roc_api roc_ree_queues_detach(struct roc_ree_vf *vf);\n+int __roc_api roc_ree_msix_offsets_get(struct roc_ree_vf *vf);\n+int __roc_api roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri,\n+\t\t\t\tuint32_t size);\n+int __roc_api roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg,\n+\t\t\t\t uint64_t *val);\n+int __roc_api roc_ree_af_reg_write(struct roc_ree_vf *vf, uint64_t reg,\n+\t\t\t\t uint64_t val);\n+int __roc_api roc_ree_rule_db_get(struct roc_ree_vf *vf, char *rule_db,\n+\t\t\t\t uint32_t rule_db_len, char *rule_dbi,\n+\t\t\t\t uint32_t rule_dbi_len);\n+int __roc_api roc_ree_rule_db_len_get(struct roc_ree_vf *vf,\n+\t\t\t\t uint32_t *rule_db_len,\n+\t\t\t\t uint32_t *rule_dbi_len);\n+int __roc_api roc_ree_rule_db_prog(struct roc_ree_vf *vf, const char *rule_db,\n+\t\t\t\t uint32_t rule_db_len, const char *rule_dbi,\n+\t\t\t\t uint32_t rule_dbi_len);\n+uintptr_t __roc_api roc_ree_qp_get_base(struct roc_ree_vf *vf, uint16_t qp_id);\n+void __roc_api roc_ree_err_intr_unregister(struct roc_ree_vf *vf);\n+int __roc_api roc_ree_err_intr_register(struct roc_ree_vf *vf);\n+int __roc_api roc_ree_iq_enable(struct roc_ree_vf *vf,\n+\t\t\t\tconst struct roc_ree_qp *qp, uint8_t pri,\n+\t\t\t\tuint32_t size_div128);\n+void __roc_api roc_ree_iq_disable(struct roc_ree_qp *qp);\n+\n+#endif /* _ROC_REE_H_ */\ndiff --git a/drivers/common/cnxk/roc_ree_priv.h b/drivers/common/cnxk/roc_ree_priv.h\nnew file mode 100644\nindex 0000000000..c39f7cf986\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_ree_priv.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_REE_PRIV_H_\n+#define _ROC_REE_PRIV_H_\n+\n+struct ree {\n+\tstruct dev dev;\n+} __plt_cache_aligned;\n+\n+static inline struct ree *\n+roc_ree_to_ree_priv(struct roc_ree_vf *roc_ree)\n+{\n+\treturn (struct ree *)&roc_ree->reserved[0];\n+}\n+\n+#endif /* _ROC_REE_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 07c6720f0c..5a03b91784 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -11,6 +11,7 @@ INTERNAL {\n \tcnxk_logtype_nix;\n \tcnxk_logtype_npa;\n \tcnxk_logtype_npc;\n+\tcnxk_logtype_ree;\n \tcnxk_logtype_sso;\n \tcnxk_logtype_tim;\n \tcnxk_logtype_tm;\n@@ -347,6 +348,21 @@ INTERNAL {\n \troc_tim_lf_enable;\n \troc_tim_lf_free;\n \troc_se_ctx_swap;\n-\n+\troc_ree_af_reg_read;\n+\troc_ree_af_reg_write;\n+\troc_ree_config_lf;\n+\troc_ree_dev_fini;\n+\troc_ree_dev_init;\n+\troc_ree_err_intr_register;\n+\troc_ree_err_intr_unregister;\n+\troc_ree_iq_disable;\n+\troc_ree_iq_enable;\n+\troc_ree_msix_offsets_get;\n+\troc_ree_qp_get_base;\n+\troc_ree_queues_attach;\n+\troc_ree_queues_detach;\n+\troc_ree_rule_db_get;\n+\troc_ree_rule_db_len_get;\n+\troc_ree_rule_db_prog;\n \tlocal: *;\n };\n", "prefixes": [ "v4", "3/4" ] }