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GET /api/patches/104997/?format=api
{ "id": 104997, "url": "http://patchwork.dpdk.org/api/patches/104997/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211207183143.27145-5-lironh@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211207183143.27145-5-lironh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211207183143.27145-5-lironh@marvell.com", "date": "2021-12-07T18:31:43", "name": "[v4,4/4] regex/cn9k: use cnxk infrastructure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a039898f859f7c12a48cbeaf612cca7685244623", "submitter": { "id": 996, "url": "http://patchwork.dpdk.org/api/people/996/?format=api", "name": "Liron Himi", "email": "lironh@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211207183143.27145-5-lironh@marvell.com/mbox/", "series": [ { "id": 20887, "url": "http://patchwork.dpdk.org/api/series/20887/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20887", "date": "2021-12-07T18:31:39", "name": "regex/cn9k: use cnxk infrastructure", "version": 4, "mbox": "http://patchwork.dpdk.org/series/20887/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104997/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/104997/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 08142A0093;\n\tTue, 7 Dec 2021 19:32:25 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 712DD426F7;\n\tTue, 7 Dec 2021 19:32:04 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 3B80042730\n for <dev@dpdk.org>; Tue, 7 Dec 2021 19:32:02 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1B7FUFg8018337\n for <dev@dpdk.org>; Tue, 7 Dec 2021 10:32:01 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ct2q92wn4-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 07 Dec 2021 10:32:01 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 7 Dec 2021 10:31:59 -0800", "from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 7 Dec 2021 10:31:58 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=Nvr5IlLhbdE8Gd0+9fypYcqNLWAu4jTdYjTLX+w1eTE=;\n b=Ph+jUwZ69vGBVzZao6/ce9//pXfaQodDF2oBipMyPnk0N8E3o95cimPqMsdFaFCOuhH1\n yKimF3jyaWOpYn2VuMlNY8LXk/Agc8V4dtuNsLof3M7QxIDvq2DkCtzrBKhct0F5YGFZ\n GViiUkcIRYafEO3XJFr9sxDf7slpo9pfJnx6AYF/0/+gWiTYvZBdfBFTK0OctO8YEtaj\n OznL4xS2wJdy8FlFU1PXXmYsz9ZVPHshBkTzLjHHP0YyH/h1sJAjPSJ6k+sFqhQNGUpf\n GtRMb00C8hXQqmoPFL/1jErWBsf89NxS3lx898Ds8Vt1zr+HAB+/0BFJ5S3crnpmPHDC 9A==", "From": "<lironh@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Liron Himi <lironh@marvell.com>", "Subject": "[PATCH v4 4/4] regex/cn9k: use cnxk infrastructure", "Date": "Tue, 7 Dec 2021 20:31:43 +0200", "Message-ID": "<20211207183143.27145-5-lironh@marvell.com>", "X-Mailer": "git-send-email 2.28.0", "In-Reply-To": "<20211207183143.27145-1-lironh@marvell.com>", "References": "<20211129194736.14518-3-lironh@marvell.com>\n <20211207183143.27145-1-lironh@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "t0L2q2uYnFeVqCJ1FVfEvnuSst9Wp5J-", "X-Proofpoint-ORIG-GUID": "t0L2q2uYnFeVqCJ1FVfEvnuSst9Wp5J-", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-07_07,2021-12-06_02,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Liron Himi <lironh@marvell.com>\n\nupdate driver to use the REE cnxk code\nreplace octeontx2/otx2 with cn9k\n\nSigned-off-by: Liron Himi <lironh@marvell.com>\n---\n MAINTAINERS | 8 +-\n doc/guides/platform/cnxk.rst | 3 +\n doc/guides/platform/octeontx2.rst | 3 -\n .../regexdevs/{octeontx2.rst => cn9k.rst} | 20 +-\n .../features/{octeontx2.ini => cn9k.ini} | 2 +-\n doc/guides/regexdevs/index.rst | 2 +-\n doc/guides/rel_notes/release_20_11.rst | 2 +-\n .../otx2_regexdev.c => cn9k/cn9k_regexdev.c} | 405 ++++++++----------\n drivers/regex/cn9k/cn9k_regexdev.h | 44 ++\n .../cn9k_regexdev_compiler.c} | 34 +-\n drivers/regex/cn9k/cn9k_regexdev_compiler.h | 11 +\n drivers/regex/{octeontx2 => cn9k}/meson.build | 10 +-\n drivers/regex/{octeontx2 => cn9k}/version.map | 0\n drivers/regex/meson.build | 2 +-\n drivers/regex/octeontx2/otx2_regexdev.h | 109 -----\n .../regex/octeontx2/otx2_regexdev_compiler.h | 11 -\n .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 --------\n .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 ---------\n drivers/regex/octeontx2/otx2_regexdev_mbox.c | 401 -----------------\n drivers/regex/octeontx2/otx2_regexdev_mbox.h | 38 --\n 20 files changed, 269 insertions(+), 1205 deletions(-)\n rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)\n rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)\n rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)\n create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h\n rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => cn9k/cn9k_regexdev_compiler.c} (86%)\n create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h\n rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)\n rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)\n delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h\n delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h\n delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c\n delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h\n delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c\n delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex e157e12f88..5f45b35c51 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1228,11 +1228,11 @@ F: doc/guides/dmadevs/cnxk.rst\n RegEx Drivers\n -------------\n \n-Marvell OCTEON TX2 regex\n+Marvell OCTEON CN9K regex\n M: Liron Himi <lironh@marvell.com>\n-F: drivers/regex/octeontx2/\n-F: doc/guides/regexdevs/octeontx2.rst\n-F: doc/guides/regexdevs/features/octeontx2.ini\n+F: drivers/regex/cn9k/\n+F: doc/guides/regexdevs/cn9k.rst\n+F: doc/guides/regexdevs/features/cn9k.ini\n \n Mellanox mlx5\n M: Ori Kam <orika@nvidia.com>\ndiff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst\nindex 88995cc70c..5213df3ccd 100644\n--- a/doc/guides/platform/cnxk.rst\n+++ b/doc/guides/platform/cnxk.rst\n@@ -156,6 +156,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.\n #. **Dmadev Driver**\n See :doc:`../dmadevs/cnxk` for DPI Dmadev driver information.\n \n+#. **Regex Device Driver**\n+ See :doc:`../regexdevs/cn9k` for REE Regex device driver information.\n+\n Procedure to Setup Platform\n ---------------------------\n \ndiff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst\nindex 3a3d28571c..5ab43abbdd 100644\n--- a/doc/guides/platform/octeontx2.rst\n+++ b/doc/guides/platform/octeontx2.rst\n@@ -155,9 +155,6 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.\n #. **Crypto Device Driver**\n See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.\n \n-#. **Regex Device Driver**\n- See :doc:`../regexdevs/octeontx2` for REE regex device driver information.\n-\n Procedure to Setup Platform\n ---------------------------\n \ndiff --git a/doc/guides/regexdevs/octeontx2.rst b/doc/guides/regexdevs/cn9k.rst\nsimilarity index 69%\nrename from doc/guides/regexdevs/octeontx2.rst\nrename to doc/guides/regexdevs/cn9k.rst\nindex b39d457d60..c23c295b93 100644\n--- a/doc/guides/regexdevs/octeontx2.rst\n+++ b/doc/guides/regexdevs/cn9k.rst\n@@ -1,20 +1,20 @@\n .. SPDX-License-Identifier: BSD-3-Clause\n Copyright(c) 2020 Marvell International Ltd.\n \n-OCTEON TX2 REE Regexdev Driver\n+CN9K REE Regexdev Driver\n ==============================\n \n-The OCTEON TX2 REE PMD (**librte_regex_octeontx2**) provides poll mode\n-regexdev driver support for the inbuilt regex device found in the **Marvell OCTEON TX2**\n+The CN9K REE PMD (**librte_regex_cn9k**) provides poll mode\n+regexdev driver support for the inbuilt regex device found in the **Marvell CN9K**\n SoC family.\n \n-More information about OCTEON TX2 SoC can be found at `Marvell Official Website\n+More information about CN9K SoC can be found at `Marvell Official Website\n <https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.\n \n Features\n --------\n \n-Features of the OCTEON TX2 REE PMD are:\n+Features of the CN9K REE PMD are:\n \n - 36 queues\n - Up to 254 matches for each regex operation\n@@ -22,12 +22,12 @@ Features of the OCTEON TX2 REE PMD are:\n Prerequisites and Compilation procedure\n ---------------------------------------\n \n- See :doc:`../platform/octeontx2` for setup information.\n+ See :doc:`../platform/cnxk` for setup information.\n \n Device Setup\n ------------\n \n-The OCTEON TX2 REE devices will need to be bound to a user-space IO driver\n+The CN9K REE devices will need to be bound to a user-space IO driver\n for use. The script ``dpdk-devbind.py`` script included with DPDK can be\n used to view the state of the devices and to bind them to a suitable\n DPDK-supported kernel driver. When querying the status of the devices,\n@@ -38,12 +38,12 @@ those devices alone.\n Debugging Options\n -----------------\n \n-.. _table_octeontx2_regex_debug_options:\n+.. _table_cn9k_regex_debug_options:\n \n-.. table:: OCTEON TX2 regex device debug options\n+.. table:: CN9K regex device debug options\n \n +---+------------+-------------------------------------------------------+\n | # | Component | EAL log command |\n +===+============+=======================================================+\n- | 1 | REE | --log-level='pmd\\.regex\\.octeontx2,8' |\n+ | 1 | REE | --log-level='pmd\\.regex\\.cn9k,8' |\n +---+------------+-------------------------------------------------------+\ndiff --git a/doc/guides/regexdevs/features/octeontx2.ini b/doc/guides/regexdevs/features/cn9k.ini\nsimilarity index 80%\nrename from doc/guides/regexdevs/features/octeontx2.ini\nrename to doc/guides/regexdevs/features/cn9k.ini\nindex c9b421a16d..b029af8ac2 100644\n--- a/doc/guides/regexdevs/features/octeontx2.ini\n+++ b/doc/guides/regexdevs/features/cn9k.ini\n@@ -1,5 +1,5 @@\n ;\n-; Supported features of the 'octeontx2' regex driver.\n+; Supported features of the 'cn9k' regex driver.\n ;\n ; Refer to default.ini for the full list of available driver features.\n ;\ndiff --git a/doc/guides/regexdevs/index.rst b/doc/guides/regexdevs/index.rst\nindex b1abc826bd..11a33fc09e 100644\n--- a/doc/guides/regexdevs/index.rst\n+++ b/doc/guides/regexdevs/index.rst\n@@ -13,4 +13,4 @@ which can be used from an application through RegEx API.\n \n features_overview\n mlx5\n- octeontx2\n+ cn9k\ndiff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex 90cc3ed680..d6d40c31df 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -290,7 +290,7 @@ New Features\n \n Added a new PMD driver for the hardware regex offload block for OCTEON TX2 SoC.\n \n- See the :doc:`../regexdevs/octeontx2` for more details.\n+ See ``regexdevs/octeontx2`` for more details.\n \n * **Updated Software Eventdev driver.**\n \ndiff --git a/drivers/regex/octeontx2/otx2_regexdev.c b/drivers/regex/cn9k/cn9k_regexdev.c\nsimilarity index 61%\nrename from drivers/regex/octeontx2/otx2_regexdev.c\nrename to drivers/regex/cn9k/cn9k_regexdev.c\nindex b6e55853e9..32d20c1be8 100644\n--- a/drivers/regex/octeontx2/otx2_regexdev.c\n+++ b/drivers/regex/cn9k/cn9k_regexdev.c\n@@ -13,12 +13,8 @@\n \n \n /* REE common headers */\n-#include \"otx2_common.h\"\n-#include \"otx2_dev.h\"\n-#include \"otx2_regexdev.h\"\n-#include \"otx2_regexdev_compiler.h\"\n-#include \"otx2_regexdev_hw_access.h\"\n-#include \"otx2_regexdev_mbox.h\"\n+#include \"cn9k_regexdev.h\"\n+#include \"cn9k_regexdev_compiler.h\"\n \n \n /* HW matches are at offset 0x80 from RES_PTR_ADDR\n@@ -35,9 +31,6 @@\n #define REE_MAX_RULES_PER_GROUP 0xFFFF\n #define REE_MAX_GROUPS 0xFFFF\n \n-/* This is temporarily here */\n-#define REE0_PF\t19\n-#define REE1_PF\t20\n \n #define REE_RULE_DB_VERSION\t2\n #define REE_RULE_DB_REVISION\t0\n@@ -58,32 +51,32 @@ struct ree_rule_db {\n static void\n qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)\n {\n-\tsnprintf(name, size, \"otx2_ree_lf_mem_%u:%u\", dev_id, qp_id);\n+\tsnprintf(name, size, \"cn9k_ree_lf_mem_%u:%u\", dev_id, qp_id);\n }\n \n-static struct otx2_ree_qp *\n+static struct roc_ree_qp *\n ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)\n {\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n \tuint64_t pg_sz = sysconf(_SC_PAGESIZE);\n-\tstruct otx2_ree_vf *vf = &data->vf;\n+\tstruct roc_ree_vf *vf = &data->vf;\n \tconst struct rte_memzone *lf_mem;\n \tuint32_t len, iq_len, size_div2;\n \tchar name[RTE_MEMZONE_NAMESIZE];\n \tuint64_t used_len, iova;\n-\tstruct otx2_ree_qp *qp;\n+\tstruct roc_ree_qp *qp;\n \tuint8_t *va;\n \tint ret;\n \n \t/* Allocate queue pair */\n-\tqp = rte_zmalloc(\"OCTEON TX2 Regex PMD Queue Pair\", sizeof(*qp),\n-\t\t\t\tOTX2_ALIGN);\n+\tqp = rte_zmalloc(\"CN9K Regex PMD Queue Pair\", sizeof(*qp),\n+\t\t\t\tROC_ALIGN);\n \tif (qp == NULL) {\n-\t\totx2_err(\"Could not allocate queue pair\");\n+\t\tcn9k_err(\"Could not allocate queue pair\");\n \t\treturn NULL;\n \t}\n \n-\tiq_len = OTX2_REE_IQ_LEN;\n+\tiq_len = REE_IQ_LEN;\n \n \t/*\n \t * Queue size must be in units of 128B 2 * REE_INST_S (which is 64B),\n@@ -93,13 +86,13 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)\n \tsize_div2 = iq_len >> 1;\n \n \t/* For pending queue */\n-\tlen = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8);\n+\tlen = iq_len * RTE_ALIGN(sizeof(struct roc_ree_rid), 8);\n \n \t/* So that instruction queues start as pg size aligned */\n \tlen = RTE_ALIGN(len, pg_sz);\n \n \t/* For instruction queues */\n-\tlen += OTX2_REE_IQ_LEN * sizeof(union otx2_ree_inst);\n+\tlen += REE_IQ_LEN * sizeof(union roc_ree_inst);\n \n \t/* Waste after instruction queues */\n \tlen = RTE_ALIGN(len, pg_sz);\n@@ -107,11 +100,11 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)\n \tqp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,\n \t\t\t qp_id);\n \n-\tlf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,\n+\tlf_mem = rte_memzone_reserve_aligned(name, len, rte_socket_id(),\n \t\t\tRTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,\n \t\t\tRTE_CACHE_LINE_SIZE);\n \tif (lf_mem == NULL) {\n-\t\totx2_err(\"Could not allocate reserved memzone\");\n+\t\tcn9k_err(\"Could not allocate reserved memzone\");\n \t\tgoto qp_free;\n \t}\n \n@@ -121,24 +114,24 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)\n \tmemset(va, 0, len);\n \n \t/* Initialize pending queue */\n-\tqp->pend_q.rid_queue = (struct otx2_ree_rid *)va;\n+\tqp->pend_q.rid_queue = (struct roc_ree_rid *)va;\n \tqp->pend_q.enq_tail = 0;\n \tqp->pend_q.deq_head = 0;\n \tqp->pend_q.pending_count = 0;\n \n-\tused_len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8);\n+\tused_len = iq_len * RTE_ALIGN(sizeof(struct roc_ree_rid), 8);\n \tused_len = RTE_ALIGN(used_len, pg_sz);\n \tiova += used_len;\n \n \tqp->iq_dma_addr = iova;\n \tqp->id = qp_id;\n-\tqp->base = OTX2_REE_LF_BAR2(vf, qp_id);\n-\tqp->otx2_regexdev_jobid = 0;\n+\tqp->base = roc_ree_qp_get_base(vf, qp_id);\n+\tqp->roc_regexdev_jobid = 0;\n \tqp->write_offset = 0;\n \n-\tret = otx2_ree_iq_enable(dev, qp, OTX2_REE_QUEUE_HI_PRIO, size_div2);\n+\tret = roc_ree_iq_enable(vf, qp, REE_QUEUE_HI_PRIO, size_div2);\n \tif (ret) {\n-\t\totx2_err(\"Could not enable instruction queue\");\n+\t\tcn9k_err(\"Could not enable instruction queue\");\n \t\tgoto qp_free;\n \t}\n \n@@ -150,13 +143,13 @@ ree_qp_create(const struct rte_regexdev *dev, uint16_t qp_id)\n }\n \n static int\n-ree_qp_destroy(const struct rte_regexdev *dev, struct otx2_ree_qp *qp)\n+ree_qp_destroy(const struct rte_regexdev *dev, struct roc_ree_qp *qp)\n {\n \tconst struct rte_memzone *lf_mem;\n \tchar name[RTE_MEMZONE_NAMESIZE];\n \tint ret;\n \n-\totx2_ree_iq_disable(qp);\n+\troc_ree_iq_disable(qp);\n \n \tqp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,\n \t\t\t qp->id);\n@@ -175,8 +168,8 @@ ree_qp_destroy(const struct rte_regexdev *dev, struct otx2_ree_qp *qp)\n static int\n ree_queue_pair_release(struct rte_regexdev *dev, uint16_t qp_id)\n {\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_qp *qp = data->queue_pairs[qp_id];\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_qp *qp = data->queue_pairs[qp_id];\n \tint ret;\n \n \tree_func_trace(\"Queue=%d\", qp_id);\n@@ -186,7 +179,7 @@ ree_queue_pair_release(struct rte_regexdev *dev, uint16_t qp_id)\n \n \tret = ree_qp_destroy(dev, qp);\n \tif (ret) {\n-\t\totx2_err(\"Could not destroy queue pair %d\", qp_id);\n+\t\tcn9k_err(\"Could not destroy queue pair %d\", qp_id);\n \t\treturn ret;\n \t}\n \n@@ -200,12 +193,12 @@ ree_dev_register(const char *name)\n {\n \tstruct rte_regexdev *dev;\n \n-\totx2_ree_dbg(\"Creating regexdev %s\\n\", name);\n+\tcn9k_ree_dbg(\"Creating regexdev %s\\n\", name);\n \n \t/* allocate device structure */\n \tdev = rte_regexdev_register(name);\n \tif (dev == NULL) {\n-\t\totx2_err(\"Failed to allocate regex device for %s\", name);\n+\t\tcn9k_err(\"Failed to allocate regex device for %s\", name);\n \t\treturn NULL;\n \t}\n \n@@ -213,12 +206,12 @@ ree_dev_register(const char *name)\n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n \t\tdev->data->dev_private =\n \t\t\t\trte_zmalloc_socket(\"regexdev device private\",\n-\t\t\t\t\t\tsizeof(struct otx2_ree_data),\n+\t\t\t\t\t\tsizeof(struct cn9k_ree_data),\n \t\t\t\t\t\tRTE_CACHE_LINE_SIZE,\n \t\t\t\t\t\trte_socket_id());\n \n \t\tif (dev->data->dev_private == NULL) {\n-\t\t\totx2_err(\"Cannot allocate memory for dev %s private data\",\n+\t\t\tcn9k_err(\"Cannot allocate memory for dev %s private data\",\n \t\t\t\t\tname);\n \n \t\t\trte_regexdev_unregister(dev);\n@@ -232,7 +225,7 @@ ree_dev_register(const char *name)\n static int\n ree_dev_unregister(struct rte_regexdev *dev)\n {\n-\totx2_ree_dbg(\"Closing regex device %s\", dev->device->name);\n+\tcn9k_ree_dbg(\"Closing regex device %s\", dev->device->name);\n \n \t/* free regex device */\n \trte_regexdev_unregister(dev);\n@@ -246,8 +239,8 @@ ree_dev_unregister(struct rte_regexdev *dev)\n static int\n ree_dev_fini(struct rte_regexdev *dev)\n {\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct rte_pci_device *pci_dev;\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_vf *vf = &data->vf;\n \tint i, ret;\n \n \tree_func_trace();\n@@ -258,9 +251,9 @@ ree_dev_fini(struct rte_regexdev *dev)\n \t\t\treturn ret;\n \t}\n \n-\tret = otx2_ree_queues_detach(dev);\n+\tret = roc_ree_queues_detach(vf);\n \tif (ret)\n-\t\totx2_err(\"Could not detach queues\");\n+\t\tcn9k_err(\"Could not detach queues\");\n \n \t/* TEMP : should be in lib */\n \tif (data->queue_pairs)\n@@ -268,33 +261,32 @@ ree_dev_fini(struct rte_regexdev *dev)\n \tif (data->rules)\n \t\trte_free(data->rules);\n \n-\tpci_dev = container_of(dev->device, struct rte_pci_device, device);\n-\totx2_dev_fini(pci_dev, &(data->vf.otx2_dev));\n+\troc_ree_dev_fini(vf);\n \n \tret = ree_dev_unregister(dev);\n \tif (ret)\n-\t\totx2_err(\"Could not destroy PMD\");\n+\t\tcn9k_err(\"Could not destroy PMD\");\n \n \treturn ret;\n }\n \n static inline int\n-ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,\n-\t\t struct otx2_ree_pending_queue *pend_q)\n+ree_enqueue(struct roc_ree_qp *qp, struct rte_regex_ops *op,\n+\t\t struct roc_ree_pending_queue *pend_q)\n {\n-\tunion otx2_ree_inst inst;\n-\tunion otx2_ree_res *res;\n+\tunion roc_ree_inst inst;\n+\tunion ree_res *res;\n \tuint32_t offset;\n \n-\tif (unlikely(pend_q->pending_count >= OTX2_REE_DEFAULT_CMD_QLEN)) {\n-\t\totx2_err(\"Pending count %\" PRIu64 \" is greater than Q size %d\",\n-\t\tpend_q->pending_count, OTX2_REE_DEFAULT_CMD_QLEN);\n+\tif (unlikely(pend_q->pending_count >= REE_DEFAULT_CMD_QLEN)) {\n+\t\tcn9k_err(\"Pending count %\" PRIu64 \" is greater than Q size %d\",\n+\t\tpend_q->pending_count, REE_DEFAULT_CMD_QLEN);\n \t\treturn -EAGAIN;\n \t}\n-\tif (unlikely(op->mbuf->data_len > OTX2_REE_MAX_PAYLOAD_SIZE ||\n+\tif (unlikely(op->mbuf->data_len > REE_MAX_PAYLOAD_SIZE ||\n \t\t\top->mbuf->data_len == 0)) {\n-\t\totx2_err(\"Packet length %d is greater than MAX payload %d\",\n-\t\t\t\top->mbuf->data_len, OTX2_REE_MAX_PAYLOAD_SIZE);\n+\t\tcn9k_err(\"Packet length %d is greater than MAX payload %d\",\n+\t\t\t\top->mbuf->data_len, REE_MAX_PAYLOAD_SIZE);\n \t\treturn -EAGAIN;\n \t}\n \n@@ -324,7 +316,7 @@ ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,\n \t\tinst.cn98xx.ree_job_ctrl = (0x1 << 8);\n \telse\n \t\tinst.cn98xx.ree_job_ctrl = 0;\n-\tinst.cn98xx.ree_job_id = qp->otx2_regexdev_jobid;\n+\tinst.cn98xx.ree_job_id = qp->roc_regexdev_jobid;\n \t/* W 7 */\n \tinst.cn98xx.ree_job_subset_id_0 = op->group_id0;\n \tif (op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F)\n@@ -348,33 +340,33 @@ ree_enqueue(struct otx2_ree_qp *qp, struct rte_regex_ops *op,\n \tpend_q->rid_queue[pend_q->enq_tail].user_id = op->user_id;\n \n \t/* Mark result as not done */\n-\tres = (union otx2_ree_res *)(op);\n+\tres = (union ree_res *)(op);\n \tres->s.done = 0;\n \tres->s.ree_err = 0;\n \n \t/* We will use soft queue length here to limit requests */\n-\tREE_MOD_INC(pend_q->enq_tail, OTX2_REE_DEFAULT_CMD_QLEN);\n+\tREE_MOD_INC(pend_q->enq_tail, REE_DEFAULT_CMD_QLEN);\n \tpend_q->pending_count += 1;\n-\tREE_MOD_INC(qp->otx2_regexdev_jobid, 0xFFFFFF);\n-\tREE_MOD_INC(qp->write_offset, OTX2_REE_IQ_LEN);\n+\tREE_MOD_INC(qp->roc_regexdev_jobid, 0xFFFFFF);\n+\tREE_MOD_INC(qp->write_offset, REE_IQ_LEN);\n \n \treturn 0;\n }\n \n static uint16_t\n-otx2_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,\n+cn9k_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,\n \t\t struct rte_regex_ops **ops, uint16_t nb_ops)\n {\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_qp *qp = data->queue_pairs[qp_id];\n-\tstruct otx2_ree_pending_queue *pend_q;\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_qp *qp = data->queue_pairs[qp_id];\n+\tstruct roc_ree_pending_queue *pend_q;\n \tuint16_t nb_allowed, count = 0;\n \tstruct rte_regex_ops *op;\n \tint ret;\n \n \tpend_q = &qp->pend_q;\n \n-\tnb_allowed = OTX2_REE_DEFAULT_CMD_QLEN - pend_q->pending_count;\n+\tnb_allowed = REE_DEFAULT_CMD_QLEN - pend_q->pending_count;\n \tif (nb_ops > nb_allowed)\n \t\tnb_ops = nb_allowed;\n \n@@ -392,7 +384,7 @@ otx2_ree_enqueue_burst(struct rte_regexdev *dev, uint16_t qp_id,\n \trte_io_wmb();\n \n \t/* Update Doorbell */\n-\totx2_write64(count, qp->base + OTX2_REE_LF_DOORBELL);\n+\tplt_write64(count, qp->base + REE_LF_DOORBELL);\n \n \treturn count;\n }\n@@ -422,15 +414,15 @@ ree_dequeue_post_process(struct rte_regex_ops *ops)\n \t}\n \n \tif (unlikely(ree_res_status != REE_TYPE_RESULT_DESC)) {\n-\t\tif (ree_res_status & OTX2_REE_STATUS_PMI_SOJ_BIT)\n+\t\tif (ree_res_status & REE_STATUS_PMI_SOJ_BIT)\n \t\t\tops->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_SOJ_F;\n-\t\tif (ree_res_status & OTX2_REE_STATUS_PMI_EOJ_BIT)\n+\t\tif (ree_res_status & REE_STATUS_PMI_EOJ_BIT)\n \t\t\tops->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_EOJ_F;\n-\t\tif (ree_res_status & OTX2_REE_STATUS_ML_CNT_DET_BIT)\n+\t\tif (ree_res_status & REE_STATUS_ML_CNT_DET_BIT)\n \t\t\tops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_SCAN_TIMEOUT_F;\n-\t\tif (ree_res_status & OTX2_REE_STATUS_MM_CNT_DET_BIT)\n+\t\tif (ree_res_status & REE_STATUS_MM_CNT_DET_BIT)\n \t\t\tops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_MATCH_F;\n-\t\tif (ree_res_status & OTX2_REE_STATUS_MP_CNT_DET_BIT)\n+\t\tif (ree_res_status & REE_STATUS_MP_CNT_DET_BIT)\n \t\t\tops->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_PREFIX_F;\n \t}\n \tif (ops->nb_matches > 0) {\n@@ -439,22 +431,22 @@ ree_dequeue_post_process(struct rte_regex_ops *ops)\n \t\t\tops->nb_matches : REE_NUM_MATCHES_ALIGN);\n \t\tmatch = (uint64_t)ops + REE_MATCH_OFFSET;\n \t\tmatch += (ops->nb_matches - off) *\n-\t\t\tsizeof(union otx2_ree_match);\n+\t\t\tsizeof(union ree_match);\n \t\tmemcpy((void *)ops->matches, (void *)match,\n-\t\t\toff * sizeof(union otx2_ree_match));\n+\t\t\toff * sizeof(union ree_match));\n \t}\n }\n \n static uint16_t\n-otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,\n+cn9k_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,\n \t\t struct rte_regex_ops **ops, uint16_t nb_ops)\n {\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_qp *qp = data->queue_pairs[qp_id];\n-\tstruct otx2_ree_pending_queue *pend_q;\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_qp *qp = data->queue_pairs[qp_id];\n+\tstruct roc_ree_pending_queue *pend_q;\n \tint i, nb_pending, nb_completed = 0;\n \tvolatile struct ree_res_s_98 *res;\n-\tstruct otx2_ree_rid *rid;\n+\tstruct roc_ree_rid *rid;\n \n \tpend_q = &qp->pend_q;\n \n@@ -474,7 +466,7 @@ otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,\n \t\tops[i] = (struct rte_regex_ops *)(rid->rid);\n \t\tops[i]->user_id = rid->user_id;\n \n-\t\tREE_MOD_INC(pend_q->deq_head, OTX2_REE_DEFAULT_CMD_QLEN);\n+\t\tREE_MOD_INC(pend_q->deq_head, REE_DEFAULT_CMD_QLEN);\n \t\tpend_q->pending_count -= 1;\n \t}\n \n@@ -487,10 +479,10 @@ otx2_ree_dequeue_burst(struct rte_regexdev *dev, uint16_t qp_id,\n }\n \n static int\n-otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)\n+cn9k_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)\n {\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_vf *vf = &data->vf;\n \n \tree_func_trace();\n \n@@ -502,7 +494,7 @@ otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)\n \n \tinfo->max_queue_pairs = vf->max_queues;\n \tinfo->max_matches = vf->max_matches;\n-\tinfo->max_payload_size = OTX2_REE_MAX_PAYLOAD_SIZE;\n+\tinfo->max_payload_size = REE_MAX_PAYLOAD_SIZE;\n \tinfo->max_rules_per_group = data->max_rules_per_group;\n \tinfo->max_groups = data->max_groups;\n \tinfo->regexdev_capa = data->regexdev_capa;\n@@ -512,11 +504,11 @@ otx2_ree_dev_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info)\n }\n \n static int\n-otx2_ree_dev_config(struct rte_regexdev *dev,\n+cn9k_ree_dev_config(struct rte_regexdev *dev,\n \t\t const struct rte_regexdev_config *cfg)\n {\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_vf *vf = &data->vf;\n \tconst struct ree_rule_db *rule_db;\n \tuint32_t rule_db_len;\n \tint ret;\n@@ -524,29 +516,29 @@ otx2_ree_dev_config(struct rte_regexdev *dev,\n \tree_func_trace();\n \n \tif (cfg->nb_queue_pairs > vf->max_queues) {\n-\t\totx2_err(\"Invalid number of queue pairs requested\");\n+\t\tcn9k_err(\"Invalid number of queue pairs requested\");\n \t\treturn -EINVAL;\n \t}\n \n \tif (cfg->nb_max_matches != vf->max_matches) {\n-\t\totx2_err(\"Invalid number of max matches requested\");\n+\t\tcn9k_err(\"Invalid number of max matches requested\");\n \t\treturn -EINVAL;\n \t}\n \n \tif (cfg->dev_cfg_flags != 0) {\n-\t\totx2_err(\"Invalid device configuration flags requested\");\n+\t\tcn9k_err(\"Invalid device configuration flags requested\");\n \t\treturn -EINVAL;\n \t}\n \n \t/* Unregister error interrupts */\n \tif (vf->err_intr_registered)\n-\t\totx2_ree_err_intr_unregister(dev);\n+\t\troc_ree_err_intr_unregister(vf);\n \n \t/* Detach queues */\n \tif (vf->nb_queues) {\n-\t\tret = otx2_ree_queues_detach(dev);\n+\t\tret = roc_ree_queues_detach(vf);\n \t\tif (ret) {\n-\t\t\totx2_err(\"Could not detach REE queues\");\n+\t\t\tcn9k_err(\"Could not detach REE queues\");\n \t\t\treturn ret;\n \t\t}\n \t}\n@@ -559,7 +551,7 @@ otx2_ree_dev_config(struct rte_regexdev *dev,\n \n \t\tif (data->queue_pairs == NULL) {\n \t\t\tdata->nb_queue_pairs = 0;\n-\t\t\totx2_err(\"Failed to get memory for qp meta data, nb_queues %u\",\n+\t\t\tcn9k_err(\"Failed to get memory for qp meta data, nb_queues %u\",\n \t\t\t\t\tcfg->nb_queue_pairs);\n \t\t\treturn -ENOMEM;\n \t\t}\n@@ -579,7 +571,7 @@ otx2_ree_dev_config(struct rte_regexdev *dev,\n \t\tqp = rte_realloc(qp, sizeof(qp[0]) * cfg->nb_queue_pairs,\n \t\t\t\tRTE_CACHE_LINE_SIZE);\n \t\tif (qp == NULL) {\n-\t\t\totx2_err(\"Failed to realloc qp meta data, nb_queues %u\",\n+\t\t\tcn9k_err(\"Failed to realloc qp meta data, nb_queues %u\",\n \t\t\t\t\tcfg->nb_queue_pairs);\n \t\t\treturn -ENOMEM;\n \t\t}\n@@ -594,52 +586,52 @@ otx2_ree_dev_config(struct rte_regexdev *dev,\n \tdata->nb_queue_pairs = cfg->nb_queue_pairs;\n \n \t/* Attach queues */\n-\totx2_ree_dbg(\"Attach %d queues\", cfg->nb_queue_pairs);\n-\tret = otx2_ree_queues_attach(dev, cfg->nb_queue_pairs);\n+\tcn9k_ree_dbg(\"Attach %d queues\", cfg->nb_queue_pairs);\n+\tret = roc_ree_queues_attach(vf, cfg->nb_queue_pairs);\n \tif (ret) {\n-\t\totx2_err(\"Could not attach queues\");\n+\t\tcn9k_err(\"Could not attach queues\");\n \t\treturn -ENODEV;\n \t}\n \n-\tret = otx2_ree_msix_offsets_get(dev);\n+\tret = roc_ree_msix_offsets_get(vf);\n \tif (ret) {\n-\t\totx2_err(\"Could not get MSI-X offsets\");\n+\t\tcn9k_err(\"Could not get MSI-X offsets\");\n \t\tgoto queues_detach;\n \t}\n \n \tif (cfg->rule_db && cfg->rule_db_len) {\n-\t\totx2_ree_dbg(\"rule_db length %d\", cfg->rule_db_len);\n+\t\tcn9k_ree_dbg(\"rule_db length %d\", cfg->rule_db_len);\n \t\trule_db = (const struct ree_rule_db *)cfg->rule_db;\n \t\trule_db_len = rule_db->number_of_entries *\n \t\t\t\tsizeof(struct ree_rule_db_entry);\n-\t\totx2_ree_dbg(\"rule_db number of entries %d\",\n+\t\tcn9k_ree_dbg(\"rule_db number of entries %d\",\n \t\t\t\trule_db->number_of_entries);\n \t\tif (rule_db_len > cfg->rule_db_len) {\n-\t\t\totx2_err(\"Could not program rule db\");\n+\t\t\tcn9k_err(\"Could not program rule db\");\n \t\t\tret = -EINVAL;\n \t\t\tgoto queues_detach;\n \t\t}\n-\t\tret = otx2_ree_rule_db_prog(dev, (const char *)rule_db->entries,\n-\t\t\t\trule_db_len, NULL, OTX2_REE_NON_INC_PROG);\n+\t\tret = roc_ree_rule_db_prog(vf, (const char *)rule_db->entries,\n+\t\t\t\trule_db_len, NULL, REE_NON_INC_PROG);\n \t\tif (ret) {\n-\t\t\totx2_err(\"Could not program rule db\");\n+\t\t\tcn9k_err(\"Could not program rule db\");\n \t\t\tgoto queues_detach;\n \t\t}\n \t}\n \n-\tdev->enqueue = otx2_ree_enqueue_burst;\n-\tdev->dequeue = otx2_ree_dequeue_burst;\n+\tdev->enqueue = cn9k_ree_enqueue_burst;\n+\tdev->dequeue = cn9k_ree_dequeue_burst;\n \n \trte_mb();\n \treturn 0;\n \n queues_detach:\n-\totx2_ree_queues_detach(dev);\n+\troc_ree_queues_detach(vf);\n \treturn ret;\n }\n \n static int\n-otx2_ree_stop(struct rte_regexdev *dev)\n+cn9k_ree_stop(struct rte_regexdev *dev)\n {\n \tRTE_SET_USED(dev);\n \n@@ -648,18 +640,20 @@ otx2_ree_stop(struct rte_regexdev *dev)\n }\n \n static int\n-otx2_ree_start(struct rte_regexdev *dev)\n+cn9k_ree_start(struct rte_regexdev *dev)\n {\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_vf *vf = &data->vf;\n \tuint32_t rule_db_len = 0;\n \tint ret;\n \n \tree_func_trace();\n \n-\tret = otx2_ree_rule_db_len_get(dev, &rule_db_len, NULL);\n+\tret = roc_ree_rule_db_len_get(vf, &rule_db_len, NULL);\n \tif (ret)\n \t\treturn ret;\n \tif (rule_db_len == 0) {\n-\t\totx2_err(\"Rule db not programmed\");\n+\t\tcn9k_err(\"Rule db not programmed\");\n \t\treturn -EFAULT;\n \t}\n \n@@ -667,56 +661,55 @@ otx2_ree_start(struct rte_regexdev *dev)\n }\n \n static int\n-otx2_ree_close(struct rte_regexdev *dev)\n+cn9k_ree_close(struct rte_regexdev *dev)\n {\n \treturn ree_dev_fini(dev);\n }\n \n static int\n-otx2_ree_queue_pair_setup(struct rte_regexdev *dev, uint16_t qp_id,\n+cn9k_ree_queue_pair_setup(struct rte_regexdev *dev, uint16_t qp_id,\n \t\tconst struct rte_regexdev_qp_conf *qp_conf)\n {\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_qp *qp;\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_qp *qp;\n \n \tree_func_trace(\"Queue=%d\", qp_id);\n \n \tif (data->queue_pairs[qp_id] != NULL)\n \t\tree_queue_pair_release(dev, qp_id);\n \n-\tif (qp_conf->nb_desc > OTX2_REE_DEFAULT_CMD_QLEN) {\n-\t\totx2_err(\"Could not setup queue pair for %u descriptors\",\n+\tif (qp_conf->nb_desc > REE_DEFAULT_CMD_QLEN) {\n+\t\tcn9k_err(\"Could not setup queue pair for %u descriptors\",\n \t\t\t\tqp_conf->nb_desc);\n \t\treturn -EINVAL;\n \t}\n \tif (qp_conf->qp_conf_flags != 0) {\n-\t\totx2_err(\"Could not setup queue pair with configuration flags 0x%x\",\n+\t\tcn9k_err(\"Could not setup queue pair with configuration flags 0x%x\",\n \t\t\t\tqp_conf->qp_conf_flags);\n \t\treturn -EINVAL;\n \t}\n \n \tqp = ree_qp_create(dev, qp_id);\n \tif (qp == NULL) {\n-\t\totx2_err(\"Could not create queue pair %d\", qp_id);\n+\t\tcn9k_err(\"Could not create queue pair %d\", qp_id);\n \t\treturn -ENOMEM;\n \t}\n-\tqp->cb = qp_conf->cb;\n \tdata->queue_pairs[qp_id] = qp;\n \n \treturn 0;\n }\n \n static int\n-otx2_ree_rule_db_compile_activate(struct rte_regexdev *dev)\n+cn9k_ree_rule_db_compile_activate(struct rte_regexdev *dev)\n {\n-\treturn otx2_ree_rule_db_compile_prog(dev);\n+\treturn cn9k_ree_rule_db_compile_prog(dev);\n }\n \n static int\n-otx2_ree_rule_db_update(struct rte_regexdev *dev,\n+cn9k_ree_rule_db_update(struct rte_regexdev *dev,\n \t\tconst struct rte_regexdev_rule *rules, uint16_t nb_rules)\n {\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n \tstruct rte_regexdev_rule *old_ptr;\n \tuint32_t i, sum_nb_rules;\n \n@@ -770,10 +763,11 @@ otx2_ree_rule_db_update(struct rte_regexdev *dev,\n }\n \n static int\n-otx2_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,\n+cn9k_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,\n \t\tuint32_t rule_db_len)\n {\n-\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_vf *vf = &data->vf;\n \tconst struct ree_rule_db *ree_rule_db;\n \tuint32_t ree_rule_db_len;\n \tint ret;\n@@ -784,21 +778,23 @@ otx2_ree_rule_db_import(struct rte_regexdev *dev, const char *rule_db,\n \tree_rule_db_len = ree_rule_db->number_of_entries *\n \t\t\tsizeof(struct ree_rule_db_entry);\n \tif (ree_rule_db_len > rule_db_len) {\n-\t\totx2_err(\"Could not program rule db\");\n+\t\tcn9k_err(\"Could not program rule db\");\n \t\treturn -EINVAL;\n \t}\n-\tret = otx2_ree_rule_db_prog(dev, (const char *)ree_rule_db->entries,\n-\t\t\tree_rule_db_len, NULL, OTX2_REE_NON_INC_PROG);\n+\tret = roc_ree_rule_db_prog(vf, (const char *)ree_rule_db->entries,\n+\t\t\tree_rule_db_len, NULL, REE_NON_INC_PROG);\n \tif (ret) {\n-\t\totx2_err(\"Could not program rule db\");\n+\t\tcn9k_err(\"Could not program rule db\");\n \t\treturn -ENOSPC;\n \t}\n \treturn 0;\n }\n \n static int\n-otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)\n+cn9k_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)\n {\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_vf *vf = &data->vf;\n \tstruct ree_rule_db *ree_rule_db;\n \tuint32_t rule_dbi_len;\n \tuint32_t rule_db_len;\n@@ -806,7 +802,7 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)\n \n \tree_func_trace();\n \n-\tret = otx2_ree_rule_db_len_get(dev, &rule_db_len, &rule_dbi_len);\n+\tret = roc_ree_rule_db_len_get(vf, &rule_db_len, &rule_dbi_len);\n \tif (ret)\n \t\treturn ret;\n \n@@ -816,10 +812,10 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)\n \t}\n \n \tree_rule_db = (struct ree_rule_db *)rule_db;\n-\tret = otx2_ree_rule_db_get(dev, (char *)ree_rule_db->entries,\n+\tret = roc_ree_rule_db_get(vf, (char *)ree_rule_db->entries,\n \t\t\trule_db_len, NULL, 0);\n \tif (ret) {\n-\t\totx2_err(\"Could not export rule db\");\n+\t\tcn9k_err(\"Could not export rule db\");\n \t\treturn -EFAULT;\n \t}\n \tree_rule_db->number_of_entries =\n@@ -830,55 +826,44 @@ otx2_ree_rule_db_export(struct rte_regexdev *dev, char *rule_db)\n \treturn 0;\n }\n \n-static int\n-ree_get_blkaddr(struct otx2_dev *dev)\n-{\n-\tint pf;\n-\n-\tpf = otx2_get_pf(dev->pf_func);\n-\tif (pf == REE0_PF)\n-\t\treturn RVU_BLOCK_ADDR_REE0;\n-\telse if (pf == REE1_PF)\n-\t\treturn RVU_BLOCK_ADDR_REE1;\n-\telse\n-\t\treturn 0;\n-}\n-\n-static struct rte_regexdev_ops otx2_ree_ops = {\n-\t\t.dev_info_get = otx2_ree_dev_info_get,\n-\t\t.dev_configure = otx2_ree_dev_config,\n-\t\t.dev_qp_setup = otx2_ree_queue_pair_setup,\n-\t\t.dev_start = otx2_ree_start,\n-\t\t.dev_stop = otx2_ree_stop,\n-\t\t.dev_close = otx2_ree_close,\n-\t\t.dev_attr_get = NULL,\n-\t\t.dev_attr_set = NULL,\n-\t\t.dev_rule_db_update = otx2_ree_rule_db_update,\n-\t\t.dev_rule_db_compile_activate =\n-\t\t\t\totx2_ree_rule_db_compile_activate,\n-\t\t.dev_db_import = otx2_ree_rule_db_import,\n-\t\t.dev_db_export = otx2_ree_rule_db_export,\n-\t\t.dev_xstats_names_get = NULL,\n-\t\t.dev_xstats_get = NULL,\n-\t\t.dev_xstats_by_name_get = NULL,\n-\t\t.dev_xstats_reset = NULL,\n-\t\t.dev_selftest = NULL,\n-\t\t.dev_dump = NULL,\n+static struct rte_regexdev_ops cn9k_ree_ops = {\n+\t.dev_info_get = cn9k_ree_dev_info_get,\n+\t.dev_configure = cn9k_ree_dev_config,\n+\t.dev_qp_setup = cn9k_ree_queue_pair_setup,\n+\t.dev_start = cn9k_ree_start,\n+\t.dev_stop = cn9k_ree_stop,\n+\t.dev_close = cn9k_ree_close,\n+\t.dev_attr_get = NULL,\n+\t.dev_attr_set = NULL,\n+\t.dev_rule_db_update = cn9k_ree_rule_db_update,\n+\t.dev_rule_db_compile_activate =\n+\t\t\tcn9k_ree_rule_db_compile_activate,\n+\t.dev_db_import = cn9k_ree_rule_db_import,\n+\t.dev_db_export = cn9k_ree_rule_db_export,\n+\t.dev_xstats_names_get = NULL,\n+\t.dev_xstats_get = NULL,\n+\t.dev_xstats_by_name_get = NULL,\n+\t.dev_xstats_reset = NULL,\n+\t.dev_selftest = NULL,\n+\t.dev_dump = NULL,\n };\n \n static int\n-otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+cn9k_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t\t struct rte_pci_device *pci_dev)\n {\n \tchar name[RTE_REGEXDEV_NAME_MAX_LEN];\n-\tstruct otx2_ree_data *data;\n-\tstruct otx2_dev *otx2_dev;\n+\tstruct cn9k_ree_data *data;\n \tstruct rte_regexdev *dev;\n-\tuint8_t max_matches = 0;\n-\tstruct otx2_ree_vf *vf;\n-\tuint16_t nb_queues = 0;\n+\tstruct roc_ree_vf *vf;\n \tint ret;\n \n+\tret = roc_plt_init();\n+\tif (ret < 0) {\n+\t\tplt_err(\"Failed to initialize platform model\");\n+\t\treturn ret;\n+\t}\n+\n \trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n \n \tdev = ree_dev_register(name);\n@@ -887,63 +872,19 @@ otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t\tgoto exit;\n \t}\n \n-\tdev->dev_ops = &otx2_ree_ops;\n+\tdev->dev_ops = &cn9k_ree_ops;\n \tdev->device = &pci_dev->device;\n \n \t/* Get private data space allocated */\n \tdata = dev->data->dev_private;\n \tvf = &data->vf;\n-\n-\totx2_dev = &vf->otx2_dev;\n-\n-\t/* Initialize the base otx2_dev object */\n-\tret = otx2_dev_init(pci_dev, otx2_dev);\n+\tvf->pci_dev = pci_dev;\n+\tret = roc_ree_dev_init(vf);\n \tif (ret) {\n-\t\totx2_err(\"Could not initialize otx2_dev\");\n+\t\tplt_err(\"Failed to initialize roc cpt rc=%d\", ret);\n \t\tgoto dev_unregister;\n \t}\n-\t/* Get REE block address */\n-\tvf->block_address = ree_get_blkaddr(otx2_dev);\n-\tif (!vf->block_address) {\n-\t\totx2_err(\"Could not determine block PF number\");\n-\t\tgoto otx2_dev_fini;\n-\t}\n-\n-\t/* Get number of queues available on the device */\n-\tret = otx2_ree_available_queues_get(dev, &nb_queues);\n-\tif (ret) {\n-\t\totx2_err(\"Could not determine the number of queues available\");\n-\t\tgoto otx2_dev_fini;\n-\t}\n-\n-\t/* Don't exceed the limits set per VF */\n-\tnb_queues = RTE_MIN(nb_queues, OTX2_REE_MAX_QUEUES_PER_VF);\n-\n-\tif (nb_queues == 0) {\n-\t\totx2_err(\"No free queues available on the device\");\n-\t\tgoto otx2_dev_fini;\n-\t}\n-\n-\tvf->max_queues = nb_queues;\n-\n-\totx2_ree_dbg(\"Max queues supported by device: %d\", vf->max_queues);\n-\n-\t/* Get number of maximum matches supported on the device */\n-\tret = otx2_ree_max_matches_get(dev, &max_matches);\n-\tif (ret) {\n-\t\totx2_err(\"Could not determine the maximum matches supported\");\n-\t\tgoto otx2_dev_fini;\n-\t}\n-\t/* Don't exceed the limits set per VF */\n-\tmax_matches = RTE_MIN(max_matches, OTX2_REE_MAX_MATCHES_PER_VF);\n-\tif (max_matches == 0) {\n-\t\totx2_err(\"Could not determine the maximum matches supported\");\n-\t\tgoto otx2_dev_fini;\n-\t}\n-\n-\tvf->max_matches = max_matches;\n \n-\totx2_ree_dbg(\"Max matches supported by device: %d\", vf->max_matches);\n \tdata->rule_flags = RTE_REGEX_PCRE_RULE_ALLOW_EMPTY_F |\n \t\t\tRTE_REGEX_PCRE_RULE_ANCHORED_F;\n \tdata->regexdev_capa = 0;\n@@ -954,18 +895,16 @@ otx2_ree_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tdev->state = RTE_REGEXDEV_READY;\n \treturn 0;\n \n-otx2_dev_fini:\n-\totx2_dev_fini(pci_dev, otx2_dev);\n dev_unregister:\n \tree_dev_unregister(dev);\n exit:\n-\totx2_err(\"Could not create device (vendor_id: 0x%x device_id: 0x%x)\",\n+\tcn9k_err(\"Could not create device (vendor_id: 0x%x device_id: 0x%x)\",\n \t\t pci_dev->id.vendor_id, pci_dev->id.device_id);\n \treturn ret;\n }\n \n static int\n-otx2_ree_pci_remove(struct rte_pci_device *pci_dev)\n+cn9k_ree_pci_remove(struct rte_pci_device *pci_dev)\n {\n \tchar name[RTE_REGEXDEV_NAME_MAX_LEN];\n \tstruct rte_regexdev *dev = NULL;\n@@ -986,20 +925,20 @@ otx2_ree_pci_remove(struct rte_pci_device *pci_dev)\n static struct rte_pci_id pci_id_ree_table[] = {\n \t{\n \t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n-\t\t\t\tPCI_DEVID_OCTEONTX2_RVU_REE_PF)\n+\t\t\t\tPCI_DEVID_CNXK_RVU_REE_PF)\n \t},\n \t{\n \t\t.vendor_id = 0,\n \t}\n };\n \n-static struct rte_pci_driver otx2_regexdev_pmd = {\n+static struct rte_pci_driver cn9k_regexdev_pmd = {\n \t.id_table = pci_id_ree_table,\n \t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n-\t.probe = otx2_ree_pci_probe,\n-\t.remove = otx2_ree_pci_remove,\n+\t.probe = cn9k_ree_pci_probe,\n+\t.remove = cn9k_ree_pci_remove,\n };\n \n \n-RTE_PMD_REGISTER_PCI(REGEXDEV_NAME_OCTEONTX2_PMD, otx2_regexdev_pmd);\n-RTE_PMD_REGISTER_PCI_TABLE(REGEXDEV_NAME_OCTEONTX2_PMD, pci_id_ree_table);\n+RTE_PMD_REGISTER_PCI(REGEXDEV_NAME_CN9K_PMD, cn9k_regexdev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(REGEXDEV_NAME_CN9K_PMD, pci_id_ree_table);\ndiff --git a/drivers/regex/cn9k/cn9k_regexdev.h b/drivers/regex/cn9k/cn9k_regexdev.h\nnew file mode 100644\nindex 0000000000..c715502167\n--- /dev/null\n+++ b/drivers/regex/cn9k/cn9k_regexdev.h\n@@ -0,0 +1,44 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef _CN9K_REGEXDEV_H_\n+#define _CN9K_REGEXDEV_H_\n+\n+#include <rte_common.h>\n+#include <rte_regexdev.h>\n+\n+#include \"roc_api.h\"\n+\n+#define cn9k_ree_dbg plt_ree_dbg\n+#define cn9k_err plt_err\n+\n+#define ree_func_trace cn9k_ree_dbg\n+\n+/* Marvell CN9K Regex PMD device name */\n+#define REGEXDEV_NAME_CN9K_PMD\tregex_cn9k\n+\n+/**\n+ * Device private data\n+ */\n+struct cn9k_ree_data {\n+\tuint32_t regexdev_capa;\n+\tuint64_t rule_flags;\n+\t/**< Feature flags exposes HW/SW features for the given device */\n+\tuint16_t max_rules_per_group;\n+\t/**< Maximum rules supported per subset by this device */\n+\tuint16_t max_groups;\n+\t/**< Maximum subset supported by this device */\n+\tvoid **queue_pairs;\n+\t/**< Array of pointers to queue pairs. */\n+\tuint16_t nb_queue_pairs;\n+\t/**< Number of device queue pairs. */\n+\tstruct roc_ree_vf vf;\n+\t/**< vf data */\n+\tstruct rte_regexdev_rule *rules;\n+\t/**< rules to be compiled */\n+\tuint16_t nb_rules;\n+\t/**< number of rules */\n+} __rte_cache_aligned;\n+\n+#endif /* _CN9K_REGEXDEV_H_ */\ndiff --git a/drivers/regex/octeontx2/otx2_regexdev_compiler.c b/drivers/regex/cn9k/cn9k_regexdev_compiler.c\nsimilarity index 86%\nrename from drivers/regex/octeontx2/otx2_regexdev_compiler.c\nrename to drivers/regex/cn9k/cn9k_regexdev_compiler.c\nindex 785459f741..935b8a53b4 100644\n--- a/drivers/regex/octeontx2/otx2_regexdev_compiler.c\n+++ b/drivers/regex/cn9k/cn9k_regexdev_compiler.c\n@@ -5,9 +5,8 @@\n #include <rte_malloc.h>\n #include <rte_regexdev.h>\n \n-#include \"otx2_regexdev.h\"\n-#include \"otx2_regexdev_compiler.h\"\n-#include \"otx2_regexdev_mbox.h\"\n+#include \"cn9k_regexdev.h\"\n+#include \"cn9k_regexdev_compiler.h\"\n \n #ifdef REE_COMPILER_SDK\n #include <rxp-compiler.h>\n@@ -65,7 +64,7 @@ ree_rule_db_compile(const struct rte_regexdev_rule *rules,\n \t\t\tnb_rules*sizeof(struct rxp_rule_entry), 0);\n \n \tif (ruleset.rules == NULL) {\n-\t\totx2_err(\"Could not allocate memory for rule compilation\\n\");\n+\t\tcn9k_err(\"Could not allocate memory for rule compilation\\n\");\n \t\treturn -EFAULT;\n \t}\n \tif (rof_for_incremental_compile)\n@@ -126,9 +125,10 @@ ree_rule_db_compile(const struct rte_regexdev_rule *rules,\n }\n \n int\n-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)\n+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev)\n {\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n+\tstruct cn9k_ree_data *data = dev->data->dev_private;\n+\tstruct roc_ree_vf *vf = &data->vf;\n \tchar compiler_version[] = \"20.5.2.eda0fa2\";\n \tchar timestamp[] = \"19700101_000001\";\n \tuint32_t rule_db_len, rule_dbi_len;\n@@ -144,25 +144,25 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)\n \n \tree_func_trace();\n \n-\tret = otx2_ree_rule_db_len_get(dev, &rule_db_len, &rule_dbi_len);\n+\tret = roc_ree_rule_db_len_get(vf, &rule_db_len, &rule_dbi_len);\n \tif (ret != 0) {\n-\t\totx2_err(\"Could not get rule db length\");\n+\t\tcn9k_err(\"Could not get rule db length\");\n \t\treturn ret;\n \t}\n \n \tif (rule_db_len > 0) {\n-\t\totx2_ree_dbg(\"Incremental compile, rule db len %d rule dbi len %d\",\n+\t\tcn9k_ree_dbg(\"Incremental compile, rule db len %d rule dbi len %d\",\n \t\t\t\trule_db_len, rule_dbi_len);\n \t\trule_db = rte_malloc(\"ree_rule_db\", rule_db_len, 0);\n \t\tif (!rule_db) {\n-\t\t\totx2_err(\"Could not allocate memory for rule db\");\n+\t\t\tcn9k_err(\"Could not allocate memory for rule db\");\n \t\t\treturn -EFAULT;\n \t\t}\n \n-\t\tret = otx2_ree_rule_db_get(dev, rule_db, rule_db_len,\n+\t\tret = roc_ree_rule_db_get(vf, rule_db, rule_db_len,\n \t\t\t\t(char *)rule_dbi, rule_dbi_len);\n \t\tif (ret) {\n-\t\t\totx2_err(\"Could not read rule db\");\n+\t\t\tcn9k_err(\"Could not read rule db\");\n \t\t\trte_free(rule_db);\n \t\t\treturn -EFAULT;\n \t\t}\n@@ -188,7 +188,7 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)\n \t\tret = ree_rule_db_compile(data->rules, data->nb_rules, &rof,\n \t\t\t\t&rofi, &rof_inc, rofi_inc_p);\n \t\tif (rofi->number_of_entries == 0) {\n-\t\t\totx2_ree_dbg(\"No change to rule db\");\n+\t\t\tcn9k_ree_dbg(\"No change to rule db\");\n \t\t\tret = 0;\n \t\t\tgoto free_structs;\n \t\t}\n@@ -201,14 +201,14 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)\n \t\t\t\t&rofi, NULL, NULL);\n \t}\n \tif (ret != 0) {\n-\t\totx2_err(\"Could not compile rule db\");\n+\t\tcn9k_err(\"Could not compile rule db\");\n \t\tgoto free_structs;\n \t}\n \trule_db_len = rof->number_of_entries * sizeof(struct rxp_rof_entry);\n-\tret = otx2_ree_rule_db_prog(dev, (char *)rof->rof_entries, rule_db_len,\n+\tret = roc_ree_rule_db_prog(vf, (char *)rof->rof_entries, rule_db_len,\n \t\t\trofi_rof_entries, rule_dbi_len);\n \tif (ret)\n-\t\totx2_err(\"Could not program rule db\");\n+\t\tcn9k_err(\"Could not program rule db\");\n \n free_structs:\n \trxp_free_structs(NULL, NULL, NULL, NULL, NULL, &rof, NULL, &rofi, NULL,\n@@ -221,7 +221,7 @@ otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)\n }\n #else\n int\n-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev)\n+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev)\n {\n \tRTE_SET_USED(dev);\n \treturn -ENOTSUP;\ndiff --git a/drivers/regex/cn9k/cn9k_regexdev_compiler.h b/drivers/regex/cn9k/cn9k_regexdev_compiler.h\nnew file mode 100644\nindex 0000000000..4c29a69ada\n--- /dev/null\n+++ b/drivers/regex/cn9k/cn9k_regexdev_compiler.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef _CN9K_REGEXDEV_COMPILER_H_\n+#define _CN9K_REGEXDEV_COMPILER_H_\n+\n+int\n+cn9k_ree_rule_db_compile_prog(struct rte_regexdev *dev);\n+\n+#endif /* _CN9K_REGEXDEV_COMPILER_H_ */\ndiff --git a/drivers/regex/octeontx2/meson.build b/drivers/regex/cn9k/meson.build\nsimilarity index 65%\nrename from drivers/regex/octeontx2/meson.build\nrename to drivers/regex/cn9k/meson.build\nindex 3f81add5bf..bb0504fba1 100644\n--- a/drivers/regex/octeontx2/meson.build\n+++ b/drivers/regex/cn9k/meson.build\n@@ -16,12 +16,10 @@ if lib.found()\n endif\n \n sources = files(\n- 'otx2_regexdev.c',\n- 'otx2_regexdev_compiler.c',\n- 'otx2_regexdev_hw_access.c',\n- 'otx2_regexdev_mbox.c',\n+ 'cn9k_regexdev.c',\n+ 'cn9k_regexdev_compiler.c',\n )\n \n-deps += ['bus_pci', 'common_octeontx2', 'regexdev']\n+deps += ['bus_pci', 'regexdev']\n+deps += ['common_cnxk', 'mempool_cnxk']\n \n-includes += include_directories('../../common/octeontx2')\ndiff --git a/drivers/regex/octeontx2/version.map b/drivers/regex/cn9k/version.map\nsimilarity index 100%\nrename from drivers/regex/octeontx2/version.map\nrename to drivers/regex/cn9k/version.map\ndiff --git a/drivers/regex/meson.build b/drivers/regex/meson.build\nindex 94222e55fe..7ad55af8ca 100644\n--- a/drivers/regex/meson.build\n+++ b/drivers/regex/meson.build\n@@ -3,6 +3,6 @@\n \n drivers = [\n 'mlx5',\n- 'octeontx2',\n+ 'cn9k',\n ]\n std_deps = ['ethdev', 'kvargs'] # 'ethdev' also pulls in mbuf, net, eal etc\ndiff --git a/drivers/regex/octeontx2/otx2_regexdev.h b/drivers/regex/octeontx2/otx2_regexdev.h\ndeleted file mode 100644\nindex d710535f5f..0000000000\n--- a/drivers/regex/octeontx2/otx2_regexdev.h\n+++ /dev/null\n@@ -1,109 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_REGEXDEV_H_\n-#define _OTX2_REGEXDEV_H_\n-\n-#include <rte_common.h>\n-#include <rte_regexdev.h>\n-\n-#include \"otx2_dev.h\"\n-\n-#define ree_func_trace otx2_ree_dbg\n-\n-/* Marvell OCTEON TX2 Regex PMD device name */\n-#define REGEXDEV_NAME_OCTEONTX2_PMD\tregex_octeontx2\n-\n-#define OTX2_REE_MAX_LFS\t\t36\n-#define OTX2_REE_MAX_QUEUES_PER_VF\t36\n-#define OTX2_REE_MAX_MATCHES_PER_VF\t254\n-\n-#define OTX2_REE_MAX_PAYLOAD_SIZE\t(1 << 14)\n-\n-#define OTX2_REE_NON_INC_PROG 0\n-#define OTX2_REE_INC_PROG 1\n-\n-#define REE_MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++)\n-\n-\n-/**\n- * Device vf data\n- */\n-struct otx2_ree_vf {\n-\tstruct otx2_dev otx2_dev;\n-\t/**< Base class */\n-\tuint16_t max_queues;\n-\t/**< Max queues supported */\n-\tuint8_t nb_queues;\n-\t/**< Number of regex queues attached */\n-\tuint16_t max_matches;\n-\t/**< Max matches supported*/\n-\tuint16_t lf_msixoff[OTX2_REE_MAX_LFS];\n-\t/**< MSI-X offsets */\n-\tuint8_t block_address;\n-\t/**< REE Block Address */\n-\tuint8_t err_intr_registered:1;\n-\t/**< Are error interrupts registered? */\n-};\n-\n-/**\n- * Device private data\n- */\n-struct otx2_ree_data {\n-\tuint32_t regexdev_capa;\n-\tuint64_t rule_flags;\n-\t/**< Feature flags exposes HW/SW features for the given device */\n-\tuint16_t max_rules_per_group;\n-\t/**< Maximum rules supported per subset by this device */\n-\tuint16_t max_groups;\n-\t/**< Maximum subset supported by this device */\n-\tvoid **queue_pairs;\n-\t/**< Array of pointers to queue pairs. */\n-\tuint16_t nb_queue_pairs;\n-\t/**< Number of device queue pairs. */\n-\tstruct otx2_ree_vf vf;\n-\t/**< vf data */\n-\tstruct rte_regexdev_rule *rules;\n-\t/**< rules to be compiled */\n-\tuint16_t nb_rules;\n-\t/**< number of rules */\n-} __rte_cache_aligned;\n-\n-struct otx2_ree_rid {\n-\tuintptr_t rid;\n-\t/** Request id of a ree operation */\n-\tuint64_t user_id;\n-\t/* Client data */\n-\t/**< IOVA address of the pattern to be matched. */\n-};\n-\n-struct otx2_ree_pending_queue {\n-\tuint64_t pending_count;\n-\t/** Pending requests count */\n-\tstruct otx2_ree_rid *rid_queue;\n-\t/** Array of pending requests */\n-\tuint16_t enq_tail;\n-\t/** Tail of queue to be used for enqueue */\n-\tuint16_t deq_head;\n-\t/** Head of queue to be used for dequeue */\n-};\n-\n-struct otx2_ree_qp {\n-\tuint32_t id;\n-\t/**< Queue pair id */\n-\tuintptr_t base;\n-\t/**< Base address where BAR is mapped */\n-\tstruct otx2_ree_pending_queue pend_q;\n-\t/**< Pending queue */\n-\trte_iova_t iq_dma_addr;\n-\t/**< Instruction queue address */\n-\tuint32_t otx2_regexdev_jobid;\n-\t/**< Job ID */\n-\tuint32_t write_offset;\n-\t/**< write offset */\n-\tregexdev_stop_flush_t cb;\n-\t/**< Callback function called during rte_regex_dev_stop()*/\n-};\n-\n-#endif /* _OTX2_REGEXDEV_H_ */\ndiff --git a/drivers/regex/octeontx2/otx2_regexdev_compiler.h b/drivers/regex/octeontx2/otx2_regexdev_compiler.h\ndeleted file mode 100644\nindex 8d2625bf7f..0000000000\n--- a/drivers/regex/octeontx2/otx2_regexdev_compiler.h\n+++ /dev/null\n@@ -1,11 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_REGEXDEV_COMPILER_H_\n-#define _OTX2_REGEXDEV_COMPILER_H_\n-\n-int\n-otx2_ree_rule_db_compile_prog(struct rte_regexdev *dev);\n-\n-#endif /* _OTX2_REGEXDEV_COMPILER_H_ */\ndiff --git a/drivers/regex/octeontx2/otx2_regexdev_hw_access.c b/drivers/regex/octeontx2/otx2_regexdev_hw_access.c\ndeleted file mode 100644\nindex f8031d0f72..0000000000\n--- a/drivers/regex/octeontx2/otx2_regexdev_hw_access.c\n+++ /dev/null\n@@ -1,167 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_dev.h\"\n-#include \"otx2_regexdev_hw_access.h\"\n-#include \"otx2_regexdev_mbox.h\"\n-\n-static void\n-ree_lf_err_intr_handler(void *param)\n-{\n-\tuintptr_t base = (uintptr_t)param;\n-\tuint8_t lf_id;\n-\tuint64_t intr;\n-\n-\tlf_id = (base >> 12) & 0xFF;\n-\n-\tintr = otx2_read64(base + OTX2_REE_LF_MISC_INT);\n-\tif (intr == 0)\n-\t\treturn;\n-\n-\totx2_ree_dbg(\"LF %d MISC_INT: 0x%\" PRIx64 \"\", lf_id, intr);\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, base + OTX2_REE_LF_MISC_INT);\n-}\n-\n-static void\n-ree_lf_err_intr_unregister(const struct rte_regexdev *dev, uint16_t msix_off,\n-\t\t\t uintptr_t base)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\n-\t/* Disable error interrupts */\n-\totx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);\n-\n-\totx2_unregister_irq(handle, ree_lf_err_intr_handler, (void *)base,\n-\t\t\t msix_off);\n-}\n-\n-void\n-otx2_ree_err_intr_unregister(const struct rte_regexdev *dev)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tuintptr_t base;\n-\tuint32_t i;\n-\n-\tfor (i = 0; i < vf->nb_queues; i++) {\n-\t\tbase = OTX2_REE_LF_BAR2(vf, i);\n-\t\tree_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);\n-\t}\n-\n-\tvf->err_intr_registered = 0;\n-}\n-\n-static int\n-ree_lf_err_intr_register(const struct rte_regexdev *dev, uint16_t msix_off,\n-\t\t\t uintptr_t base)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tint ret;\n-\n-\t/* Disable error interrupts */\n-\totx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);\n-\n-\t/* Register error interrupt handler */\n-\tret = otx2_register_irq(handle, ree_lf_err_intr_handler, (void *)base,\n-\t\t\t\tmsix_off);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* Enable error interrupts */\n-\totx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1S);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_ree_err_intr_register(const struct rte_regexdev *dev)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tuint32_t i, j, ret;\n-\tuintptr_t base;\n-\n-\tfor (i = 0; i < vf->nb_queues; i++) {\n-\t\tif (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {\n-\t\t\totx2_err(\"Invalid REE LF MSI-X offset: 0x%x\",\n-\t\t\t\t vf->lf_msixoff[i]);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\tfor (i = 0; i < vf->nb_queues; i++) {\n-\t\tbase = OTX2_REE_LF_BAR2(vf, i);\n-\t\tret = ree_lf_err_intr_register(dev, vf->lf_msixoff[i], base);\n-\t\tif (ret)\n-\t\t\tgoto intr_unregister;\n-\t}\n-\n-\tvf->err_intr_registered = 1;\n-\treturn 0;\n-\n-intr_unregister:\n-\t/* Unregister the ones already registered */\n-\tfor (j = 0; j < i; j++) {\n-\t\tbase = OTX2_REE_LF_BAR2(vf, j);\n-\t\tree_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);\n-\t}\n-\treturn ret;\n-}\n-\n-int\n-otx2_ree_iq_enable(const struct rte_regexdev *dev, const struct otx2_ree_qp *qp,\n-\t\t uint8_t pri, uint32_t size_div2)\n-{\n-\tunion otx2_ree_lf_sbuf_addr base;\n-\tunion otx2_ree_lf_ena lf_ena;\n-\n-\t/* Set instruction queue size and priority */\n-\totx2_ree_config_lf(dev, qp->id, pri, size_div2);\n-\n-\t/* Set instruction queue base address */\n-\t/* Should be written after SBUF_CTL and before LF_ENA */\n-\n-\tbase.u = otx2_read64(qp->base + OTX2_REE_LF_SBUF_ADDR);\n-\tbase.s.ptr = qp->iq_dma_addr >> 7;\n-\totx2_write64(base.u, qp->base + OTX2_REE_LF_SBUF_ADDR);\n-\n-\t/* Enable instruction queue */\n-\n-\tlf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);\n-\tlf_ena.s.ena = 1;\n-\totx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);\n-\n-\treturn 0;\n-}\n-\n-void\n-otx2_ree_iq_disable(struct otx2_ree_qp *qp)\n-{\n-\tunion otx2_ree_lf_ena lf_ena;\n-\n-\t/* Stop instruction execution */\n-\tlf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);\n-\tlf_ena.s.ena = 0x0;\n-\totx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);\n-}\n-\n-int\n-otx2_ree_max_matches_get(const struct rte_regexdev *dev, uint8_t *max_matches)\n-{\n-\tunion otx2_ree_af_reexm_max_match reexm_max_match;\n-\tint ret;\n-\n-\tret = otx2_ree_af_reg_read(dev, REE_AF_REEXM_MAX_MATCH,\n-\t\t\t\t &reexm_max_match.u);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t*max_matches = reexm_max_match.s.max;\n-\treturn 0;\n-}\ndiff --git a/drivers/regex/octeontx2/otx2_regexdev_hw_access.h b/drivers/regex/octeontx2/otx2_regexdev_hw_access.h\ndeleted file mode 100644\nindex dedf5f3282..0000000000\n--- a/drivers/regex/octeontx2/otx2_regexdev_hw_access.h\n+++ /dev/null\n@@ -1,202 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_REGEXDEV_HW_ACCESS_H_\n-#define _OTX2_REGEXDEV_HW_ACCESS_H_\n-\n-#include <stdint.h>\n-\n-#include \"otx2_regexdev.h\"\n-\n-/* REE instruction queue length */\n-#define OTX2_REE_IQ_LEN\t\t\t(1 << 13)\n-\n-#define OTX2_REE_DEFAULT_CMD_QLEN\tOTX2_REE_IQ_LEN\n-\n-/* Status register bits */\n-#define OTX2_REE_STATUS_PMI_EOJ_BIT\t\t(1 << 14)\n-#define OTX2_REE_STATUS_PMI_SOJ_BIT\t\t(1 << 13)\n-#define OTX2_REE_STATUS_MP_CNT_DET_BIT\t\t(1 << 7)\n-#define OTX2_REE_STATUS_MM_CNT_DET_BIT\t\t(1 << 6)\n-#define OTX2_REE_STATUS_ML_CNT_DET_BIT\t\t(1 << 5)\n-#define OTX2_REE_STATUS_MST_CNT_DET_BIT\t\t(1 << 4)\n-#define OTX2_REE_STATUS_MPT_CNT_DET_BIT\t\t(1 << 3)\n-\n-/* Register offsets */\n-/* REE LF registers */\n-#define OTX2_REE_LF_DONE_INT\t\t0x120ull\n-#define OTX2_REE_LF_DONE_INT_W1S\t0x130ull\n-#define OTX2_REE_LF_DONE_INT_ENA_W1S\t0x138ull\n-#define OTX2_REE_LF_DONE_INT_ENA_W1C\t0x140ull\n-#define OTX2_REE_LF_MISC_INT\t\t0x300ull\n-#define OTX2_REE_LF_MISC_INT_W1S\t0x310ull\n-#define OTX2_REE_LF_MISC_INT_ENA_W1S\t0x320ull\n-#define OTX2_REE_LF_MISC_INT_ENA_W1C\t0x330ull\n-#define OTX2_REE_LF_ENA\t\t\t0x10ull\n-#define OTX2_REE_LF_SBUF_ADDR\t\t0x20ull\n-#define OTX2_REE_LF_DONE\t\t0x100ull\n-#define OTX2_REE_LF_DONE_ACK\t\t0x110ull\n-#define OTX2_REE_LF_DONE_WAIT\t\t0x148ull\n-#define OTX2_REE_LF_DOORBELL\t\t0x400ull\n-#define OTX2_REE_LF_OUTSTAND_JOB\t0x410ull\n-\n-/* BAR 0 */\n-#define OTX2_REE_AF_QUE_SBUF_CTL(a)\t(0x1200ull | (uint64_t)(a) << 3)\n-#define OTX2_REE_PRIV_LF_CFG(a)\t\t(0x41000ull | (uint64_t)(a) << 3)\n-\n-#define OTX2_REE_LF_BAR2(vf, q_id) \\\n-\t\t((vf)->otx2_dev.bar2 + \\\n-\t\t (((vf)->block_address << 20) | ((q_id) << 12)))\n-\n-\n-#define OTX2_REE_QUEUE_HI_PRIO 0x1\n-\n-enum ree_desc_type_e {\n-\tREE_TYPE_JOB_DESC = 0x0,\n-\tREE_TYPE_RESULT_DESC = 0x1,\n-\tREE_TYPE_ENUM_LAST = 0x2\n-};\n-\n-union otx2_ree_priv_lf_cfg {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t slot : 8;\n-\t\tuint64_t pf_func : 16;\n-\t\tuint64_t reserved_24_62 : 39;\n-\t\tuint64_t ena : 1;\n-\t} s;\n-};\n-\n-\n-union otx2_ree_lf_sbuf_addr {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t off : 7;\n-\t\tuint64_t ptr : 46;\n-\t\tuint64_t reserved_53_63 : 11;\n-\t} s;\n-};\n-\n-union otx2_ree_lf_ena {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t ena : 1;\n-\t\tuint64_t reserved_1_63 : 63;\n-\t} s;\n-};\n-\n-union otx2_ree_af_reexm_max_match {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t max : 8;\n-\t\tuint64_t reserved_8_63 : 56;\n-\t} s;\n-};\n-\n-union otx2_ree_lf_done {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t done : 20;\n-\t\tuint64_t reserved_20_63 : 44;\n-\t} s;\n-};\n-\n-union otx2_ree_inst {\n-\tuint64_t u[8];\n-\tstruct {\n-\t\tuint64_t doneint : 1;\n-\t\tuint64_t reserved_1_3 : 3;\n-\t\tuint64_t dg : 1;\n-\t\tuint64_t reserved_5_7 : 3;\n-\t\tuint64_t ooj : 1;\n-\t\tuint64_t reserved_9_15 : 7;\n-\t\tuint64_t reserved_16_63 : 48;\n-\t\tuint64_t inp_ptr_addr : 64;\n-\t\tuint64_t inp_ptr_ctl : 64;\n-\t\tuint64_t res_ptr_addr : 64;\n-\t\tuint64_t wq_ptr : 64;\n-\t\tuint64_t tag : 32;\n-\t\tuint64_t tt : 2;\n-\t\tuint64_t ggrp : 10;\n-\t\tuint64_t reserved_364_383 : 20;\n-\t\tuint64_t reserved_384_391 : 8;\n-\t\tuint64_t ree_job_id : 24;\n-\t\tuint64_t ree_job_ctrl : 16;\n-\t\tuint64_t ree_job_length : 15;\n-\t\tuint64_t reserved_447_447 : 1;\n-\t\tuint64_t ree_job_subset_id_0 : 16;\n-\t\tuint64_t ree_job_subset_id_1 : 16;\n-\t\tuint64_t ree_job_subset_id_2 : 16;\n-\t\tuint64_t ree_job_subset_id_3 : 16;\n-\t} cn98xx;\n-};\n-\n-union otx2_ree_res_status {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t job_type : 3;\n-\t\tuint64_t mpt_cnt_det : 1;\n-\t\tuint64_t mst_cnt_det : 1;\n-\t\tuint64_t ml_cnt_det : 1;\n-\t\tuint64_t mm_cnt_det : 1;\n-\t\tuint64_t mp_cnt_det : 1;\n-\t\tuint64_t mode : 2;\n-\t\tuint64_t reserved_10_11 : 2;\n-\t\tuint64_t reserved_12_12 : 1;\n-\t\tuint64_t pmi_soj : 1;\n-\t\tuint64_t pmi_eoj : 1;\n-\t\tuint64_t reserved_15_15 : 1;\n-\t\tuint64_t reserved_16_63 : 48;\n-\t} s;\n-};\n-\n-union otx2_ree_res {\n-\tuint64_t u[8];\n-\tstruct ree_res_s_98 {\n-\t\tuint64_t done\t\t\t: 1;\n-\t\tuint64_t hwjid\t\t\t: 7;\n-\t\tuint64_t ree_res_job_id\t\t: 24;\n-\t\tuint64_t ree_res_status\t\t: 16;\n-\t\tuint64_t ree_res_dmcnt\t\t: 8;\n-\t\tuint64_t ree_res_mcnt\t\t: 8;\n-\t\tuint64_t ree_meta_ptcnt\t\t: 16;\n-\t\tuint64_t ree_meta_icnt\t\t: 16;\n-\t\tuint64_t ree_meta_lcnt\t\t: 16;\n-\t\tuint64_t ree_pmi_min_byte_ptr\t: 16;\n-\t\tuint64_t ree_err\t\t: 1;\n-\t\tuint64_t reserved_129_190\t: 62;\n-\t\tuint64_t doneint\t\t: 1;\n-\t\tuint64_t reserved_192_255\t: 64;\n-\t\tuint64_t reserved_256_319\t: 64;\n-\t\tuint64_t reserved_320_383\t: 64;\n-\t\tuint64_t reserved_384_447\t: 64;\n-\t\tuint64_t reserved_448_511\t: 64;\n-\t} s;\n-};\n-\n-union otx2_ree_match {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t ree_rule_id : 32;\n-\t\tuint64_t start_ptr : 14;\n-\t\tuint64_t reserved_46_47 : 2;\n-\t\tuint64_t match_length : 15;\n-\t\tuint64_t reserved_63_63 : 1;\n-\t} s;\n-};\n-\n-void otx2_ree_err_intr_unregister(const struct rte_regexdev *dev);\n-\n-int otx2_ree_err_intr_register(const struct rte_regexdev *dev);\n-\n-int otx2_ree_iq_enable(const struct rte_regexdev *dev,\n-\t\t const struct otx2_ree_qp *qp,\n-\t\t uint8_t pri, uint32_t size_div128);\n-\n-void otx2_ree_iq_disable(struct otx2_ree_qp *qp);\n-\n-int otx2_ree_max_matches_get(const struct rte_regexdev *dev,\n-\t\t\t uint8_t *max_matches);\n-\n-#endif /* _OTX2_REGEXDEV_HW_ACCESS_H_ */\ndiff --git a/drivers/regex/octeontx2/otx2_regexdev_mbox.c b/drivers/regex/octeontx2/otx2_regexdev_mbox.c\ndeleted file mode 100644\nindex 6d58d367d4..0000000000\n--- a/drivers/regex/octeontx2/otx2_regexdev_mbox.c\n+++ /dev/null\n@@ -1,401 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_dev.h\"\n-#include \"otx2_regexdev_mbox.h\"\n-#include \"otx2_regexdev.h\"\n-\n-int\n-otx2_ree_available_queues_get(const struct rte_regexdev *dev,\n-\t\t\t uint16_t *nb_queues)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tstruct free_rsrcs_rsp *rsp;\n-\tstruct otx2_dev *otx2_dev;\n-\tint ret;\n-\n-\totx2_dev = &vf->otx2_dev;\n-\totx2_mbox_alloc_msg_free_rsrc_cnt(otx2_dev->mbox);\n-\n-\tret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);\n-\tif (ret)\n-\t\treturn -EIO;\n-\n-\tif (vf->block_address == RVU_BLOCK_ADDR_REE0)\n-\t\t*nb_queues = rsp->ree0;\n-\telse\n-\t\t*nb_queues = rsp->ree1;\n-\treturn 0;\n-}\n-\n-int\n-otx2_ree_queues_attach(const struct rte_regexdev *dev, uint8_t nb_queues)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tstruct rsrc_attach_req *req;\n-\tstruct otx2_mbox *mbox;\n-\n-\t/* Ask AF to attach required LFs */\n-\tmbox = vf->otx2_dev.mbox;\n-\treq = otx2_mbox_alloc_msg_attach_resources(mbox);\n-\n-\t/* 1 LF = 1 queue */\n-\treq->reelfs = nb_queues;\n-\treq->ree_blkaddr = vf->block_address;\n-\n-\tif (otx2_mbox_process(mbox) < 0)\n-\t\treturn -EIO;\n-\n-\t/* Update number of attached queues */\n-\tvf->nb_queues = nb_queues;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_ree_queues_detach(const struct rte_regexdev *dev)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tstruct rsrc_detach_req *req;\n-\tstruct otx2_mbox *mbox;\n-\n-\tmbox = vf->otx2_dev.mbox;\n-\treq = otx2_mbox_alloc_msg_detach_resources(mbox);\n-\treq->reelfs = true;\n-\treq->partial = true;\n-\tif (otx2_mbox_process(mbox) < 0)\n-\t\treturn -EIO;\n-\n-\t/* Queues have been detached */\n-\tvf->nb_queues = 0;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_ree_msix_offsets_get(const struct rte_regexdev *dev)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tstruct msix_offset_rsp *rsp;\n-\tstruct otx2_mbox *mbox;\n-\tuint32_t i, ret;\n-\n-\t/* Get REE MSI-X vector offsets */\n-\tmbox = vf->otx2_dev.mbox;\n-\totx2_mbox_alloc_msg_msix_offset(mbox);\n-\n-\tret = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tfor (i = 0; i < vf->nb_queues; i++) {\n-\t\tif (vf->block_address == RVU_BLOCK_ADDR_REE0)\n-\t\t\tvf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];\n-\t\telse\n-\t\t\tvf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];\n-\t\totx2_ree_dbg(\"lf_msixoff[%d] 0x%x\", i, vf->lf_msixoff[i]);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-ree_send_mbox_msg(struct otx2_ree_vf *vf)\n-{\n-\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n-\tint ret;\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\n-\tret = otx2_mbox_wait_for_rsp(mbox, 0);\n-\tif (ret < 0) {\n-\t\totx2_err(\"Could not get mailbox response\");\n-\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_ree_config_lf(const struct rte_regexdev *dev, uint8_t lf, uint8_t pri,\n-\t\t uint32_t size)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tstruct ree_lf_req_msg *req;\n-\tstruct otx2_mbox *mbox;\n-\tint ret;\n-\n-\tmbox = vf->otx2_dev.mbox;\n-\treq = otx2_mbox_alloc_msg_ree_config_lf(mbox);\n-\n-\treq->lf = lf;\n-\treq->pri = pri ? 1 : 0;\n-\treq->size = size;\n-\treq->blkaddr = vf->block_address;\n-\n-\tret = otx2_mbox_process(mbox);\n-\tif (ret < 0) {\n-\t\totx2_err(\"Could not get mailbox response\");\n-\t\treturn ret;\n-\t}\n-\treturn 0;\n-}\n-\n-int\n-otx2_ree_af_reg_read(const struct rte_regexdev *dev, uint64_t reg,\n-\t\t uint64_t *val)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tstruct ree_rd_wr_reg_msg *msg;\n-\tstruct otx2_mbox_dev *mdev;\n-\tstruct otx2_mbox *mbox;\n-\tint ret, off;\n-\n-\tmbox = vf->otx2_dev.mbox;\n-\tmdev = &mbox->dev[0];\n-\tmsg = (struct ree_rd_wr_reg_msg *)otx2_mbox_alloc_msg_rsp(mbox, 0,\n-\t\t\t\t\t\tsizeof(*msg), sizeof(*msg));\n-\tif (msg == NULL) {\n-\t\totx2_err(\"Could not allocate mailbox message\");\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tmsg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;\n-\tmsg->hdr.sig = OTX2_MBOX_REQ_SIG;\n-\tmsg->hdr.pcifunc = vf->otx2_dev.pf_func;\n-\tmsg->is_write = 0;\n-\tmsg->reg_offset = reg;\n-\tmsg->ret_val = val;\n-\tmsg->blkaddr = vf->block_address;\n-\n-\tret = ree_send_mbox_msg(vf);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\toff = mbox->rx_start +\n-\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n-\tmsg = (struct ree_rd_wr_reg_msg *) ((uintptr_t)mdev->mbase + off);\n-\n-\t*val = msg->val;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_ree_af_reg_write(const struct rte_regexdev *dev, uint64_t reg,\n-\t\t uint64_t val)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tstruct ree_rd_wr_reg_msg *msg;\n-\tstruct otx2_mbox *mbox;\n-\n-\tmbox = vf->otx2_dev.mbox;\n-\tmsg = (struct ree_rd_wr_reg_msg *)otx2_mbox_alloc_msg_rsp(mbox, 0,\n-\t\t\t\t\t\tsizeof(*msg), sizeof(*msg));\n-\tif (msg == NULL) {\n-\t\totx2_err(\"Could not allocate mailbox message\");\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tmsg->hdr.id = MBOX_MSG_REE_RD_WR_REGISTER;\n-\tmsg->hdr.sig = OTX2_MBOX_REQ_SIG;\n-\tmsg->hdr.pcifunc = vf->otx2_dev.pf_func;\n-\tmsg->is_write = 1;\n-\tmsg->reg_offset = reg;\n-\tmsg->val = val;\n-\tmsg->blkaddr = vf->block_address;\n-\n-\treturn ree_send_mbox_msg(vf);\n-}\n-\n-int\n-otx2_ree_rule_db_get(const struct rte_regexdev *dev, char *rule_db,\n-\t\tuint32_t rule_db_len, char *rule_dbi, uint32_t rule_dbi_len)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct ree_rule_db_get_req_msg *req;\n-\tstruct ree_rule_db_get_rsp_msg *rsp;\n-\tchar *rule_db_ptr = (char *)rule_db;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tstruct otx2_mbox *mbox;\n-\tint ret, last = 0;\n-\tuint32_t len = 0;\n-\n-\tmbox = vf->otx2_dev.mbox;\n-\tif (!rule_db) {\n-\t\totx2_err(\"Couldn't return rule db due to NULL pointer\");\n-\t\treturn -EFAULT;\n-\t}\n-\n-\twhile (!last) {\n-\t\treq = (struct ree_rule_db_get_req_msg *)\n-\t\t\totx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),\n-\t\t\t\t\t\tsizeof(*rsp));\n-\t\tif (!req) {\n-\t\t\totx2_err(\"Could not allocate mailbox message\");\n-\t\t\treturn -EFAULT;\n-\t\t}\n-\n-\t\treq->hdr.id = MBOX_MSG_REE_RULE_DB_GET;\n-\t\treq->hdr.sig = OTX2_MBOX_REQ_SIG;\n-\t\treq->hdr.pcifunc = vf->otx2_dev.pf_func;\n-\t\treq->blkaddr = vf->block_address;\n-\t\treq->is_dbi = 0;\n-\t\treq->offset = len;\n-\t\tret = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t\tif (rule_db_len < len + rsp->len) {\n-\t\t\totx2_err(\"Rule db size is too small\");\n-\t\t\treturn -EFAULT;\n-\t\t}\n-\t\totx2_mbox_memcpy(rule_db_ptr, rsp->rule_db, rsp->len);\n-\t\tlen += rsp->len;\n-\t\trule_db_ptr = rule_db_ptr + rsp->len;\n-\t\tlast = rsp->is_last;\n-\t}\n-\n-\tif (rule_dbi) {\n-\t\treq = (struct ree_rule_db_get_req_msg *)\n-\t\t\totx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),\n-\t\t\t\t\t\tsizeof(*rsp));\n-\t\tif (!req) {\n-\t\t\totx2_err(\"Could not allocate mailbox message\");\n-\t\t\treturn -EFAULT;\n-\t\t}\n-\n-\t\treq->hdr.id = MBOX_MSG_REE_RULE_DB_GET;\n-\t\treq->hdr.sig = OTX2_MBOX_REQ_SIG;\n-\t\treq->hdr.pcifunc = vf->otx2_dev.pf_func;\n-\t\treq->blkaddr = vf->block_address;\n-\t\treq->is_dbi = 1;\n-\t\treq->offset = 0;\n-\n-\t\tret = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t\tif (rule_dbi_len < rsp->len) {\n-\t\t\totx2_err(\"Rule dbi size is too small\");\n-\t\t\treturn -EFAULT;\n-\t\t}\n-\t\totx2_mbox_memcpy(rule_dbi, rsp->rule_db, rsp->len);\n-\t}\n-\treturn 0;\n-}\n-\n-int\n-otx2_ree_rule_db_len_get(const struct rte_regexdev *dev,\n-\t\tuint32_t *rule_db_len,\n-\t\tuint32_t *rule_dbi_len)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tstruct ree_rule_db_len_rsp_msg *rsp;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tstruct ree_req_msg *req;\n-\tstruct otx2_mbox *mbox;\n-\tint ret;\n-\n-\tmbox = vf->otx2_dev.mbox;\n-\treq = (struct ree_req_msg *)\n-\t\totx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req), sizeof(*rsp));\n-\tif (!req) {\n-\t\totx2_err(\"Could not allocate mailbox message\");\n-\t\treturn -EFAULT;\n-\t}\n-\n-\treq->hdr.id = MBOX_MSG_REE_RULE_DB_LEN_GET;\n-\treq->hdr.sig = OTX2_MBOX_REQ_SIG;\n-\treq->hdr.pcifunc = vf->otx2_dev.pf_func;\n-\treq->blkaddr = vf->block_address;\n-\tret = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (ret)\n-\t\treturn ret;\n-\tif (rule_db_len != NULL)\n-\t\t*rule_db_len = rsp->len;\n-\tif (rule_dbi_len != NULL)\n-\t\t*rule_dbi_len = rsp->inc_len;\n-\n-\treturn 0;\n-}\n-\n-static int\n-ree_db_msg(const struct rte_regexdev *dev, const char *db, uint32_t db_len,\n-\t\tint inc, int dbi)\n-{\n-\tstruct otx2_ree_data *data = dev->data->dev_private;\n-\tuint32_t len_left = db_len, offset = 0;\n-\tstruct ree_rule_db_prog_req_msg *req;\n-\tstruct otx2_ree_vf *vf = &data->vf;\n-\tconst char *rule_db_ptr = db;\n-\tstruct otx2_mbox *mbox;\n-\tstruct msg_rsp *rsp;\n-\tint ret;\n-\n-\tmbox = vf->otx2_dev.mbox;\n-\twhile (len_left) {\n-\t\treq = (struct ree_rule_db_prog_req_msg *)\n-\t\t\totx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),\n-\t\t\t\t\t\tsizeof(*rsp));\n-\t\tif (!req) {\n-\t\t\totx2_err(\"Could not allocate mailbox message\");\n-\t\t\treturn -EFAULT;\n-\t\t}\n-\t\treq->hdr.id = MBOX_MSG_REE_RULE_DB_PROG;\n-\t\treq->hdr.sig = OTX2_MBOX_REQ_SIG;\n-\t\treq->hdr.pcifunc = vf->otx2_dev.pf_func;\n-\t\treq->offset = offset;\n-\t\treq->total_len = db_len;\n-\t\treq->len = REE_RULE_DB_REQ_BLOCK_SIZE;\n-\t\treq->is_incremental = inc;\n-\t\treq->is_dbi = dbi;\n-\t\treq->blkaddr = vf->block_address;\n-\n-\t\tif (len_left < REE_RULE_DB_REQ_BLOCK_SIZE) {\n-\t\t\treq->is_last = true;\n-\t\t\treq->len = len_left;\n-\t\t}\n-\t\totx2_mbox_memcpy(req->rule_db, rule_db_ptr, req->len);\n-\t\tret = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (ret) {\n-\t\t\totx2_err(\"Programming mailbox processing failed\");\n-\t\t\treturn ret;\n-\t\t}\n-\t\tlen_left -= req->len;\n-\t\toffset += req->len;\n-\t\trule_db_ptr = rule_db_ptr + req->len;\n-\t}\n-\treturn 0;\n-}\n-\n-int\n-otx2_ree_rule_db_prog(const struct rte_regexdev *dev, const char *rule_db,\n-\t\tuint32_t rule_db_len, const char *rule_dbi,\n-\t\tuint32_t rule_dbi_len)\n-{\n-\tint inc, ret;\n-\n-\tif (rule_db_len == 0) {\n-\t\totx2_err(\"Couldn't program empty rule db\");\n-\t\treturn -EFAULT;\n-\t}\n-\tinc = (rule_dbi_len != 0);\n-\tif ((rule_db == NULL) || (inc && (rule_dbi == NULL))) {\n-\t\totx2_err(\"Couldn't program NULL rule db\");\n-\t\treturn -EFAULT;\n-\t}\n-\tif (inc) {\n-\t\tret = ree_db_msg(dev, rule_dbi, rule_dbi_len, inc, 1);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\treturn ree_db_msg(dev, rule_db, rule_db_len, inc, 0);\n-}\ndiff --git a/drivers/regex/octeontx2/otx2_regexdev_mbox.h b/drivers/regex/octeontx2/otx2_regexdev_mbox.h\ndeleted file mode 100644\nindex 953efa6724..0000000000\n--- a/drivers/regex/octeontx2/otx2_regexdev_mbox.h\n+++ /dev/null\n@@ -1,38 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_REGEXDEV_MBOX_H_\n-#define _OTX2_REGEXDEV_MBOX_H_\n-\n-#include <rte_regexdev.h>\n-\n-int otx2_ree_available_queues_get(const struct rte_regexdev *dev,\n-\t\t\t\t uint16_t *nb_queues);\n-\n-int otx2_ree_queues_attach(const struct rte_regexdev *dev, uint8_t nb_queues);\n-\n-int otx2_ree_queues_detach(const struct rte_regexdev *dev);\n-\n-int otx2_ree_msix_offsets_get(const struct rte_regexdev *dev);\n-\n-int otx2_ree_config_lf(const struct rte_regexdev *dev, uint8_t lf, uint8_t pri,\n-\t\t uint32_t size);\n-\n-int otx2_ree_af_reg_read(const struct rte_regexdev *dev, uint64_t reg,\n-\t\t\t uint64_t *val);\n-\n-int otx2_ree_af_reg_write(const struct rte_regexdev *dev, uint64_t reg,\n-\t\t\t uint64_t val);\n-\n-int otx2_ree_rule_db_get(const struct rte_regexdev *dev, char *rule_db,\n-\t\t uint32_t rule_db_len, char *rule_dbi, uint32_t rule_dbi_len);\n-\n-int otx2_ree_rule_db_len_get(const struct rte_regexdev *dev,\n-\t\t\t uint32_t *rule_db_len, uint32_t *rule_dbi_len);\n-\n-int otx2_ree_rule_db_prog(const struct rte_regexdev *dev, const char *rule_db,\n-\t\tuint32_t rule_db_len, const char *rule_dbi,\n-\t\tuint32_t rule_dbi_len);\n-\n-#endif /* _OTX2_REGEXDEV_MBOX_H_ */\n", "prefixes": [ "v4", "4/4" ] }