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GET /api/patches/105550/?format=api
{ "id": 105550, "url": "http://patchwork.dpdk.org/api/patches/105550/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220103055709.82768-3-psatheesh@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220103055709.82768-3-psatheesh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220103055709.82768-3-psatheesh@marvell.com", "date": "2022-01-03T05:57:08", "name": "[3/4] common/cnxk: support matching VLAN existence in RTE Flow", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "02a3c50665a8934bf3292e95a4a5f09cc8d374ce", "submitter": { "id": 1663, "url": "http://patchwork.dpdk.org/api/people/1663/?format=api", "name": "Satheesh Paul Antonysamy", "email": "psatheesh@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220103055709.82768-3-psatheesh@marvell.com/mbox/", "series": [ { "id": 21047, "url": "http://patchwork.dpdk.org/api/series/21047/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21047", "date": "2022-01-03T05:57:06", "name": "[1/4] drivers: add support for switch header type pre L2", "version": 1, "mbox": "http://patchwork.dpdk.org/series/21047/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/105550/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/105550/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F1C6BA0350;\n\tMon, 3 Jan 2022 06:57:44 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5AD2441147;\n\tMon, 3 Jan 2022 06:57:41 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 3E45C4069F\n for <dev@dpdk.org>; Mon, 3 Jan 2022 06:57:38 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 202MENtt027084\n for <dev@dpdk.org>; Sun, 2 Jan 2022 21:57:37 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3daqbrkxwh-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 02 Jan 2022 21:57:37 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sun, 2 Jan 2022 21:57:29 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sun, 2 Jan 2022 21:57:29 -0800", "from localhost.localdomain (unknown [10.28.34.33])\n by maili.marvell.com (Postfix) with ESMTP id A61D53F7051;\n Sun, 2 Jan 2022 21:57:27 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=Yyy3Ht8O0j0RjJtdIJ8dY4Ea0Zn9TSOYT/L3TEVBTX0=;\n b=Y55cI/oZ0mKbUfMvLPlf7M8GpsM+XKqv/5ruP4OCpXKzHQ1/hsx2ugmr15f1QnnC4Z9c\n s75NfZhWeqyhKpB9rKDVilo3M7R+9eioc7j7yMw9TmsYD2zGVrjNI5lSxdzakO6daPMk\n gnwqdpyp8bDxT5E6196sgE9mm0xxhwt0kIAL321DPkf51XMS7254rXFEmqlItlH+f1Cq\n BAhbQQrxA8UJFv8vrkZ+WDFHsy35LWciXtJZ914xJcpv+C9Mxlm3O8Cj3nQQUroBABDP\n IxBOojiuIzN7U31W+YXchAwZj/8Pu4ZHGJLUdzcBu3haF9xe3Tx2lDf5dxcCAxlfcdVS rg==", "From": "<psatheesh@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Satheesh Paul <psatheesh@marvell.com>,\n sa_ip-toolkits-Jenkins <sa_ip-toolkits-jenkins@marvell.com>", "Subject": "[dpdk-dev] [PATCH 3/4] common/cnxk: support matching VLAN existence\n in RTE Flow", "Date": "Mon, 3 Jan 2022 11:27:08 +0530", "Message-ID": "<20220103055709.82768-3-psatheesh@marvell.com>", "X-Mailer": "git-send-email 2.25.4", "In-Reply-To": "<20220103055709.82768-1-psatheesh@marvell.com>", "References": "<20220103055709.82768-1-psatheesh@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "SL9dDI39sR91VrNcDZWBHo33cbehCA2_", "X-Proofpoint-ORIG-GUID": "SL9dDI39sR91VrNcDZWBHo33cbehCA2_", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-01-03_02,2022-01-01_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Satheesh Paul <psatheesh@marvell.com>\n\nSupport matching existence of VLAN after\nRTE_FLOW_ITEM_TYPE_ETH and RTE_FLOW_ITEM_TYPE_VLAN items.\n\nci: skip_checkformat\n\nSigned-off-by: Satheesh Paul <psatheesh@marvell.com>\nChange-Id: Ieebeaee5f13e58e7db20a171ea878bb33ddd57bb\nReviewed-on: https://sj1git1.cavium.com/c/IP/SW/dataplane/dpdk/+/67088\nTested-by: sa_ip-toolkits-Jenkins <sa_ip-toolkits-jenkins@marvell.com>\nReviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>\n---\n drivers/common/cnxk/roc_npc.h | 58 ++++++++++++++++++++++++++++-\n drivers/common/cnxk/roc_npc_mcam.c | 37 ++++++++++++++++--\n drivers/common/cnxk/roc_npc_parse.c | 56 +++++++++++++++++++++++++---\n drivers/common/cnxk/roc_npc_priv.h | 7 ++++\n drivers/common/cnxk/roc_platform.h | 6 ++-\n 5 files changed, 151 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h\nindex 8b57678863..634c67e6f6 100644\n--- a/drivers/common/cnxk/roc_npc.h\n+++ b/drivers/common/cnxk/roc_npc.h\n@@ -58,6 +58,60 @@ struct roc_npc_flow_item_raw {\n \tconst uint8_t *pattern; /**< Byte string to look for. */\n };\n \n+struct roc_ether_addr {\n+\tuint8_t addr_bytes[PLT_ETHER_ADDR_LEN]; /**< Addr bytes in tx order */\n+} __plt_aligned(2);\n+\n+struct roc_ether_hdr {\n+\tstruct roc_ether_addr d_addr; /**< Destination address. */\n+\tPLT_STD_C11\n+\tunion {\n+\t\tstruct roc_ether_addr s_addr; /**< Source address. */\n+\t\tstruct {\n+\t\t\tstruct roc_ether_addr S_addr;\n+\t\t} S_un; /**< Do not use directly; use s_addr instead.*/\n+\t};\n+\tuint16_t ether_type; /**< Frame type. */\n+} __plt_aligned(2);\n+\n+PLT_STD_C11\n+struct roc_npc_flow_item_eth {\n+\tunion {\n+\t\tstruct {\n+\t\t\t/*\n+\t\t\t * These fields are retained\n+\t\t\t * for compatibility.\n+\t\t\t * Please switch to the new header field below.\n+\t\t\t */\n+\t\t\tstruct roc_ether_addr dst; /**< Destination MAC. */\n+\t\t\tstruct roc_ether_addr src; /**< Source MAC. */\n+\t\t\tuint16_t type;\t\t /**< EtherType or TPID. */\n+\t\t};\n+\t\tstruct roc_ether_hdr hdr;\n+\t};\n+\tuint32_t has_vlan : 1; /**< Packet header contains at least one VLAN. */\n+\tuint32_t reserved : 31; /**< Reserved, must be zero. */\n+};\n+\n+struct roc_vlan_hdr {\n+\tuint16_t vlan_tci; /**< Priority (3) + CFI (1) + Identifier Code (12) */\n+\tuint16_t eth_proto; /**< Ethernet type of encapsulated frame. */\n+} __plt_packed;\n+\n+PLT_STD_C11\n+struct roc_npc_flow_item_vlan {\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint16_t tci;\t /**< Tag control information. */\n+\t\t\tuint16_t inner_type; /**< Inner EtherType or TPID. */\n+\t\t};\n+\t\tstruct roc_vlan_hdr hdr;\n+\t};\n+\tuint32_t has_more_vlan : 1;\n+\t/**< Packet header contains at least one more VLAN, after this VLAN. */\n+\tuint32_t reserved : 31; /**< Reserved, must be zero. */\n+};\n+\n #define ROC_NPC_MAX_ACTION_COUNT 19\n \n enum roc_npc_action_type {\n@@ -97,7 +151,7 @@ struct roc_npc_action_vf {\n };\n \n struct roc_npc_action_port_id {\n-\tuint32_t original : 1;\t/**< Use original DPDK port ID if possible. */\n+\tuint32_t original : 1;\t/**< Use original port ID if possible. */\n \tuint32_t reserved : 31; /**< Reserved, must be zero. */\n \tuint32_t id;\t\t/**< port ID. */\n };\n@@ -167,7 +221,7 @@ enum roc_npc_rss_hash_function {\n struct roc_npc_action_rss {\n \tenum roc_npc_rss_hash_function func;\n \tuint32_t level;\n-\tuint64_t types;\t /**< Specific RSS hash types (see RTE_ETH_RSS_*). */\n+\tuint64_t types;\t /**< Specific RSS hash types (see ETH_RSS_*). */\n \tuint32_t key_len; /**< Hash key length in bytes. */\n \tuint32_t queue_num; /**< Number of entries in @p queue. */\n \tconst uint8_t *key; /**< Hash key. */\ndiff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c\nindex 80851d6f9f..2349317c5c 100644\n--- a/drivers/common/cnxk/roc_npc_mcam.c\n+++ b/drivers/common/cnxk/roc_npc_mcam.c\n@@ -613,6 +613,28 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,\n \treturn 0;\n }\n \n+static void\n+npc_set_vlan_ltype(struct npc_parse_state *pst)\n+{\n+\tuint64_t val, mask;\n+\tuint8_t lb_offset;\n+\n+\tlb_offset =\n+\t\t__builtin_popcount(pst->npc->keyx_supp_nmask[pst->nix_intf] &\n+\t\t\t\t ((1ULL << NPC_LTYPE_LB_OFFSET) - 1));\n+\tlb_offset *= 4;\n+\n+\tmask = ~((0xfULL << lb_offset));\n+\tpst->flow->mcam_data[0] &= mask;\n+\tpst->flow->mcam_mask[0] &= mask;\n+\t/* NPC_LT_LB_CTAG: 0b0010, NPC_LT_LB_STAG_QINQ: 0b0011\n+\t * Set LB layertype/mask as 0b0010/0b1110 to match both.\n+\t */\n+\tval = ((uint64_t)(NPC_LT_LB_CTAG & NPC_LT_LB_STAG_QINQ)) << lb_offset;\n+\tpst->flow->mcam_data[0] |= val;\n+\tpst->flow->mcam_mask[0] |= (0xeULL << lb_offset);\n+}\n+\n int\n npc_program_mcam(struct npc *npc, struct npc_parse_state *pst, bool mcam_alloc)\n {\n@@ -651,12 +673,16 @@ npc_program_mcam(struct npc *npc, struct npc_parse_state *pst, bool mcam_alloc)\n \t\tif (layer_info) {\n \t\t\tfor (idx = 0; idx <= 2; idx++) {\n \t\t\t\tif (layer_info & (1 << idx)) {\n-\t\t\t\t\tif (idx == 2)\n+\t\t\t\t\tif (idx == 2) {\n \t\t\t\t\t\tdata = lt;\n-\t\t\t\t\telse if (idx == 1)\n+\t\t\t\t\t\tmask = 0xf;\n+\t\t\t\t\t} else if (idx == 1) {\n \t\t\t\t\t\tdata = ((flags >> 4) & 0xf);\n-\t\t\t\t\telse\n+\t\t\t\t\t\tmask = ((flags >> 4) & 0xf);\n+\t\t\t\t\t} else {\n \t\t\t\t\t\tdata = (flags & 0xf);\n+\t\t\t\t\t\tmask = (flags & 0xf);\n+\t\t\t\t\t}\n \n \t\t\t\t\tif (data_off >= 64) {\n \t\t\t\t\t\tdata_off = 0;\n@@ -664,7 +690,7 @@ npc_program_mcam(struct npc *npc, struct npc_parse_state *pst, bool mcam_alloc)\n \t\t\t\t\t}\n \t\t\t\t\tkey_data[index] |=\n \t\t\t\t\t\t((uint64_t)data << data_off);\n-\t\t\t\t\tmask = 0xf;\n+\n \t\t\t\t\tif (lt == 0)\n \t\t\t\t\t\tmask = 0;\n \t\t\t\t\tkey_mask[index] |=\n@@ -680,6 +706,9 @@ npc_program_mcam(struct npc *npc, struct npc_parse_state *pst, bool mcam_alloc)\n \tmemcpy(pst->flow->mcam_data, key_data, key_len);\n \tmemcpy(pst->flow->mcam_mask, key_mask, key_len);\n \n+\tif (pst->set_vlan_ltype_mask)\n+\t\tnpc_set_vlan_ltype(pst);\n+\n \tif (pst->is_vf) {\n \t\t(void)mbox_alloc_msg_npc_read_base_steer_rule(npc->mbox);\n \t\trc = mbox_process_msg(npc->mbox, (void *)&base_rule_rsp);\ndiff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c\nindex c9ab9aef28..75724661da 100644\n--- a/drivers/common/cnxk/roc_npc_parse.c\n+++ b/drivers/common/cnxk/roc_npc_parse.c\n@@ -167,6 +167,7 @@ npc_parse_higig2_hdr(struct npc_parse_state *pst)\n int\n npc_parse_la(struct npc_parse_state *pst)\n {\n+\tconst struct roc_npc_flow_item_eth *eth_item;\n \tuint8_t hw_mask[NPC_MAX_EXTRACT_HW_LEN];\n \tstruct npc_parse_item_info info;\n \tint lid, lt;\n@@ -176,6 +177,8 @@ npc_parse_la(struct npc_parse_state *pst)\n \tif (pst->pattern->type != ROC_NPC_ITEM_TYPE_ETH)\n \t\treturn 0;\n \n+\teth_item = pst->pattern->spec;\n+\n \tlid = NPC_LID_LA;\n \tlt = NPC_LT_LA_ETHER;\n \tinfo.hw_hdr_len = 0;\n@@ -196,7 +199,7 @@ npc_parse_la(struct npc_parse_state *pst)\n \n \t/* Prepare for parsing the item */\n \tinfo.hw_mask = &hw_mask;\n-\tinfo.len = pst->pattern->size;\n+\tinfo.len = sizeof(eth_item->hdr);\n \tnpc_get_hw_supp_mask(pst, &info, lid, lt);\n \tinfo.spec = NULL;\n \tinfo.mask = NULL;\n@@ -206,13 +209,22 @@ npc_parse_la(struct npc_parse_state *pst)\n \tif (rc)\n \t\treturn rc;\n \n-\t/* Update pst if not validate only? clash check? */\n-\treturn npc_update_parse_state(pst, &info, lid, lt, 0);\n+\trc = npc_update_parse_state(pst, &info, lid, lt, 0);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (eth_item && eth_item->has_vlan)\n+\t\tpst->set_vlan_ltype_mask = true;\n+\n+\treturn 0;\n }\n \n+#define NPC_MAX_SUPPORTED_VLANS 3\n+\n int\n npc_parse_lb(struct npc_parse_state *pst)\n {\n+\tconst struct roc_npc_flow_item_vlan *vlan_item[NPC_MAX_SUPPORTED_VLANS];\n \tconst struct roc_npc_item_info *pattern = pst->pattern;\n \tconst struct roc_npc_item_info *last_pattern;\n \tconst struct roc_npc_flow_item_raw *raw_spec;\n@@ -240,10 +252,14 @@ npc_parse_lb(struct npc_parse_state *pst)\n \t\t * supported on first tag only.\n \t\t */\n \t\tinfo.hw_mask = NULL;\n-\t\tinfo.len = pst->pattern->size;\n+\t\tinfo.len = sizeof(vlan_item[0]->hdr);\n \n \t\tpattern = pst->pattern;\n \t\twhile (pattern->type == ROC_NPC_ITEM_TYPE_VLAN) {\n+\t\t\tif (nr_vlans > NPC_MAX_SUPPORTED_VLANS - 1)\n+\t\t\t\treturn NPC_ERR_PATTERN_NOTSUP;\n+\n+\t\t\tvlan_item[nr_vlans] = pattern->spec;\n \t\t\tnr_vlans++;\n \n \t\t\t/* Basic validation of Second/Third vlan item */\n@@ -260,12 +276,35 @@ npc_parse_lb(struct npc_parse_state *pst)\n \t\tswitch (nr_vlans) {\n \t\tcase 1:\n \t\t\tlt = NPC_LT_LB_CTAG;\n+\t\t\tif (vlan_item[0] && vlan_item[0]->has_more_vlan)\n+\t\t\t\tlt = NPC_LT_LB_STAG_QINQ;\n \t\t\tbreak;\n \t\tcase 2:\n+\t\t\tif (vlan_item[1] && vlan_item[1]->has_more_vlan) {\n+\t\t\t\tif (!(pst->npc->keyx_supp_nmask[pst->nix_intf] &\n+\t\t\t\t 0x3ULL << NPC_LFLAG_LB_OFFSET))\n+\t\t\t\t\treturn NPC_ERR_PATTERN_NOTSUP;\n+\n+\t\t\t\t/* This lflag value will match either one of\n+\t\t\t\t * NPC_F_LB_L_WITH_STAG_STAG,\n+\t\t\t\t * NPC_F_LB_L_WITH_QINQ_CTAG,\n+\t\t\t\t * NPC_F_LB_L_WITH_QINQ_QINQ and\n+\t\t\t\t * NPC_F_LB_L_WITH_ITAG (0b0100 to 0b0111). For\n+\t\t\t\t * NPC_F_LB_L_WITH_ITAG, ltype is NPC_LT_LB_ETAG\n+\t\t\t\t * hence will not match.\n+\t\t\t\t */\n+\n+\t\t\t\tlflags = NPC_F_LB_L_WITH_QINQ_CTAG &\n+\t\t\t\t\t NPC_F_LB_L_WITH_QINQ_QINQ &\n+\t\t\t\t\t NPC_F_LB_L_WITH_STAG_STAG;\n+\t\t\t} else {\n+\t\t\t\tlflags = NPC_F_LB_L_WITH_CTAG;\n+\t\t\t}\n \t\t\tlt = NPC_LT_LB_STAG_QINQ;\n-\t\t\tlflags = NPC_F_STAG_CTAG;\n \t\t\tbreak;\n \t\tcase 3:\n+\t\t\tif (vlan_item[2] && vlan_item[2]->has_more_vlan)\n+\t\t\t\treturn NPC_ERR_PATTERN_NOTSUP;\n \t\t\tlt = NPC_LT_LB_STAG_QINQ;\n \t\t\tlflags = NPC_F_STAG_STAG_CTAG;\n \t\t\tbreak;\n@@ -294,10 +333,15 @@ npc_parse_lb(struct npc_parse_state *pst)\n \t\t}\n \t\tinfo.len = pattern->size;\n \t} else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_QINQ) {\n+\t\tvlan_item[0] = pst->pattern->spec;\n \t\tinfo.hw_mask = NULL;\n-\t\tinfo.len = pst->pattern->size;\n+\t\tinfo.len = sizeof(vlan_item[0]->hdr);\n \t\tlt = NPC_LT_LB_STAG_QINQ;\n \t\tlflags = NPC_F_STAG_CTAG;\n+\t\tif (vlan_item[0] && vlan_item[0]->has_more_vlan) {\n+\t\t\tlflags = NPC_F_LB_L_WITH_QINQ_CTAG &\n+\t\t\t\t NPC_F_LB_L_WITH_QINQ_QINQ;\n+\t\t}\n \t} else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_RAW) {\n \t\traw_spec = pst->pattern->spec;\n \t\tif (raw_spec->relative)\ndiff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h\nindex 1a40192599..ef7985f4cf 100644\n--- a/drivers/common/cnxk/roc_npc_priv.h\n+++ b/drivers/common/cnxk/roc_npc_priv.h\n@@ -67,6 +67,11 @@\n #define NPC_ACTION_MAX_VLAN_PARAMS 3\n #define NPC_ACTION_MAX_VLANS_STRIPPED 2\n \n+#define NPC_LTYPE_OFFSET_START 7\n+/* LB OFFSET : START + LA (2b flags + 1b ltype) + LB (2b flags) */\n+#define NPC_LTYPE_LB_OFFSET (NPC_LTYPE_OFFSET_START + 5)\n+#define NPC_LFLAG_LB_OFFSET (NPC_LTYPE_OFFSET_START + 3)\n+\n struct npc_action_vtag_info {\n \tuint16_t vlan_id;\n \tuint16_t vlan_ethtype;\n@@ -176,6 +181,8 @@ struct npc_parse_state {\n \tuint8_t *mcam_data; /* point to flow->mcam_data + key_len */\n \tuint8_t *mcam_mask; /* point to flow->mcam_mask + key_len */\n \tbool is_vf;\n+\t/* adjust ltype in MCAM to match at least one vlan */\n+\tbool set_vlan_ltype_mask;\n };\n \n enum npc_kpu_parser_flag {\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 61d4781209..7eecb365bf 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -11,6 +11,7 @@\n #include <rte_byteorder.h>\n #include <rte_common.h>\n #include <rte_cycles.h>\n+#include <rte_ether.h>\n #include <rte_interrupts.h>\n #include <rte_io.h>\n #include <rte_log.h>\n@@ -53,7 +54,9 @@\n #define BITMASK_ULL\t\t GENMASK_ULL\n #define PLT_ALIGN_CEIL\t\t RTE_ALIGN_CEIL\n #define PLT_INIT\t\t RTE_INIT\n-\n+#ifndef PLT_ETHER_ADDR_LEN\n+#define PLT_ETHER_ADDR_LEN RTE_ETHER_ADDR_LEN\n+#endif\n /** Divide ceil */\n #define PLT_DIV_CEIL(x, y)\t\t\t\\\n \t({\t\t\t\t\t\\\n@@ -62,6 +65,7 @@\n \t\t(__x + __y - 1) / __y;\t\t\\\n \t})\n \n+#define __plt_aligned\t __rte_aligned\n #define __plt_cache_aligned __rte_cache_aligned\n #define __plt_always_inline __rte_always_inline\n #define __plt_packed\t __rte_packed\n", "prefixes": [ "3/4" ] }