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GET /api/patches/106951/?format=api
{ "id": 106951, "url": "http://patchwork.dpdk.org/api/patches/106951/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220207072932.22409-19-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220207072932.22409-19-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220207072932.22409-19-ndabilpuram@marvell.com", "date": "2022-02-07T07:29:31", "name": "[19/20] net/cnxk: add dev args for min-max spi", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "047db1f1068e69ef4755880c7d69b9a5aba0cec7", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220207072932.22409-19-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 21483, "url": "http://patchwork.dpdk.org/api/series/21483/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21483", "date": "2022-02-07T07:29:13", "name": "[01/20] common/cnxk: increase resource count for bitmap alloc", "version": 1, "mbox": "http://patchwork.dpdk.org/series/21483/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/106951/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/106951/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A39ABA034F;\n\tMon, 7 Feb 2022 08:32:18 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 617FC41154;\n\tMon, 7 Feb 2022 08:30:51 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id A5A2241140\n for <dev@dpdk.org>; Mon, 7 Feb 2022 08:30:49 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 216KkLS2010691;\n Sun, 6 Feb 2022 23:30:42 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e1smr4p6w-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sun, 06 Feb 2022 23:30:42 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sun, 6 Feb 2022 23:30:39 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sun, 6 Feb 2022 23:30:39 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 8CA133F7068;\n Sun, 6 Feb 2022 23:30:37 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=BkjF+RWYAejSAwD1zNby8yKSuuC92qFybRSdyvLCJDM=;\n b=MbgWwKOhW+YGdgg+tlTWdlG6k/cCy5xNGPef0vKDul84O4vnpG7UrQozu4+C7lq+GUcK\n 9lF8C5HAUmff0YnTjONbxsl97/FvyRKlR9Fzs2rc1SwqKdjq9pWSzY2TseE1vLCthFJu\n GnVYJtDYcZeFRPPUEeV0kJLjztxm6g4iNC/8F/6R1J/Slp8/C+XByH9o9nnGlOqMgm0Y\n 580c2pOCbYOspAU7i0J6wCIHXE1MxNrIo/R+zwH5YEGOVScy0LfFbBKVIcENyB4aiBQt\n +2xnKqKnH5QDC+1F7Dzq+a7RdvZSaMvDvPEL/uaYkuAvlsHh99CPz23ZDFenu33fSkEE 3Q==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 19/20] net/cnxk: add dev args for min-max spi", "Date": "Mon, 7 Feb 2022 12:59:31 +0530", "Message-ID": "<20220207072932.22409-19-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220207072932.22409-1-ndabilpuram@marvell.com>", "References": "<20220207072932.22409-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "cnpbyPFdo7psJlg5gUrKvFDsULMvVkbx", "X-Proofpoint-ORIG-GUID": "cnpbyPFdo7psJlg5gUrKvFDsULMvVkbx", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-02-07_02,2022-02-03_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for inline inbound SPI range via devargs\ninstead of just max SPI value and range being 0..max.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 28 +++++++++++++-\n drivers/common/cnxk/roc_nix.h | 5 ++-\n drivers/common/cnxk/roc_nix_inl.c | 68 ++++++++++++++++++++--------------\n drivers/common/cnxk/roc_nix_inl.h | 8 ++--\n drivers/common/cnxk/roc_nix_inl_dev.c | 22 +++++++----\n drivers/common/cnxk/roc_nix_inl_priv.h | 4 +-\n drivers/common/cnxk/roc_nix_priv.h | 1 +\n drivers/common/cnxk/version.map | 2 +-\n drivers/net/cnxk/cn10k_ethdev_sec.c | 13 +++++--\n drivers/net/cnxk/cn9k_ethdev_sec.c | 10 +++--\n drivers/net/cnxk/cnxk_ethdev_devargs.c | 25 +++++++++----\n drivers/net/cnxk/cnxk_ethdev_sec.c | 16 ++++++--\n drivers/net/cnxk/cnxk_lookup.c | 3 +-\n 13 files changed, 142 insertions(+), 63 deletions(-)", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex 27a9420..e7c5ea5 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -214,6 +214,18 @@ Runtime Config Options\n \n -a 0002:02:00.0,tag_as_xor=1\n \n+- ``Min SPI for inbound inline IPsec`` (default ``0``)\n+\n+ Min SPI supported for inbound inline IPsec processing can be specified by\n+ ``ipsec_in_min_spi`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0002:02:00.0,ipsec_in_min_spi=6\n+\n+ With the above configuration, application can enable inline IPsec processing\n+ for inbound SA with min SPI of 6.\n+\n - ``Max SPI for inbound inline IPsec`` (default ``255``)\n \n Max SPI supported for inbound inline IPsec processing can be specified by\n@@ -224,7 +236,7 @@ Runtime Config Options\n -a 0002:02:00.0,ipsec_in_max_spi=128\n \n With the above configuration, application can enable inline IPsec processing\n- for 128 inbound SAs (SPI 0-127).\n+ with max SPI of 128.\n \n - ``Max SA's for outbound inline IPsec`` (default ``4096``)\n \n@@ -413,6 +425,18 @@ VF ``177D:A0F1``.\n Runtime Config Options for inline device\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n \n+- ``Min SPI for inbound inline IPsec`` (default ``0``)\n+\n+ Min SPI supported for inbound inline IPsec processing can be specified by\n+ ``ipsec_in_min_spi`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0002:1d:00.0,ipsec_in_min_spi=6\n+\n+ With the above configuration, application can enable inline IPsec processing\n+ for inbound SA with min SPI of 6 for traffic aggregated on inline device.\n+\n - ``Max SPI for inbound inline IPsec`` (default ``255``)\n \n Max SPI supported for inbound inline IPsec processing can be specified by\n@@ -423,7 +447,7 @@ Runtime Config Options for inline device\n -a 0002:1d:00.0,ipsec_in_max_spi=128\n \n With the above configuration, application can enable inline IPsec processing\n- for 128 inbound SAs (SPI 0-127) for traffic aggregated on inline device.\n+ for inbound SA with max SPI of 128 for traffic aggregated on inline device.\n \n \n Debugging Options\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 57a595f..ea58e06 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -384,8 +384,9 @@ struct roc_nix {\n \tuint8_t lock_rx_ctx;\n \tuint32_t outb_nb_desc;\n \tuint16_t outb_nb_crypto_qs;\n-\tuint16_t ipsec_in_max_spi;\n-\tuint16_t ipsec_out_max_sa;\n+\tuint32_t ipsec_in_min_spi;\n+\tuint32_t ipsec_in_max_spi;\n+\tuint32_t ipsec_out_max_sa;\n \tbool ipsec_out_sso_pffunc;\n \t/* End of input parameters */\n \t/* LMT line base for \"Per Core Tx LMT line\" mode*/\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 11a1691..7bf89a4 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -19,12 +19,16 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==\n static int\n nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)\n {\n-\tuint16_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;\n+\tuint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi;\n+\tuint32_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct roc_nix_ipsec_cfg cfg;\n+\tuint64_t max_sa, i;\n \tsize_t inb_sa_sz;\n-\tint rc, i;\n \tvoid *sa;\n+\tint rc;\n+\n+\tmax_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);\n \n \t/* CN9K SA size is different */\n \tif (roc_model_is_cn9k())\n@@ -34,14 +38,15 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)\n \n \t/* Alloc contiguous memory for Inbound SA's */\n \tnix->inb_sa_sz = inb_sa_sz;\n-\tnix->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,\n+\tnix->inb_spi_mask = max_sa - 1;\n+\tnix->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,\n \t\t\t\t ROC_NIX_INL_SA_BASE_ALIGN);\n \tif (!nix->inb_sa_base) {\n \t\tplt_err(\"Failed to allocate memory for Inbound SA\");\n \t\treturn -ENOMEM;\n \t}\n \tif (roc_model_is_cn10k()) {\n-\t\tfor (i = 0; i < ipsec_in_max_spi; i++) {\n+\t\tfor (i = 0; i < max_sa; i++) {\n \t\t\tsa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);\n \t\t\troc_ot_ipsec_inb_sa_init(sa, true);\n \t\t}\n@@ -50,7 +55,7 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)\n \tmemset(&cfg, 0, sizeof(cfg));\n \tcfg.sa_size = inb_sa_sz;\n \tcfg.iova = (uintptr_t)nix->inb_sa_base;\n-\tcfg.max_sa = ipsec_in_max_spi + 1;\n+\tcfg.max_sa = max_sa;\n \tcfg.tt = SSO_TT_ORDERED;\n \n \t/* Setup device specific inb SA table */\n@@ -135,11 +140,13 @@ roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)\n }\n \n uint32_t\n-roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)\n+roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix, bool inb_inl_dev,\n+\t\t\t uint32_t *min_spi, uint32_t *max_spi)\n {\n \tstruct idev_cfg *idev = idev_get_cfg();\n+\tuint32_t min = 0, max = 0, mask = 0;\n \tstruct nix_inl_dev *inl_dev;\n-\tstruct nix *nix;\n+\tstruct nix *nix = NULL;\n \n \tif (idev == NULL)\n \t\treturn 0;\n@@ -147,20 +154,25 @@ roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)\n \tif (!inb_inl_dev && roc_nix == NULL)\n \t\treturn -EINVAL;\n \n-\tif (roc_nix) {\n+\tinl_dev = idev->nix_inl_dev;\n+\tif (inb_inl_dev) {\n+\t\tmin = inl_dev->ipsec_in_min_spi;\n+\t\tmax = inl_dev->ipsec_in_max_spi;\n+\t\tmask = inl_dev->inb_spi_mask;\n+\t} else {\n \t\tnix = roc_nix_to_nix_priv(roc_nix);\n \t\tif (!nix->inl_inb_ena)\n-\t\t\treturn 0;\n+\t\t\tgoto exit;\n+\t\tmin = roc_nix->ipsec_in_min_spi;\n+\t\tmax = roc_nix->ipsec_in_max_spi;\n+\t\tmask = nix->inb_spi_mask;\n \t}\n-\n-\tif (inb_inl_dev) {\n-\t\tinl_dev = idev->nix_inl_dev;\n-\t\tif (inl_dev)\n-\t\t\treturn inl_dev->ipsec_in_max_spi;\n-\t\treturn 0;\n-\t}\n-\n-\treturn roc_nix->ipsec_in_max_spi;\n+exit:\n+\tif (min_spi)\n+\t\t*min_spi = min;\n+\tif (max_spi)\n+\t\t*max_spi = max;\n+\treturn mask;\n }\n \n uint32_t\n@@ -194,8 +206,8 @@ roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa)\n uintptr_t\n roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)\n {\n+\tuint32_t max_spi, min_spi, mask;\n \tuintptr_t sa_base;\n-\tuint32_t max_spi;\n \tuint64_t sz;\n \n \tsa_base = roc_nix_inl_inb_sa_base_get(roc_nix, inb_inl_dev);\n@@ -204,11 +216,11 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)\n \t\treturn 0;\n \n \t/* Check if SPI is in range */\n-\tmax_spi = roc_nix_inl_inb_sa_max_spi(roc_nix, inb_inl_dev);\n-\tif (spi > max_spi) {\n-\t\tplt_err(\"Inbound SA SPI %u exceeds max %u\", spi, max_spi);\n-\t\treturn 0;\n-\t}\n+\tmask = roc_nix_inl_inb_spi_range(roc_nix, inb_inl_dev, &min_spi,\n+\t\t\t\t\t &max_spi);\n+\tif (spi > max_spi || spi < min_spi)\n+\t\tplt_warn(\"Inbound SA SPI %u not in range (%u..%u)\", spi,\n+\t\t\t min_spi, max_spi);\n \n \t/* Get SA size */\n \tsz = roc_nix_inl_inb_sa_sz(roc_nix, inb_inl_dev);\n@@ -216,7 +228,7 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)\n \t\treturn 0;\n \n \t/* Basic logic of SPI->SA for now */\n-\treturn (sa_base + (spi * sz));\n+\treturn (sa_base + ((spi & mask) * sz));\n }\n \n int\n@@ -295,11 +307,11 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)\n \tstruct nix_inl_dev *inl_dev;\n \tuint16_t sso_pffunc;\n \tuint8_t eng_grpmask;\n-\tuint64_t blkaddr;\n+\tuint64_t blkaddr, i;\n \tuint16_t nb_lf;\n \tvoid *sa_base;\n \tsize_t sa_sz;\n-\tint i, j, rc;\n+\tint j, rc;\n \tvoid *sa;\n \n \tif (idev == NULL)\n@@ -775,7 +787,7 @@ roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t tag_const,\n \tmemset(&cfg, 0, sizeof(cfg));\n \tcfg.sa_size = nix->inb_sa_sz;\n \tcfg.iova = (uintptr_t)nix->inb_sa_base;\n-\tcfg.max_sa = roc_nix->ipsec_in_max_spi + 1;\n+\tcfg.max_sa = nix->inb_spi_mask + 1;\n \tcfg.tt = tt;\n \tcfg.tag_const = tag_const;\n \ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex 728225b..5eb1a81 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -105,7 +105,8 @@ typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args);\n struct roc_nix_inl_dev {\n \t/* Input parameters */\n \tstruct plt_pci_device *pci_dev;\n-\tuint16_t ipsec_in_max_spi;\n+\tuint32_t ipsec_in_min_spi;\n+\tuint32_t ipsec_in_max_spi;\n \tbool selftest;\n \tbool is_multi_channel;\n \tuint16_t channel;\n@@ -136,8 +137,9 @@ int __roc_api roc_nix_inl_inb_fini(struct roc_nix *roc_nix);\n bool __roc_api roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix);\n uintptr_t __roc_api roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix,\n \t\t\t\t\t\tbool inl_dev_sa);\n-uint32_t __roc_api roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix,\n-\t\t\t\t\t bool inl_dev_sa);\n+uint32_t __roc_api roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix,\n+\t\t\t\t\t bool inl_dev_sa, uint32_t *min,\n+\t\t\t\t\t uint32_t *max);\n uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix,\n \t\t\t\t\t bool inl_dev_sa);\n uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix,\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex 4c1d85a..aeec406 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -120,6 +120,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)\n {\n \tstruct nix_inline_ipsec_lf_cfg *lf_cfg;\n \tstruct mbox *mbox = (&inl_dev->dev)->mbox;\n+\tuint64_t max_sa;\n \tuint32_t sa_w;\n \n \tlf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);\n@@ -127,8 +128,9 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)\n \t\treturn -ENOSPC;\n \n \tif (ena) {\n-\t\tsa_w = plt_align32pow2(inl_dev->ipsec_in_max_spi + 1);\n-\t\tsa_w = plt_log2_u32(sa_w);\n+\n+\t\tmax_sa = inl_dev->inb_spi_mask + 1;\n+\t\tsa_w = plt_log2_u32(max_sa);\n \n \t\tlf_cfg->enable = 1;\n \t\tlf_cfg->sa_base_addr = (uintptr_t)inl_dev->inb_sa_base;\n@@ -138,7 +140,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)\n \t\t\tlf_cfg->ipsec_cfg0.lenm1_max = NIX_CN9K_MAX_HW_FRS - 1;\n \t\telse\n \t\t\tlf_cfg->ipsec_cfg0.lenm1_max = NIX_RPM_MAX_HW_FRS - 1;\n-\t\tlf_cfg->ipsec_cfg1.sa_idx_max = inl_dev->ipsec_in_max_spi;\n+\t\tlf_cfg->ipsec_cfg1.sa_idx_max = max_sa - 1;\n \t\tlf_cfg->ipsec_cfg0.sa_pow2_size =\n \t\t\tplt_log2_u32(inl_dev->inb_sa_sz);\n \n@@ -319,16 +321,20 @@ nix_inl_sso_release(struct nix_inl_dev *inl_dev)\n static int\n nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n {\n-\tuint16_t ipsec_in_max_spi = inl_dev->ipsec_in_max_spi;\n+\tuint32_t ipsec_in_min_spi = inl_dev->ipsec_in_min_spi;\n+\tuint32_t ipsec_in_max_spi = inl_dev->ipsec_in_max_spi;\n \tstruct dev *dev = &inl_dev->dev;\n \tstruct mbox *mbox = dev->mbox;\n \tstruct nix_lf_alloc_rsp *rsp;\n \tstruct nix_lf_alloc_req *req;\n \tstruct nix_hw_info *hw_info;\n+\tuint64_t max_sa, i;\n \tsize_t inb_sa_sz;\n-\tint i, rc = -ENOSPC;\n+\tint rc = -ENOSPC;\n \tvoid *sa;\n \n+\tmax_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);\n+\n \t/* Alloc NIX LF needed for single RQ */\n \treq = mbox_alloc_msg_nix_lf_alloc(mbox);\n \tif (req == NULL)\n@@ -387,7 +393,8 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n \n \t/* Alloc contiguous memory for Inbound SA's */\n \tinl_dev->inb_sa_sz = inb_sa_sz;\n-\tinl_dev->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,\n+\tinl_dev->inb_spi_mask = max_sa - 1;\n+\tinl_dev->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,\n \t\t\t\t\t ROC_NIX_INL_SA_BASE_ALIGN);\n \tif (!inl_dev->inb_sa_base) {\n \t\tplt_err(\"Failed to allocate memory for Inbound SA\");\n@@ -396,7 +403,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n \t}\n \n \tif (roc_model_is_cn10k()) {\n-\t\tfor (i = 0; i < ipsec_in_max_spi; i++) {\n+\t\tfor (i = 0; i < max_sa; i++) {\n \t\t\tsa = ((uint8_t *)inl_dev->inb_sa_base) +\n \t\t\t (i * inb_sa_sz);\n \t\t\troc_ot_ipsec_inb_sa_init(sa, true);\n@@ -657,6 +664,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)\n \tmemset(inl_dev, 0, sizeof(*inl_dev));\n \n \tinl_dev->pci_dev = pci_dev;\n+\tinl_dev->ipsec_in_min_spi = roc_inl_dev->ipsec_in_min_spi;\n \tinl_dev->ipsec_in_max_spi = roc_inl_dev->ipsec_in_max_spi;\n \tinl_dev->selftest = roc_inl_dev->selftest;\n \tinl_dev->is_multi_channel = roc_inl_dev->is_multi_channel;\ndiff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h\nindex b6d8602..24dabbc 100644\n--- a/drivers/common/cnxk/roc_nix_inl_priv.h\n+++ b/drivers/common/cnxk/roc_nix_inl_priv.h\n@@ -58,7 +58,9 @@ struct nix_inl_dev {\n \tuint16_t channel;\n \tuint16_t chan_mask;\n \tbool is_multi_channel;\n-\tuint16_t ipsec_in_max_spi;\n+\tuint32_t ipsec_in_min_spi;\n+\tuint32_t ipsec_in_max_spi;\n+\tuint32_t inb_spi_mask;\n \tbool attach_cptlf;\n \tbool wqe_skip;\n };\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex ec6f106..51b022e 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -174,6 +174,7 @@ struct nix {\n \tbool inl_outb_ena;\n \tvoid *inb_sa_base;\n \tsize_t inb_sa_sz;\n+\tuint32_t inb_spi_mask;\n \tvoid *outb_sa_base;\n \tsize_t outb_sa_sz;\n \tuint16_t outb_err_sso_pffunc;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 0f990d3..2a64090 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -142,7 +142,7 @@ INTERNAL {\n \troc_nix_inl_inb_init;\n \troc_nix_inl_inb_sa_base_get;\n \troc_nix_inl_inb_sa_get;\n-\troc_nix_inl_inb_sa_max_spi;\n+\troc_nix_inl_inb_spi_range;\n \troc_nix_inl_inb_sa_sz;\n \troc_nix_inl_inb_tag_update;\n \troc_nix_inl_inb_fini;\ndiff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c\nindex 044b20c..a2a53c1 100644\n--- a/drivers/net/cnxk/cn10k_ethdev_sec.c\n+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c\n@@ -264,6 +264,7 @@ cn10k_eth_sec_session_create(void *device,\n \tstruct cn10k_sec_sess_priv sess_priv;\n \tstruct rte_crypto_sym_xform *crypto;\n \tstruct cnxk_eth_sec_sess *eth_sec;\n+\tstruct roc_nix *nix = &dev->nix;\n \tbool inbound, inl_dev;\n \trte_spinlock_t *lock;\n \tchar tbuf[128] = {0};\n@@ -308,13 +309,16 @@ cn10k_eth_sec_session_create(void *device,\n \tif (inbound) {\n \t\tstruct roc_ot_ipsec_inb_sa *inb_sa, *inb_sa_dptr;\n \t\tstruct cn10k_inb_priv_data *inb_priv;\n+\t\tuint32_t spi_mask;\n \t\tuintptr_t sa;\n \n \t\tPLT_STATIC_ASSERT(sizeof(struct cn10k_inb_priv_data) <\n \t\t\t\t ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD);\n \n+\t\tspi_mask = roc_nix_inl_inb_spi_range(nix, inl_dev, NULL, NULL);\n+\n \t\t/* Get Inbound SA from NIX_RX_IPSEC_SA_BASE */\n-\t\tsa = roc_nix_inl_inb_sa_get(&dev->nix, inl_dev, ipsec->spi);\n+\t\tsa = roc_nix_inl_inb_sa_get(nix, inl_dev, ipsec->spi);\n \t\tif (!sa && dev->inb.inl_dev) {\n \t\t\tsnprintf(tbuf, sizeof(tbuf),\n \t\t\t\t \"Failed to create ingress sa, inline dev \"\n@@ -358,16 +362,17 @@ cn10k_eth_sec_session_create(void *device,\n \t\tinb_priv->userdata = conf->userdata;\n \n \t\t/* Save SA index/SPI in cookie for now */\n-\t\tinb_sa_dptr->w1.s.cookie = rte_cpu_to_be_32(ipsec->spi);\n+\t\tinb_sa_dptr->w1.s.cookie =\n+\t\t\trte_cpu_to_be_32(ipsec->spi & spi_mask);\n \n \t\t/* Prepare session priv */\n \t\tsess_priv.inb_sa = 1;\n-\t\tsess_priv.sa_idx = ipsec->spi;\n+\t\tsess_priv.sa_idx = ipsec->spi & spi_mask;\n \n \t\t/* Pointer from eth_sec -> inb_sa */\n \t\teth_sec->sa = inb_sa;\n \t\teth_sec->sess = sess;\n-\t\teth_sec->sa_idx = ipsec->spi;\n+\t\teth_sec->sa_idx = ipsec->spi & spi_mask;\n \t\teth_sec->spi = ipsec->spi;\n \t\teth_sec->inl_dev = !!dev->inb.inl_dev;\n \t\teth_sec->inb = true;\ndiff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c\nindex 27930d1..fa72424 100644\n--- a/drivers/net/cnxk/cn9k_ethdev_sec.c\n+++ b/drivers/net/cnxk/cn9k_ethdev_sec.c\n@@ -146,6 +146,7 @@ cn9k_eth_sec_session_create(void *device,\n \tstruct cn9k_sec_sess_priv sess_priv;\n \tstruct rte_crypto_sym_xform *crypto;\n \tstruct cnxk_eth_sec_sess *eth_sec;\n+\tstruct roc_nix *nix = &dev->nix;\n \trte_spinlock_t *lock;\n \tchar tbuf[128] = {0};\n \tbool inbound;\n@@ -185,15 +186,18 @@ cn9k_eth_sec_session_create(void *device,\n \tif (inbound) {\n \t\tstruct cn9k_inb_priv_data *inb_priv;\n \t\tstruct roc_onf_ipsec_inb_sa *inb_sa;\n+\t\tuint32_t spi_mask;\n \n \t\tPLT_STATIC_ASSERT(sizeof(struct cn9k_inb_priv_data) <\n \t\t\t\t ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD);\n \n+\t\tspi_mask = roc_nix_inl_inb_spi_range(nix, false, NULL, NULL);\n+\n \t\t/* Get Inbound SA from NIX_RX_IPSEC_SA_BASE. Assume no inline\n \t\t * device always for CN9K.\n \t\t */\n \t\tinb_sa = (struct roc_onf_ipsec_inb_sa *)\n-\t\t\t roc_nix_inl_inb_sa_get(&dev->nix, false, ipsec->spi);\n+\t\t\t roc_nix_inl_inb_sa_get(nix, false, ipsec->spi);\n \t\tif (!inb_sa) {\n \t\t\tsnprintf(tbuf, sizeof(tbuf),\n \t\t\t\t \"Failed to create ingress sa\");\n@@ -236,12 +240,12 @@ cn9k_eth_sec_session_create(void *device,\n \n \t\t/* Prepare session priv */\n \t\tsess_priv.inb_sa = 1;\n-\t\tsess_priv.sa_idx = ipsec->spi;\n+\t\tsess_priv.sa_idx = ipsec->spi & spi_mask;\n \n \t\t/* Pointer from eth_sec -> inb_sa */\n \t\teth_sec->sa = inb_sa;\n \t\teth_sec->sess = sess;\n-\t\teth_sec->sa_idx = ipsec->spi;\n+\t\teth_sec->sa_idx = ipsec->spi & spi_mask;\n \t\teth_sec->spi = ipsec->spi;\n \t\teth_sec->inb = true;\n \ndiff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c\nindex 157b27d..8a71644 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c\n@@ -49,14 +49,17 @@ parse_outb_nb_crypto_qs(const char *key, const char *value, void *extra_args)\n }\n \n static int\n-parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args)\n+parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args)\n {\n \tRTE_SET_USED(key);\n \tuint32_t val;\n \n-\tval = atoi(value);\n+\terrno = 0;\n+\tval = strtoul(value, NULL, 0);\n+\tif (errno)\n+\t\tval = 0;\n \n-\t*(uint16_t *)extra_args = val;\n+\t*(uint32_t *)extra_args = val;\n \n \treturn 0;\n }\n@@ -67,7 +70,10 @@ parse_ipsec_out_max_sa(const char *key, const char *value, void *extra_args)\n \tRTE_SET_USED(key);\n \tuint32_t val;\n \n-\tval = atoi(value);\n+\terrno = 0;\n+\tval = strtoul(value, NULL, 0);\n+\tif (errno)\n+\t\tval = 0;\n \n \t*(uint16_t *)extra_args = val;\n \n@@ -231,6 +237,7 @@ parse_sdp_channel_mask(const char *key, const char *value, void *extra_args)\n #define CNXK_SWITCH_HEADER_TYPE \"switch_header\"\n #define CNXK_RSS_TAG_AS_XOR\t\"tag_as_xor\"\n #define CNXK_LOCK_RX_CTX\t\"lock_rx_ctx\"\n+#define CNXK_IPSEC_IN_MIN_SPI\t\"ipsec_in_min_spi\"\n #define CNXK_IPSEC_IN_MAX_SPI\t\"ipsec_in_max_spi\"\n #define CNXK_IPSEC_OUT_MAX_SA\t\"ipsec_out_max_sa\"\n #define CNXK_OUTB_NB_DESC\t\"outb_nb_desc\"\n@@ -245,13 +252,14 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)\n \tuint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64;\n \tuint16_t sqb_count = CNXK_NIX_TX_MAX_SQB;\n \tstruct flow_pre_l2_size_info pre_l2_info;\n-\tuint16_t ipsec_in_max_spi = BIT(8) - 1;\n-\tuint16_t ipsec_out_max_sa = BIT(12);\n+\tuint32_t ipsec_in_max_spi = BIT(8) - 1;\n+\tuint32_t ipsec_out_max_sa = BIT(12);\n \tuint16_t flow_prealloc_size = 1;\n \tuint16_t switch_header_type = 0;\n \tuint16_t flow_max_priority = 3;\n \tuint16_t force_inb_inl_dev = 0;\n \tuint16_t outb_nb_crypto_qs = 1;\n+\tuint32_t ipsec_in_min_spi = 0;\n \tuint16_t outb_nb_desc = 8200;\n \tstruct sdp_channel sdp_chan;\n \tuint16_t rss_tag_as_xor = 0;\n@@ -284,8 +292,10 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)\n \trte_kvargs_process(kvlist, CNXK_RSS_TAG_AS_XOR, &parse_flag,\n \t\t\t &rss_tag_as_xor);\n \trte_kvargs_process(kvlist, CNXK_LOCK_RX_CTX, &parse_flag, &lock_rx_ctx);\n+\trte_kvargs_process(kvlist, CNXK_IPSEC_IN_MIN_SPI,\n+\t\t\t &parse_ipsec_in_spi_range, &ipsec_in_min_spi);\n \trte_kvargs_process(kvlist, CNXK_IPSEC_IN_MAX_SPI,\n-\t\t\t &parse_ipsec_in_max_spi, &ipsec_in_max_spi);\n+\t\t\t &parse_ipsec_in_spi_range, &ipsec_in_max_spi);\n \trte_kvargs_process(kvlist, CNXK_IPSEC_OUT_MAX_SA,\n \t\t\t &parse_ipsec_out_max_sa, &ipsec_out_max_sa);\n \trte_kvargs_process(kvlist, CNXK_OUTB_NB_DESC, &parse_outb_nb_desc,\n@@ -307,6 +317,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)\n \tdev->outb.max_sa = ipsec_out_max_sa;\n \tdev->outb.nb_desc = outb_nb_desc;\n \tdev->outb.nb_crypto_qs = outb_nb_crypto_qs;\n+\tdev->nix.ipsec_in_min_spi = ipsec_in_min_spi;\n \tdev->nix.ipsec_in_max_spi = ipsec_in_max_spi;\n \tdev->nix.ipsec_out_max_sa = ipsec_out_max_sa;\n \tdev->nix.rss_tag_as_xor = !!rss_tag_as_xor;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c\nindex ea204ca..3831889 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_sec.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c\n@@ -5,6 +5,7 @@\n #include <cnxk_ethdev.h>\n \n #define CNXK_NIX_INL_SELFTEST\t \"selftest\"\n+#define CNXK_NIX_INL_IPSEC_IN_MIN_SPI \"ipsec_in_min_spi\"\n #define CNXK_NIX_INL_IPSEC_IN_MAX_SPI \"ipsec_in_max_spi\"\n #define CNXK_INL_CPT_CHANNEL\t \"inl_cpt_channel\"\n \n@@ -119,14 +120,17 @@ struct rte_security_ops cnxk_eth_sec_ops = {\n };\n \n static int\n-parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args)\n+parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args)\n {\n \tRTE_SET_USED(key);\n \tuint32_t val;\n \n-\tval = atoi(value);\n+\terrno = 0;\n+\tval = strtoul(value, NULL, 0);\n+\tif (errno)\n+\t\tval = 0;\n \n-\t*(uint16_t *)extra_args = val;\n+\t*(uint32_t *)extra_args = val;\n \n \treturn 0;\n }\n@@ -169,6 +173,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,\n \t\t struct roc_nix_inl_dev *inl_dev)\n {\n \tuint32_t ipsec_in_max_spi = BIT(8) - 1;\n+\tuint32_t ipsec_in_min_spi = 0;\n \tstruct inl_cpt_channel cpt_channel;\n \tstruct rte_kvargs *kvlist;\n \tuint8_t selftest = 0;\n@@ -184,13 +189,16 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,\n \n \trte_kvargs_process(kvlist, CNXK_NIX_INL_SELFTEST, &parse_selftest,\n \t\t\t &selftest);\n+\trte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MIN_SPI,\n+\t\t\t &parse_ipsec_in_spi_range, &ipsec_in_min_spi);\n \trte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MAX_SPI,\n-\t\t\t &parse_ipsec_in_max_spi, &ipsec_in_max_spi);\n+\t\t\t &parse_ipsec_in_spi_range, &ipsec_in_max_spi);\n \trte_kvargs_process(kvlist, CNXK_INL_CPT_CHANNEL, &parse_inl_cpt_channel,\n \t\t\t &cpt_channel);\n \trte_kvargs_free(kvlist);\n \n null_devargs:\n+\tinl_dev->ipsec_in_min_spi = ipsec_in_min_spi;\n \tinl_dev->ipsec_in_max_spi = ipsec_in_max_spi;\n \tinl_dev->selftest = selftest;\n \tinl_dev->channel = cpt_channel.channel;\ndiff --git a/drivers/net/cnxk/cnxk_lookup.c b/drivers/net/cnxk/cnxk_lookup.c\nindex 4eb1ecf..f36fb8f 100644\n--- a/drivers/net/cnxk/cnxk_lookup.c\n+++ b/drivers/net/cnxk/cnxk_lookup.c\n@@ -337,7 +337,8 @@ cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev)\n \tif (!sa_base)\n \t\treturn -ENOTSUP;\n \n-\tsa_w = plt_log2_u32(dev->nix.ipsec_in_max_spi + 1);\n+\tsa_w = plt_log2_u32(dev->nix.ipsec_in_max_spi + 1 -\n+\t\t\t dev->nix.ipsec_in_min_spi);\n \n \t/* Set SA Base in lookup mem */\n \tsa_base_tbl = (uintptr_t)lookup_mem;\n", "prefixes": [ "19/20" ] }