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GET /api/patches/107818/?format=api
{ "id": 107818, "url": "http://patchwork.dpdk.org/api/patches/107818/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220218171527.56719-2-kai.ji@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220218171527.56719-2-kai.ji@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220218171527.56719-2-kai.ji@intel.com", "date": "2022-02-18T17:15:19", "name": "[v9,1/9] common/qat: define build request and dequeue ops", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3063478359f8ffed5948ea267b5bd0c5ef0d47e1", "submitter": { "id": 2202, "url": "http://patchwork.dpdk.org/api/people/2202/?format=api", "name": "Ji, Kai", "email": "kai.ji@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220218171527.56719-2-kai.ji@intel.com/mbox/", "series": [ { "id": 21741, "url": "http://patchwork.dpdk.org/api/series/21741/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21741", "date": "2022-02-18T17:15:18", "name": "drivers/qat: QAT symmetric crypto datapatch rework", "version": 9, "mbox": "http://patchwork.dpdk.org/series/21741/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/107818/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/107818/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5B362A0032;\n\tFri, 18 Feb 2022 18:15:53 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 866BC4114B;\n\tFri, 18 Feb 2022 18:15:50 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 1472C4014E\n for <dev@dpdk.org>; Fri, 18 Feb 2022 18:15:46 +0100 (CET)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Feb 2022 09:15:32 -0800", "from silpixa00400465.ir.intel.com ([10.55.128.22])\n by orsmga005.jf.intel.com with ESMTP; 18 Feb 2022 09:15:30 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1645204547; x=1676740547;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=vAd9Nc8YG2NI54GlIfk3d4NbvQ5vNFTvDnhbdPtVjX0=;\n b=CYl/FfYf7VTvVy8PCdXwibYReXxPs/FtU3Degb0DoxyGfxEqL+3EUXmB\n p+1sfaKUmE0S3lk1pCzXT6BSlmzU7uM6tqeC3rGPZ8/U7wwXN4TtEIEns\n fv0I+TBVNHSlvmplliA5cUV1BHbCQSwHc6phsXaryLQyx9gDRC5W9W/9b\n 2BXQnL3g5VlxsqZ8Fae4ACO3PD5Q3I6hkVz5eAOSE6J/tEdzMrKdHpR9Z\n AX86AfBaYnH0rGQBTHh2E9nU6JTi9v4babilvWsv689iA6kCLOTaS3lb2\n PTn3r+Oz/83pjhHPsqkFxDFbEhQlnmqLzO1/TlJld75uohklI0hfI5xf3 Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10262\"; a=\"238571891\"", "E=Sophos;i=\"5.88,379,1635231600\"; d=\"scan'208\";a=\"238571891\"", "E=Sophos;i=\"5.88,379,1635231600\"; d=\"scan'208\";a=\"705446183\"" ], "X-ExtLoop1": "1", "From": "Kai Ji <kai.ji@intel.com>", "To": "dev@dpdk.org", "Cc": "gakhil@marvell.com,\n\troy.fan.zhang@intel.com,\n\tKai Ji <kai.ji@intel.com>", "Subject": "[dpdk-dev v9 1/9] common/qat: define build request and dequeue ops", "Date": "Sat, 19 Feb 2022 01:15:19 +0800", "Message-Id": "<20220218171527.56719-2-kai.ji@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20220218171527.56719-1-kai.ji@intel.com>", "References": "<20220217162909.22713-1-kai.ji@intel.com>\n <20220218171527.56719-1-kai.ji@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch introduce build request and dequeue op function\npointers to the qat queue pair implementation. The function\nponiters are assigned during qat session generation based on input\ncrypto operation request.\n\nSigned-off-by: Kai Ji <kai.ji@intel.com>\n---\n drivers/common/qat/qat_qp.c | 10 ++++--\n drivers/common/qat/qat_qp.h | 54 ++++++++++++++++++++++++++--\n drivers/compress/qat/qat_comp_pmd.c | 4 +--\n drivers/crypto/qat/qat_asym_pmd.c | 4 +--\n drivers/crypto/qat/qat_sym_pmd.c | 4 +--\n drivers/crypto/qat/qat_sym_session.h | 13 ++++++-\n 6 files changed, 76 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c\nindex 57ac8fefca..56234ca1a4 100644\n--- a/drivers/common/qat/qat_qp.c\n+++ b/drivers/common/qat/qat_qp.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2015-2018 Intel Corporation\n+ * Copyright(c) 2015-2022 Intel Corporation\n */\n \n #include <rte_common.h>\n@@ -547,7 +547,9 @@ adf_modulo(uint32_t data, uint32_t modulo_mask)\n }\n \n uint16_t\n-qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)\n+qat_enqueue_op_burst(void *qp,\n+\t\t__rte_unused qat_op_build_request_t op_build_request,\n+\t\tvoid **ops, uint16_t nb_ops)\n {\n \tregister struct qat_queue *queue;\n \tstruct qat_qp *tmp_qp = (struct qat_qp *)qp;\n@@ -814,7 +816,9 @@ qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops)\n }\n \n uint16_t\n-qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)\n+qat_dequeue_op_burst(void *qp, void **ops,\n+\t\t__rte_unused qat_op_dequeue_t qat_dequeue_process_response,\n+\t\tuint16_t nb_ops)\n {\n \tstruct qat_queue *rx_queue;\n \tstruct qat_qp *tmp_qp = (struct qat_qp *)qp;\ndiff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h\nindex deafb407b3..66f00943a5 100644\n--- a/drivers/common/qat/qat_qp.h\n+++ b/drivers/common/qat/qat_qp.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2018 Intel Corporation\n+ * Copyright(c) 2018-2022 Intel Corporation\n */\n #ifndef _QAT_QP_H_\n #define _QAT_QP_H_\n@@ -36,6 +36,51 @@ struct qat_queue {\n \t/* number of responses processed since last CSR head write */\n };\n \n+/**\n+ * Type define qat_op_build_request_t function pointer, passed in as argument\n+ * in enqueue op burst, where a build request assigned base on the type of\n+ * crypto op.\n+ *\n+ * @param in_op\n+ * An input op pointer\n+ * @param out_msg\n+ * out_meg pointer\n+ * @param op_cookie\n+ * op cookie pointer\n+ * @param opaque\n+ * an opaque data may be used to store context may be useful between\n+ * 2 enqueue operations.\n+ * @param dev_gen\n+ * qat device gen id\n+ * @return\n+ * - 0 if the crypto request is build successfully,\n+ * - EINVAL if error\n+ **/\n+typedef int (*qat_op_build_request_t)(void *in_op, uint8_t *out_msg,\n+\t\tvoid *op_cookie, uint64_t *opaque, enum qat_device_gen dev_gen);\n+\n+/**\n+ * Type define qat_op_dequeue_t function pointer, passed in as argument\n+ * in dequeue op burst, where a dequeue op assigned base on the type of\n+ * crypto op.\n+ *\n+ * @param op\n+ * An input op pointer\n+ * @param resp\n+ * qat response msg pointer\n+ * @param op_cookie\n+ * op cookie pointer\n+ * @param dequeue_err_count\n+ * dequeue error counter\n+ * @return\n+ * - 0 if dequeue OP is successful\n+ * - EINVAL if error\n+ **/\n+typedef int (*qat_op_dequeue_t)(void **op, uint8_t *resp, void *op_cookie,\n+\t\tuint64_t *dequeue_err_count __rte_unused);\n+\n+#define QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE\t2\n+\n struct qat_qp {\n \tvoid\t\t\t*mmap_bar_addr;\n \tstruct qat_queue\ttx_q;\n@@ -44,6 +89,7 @@ struct qat_qp {\n \tstruct rte_mempool *op_cookie_pool;\n \tvoid **op_cookies;\n \tuint32_t nb_descriptors;\n+\tuint64_t opaque[QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE];\n \tenum qat_device_gen qat_dev_gen;\n \tenum qat_service_type service_type;\n \tstruct qat_pci_device *qat_dev;\n@@ -78,13 +124,15 @@ struct qat_qp_config {\n };\n \n uint16_t\n-qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);\n+qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request,\n+\t\tvoid **ops, uint16_t nb_ops);\n \n uint16_t\n qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops);\n \n uint16_t\n-qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops);\n+qat_dequeue_op_burst(void *qp, void **ops,\n+\t\tqat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops);\n \n int\n qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr);\ndiff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c\nindex da6404c017..8e497e7a09 100644\n--- a/drivers/compress/qat/qat_comp_pmd.c\n+++ b/drivers/compress/qat/qat_comp_pmd.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2015-2019 Intel Corporation\n+ * Copyright(c) 2015-2022 Intel Corporation\n */\n \n #include <rte_malloc.h>\n@@ -620,7 +620,7 @@ static uint16_t\n qat_comp_pmd_dequeue_first_op_burst(void *qp, struct rte_comp_op **ops,\n \t\t\t\t uint16_t nb_ops)\n {\n-\tuint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, nb_ops);\n+\tuint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, NULL, nb_ops);\n \tstruct qat_qp *tmp_qp = (struct qat_qp *)qp;\n \n \tif (ret) {\ndiff --git a/drivers/crypto/qat/qat_asym_pmd.c b/drivers/crypto/qat/qat_asym_pmd.c\nindex addee384e3..9a7596b227 100644\n--- a/drivers/crypto/qat/qat_asym_pmd.c\n+++ b/drivers/crypto/qat/qat_asym_pmd.c\n@@ -62,13 +62,13 @@ static struct rte_cryptodev_ops crypto_qat_ops = {\n uint16_t qat_asym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\t\t\t uint16_t nb_ops)\n {\n-\treturn qat_enqueue_op_burst(qp, (void **)ops, nb_ops);\n+\treturn qat_enqueue_op_burst(qp, NULL, (void **)ops, nb_ops);\n }\n \n uint16_t qat_asym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\t\t\t uint16_t nb_ops)\n {\n-\treturn qat_dequeue_op_burst(qp, (void **)ops, nb_ops);\n+\treturn qat_dequeue_op_burst(qp, (void **)ops, NULL, nb_ops);\n }\n \n /* An rte_driver is needed in the registration of both the device and the driver\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c\nindex b835245f17..28a26260fb 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.c\n+++ b/drivers/crypto/qat/qat_sym_pmd.c\n@@ -49,14 +49,14 @@ static uint16_t\n qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\tuint16_t nb_ops)\n {\n-\treturn qat_enqueue_op_burst(qp, (void **)ops, nb_ops);\n+\treturn qat_enqueue_op_burst(qp, NULL, (void **)ops, nb_ops);\n }\n \n static uint16_t\n qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\tuint16_t nb_ops)\n {\n-\treturn qat_dequeue_op_burst(qp, (void **)ops, nb_ops);\n+\treturn qat_dequeue_op_burst(qp, (void **)ops, NULL, nb_ops);\n }\n \n /* An rte_driver is needed in the registration of both the device and the driver\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex 6ebc176729..fe875a7fd0 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2015-2019 Intel Corporation\n+ * Copyright(c) 2015-2022 Intel Corporation\n */\n #ifndef _QAT_SYM_SESSION_H_\n #define _QAT_SYM_SESSION_H_\n@@ -63,6 +63,16 @@ enum qat_sym_proto_flag {\n \tQAT_CRYPTO_PROTO_FLAG_ZUC = 4\n };\n \n+struct qat_sym_session;\n+\n+/*\n+ * typedef qat_op_build_request_t function pointer, passed in as argument\n+ * in enqueue op burst, where a build request assigned base on the type of\n+ * crypto op.\n+ */\n+typedef int (*qat_sym_build_request_t)(void *in_op, struct qat_sym_session *ctx,\n+\t\tuint8_t *out_msg, void *op_cookie);\n+\n /* Common content descriptor */\n struct qat_sym_cd {\n \tstruct icp_qat_hw_cipher_algo_blk cipher;\n@@ -107,6 +117,7 @@ struct qat_sym_session {\n \t/* Some generations need different setup of counter */\n \tuint32_t slice_types;\n \tenum qat_sym_proto_flag qat_proto_flag;\n+\tqat_sym_build_request_t build_request[2];\n };\n \n int\n", "prefixes": [ "v9", "1/9" ] }