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GET /api/patches/107823/?format=api
{ "id": 107823, "url": "http://patchwork.dpdk.org/api/patches/107823/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220218171527.56719-7-kai.ji@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220218171527.56719-7-kai.ji@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220218171527.56719-7-kai.ji@intel.com", "date": "2022-02-18T17:15:24", "name": "[v9,6/9] crypto/qat: unify asymmetric functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f21f589c6b839d25ccaa317509216b2f99ee8680", "submitter": { "id": 2202, "url": "http://patchwork.dpdk.org/api/people/2202/?format=api", "name": "Ji, Kai", "email": "kai.ji@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220218171527.56719-7-kai.ji@intel.com/mbox/", "series": [ { "id": 21741, "url": "http://patchwork.dpdk.org/api/series/21741/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21741", "date": "2022-02-18T17:15:18", "name": "drivers/qat: QAT symmetric crypto datapatch rework", "version": 9, "mbox": "http://patchwork.dpdk.org/series/21741/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/107823/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/107823/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C0F5CA0032;\n\tFri, 18 Feb 2022 18:16:31 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B18D341186;\n\tFri, 18 Feb 2022 18:16:01 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 70F0741154\n for <dev@dpdk.org>; Fri, 18 Feb 2022 18:15:49 +0100 (CET)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Feb 2022 09:15:40 -0800", "from silpixa00400465.ir.intel.com ([10.55.128.22])\n by orsmga005.jf.intel.com with ESMTP; 18 Feb 2022 09:15:39 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1645204549; x=1676740549;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=tDWvtjvJrO53QAKUrSVij2jn7oDNPb1s+i3xJ2Pd0XY=;\n b=k5jms32wrYqk40VkElxGnEXuf38ZBycJhfgC3y0C7GoU+3wsitYvnwhi\n kmTUH2ZpEU2S85ka71QuhPMyhUDUVT2f/Ufhlxow8BsVDXYf/yEZuc80+\n L0dho6xfO5K4O3f08BFucahzGjM2D0lXoZ1Fv+g5zIHueXwfVWmkLepaY\n vziwdFYNdDI1cmORp8Q7yNZF4D14mYcQA+PIc95zHD8V3gUBa/e4DY1+o\n V5Mj3eo0HrVN01xt9NIYYbVTsrxz5g2RUWzDsTdO1iiFAh0mtIbd7Qumq\n 2igOdb82RQnW262Thr6ATCvYOXRcgbrqUa3juwkfQ5KIq3WukraU+/2wv Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10262\"; a=\"238571904\"", "E=Sophos;i=\"5.88,379,1635231600\"; d=\"scan'208\";a=\"238571904\"", "E=Sophos;i=\"5.88,379,1635231600\"; d=\"scan'208\";a=\"705446267\"" ], "X-ExtLoop1": "1", "From": "Kai Ji <kai.ji@intel.com>", "To": "dev@dpdk.org", "Cc": "gakhil@marvell.com,\n\troy.fan.zhang@intel.com,\n\tKai Ji <kai.ji@intel.com>", "Subject": "[dpdk-dev v9 6/9] crypto/qat: unify asymmetric functions", "Date": "Sat, 19 Feb 2022 01:15:24 +0800", "Message-Id": "<20220218171527.56719-7-kai.ji@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20220218171527.56719-1-kai.ji@intel.com>", "References": "<20220217162909.22713-1-kai.ji@intel.com>\n <20220218171527.56719-1-kai.ji@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch removes qat_asym_pmd.c and integrates all the\nfunctions into qat_asym.c. The unified/integrated asym crypto\npmd functions should make them easier to maintain.\n\nSigned-off-by: Kai Ji <kai.ji@intel.com>\n---\n drivers/common/qat/meson.build | 2 +-\n drivers/crypto/qat/qat_asym.c | 180 +++++++++++++++++++++++\n drivers/crypto/qat/qat_asym_pmd.c | 231 ------------------------------\n drivers/crypto/qat/qat_asym_pmd.h | 54 -------\n 4 files changed, 181 insertions(+), 286 deletions(-)\n delete mode 100644 drivers/crypto/qat/qat_asym_pmd.c\n delete mode 100644 drivers/crypto/qat/qat_asym_pmd.h", "diff": "diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build\nindex 1bf6896a7e..f687f5c9d8 100644\n--- a/drivers/common/qat/meson.build\n+++ b/drivers/common/qat/meson.build\n@@ -74,7 +74,7 @@ endif\n \n if qat_crypto\n foreach f: ['qat_sym.c', 'qat_sym_session.c',\n- 'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c',\n+ 'qat_sym_hw_dp.c', 'qat_asym.c', 'qat_crypto.c',\n 'dev/qat_sym_pmd_gen1.c',\n 'dev/qat_asym_pmd_gen1.c',\n 'dev/qat_crypto_pmd_gen2.c',\ndiff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c\nindex 845e905a89..76d50dd6f9 100644\n--- a/drivers/crypto/qat/qat_asym.c\n+++ b/drivers/crypto/qat/qat_asym.c\n@@ -19,6 +19,32 @@ uint8_t qat_asym_driver_id;\n \n struct qat_crypto_gen_dev_ops qat_asym_gen_dev_ops[QAT_N_GENS];\n \n+void\n+qat_asym_init_op_cookie(void *op_cookie)\n+{\n+\tint j;\n+\tstruct qat_asym_op_cookie *cookie = op_cookie;\n+\n+\tcookie->input_addr = rte_mempool_virt2iova(cookie) +\n+\t\t\toffsetof(struct qat_asym_op_cookie,\n+\t\t\t\t\tinput_params_ptrs);\n+\n+\tcookie->output_addr = rte_mempool_virt2iova(cookie) +\n+\t\t\toffsetof(struct qat_asym_op_cookie,\n+\t\t\t\t\toutput_params_ptrs);\n+\n+\tfor (j = 0; j < 8; j++) {\n+\t\tcookie->input_params_ptrs[j] =\n+\t\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\t\toffsetof(struct qat_asym_op_cookie,\n+\t\t\t\t\t\tinput_array[j]);\n+\t\tcookie->output_params_ptrs[j] =\n+\t\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\t\toffsetof(struct qat_asym_op_cookie,\n+\t\t\t\t\t\toutput_array[j]);\n+\t}\n+}\n+\n /* An rte_driver is needed in the registration of both the device and the driver\n * with cryptodev.\n * The actual qat pci's rte_driver can't be used as its name represents\n@@ -788,6 +814,160 @@ qat_asym_session_clear(struct rte_cryptodev *dev,\n \t\tmemset(s, 0, qat_asym_session_get_private_size(dev));\n }\n \n+static uint16_t\n+qat_asym_crypto_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n+\t\tuint16_t nb_ops)\n+{\n+\treturn qat_enqueue_op_burst(qp, qat_asym_build_request, (void **)ops,\n+\t\t\tnb_ops);\n+}\n+\n+static uint16_t\n+qat_asym_crypto_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n+\t\tuint16_t nb_ops)\n+{\n+\treturn qat_dequeue_op_burst(qp, (void **)ops, qat_asym_process_response,\n+\t\t\t\tnb_ops);\n+}\n+\n+int\n+qat_asym_dev_create(struct qat_pci_device *qat_pci_dev,\n+\t\tstruct qat_dev_cmd_param *qat_dev_cmd_param)\n+{\n+\tstruct qat_cryptodev_private *internals;\n+\tstruct rte_cryptodev *cryptodev;\n+\tstruct qat_device_info *qat_dev_instance =\n+\t\t&qat_pci_devs[qat_pci_dev->qat_dev_id];\n+\tstruct rte_cryptodev_pmd_init_params init_params = {\n+\t\t.name = \"\",\n+\t\t.socket_id = qat_dev_instance->pci_dev->device.numa_node,\n+\t\t.private_data_size = sizeof(struct qat_cryptodev_private)\n+\t};\n+\tstruct qat_capabilities_info capa_info;\n+\tconst struct rte_cryptodev_capabilities *capabilities;\n+\tconst struct qat_crypto_gen_dev_ops *gen_dev_ops =\n+\t\t&qat_asym_gen_dev_ops[qat_pci_dev->qat_dev_gen];\n+\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n+\tchar capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];\n+\tuint64_t capa_size;\n+\tint i = 0;\n+\n+\tsnprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, \"%s_%s\",\n+\t\t\tqat_pci_dev->name, \"asym\");\n+\tQAT_LOG(DEBUG, \"Creating QAT ASYM device %s\\n\", name);\n+\n+\tif (gen_dev_ops->cryptodev_ops == NULL) {\n+\t\tQAT_LOG(ERR, \"Device %s does not support asymmetric crypto\",\n+\t\t\t\tname);\n+\t\treturn -(EFAULT);\n+\t}\n+\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n+\t\tqat_pci_dev->qat_asym_driver_id =\n+\t\t\t\tqat_asym_driver_id;\n+\t} else if (rte_eal_process_type() == RTE_PROC_SECONDARY) {\n+\t\tif (qat_pci_dev->qat_asym_driver_id !=\n+\t\t\t\tqat_asym_driver_id) {\n+\t\t\tQAT_LOG(ERR,\n+\t\t\t\t\"Device %s have different driver id than corresponding device in primary process\",\n+\t\t\t\tname);\n+\t\t\treturn -(EFAULT);\n+\t\t}\n+\t}\n+\n+\t/* Populate subset device to use in cryptodev device creation */\n+\tqat_dev_instance->asym_rte_dev.driver = &cryptodev_qat_asym_driver;\n+\tqat_dev_instance->asym_rte_dev.numa_node =\n+\t\t\tqat_dev_instance->pci_dev->device.numa_node;\n+\tqat_dev_instance->asym_rte_dev.devargs = NULL;\n+\n+\tcryptodev = rte_cryptodev_pmd_create(name,\n+\t\t\t&(qat_dev_instance->asym_rte_dev), &init_params);\n+\n+\tif (cryptodev == NULL)\n+\t\treturn -ENODEV;\n+\n+\tqat_dev_instance->asym_rte_dev.name = cryptodev->data->name;\n+\tcryptodev->driver_id = qat_asym_driver_id;\n+\tcryptodev->dev_ops = gen_dev_ops->cryptodev_ops;\n+\n+\tcryptodev->enqueue_burst = qat_asym_crypto_enqueue_op_burst;\n+\tcryptodev->dequeue_burst = qat_asym_crypto_dequeue_op_burst;\n+\n+\tcryptodev->feature_flags = gen_dev_ops->get_feature_flags(qat_pci_dev);\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tsnprintf(capa_memz_name, RTE_CRYPTODEV_NAME_MAX_LEN,\n+\t\t\t\"QAT_ASYM_CAPA_GEN_%d\",\n+\t\t\tqat_pci_dev->qat_dev_gen);\n+\n+\tinternals = cryptodev->data->dev_private;\n+\tinternals->qat_dev = qat_pci_dev;\n+\tinternals->dev_id = cryptodev->data->dev_id;\n+\n+\tcapa_info = gen_dev_ops->get_capabilities(qat_pci_dev);\n+\tcapabilities = capa_info.data;\n+\tcapa_size = capa_info.size;\n+\n+\tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n+\tif (internals->capa_mz == NULL) {\n+\t\tinternals->capa_mz = rte_memzone_reserve(capa_memz_name,\n+\t\t\t\tcapa_size, rte_socket_id(), 0);\n+\t\tif (internals->capa_mz == NULL) {\n+\t\t\tQAT_LOG(DEBUG,\n+\t\t\t\t\"Error allocating memzone for capabilities, \"\n+\t\t\t\t\"destroying PMD for %s\",\n+\t\t\t\tname);\n+\t\t\trte_cryptodev_pmd_destroy(cryptodev);\n+\t\t\tmemset(&qat_dev_instance->asym_rte_dev, 0,\n+\t\t\t\tsizeof(qat_dev_instance->asym_rte_dev));\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t}\n+\n+\tmemcpy(internals->capa_mz->addr, capabilities, capa_size);\n+\tinternals->qat_dev_capabilities = internals->capa_mz->addr;\n+\n+\twhile (1) {\n+\t\tif (qat_dev_cmd_param[i].name == NULL)\n+\t\t\tbreak;\n+\t\tif (!strcmp(qat_dev_cmd_param[i].name, ASYM_ENQ_THRESHOLD_NAME))\n+\t\t\tinternals->min_enq_burst_threshold =\n+\t\t\t\t\tqat_dev_cmd_param[i].val;\n+\t\ti++;\n+\t}\n+\n+\tqat_pci_dev->asym_dev = internals;\n+\tinternals->service_type = QAT_SERVICE_ASYMMETRIC;\n+\tQAT_LOG(DEBUG, \"Created QAT ASYM device %s as cryptodev instance %d\",\n+\t\t\tcryptodev->data->name, internals->dev_id);\n+\treturn 0;\n+}\n+\n+int\n+qat_asym_dev_destroy(struct qat_pci_device *qat_pci_dev)\n+{\n+\tstruct rte_cryptodev *cryptodev;\n+\n+\tif (qat_pci_dev == NULL)\n+\t\treturn -ENODEV;\n+\tif (qat_pci_dev->asym_dev == NULL)\n+\t\treturn 0;\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n+\t\trte_memzone_free(qat_pci_dev->asym_dev->capa_mz);\n+\n+\t/* free crypto device */\n+\tcryptodev = rte_cryptodev_pmd_get_dev(\n+\t\t\tqat_pci_dev->asym_dev->dev_id);\n+\trte_cryptodev_pmd_destroy(cryptodev);\n+\tqat_pci_devs[qat_pci_dev->qat_dev_id].asym_rte_dev.name = NULL;\n+\tqat_pci_dev->asym_dev = NULL;\n+\n+\treturn 0;\n+}\n+\n static struct cryptodev_driver qat_crypto_drv;\n RTE_PMD_REGISTER_CRYPTO_DRIVER(qat_crypto_drv,\n \t\tcryptodev_qat_asym_driver,\ndiff --git a/drivers/crypto/qat/qat_asym_pmd.c b/drivers/crypto/qat/qat_asym_pmd.c\ndeleted file mode 100644\nindex 9a7596b227..0000000000\n--- a/drivers/crypto/qat/qat_asym_pmd.c\n+++ /dev/null\n@@ -1,231 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2019 Intel Corporation\n- */\n-\n-#include <cryptodev_pmd.h>\n-\n-#include \"qat_logs.h\"\n-\n-#include \"qat_crypto.h\"\n-#include \"qat_asym.h\"\n-#include \"qat_asym_pmd.h\"\n-\n-uint8_t qat_asym_driver_id;\n-struct qat_crypto_gen_dev_ops qat_asym_gen_dev_ops[QAT_N_GENS];\n-\n-void\n-qat_asym_init_op_cookie(void *op_cookie)\n-{\n-\tint j;\n-\tstruct qat_asym_op_cookie *cookie = op_cookie;\n-\n-\tcookie->input_addr = rte_mempool_virt2iova(cookie) +\n-\t\t\toffsetof(struct qat_asym_op_cookie,\n-\t\t\t\t\tinput_params_ptrs);\n-\n-\tcookie->output_addr = rte_mempool_virt2iova(cookie) +\n-\t\t\toffsetof(struct qat_asym_op_cookie,\n-\t\t\t\t\toutput_params_ptrs);\n-\n-\tfor (j = 0; j < 8; j++) {\n-\t\tcookie->input_params_ptrs[j] =\n-\t\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\t\toffsetof(struct qat_asym_op_cookie,\n-\t\t\t\t\t\tinput_array[j]);\n-\t\tcookie->output_params_ptrs[j] =\n-\t\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\t\toffsetof(struct qat_asym_op_cookie,\n-\t\t\t\t\t\toutput_array[j]);\n-\t}\n-}\n-\n-static struct rte_cryptodev_ops crypto_qat_ops = {\n-\n-\t/* Device related operations */\n-\t.dev_configure\t\t= qat_cryptodev_config,\n-\t.dev_start\t\t= qat_cryptodev_start,\n-\t.dev_stop\t\t= qat_cryptodev_stop,\n-\t.dev_close\t\t= qat_cryptodev_close,\n-\t.dev_infos_get\t\t= qat_cryptodev_info_get,\n-\n-\t.stats_get\t\t= qat_cryptodev_stats_get,\n-\t.stats_reset\t\t= qat_cryptodev_stats_reset,\n-\t.queue_pair_setup\t= qat_cryptodev_qp_setup,\n-\t.queue_pair_release\t= qat_cryptodev_qp_release,\n-\n-\t/* Crypto related operations */\n-\t.asym_session_get_size\t= qat_asym_session_get_private_size,\n-\t.asym_session_configure\t= qat_asym_session_configure,\n-\t.asym_session_clear\t= qat_asym_session_clear\n-};\n-\n-uint16_t qat_asym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n-\t\t\t\t uint16_t nb_ops)\n-{\n-\treturn qat_enqueue_op_burst(qp, NULL, (void **)ops, nb_ops);\n-}\n-\n-uint16_t qat_asym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n-\t\t\t\t uint16_t nb_ops)\n-{\n-\treturn qat_dequeue_op_burst(qp, (void **)ops, NULL, nb_ops);\n-}\n-\n-/* An rte_driver is needed in the registration of both the device and the driver\n- * with cryptodev.\n- * The actual qat pci's rte_driver can't be used as its name represents\n- * the whole pci device with all services. Think of this as a holder for a name\n- * for the crypto part of the pci device.\n- */\n-static const char qat_asym_drv_name[] = RTE_STR(CRYPTODEV_NAME_QAT_ASYM_PMD);\n-static const struct rte_driver cryptodev_qat_asym_driver = {\n-\t.name = qat_asym_drv_name,\n-\t.alias = qat_asym_drv_name\n-};\n-\n-int\n-qat_asym_dev_create(struct qat_pci_device *qat_pci_dev,\n-\t\tstruct qat_dev_cmd_param *qat_dev_cmd_param)\n-{\n-\tint i = 0;\n-\tstruct qat_device_info *qat_dev_instance =\n-\t\t\t&qat_pci_devs[qat_pci_dev->qat_dev_id];\n-\tstruct rte_cryptodev_pmd_init_params init_params = {\n-\t\t.name = \"\",\n-\t\t.socket_id = qat_dev_instance->pci_dev->device.numa_node,\n-\t\t.private_data_size = sizeof(struct qat_cryptodev_private)\n-\t};\n-\tstruct qat_capabilities_info capa_info;\n-\tconst struct rte_cryptodev_capabilities *capabilities;\n-\tconst struct qat_crypto_gen_dev_ops *gen_dev_ops =\n-\t\t&qat_asym_gen_dev_ops[qat_pci_dev->qat_dev_gen];\n-\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n-\tchar capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];\n-\tstruct rte_cryptodev *cryptodev;\n-\tstruct qat_cryptodev_private *internals;\n-\tuint64_t capa_size;\n-\n-\tsnprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, \"%s_%s\",\n-\t\t\tqat_pci_dev->name, \"asym\");\n-\tQAT_LOG(DEBUG, \"Creating QAT ASYM device %s\\n\", name);\n-\n-\tif (gen_dev_ops->cryptodev_ops == NULL) {\n-\t\tQAT_LOG(ERR, \"Device %s does not support asymmetric crypto\",\n-\t\t\t\tname);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n-\t\tqat_pci_dev->qat_asym_driver_id =\n-\t\t\t\tqat_asym_driver_id;\n-\t} else if (rte_eal_process_type() == RTE_PROC_SECONDARY) {\n-\t\tif (qat_pci_dev->qat_asym_driver_id !=\n-\t\t\t\tqat_asym_driver_id) {\n-\t\t\tQAT_LOG(ERR,\n-\t\t\t\t\"Device %s have different driver id than corresponding device in primary process\",\n-\t\t\t\tname);\n-\t\t\treturn -(EFAULT);\n-\t\t}\n-\t}\n-\n-\t/* Populate subset device to use in cryptodev device creation */\n-\tqat_dev_instance->asym_rte_dev.driver = &cryptodev_qat_asym_driver;\n-\tqat_dev_instance->asym_rte_dev.numa_node =\n-\t\t\tqat_dev_instance->pci_dev->device.numa_node;\n-\tqat_dev_instance->asym_rte_dev.devargs = NULL;\n-\n-\tcryptodev = rte_cryptodev_pmd_create(name,\n-\t\t\t&(qat_dev_instance->asym_rte_dev), &init_params);\n-\n-\tif (cryptodev == NULL)\n-\t\treturn -ENODEV;\n-\n-\tqat_dev_instance->asym_rte_dev.name = cryptodev->data->name;\n-\tcryptodev->driver_id = qat_asym_driver_id;\n-\tcryptodev->dev_ops = &crypto_qat_ops;\n-\n-\tcryptodev->enqueue_burst = qat_asym_pmd_enqueue_op_burst;\n-\tcryptodev->dequeue_burst = qat_asym_pmd_dequeue_op_burst;\n-\n-\n-\tcryptodev->feature_flags = gen_dev_ops->get_feature_flags(qat_pci_dev);\n-\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn 0;\n-\n-\tsnprintf(capa_memz_name, RTE_CRYPTODEV_NAME_MAX_LEN,\n-\t\t\t\"QAT_ASYM_CAPA_GEN_%d\",\n-\t\t\tqat_pci_dev->qat_dev_gen);\n-\n-\tinternals = cryptodev->data->dev_private;\n-\tinternals->qat_dev = qat_pci_dev;\n-\tinternals->dev_id = cryptodev->data->dev_id;\n-\tinternals->service_type = QAT_SERVICE_ASYMMETRIC;\n-\n-\tcapa_info = gen_dev_ops->get_capabilities(qat_pci_dev);\n-\tcapabilities = capa_info.data;\n-\tcapa_size = capa_info.size;\n-\n-\tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n-\tif (internals->capa_mz == NULL) {\n-\t\tinternals->capa_mz = rte_memzone_reserve(capa_memz_name,\n-\t\t\t\tcapa_size, rte_socket_id(), 0);\n-\t\tif (internals->capa_mz == NULL) {\n-\t\t\tQAT_LOG(DEBUG,\n-\t\t\t\t\"Error allocating memzone for capabilities, \"\n-\t\t\t\t\"destroying PMD for %s\",\n-\t\t\t\tname);\n-\t\t\trte_cryptodev_pmd_destroy(cryptodev);\n-\t\t\tmemset(&qat_dev_instance->asym_rte_dev, 0,\n-\t\t\t\tsizeof(qat_dev_instance->asym_rte_dev));\n-\t\t\treturn -EFAULT;\n-\t\t}\n-\t}\n-\n-\tmemcpy(internals->capa_mz->addr, capabilities, capa_size);\n-\tinternals->qat_dev_capabilities = internals->capa_mz->addr;\n-\n-\twhile (1) {\n-\t\tif (qat_dev_cmd_param[i].name == NULL)\n-\t\t\tbreak;\n-\t\tif (!strcmp(qat_dev_cmd_param[i].name, ASYM_ENQ_THRESHOLD_NAME))\n-\t\t\tinternals->min_enq_burst_threshold =\n-\t\t\t\t\tqat_dev_cmd_param[i].val;\n-\t\ti++;\n-\t}\n-\n-\tqat_pci_dev->asym_dev = internals;\n-\n-\trte_cryptodev_pmd_probing_finish(cryptodev);\n-\n-\tQAT_LOG(DEBUG, \"Created QAT ASYM device %s as cryptodev instance %d\",\n-\t\t\tcryptodev->data->name, internals->dev_id);\n-\treturn 0;\n-}\n-\n-int\n-qat_asym_dev_destroy(struct qat_pci_device *qat_pci_dev)\n-{\n-\tstruct rte_cryptodev *cryptodev;\n-\n-\tif (qat_pci_dev == NULL)\n-\t\treturn -ENODEV;\n-\tif (qat_pci_dev->asym_dev == NULL)\n-\t\treturn 0;\n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n-\t\trte_memzone_free(qat_pci_dev->asym_dev->capa_mz);\n-\n-\t/* free crypto device */\n-\tcryptodev = rte_cryptodev_pmd_get_dev(\n-\t\t\tqat_pci_dev->asym_dev->dev_id);\n-\trte_cryptodev_pmd_destroy(cryptodev);\n-\tqat_pci_devs[qat_pci_dev->qat_dev_id].asym_rte_dev.name = NULL;\n-\tqat_pci_dev->asym_dev = NULL;\n-\n-\treturn 0;\n-}\n-\n-static struct cryptodev_driver qat_crypto_drv;\n-RTE_PMD_REGISTER_CRYPTO_DRIVER(qat_crypto_drv,\n-\t\tcryptodev_qat_asym_driver,\n-\t\tqat_asym_driver_id);\ndiff --git a/drivers/crypto/qat/qat_asym_pmd.h b/drivers/crypto/qat/qat_asym_pmd.h\ndeleted file mode 100644\nindex f988d646e5..0000000000\n--- a/drivers/crypto/qat/qat_asym_pmd.h\n+++ /dev/null\n@@ -1,54 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2019 Intel Corporation\n- */\n-\n-\n-#ifndef _QAT_ASYM_PMD_H_\n-#define _QAT_ASYM_PMD_H_\n-\n-#include <rte_cryptodev.h>\n-#include \"qat_crypto.h\"\n-#include \"qat_device.h\"\n-\n-/** Intel(R) QAT Asymmetric Crypto PMD name */\n-#define CRYPTODEV_NAME_QAT_ASYM_PMD\tcrypto_qat_asym\n-\n-\n-/**\n- * Helper function to add an asym capability\n- * <name> <op type> <modlen (min, max, increment)>\n- **/\n-#define QAT_ASYM_CAP(n, o, l, r, i)\t\t\t\t\t\\\n-\t{\t\t\t\t\t\t\t\t\\\n-\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\t\t\t\\\n-\t\t{.asym = {\t\t\t\t\t\t\\\n-\t\t\t.xform_capa = {\t\t\t\t\t\\\n-\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_##n,\\\n-\t\t\t\t.op_types = o,\t\t\t\t\\\n-\t\t\t\t{\t\t\t\t\t\\\n-\t\t\t\t.modlen = {\t\t\t\t\\\n-\t\t\t\t.min = l,\t\t\t\t\\\n-\t\t\t\t.max = r,\t\t\t\t\\\n-\t\t\t\t.increment = i\t\t\t\t\\\n-\t\t\t\t}, }\t\t\t\t\t\\\n-\t\t\t}\t\t\t\t\t\t\\\n-\t\t},\t\t\t\t\t\t\t\\\n-\t\t}\t\t\t\t\t\t\t\\\n-\t}\n-\n-extern uint8_t qat_asym_driver_id;\n-\n-extern struct qat_crypto_gen_dev_ops qat_asym_gen_dev_ops[];\n-\n-void\n-qat_asym_init_op_cookie(void *op_cookie);\n-\n-uint16_t\n-qat_asym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n-\t\t\t uint16_t nb_ops);\n-\n-uint16_t\n-qat_asym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n-\t\t\t uint16_t nb_ops);\n-\n-#endif /* _QAT_ASYM_PMD_H_ */\n", "prefixes": [ "v9", "6/9" ] }