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GET /api/patches/108703/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 108703,
    "url": "http://patchwork.dpdk.org/api/patches/108703/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220314014414.251869-1-yajunw@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220314014414.251869-1-yajunw@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220314014414.251869-1-yajunw@nvidia.com",
    "date": "2022-03-14T01:44:12",
    "name": "vdpa/mlx5: workaround var offset within page",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c59402eea11316e9a558e69a9e7183e5aea01a3b",
    "submitter": {
        "id": 2517,
        "url": "http://patchwork.dpdk.org/api/people/2517/?format=api",
        "name": "Yajun Wu",
        "email": "yajunw@nvidia.com"
    },
    "delegate": {
        "id": 2642,
        "url": "http://patchwork.dpdk.org/api/users/2642/?format=api",
        "username": "mcoquelin",
        "first_name": "Maxime",
        "last_name": "Coquelin",
        "email": "maxime.coquelin@redhat.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220314014414.251869-1-yajunw@nvidia.com/mbox/",
    "series": [
        {
            "id": 22132,
            "url": "http://patchwork.dpdk.org/api/series/22132/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=22132",
            "date": "2022-03-14T01:44:12",
            "name": "vdpa/mlx5: workaround var offset within page",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/22132/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/108703/comments/",
    "check": "fail",
    "checks": "http://patchwork.dpdk.org/api/patches/108703/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Yajun Wu <yajunw@nvidia.com>",
        "To": "<orika@nvidia.com>, <viacheslavo@nvidia.com>, <matan@nvidia.com>,\n <shahafs@nvidia.com>, Maxime Coquelin <maxime.coquelin@redhat.com>",
        "CC": "<dev@dpdk.org>, <thomas@monjalon.net>, <rasland@nvidia.com>,\n <roniba@nvidia.com>, <stable@dpdk.org>",
        "Subject": "[PATCH] vdpa/mlx5: workaround var offset within page",
        "Date": "Mon, 14 Mar 2022 03:44:12 +0200",
        "Message-ID": "<20220314014414.251869-1-yajunw@nvidia.com>",
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    },
    "content": "vDPA driver first uses kernel driver to allocate doorbell(VAR) area for\neach device. Then uses var->mmap_off and var->length to mmap uverbs device\nfile as doorbell userspace virtual address.\n\nCurrent kernel driver provides var->mmap_off equal to page start of VAR.\nIt's fine with x86 4K page server, because VAR physical address is only 4K\naligned thus locate in 4K page start.\n\nBut with aarch64 64K page server, the actual VAR physical address has\noffset within page(not locate in 64K page start). So vDPA driver need add\nthis within page offset(caps.doorbell_bar_offset) to get right VAR virtual\naddress.\n\nFixes: 62c813706e4 (\"vdpa/mlx5: map doorbell\")\nCc: stable@dpdk.org\n\nSigned-off-by: Yajun Wu <yajunw@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 10 +++++++++-\n 1 file changed, 9 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\nindex 3416797d28..0748710a76 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\n@@ -9,6 +9,7 @@\n #include <rte_malloc.h>\n #include <rte_errno.h>\n #include <rte_io.h>\n+#include <rte_eal_paging.h>\n \n #include <mlx5_common.h>\n \n@@ -123,7 +124,10 @@ mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv)\n \t\tpriv->td = NULL;\n \t}\n \tif (priv->virtq_db_addr) {\n-\t\tclaim_zero(munmap(priv->virtq_db_addr, priv->var->length));\n+\t\t/* Mask out the within page offset for ummap. */\n+\t\tclaim_zero(munmap((void *)((uint64_t)priv->virtq_db_addr &\n+\t\t\t~(rte_mem_page_size() - 1ULL)),\n+\t\t\tpriv->var->length));\n \t\tpriv->virtq_db_addr = NULL;\n \t}\n \tpriv->features = 0;\n@@ -486,6 +490,10 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv)\n \t\tpriv->virtq_db_addr = NULL;\n \t\tgoto error;\n \t} else {\n+\t\t/* Add within page offset for 64K page system. */\n+\t\tpriv->virtq_db_addr = (char *)priv->virtq_db_addr +\n+\t\t\t((rte_mem_page_size() - 1) &\n+\t\t\tpriv->caps.doorbell_bar_offset);\n \t\tDRV_LOG(DEBUG, \"VAR address of doorbell mapping is %p.\",\n \t\t\tpriv->virtq_db_addr);\n \t}\n",
    "prefixes": []
}