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GET /api/patches/112836/?format=api
{ "id": 112836, "url": "http://patchwork.dpdk.org/api/patches/112836/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220616070743.30658-4-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220616070743.30658-4-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220616070743.30658-4-ndabilpuram@marvell.com", "date": "2022-06-16T07:07:35", "name": "[04/12] common/cnxk: support same TC value across multiple queues", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "c975d03ea634b1c609f1e1a958830122cf46e894", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220616070743.30658-4-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 23552, "url": "http://patchwork.dpdk.org/api/series/23552/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=23552", "date": "2022-06-16T07:07:32", "name": "[01/12] common/cnxk: use computed value for wqe skip", "version": 1, "mbox": "http://patchwork.dpdk.org/series/23552/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/112836/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/112836/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4BB63A00C3;\n\tThu, 16 Jun 2022 09:09:45 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3F19842BCB;\n\tThu, 16 Jun 2022 09:09:45 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 6DC54410D0\n for <dev@dpdk.org>; Thu, 16 Jun 2022 09:09:44 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 25G2BTk7015005\n for <dev@dpdk.org>; Thu, 16 Jun 2022 00:09:43 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gq83yx50b-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 16 Jun 2022 00:09:43 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 16 Jun 2022 00:09:41 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 16 Jun 2022 00:09:41 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 62FE83F709D;\n Thu, 16 Jun 2022 00:09:39 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=8Eqmuzbx1ZMRxdXAKmO4VzRyGnNSoA7z/hpAb1UpiEs=;\n b=Y2gqnzeeDYSco96vqcGF4EGAbLdJkPzasv4VZH77aMyKXQQcRt5w7SDXsx8jgJg2G4gl\n e3neRsD1x70uesiRuFMwbhz/+g74VhxJnWAgKrr2XrJa5IC+gHW5W4XAjwYrIfkt6L21\n drI90ZCFfwd9IQpy6eLQ8HZam0RVHL+QMoJK8CSgp4tqOLyCydtrHLIjn/P7tlRPvDTd\n sm3K0opKRx09ZomvqslvqtU6FnINJjUZzWV1qtOpoAmADuLxPny0elzrPETbf7IIFSsk\n s4oAmQapEqsaYOCmLP7Rp+SKkb2Jl00m1k73zJk5AuNcarPs3YkBtmHAmPWHG1gvAWAJ fw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Harman Kalra <hkalra@marvell.com>", "Subject": "[PATCH 04/12] common/cnxk: support same TC value across multiple\n queues", "Date": "Thu, 16 Jun 2022 12:37:35 +0530", "Message-ID": "<20220616070743.30658-4-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220616070743.30658-1-ndabilpuram@marvell.com>", "References": "<20220616070743.30658-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "dcj5nzo0fBVnzhC0v7RvSwkCOU1eRjRb", "X-Proofpoint-GUID": "dcj5nzo0fBVnzhC0v7RvSwkCOU1eRjRb", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-16_03,2022-06-15_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Harman Kalra <hkalra@marvell.com>\n\nUser may want to configure same TC value across multiple queues, but\nfor that all queues should have a common TL3 where this TC value will\nget configured.\n\nChanged the pfc_tc_cq_map/pfc_tc_sq_map array indexing to qid and store\nTC values in the array. As multiple queues may have same TC value.\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/common/cnxk/roc_dev.c | 18 ++++++++\n drivers/common/cnxk/roc_nix.h | 4 +-\n drivers/common/cnxk/roc_nix_fc.c | 2 +-\n drivers/common/cnxk/roc_nix_priv.h | 3 +-\n drivers/common/cnxk/roc_nix_tm.c | 87 ++++++++++++++++++++++++------------\n drivers/common/cnxk/roc_nix_tm_ops.c | 3 +-\n 6 files changed, 84 insertions(+), 33 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c\nindex 09199ac..59128a3 100644\n--- a/drivers/common/cnxk/roc_dev.c\n+++ b/drivers/common/cnxk/roc_dev.c\n@@ -421,6 +421,24 @@ process_msgs(struct dev *dev, struct mbox *mbox)\n \t\t\t/* Get our identity */\n \t\t\tdev->pf_func = msg->pcifunc;\n \t\t\tbreak;\n+\t\tcase MBOX_MSG_CGX_PRIO_FLOW_CTRL_CFG:\n+\t\t\t/* Handling the case where one VF tries to disable PFC\n+\t\t\t * while PFC already configured on other VFs. This is\n+\t\t\t * not an error but a warning which can be ignored.\n+\t\t\t */\n+#define LMAC_AF_ERR_PERM_DENIED -1103\n+\t\t\tif (msg->rc) {\n+\t\t\t\tif (msg->rc == LMAC_AF_ERR_PERM_DENIED) {\n+\t\t\t\t\tplt_mbox_dbg(\n+\t\t\t\t\t\t\"Receive Flow control disable not permitted \"\n+\t\t\t\t\t\t\"as its used by other PFVFs\");\n+\t\t\t\t\tmsg->rc = 0;\n+\t\t\t\t} else {\n+\t\t\t\t\tplt_err(\"Message (%s) response has err=%d\",\n+\t\t\t\t\t\tmbox_id2name(msg->id), msg->rc);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n \n \t\tdefault:\n \t\t\tif (msg->rc)\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex f0d7fc8..4e5cf05 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -11,7 +11,8 @@\n #define ROC_NIX_BPF_LEVEL_IDX_INVALID 0xFF\n #define ROC_NIX_BPF_LEVEL_MAX\t 3\n #define ROC_NIX_BPF_STATS_MAX\t 12\n-#define ROC_NIX_MTR_ID_INVALID UINT32_MAX\n+#define ROC_NIX_MTR_ID_INVALID\t UINT32_MAX\n+#define ROC_NIX_PFC_CLASS_INVALID UINT8_MAX\n \n enum roc_nix_rss_reta_sz {\n \tROC_NIX_RSS_RETA_SZ_64 = 64,\n@@ -349,6 +350,7 @@ struct roc_nix_sq {\n \tvoid *lmt_addr;\n \tvoid *sqe_mem;\n \tvoid *fc;\n+\tuint8_t tc;\n };\n \n struct roc_nix_link_info {\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex daae285..f4cfa11 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -312,7 +312,7 @@ roc_nix_fc_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \telse if (fc_cfg->type == ROC_NIX_FC_TM_CFG)\n \t\treturn nix_tm_bp_config_set(roc_nix, fc_cfg->tm_cfg.sq,\n \t\t\t\t\t fc_cfg->tm_cfg.tc,\n-\t\t\t\t\t fc_cfg->tm_cfg.enable);\n+\t\t\t\t\t fc_cfg->tm_cfg.enable, false);\n \n \treturn -EINVAL;\n }\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 5e865f8..5b0522c 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -100,6 +100,7 @@ struct nix_tm_node {\n \t/* Last stats */\n \tuint64_t last_pkts;\n \tuint64_t last_bytes;\n+\tuint32_t tc_refcnt;\n };\n \n struct nix_tm_shaper_profile {\n@@ -402,7 +403,7 @@ int nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable);\n int nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled);\n int nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n-\t\t\t bool enable);\n+\t\t\t bool enable, bool force_flush);\n void nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval);\n int nix_tm_mark_init(struct nix *nix);\n \ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex 151e217..a31abde 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -314,7 +314,7 @@ nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node)\n \n int\n nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n-\t\t bool enable)\n+\t\t bool enable, bool force_flush)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tenum roc_nix_tm_tree tree = nix->tm_tree;\n@@ -325,10 +325,15 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \tstruct nix_tm_node *sq_node;\n \tstruct nix_tm_node *parent;\n \tstruct nix_tm_node *node;\n+\tstruct roc_nix_sq *sq_s;\n \tuint8_t parent_lvl;\n \tuint8_t k = 0;\n \tint rc = 0;\n \n+\tsq_s = nix->sqs[sq];\n+\tif (!sq_s)\n+\t\treturn -ENOENT;\n+\n \tsq_node = nix_tm_node_search(nix, sq, nix->tm_tree);\n \tif (!sq_node)\n \t\treturn -ENOENT;\n@@ -348,11 +353,22 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \n \tlist = nix_tm_node_list(nix, tree);\n \n-\tif (parent->rel_chan != NIX_TM_CHAN_INVALID && parent->rel_chan != tc) {\n+\t/* Enable request, parent rel chan already configured */\n+\tif (enable && parent->rel_chan != NIX_TM_CHAN_INVALID &&\n+\t parent->rel_chan != tc) {\n \t\trc = -EINVAL;\n \t\tgoto err;\n \t}\n \n+\t/* No action if enable request for a non participating SQ. This case is\n+\t * required to handle post flush where TCs should be reconfigured after\n+\t * pre flush.\n+\t */\n+\tif (enable && sq_s->tc == ROC_NIX_PFC_CLASS_INVALID &&\n+\t tc == ROC_NIX_PFC_CLASS_INVALID)\n+\t\treturn 0;\n+\n+\t/* Find the parent TL3 */\n \tTAILQ_FOREACH(node, list, node) {\n \t\tif (node->hw_lvl != nix->tm_link_cfg_lvl)\n \t\t\tcontinue;\n@@ -360,38 +376,51 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \t\tif (!(node->flags & NIX_TM_NODE_HWRES) || !node->bp_capa)\n \t\t\tcontinue;\n \n-\t\tif (node->hw_id != parent->hw_id)\n-\t\t\tcontinue;\n-\n-\t\tif (!req) {\n-\t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\t\t\treq->lvl = nix->tm_link_cfg_lvl;\n-\t\t\tk = 0;\n+\t\t/* Restrict sharing of TL3 across the queues */\n+\t\tif (enable && node != parent && node->rel_chan == tc) {\n+\t\t\tplt_err(\"SQ %d node TL3 id %d already has %d tc value set\",\n+\t\t\t\tsq, node->hw_id, tc);\n+\t\t\treturn -EINVAL;\n \t\t}\n+\t}\n \n-\t\treq->reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(node->hw_id, link);\n-\t\treq->regval[k] = enable ? tc : 0;\n-\t\treq->regval[k] |= enable ? BIT_ULL(13) : 0;\n-\t\treq->regval_mask[k] = ~(BIT_ULL(13) | GENMASK_ULL(7, 0));\n-\t\tk++;\n-\n-\t\tif (k >= MAX_REGS_PER_MBOX_MSG) {\n-\t\t\treq->num_regs = k;\n-\t\t\trc = mbox_process(mbox);\n-\t\t\tif (rc)\n-\t\t\t\tgoto err;\n-\t\t\treq = NULL;\n-\t\t}\n+\t/* In case of user tree i.e. multiple SQs may share a TL3, disabling PFC\n+\t * on one of such SQ should not hamper the traffic control on other SQs.\n+\t * Maitaining a reference count scheme to account no of SQs sharing the\n+\t * TL3 before disabling PFC on it.\n+\t */\n+\tif (!force_flush && !enable &&\n+\t parent->rel_chan != NIX_TM_CHAN_INVALID) {\n+\t\tif (sq_s->tc != ROC_NIX_PFC_CLASS_INVALID)\n+\t\t\tparent->tc_refcnt--;\n+\t\tif (parent->tc_refcnt > 0)\n+\t\t\treturn 0;\n \t}\n \n-\tif (req) {\n-\t\treq->num_regs = k;\n-\t\trc = mbox_process(mbox);\n-\t\tif (rc)\n-\t\t\tgoto err;\n+\t/* Allocating TL3 resources */\n+\tif (!req) {\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq->lvl = nix->tm_link_cfg_lvl;\n+\t\tk = 0;\n \t}\n \n+\t/* Enable PFC on the identified TL3 */\n+\treq->reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(parent->hw_id, link);\n+\treq->regval[k] = enable ? tc : 0;\n+\treq->regval[k] |= enable ? BIT_ULL(13) : 0;\n+\treq->regval_mask[k] = ~(BIT_ULL(13) | GENMASK_ULL(7, 0));\n+\tk++;\n+\n+\treq->num_regs = k;\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\tgoto err;\n+\n \tparent->rel_chan = enable ? tc : NIX_TM_CHAN_INVALID;\n+\t/* Increase reference count for parent TL3 */\n+\tif (enable && sq_s->tc == ROC_NIX_PFC_CLASS_INVALID)\n+\t\tparent->tc_refcnt++;\n+\n \treturn 0;\n err:\n \tplt_err(\"Failed to %s bp on link %u, rc=%d(%s)\",\n@@ -629,7 +658,7 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n \t}\n \n \t/* Disable backpressure */\n-\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, false);\n+\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, false, true);\n \tif (rc) {\n \t\tplt_err(\"Failed to disable backpressure for flush, rc=%d\", rc);\n \t\treturn rc;\n@@ -764,7 +793,7 @@ nix_tm_sq_flush_post(struct roc_nix_sq *sq)\n \t\treturn 0;\n \n \t/* Restore backpressure */\n-\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, true);\n+\trc = nix_tm_bp_config_set(roc_nix, sq->qid, sq->tc, true, false);\n \tif (rc) {\n \t\tplt_err(\"Failed to restore backpressure, rc=%d\", rc);\n \t\treturn rc;\ndiff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c\nindex 5884ce5..4aa5500 100644\n--- a/drivers/common/cnxk/roc_nix_tm_ops.c\n+++ b/drivers/common/cnxk/roc_nix_tm_ops.c\n@@ -292,6 +292,7 @@ roc_nix_tm_node_add(struct roc_nix *roc_nix, struct roc_nix_tm_node *roc_node)\n \tnode->pkt_mode_set = roc_node->pkt_mode_set;\n \tnode->free_fn = roc_node->free_fn;\n \tnode->tree = ROC_NIX_TM_USER;\n+\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n \n \treturn nix_tm_node_add(roc_nix, node);\n }\n@@ -473,7 +474,7 @@ roc_nix_tm_hierarchy_disable(struct roc_nix *roc_nix)\n \t\tif (!sq)\n \t\t\tcontinue;\n \n-\t\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, false);\n+\t\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, false, false);\n \t\tif (rc && rc != -ENOENT) {\n \t\t\tplt_err(\"Failed to disable backpressure, rc=%d\", rc);\n \t\t\tgoto cleanup;\n", "prefixes": [ "04/12" ] }