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GET /api/patches/112846/?format=api
{ "id": 112846, "url": "http://patchwork.dpdk.org/api/patches/112846/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220616070743.30658-3-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220616070743.30658-3-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220616070743.30658-3-ndabilpuram@marvell.com", "date": "2022-06-16T07:07:34", "name": "[03/12] common/cnxk: add PFC support for VFs", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "0d79b7363ca92802cf5e1267bfd3f483a62d1a92", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220616070743.30658-3-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 23552, "url": "http://patchwork.dpdk.org/api/series/23552/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=23552", "date": "2022-06-16T07:07:32", "name": "[01/12] common/cnxk: use computed value for wqe skip", "version": 1, "mbox": "http://patchwork.dpdk.org/series/23552/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/112846/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/112846/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2ABD5A00C3;\n\tThu, 16 Jun 2022 09:12:09 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1BEF142BCA;\n\tThu, 16 Jun 2022 09:12:09 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 46AFF4114F\n for <dev@dpdk.org>; Thu, 16 Jun 2022 09:12:07 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 25G2BTY1015011;\n Thu, 16 Jun 2022 00:10:04 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gq83yx4yv-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 16 Jun 2022 00:10:03 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 16 Jun 2022 00:09:38 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 16 Jun 2022 00:09:38 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id E67073F7075;\n Thu, 16 Jun 2022 00:09:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=nA9S9d9oPariaZ7ZK39FrBEc3/Q8VGxm8u+Xp5Lg9TE=;\n b=XQLP2hnXIExNQrtodK48G/RiQmkGbazlWsVI+J8c8PHvUV4H8IvTQpa1DuegKBjVX9fA\n mDuZ0BRkb0J4dnJ41amPbvLW+kdAgAeGx05FGuuCeOUsiWdue8W9JNNRtTAbkHX6h5lV\n cqznWgfEhQn/iDISeTJrrGe4SFeU4eV5+Ibxulj/j7+j686Uowj/GL5YoYMQKaXQyACA\n Srt+H85OvlTgRc+i8lIExh3JhGRKxQm6kwS+mMjYJ1gchH8hEJi94s9yDWPnpVeETfxv\n 0anAIskxjZd7IobZy4U433JeIB4xQrJZ02Yq4lKAXjKPUy1tn8NL4J7rJICDBZeCJsIa KA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>, \"Pavan\n Nikhilesh\" <pbhagavatula@marvell.com>,\n Shijith Thotton <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 03/12] common/cnxk: add PFC support for VFs", "Date": "Thu, 16 Jun 2022 12:37:34 +0530", "Message-ID": "<20220616070743.30658-3-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220616070743.30658-1-ndabilpuram@marvell.com>", "References": "<20220616070743.30658-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "nQh2dKK5jlhRRRitqJVvoakAg-L-tON-", "X-Proofpoint-GUID": "nQh2dKK5jlhRRRitqJVvoakAg-L-tON-", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-16_03,2022-06-15_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nCurrent PFC implementation does not support VFs.\nPatch enables PFC on VFs too.\n\nAlso fix the config of aura.bp to be based on number\nof buffers(aura.limit) and corresponding shift\nvalue(aura.shift).\nFixes: cb4bfd6e7bdf (\"event/cnxk: support Rx adapter\")\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 14 +++-\n drivers/common/cnxk/roc_nix_fc.c | 120 +++++++++++++++++++++++++++----\n drivers/common/cnxk/roc_nix_priv.h | 2 +\n drivers/common/cnxk/roc_nix_queue.c | 47 ++++++++++++\n drivers/common/cnxk/roc_nix_tm.c | 67 +++++++++--------\n drivers/common/cnxk/version.map | 3 +-\n drivers/event/cnxk/cnxk_eventdev_adptr.c | 12 ++--\n drivers/net/cnxk/cnxk_ethdev.h | 2 +\n 8 files changed, 217 insertions(+), 50 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 944e4c6..f0d7fc8 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -157,6 +157,7 @@ struct roc_nix_fc_cfg {\n #define ROC_NIX_FC_RXCHAN_CFG 0\n #define ROC_NIX_FC_CQ_CFG 1\n #define ROC_NIX_FC_TM_CFG 2\n+#define ROC_NIX_FC_RQ_CFG 3\n \tuint8_t type;\n \tunion {\n \t\tstruct {\n@@ -171,6 +172,14 @@ struct roc_nix_fc_cfg {\n \t\t} cq_cfg;\n \n \t\tstruct {\n+\t\t\tuint32_t rq;\n+\t\t\tuint16_t tc;\n+\t\t\tuint16_t cq_drop;\n+\t\t\tbool enable;\n+\t\t\tuint64_t pool;\n+\t\t} rq_cfg;\n+\n+\t\tstruct {\n \t\t\tuint32_t sq;\n \t\t\tuint16_t tc;\n \t\t\tbool enable;\n@@ -791,8 +800,8 @@ uint16_t __roc_api roc_nix_chan_count_get(struct roc_nix *roc_nix);\n \n enum roc_nix_fc_mode __roc_api roc_nix_fc_mode_get(struct roc_nix *roc_nix);\n \n-void __roc_api rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id,\n-\t\t\t\t uint8_t ena, uint8_t force);\n+void __roc_api roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id,\n+\t\t\t\t uint8_t ena, uint8_t force, uint8_t tc);\n \n /* NPC */\n int __roc_api roc_nix_npc_promisc_ena_dis(struct roc_nix *roc_nix, int enable);\n@@ -845,6 +854,7 @@ int __roc_api roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq,\n int __roc_api roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq,\n \t\t\t\tbool ena);\n int __roc_api roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable);\n+int __roc_api roc_nix_rq_is_sso_enable(struct roc_nix *roc_nix, uint32_t qid);\n int __roc_api roc_nix_rq_fini(struct roc_nix_rq *rq);\n int __roc_api roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq);\n int __roc_api roc_nix_cq_fini(struct roc_nix_cq *cq);\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex cef5d07..daae285 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -148,6 +148,61 @@ nix_fc_cq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n }\n \n static int\n+nix_fc_rq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n+{\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix_aq_enq_rsp *rsp;\n+\tstruct npa_aq_enq_req *npa_req;\n+\tstruct npa_aq_enq_rsp *npa_rsp;\n+\tint rc;\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tstruct nix_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n+\t\taq->qidx = fc_cfg->rq_cfg.rq;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\t} else {\n+\t\tstruct nix_cn10k_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n+\t\taq->qidx = fc_cfg->rq_cfg.rq;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\t}\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tnpa_req = mbox_alloc_msg_npa_aq_enq(mbox);\n+\tif (!npa_req)\n+\t\treturn -ENOSPC;\n+\n+\tnpa_req->aura_id = rsp->rq.lpb_aura;\n+\tnpa_req->ctype = NPA_AQ_CTYPE_AURA;\n+\tnpa_req->op = NPA_AQ_INSTOP_READ;\n+\n+\trc = mbox_process_msg(mbox, (void *)&npa_rsp);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tfc_cfg->cq_cfg.cq_drop = npa_rsp->aura.bp;\n+\tfc_cfg->cq_cfg.enable = npa_rsp->aura.bp_ena;\n+\tfc_cfg->type = ROC_NIX_FC_RQ_CFG;\n+\n+exit:\n+\treturn rc;\n+}\n+\n+static int\n nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n@@ -198,6 +253,33 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \treturn mbox_process(mbox);\n }\n \n+static int\n+nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n+{\n+\tstruct roc_nix_fc_cfg tmp;\n+\tint sso_ena = 0;\n+\n+\t/* Check whether RQ is connected to SSO or not */\n+\tsso_ena = roc_nix_rq_is_sso_enable(roc_nix, fc_cfg->rq_cfg.rq);\n+\tif (sso_ena < 0)\n+\t\treturn -EINVAL;\n+\n+\tif (sso_ena)\n+\t\troc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool,\n+\t\t\t\t fc_cfg->rq_cfg.enable, true,\n+\t\t\t\t fc_cfg->rq_cfg.tc);\n+\n+\t/* Copy RQ config to CQ config as they are occupying same area */\n+\tmemset(&tmp, 0, sizeof(tmp));\n+\ttmp.type = ROC_NIX_FC_CQ_CFG;\n+\ttmp.cq_cfg.rq = fc_cfg->rq_cfg.rq;\n+\ttmp.cq_cfg.tc = fc_cfg->rq_cfg.tc;\n+\ttmp.cq_cfg.cq_drop = fc_cfg->rq_cfg.cq_drop;\n+\ttmp.cq_cfg.enable = fc_cfg->rq_cfg.enable;\n+\n+\treturn nix_fc_cq_config_set(roc_nix, &tmp);\n+}\n+\n int\n roc_nix_fc_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n {\n@@ -207,6 +289,8 @@ roc_nix_fc_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \n \tif (fc_cfg->type == ROC_NIX_FC_CQ_CFG)\n \t\treturn nix_fc_cq_config_get(roc_nix, fc_cfg);\n+\telse if (fc_cfg->type == ROC_NIX_FC_RQ_CFG)\n+\t\treturn nix_fc_rq_config_get(roc_nix, fc_cfg);\n \telse if (fc_cfg->type == ROC_NIX_FC_RXCHAN_CFG)\n \t\treturn nix_fc_rxchan_bpid_get(roc_nix, fc_cfg);\n \telse if (fc_cfg->type == ROC_NIX_FC_TM_CFG)\n@@ -218,12 +302,10 @@ roc_nix_fc_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n int\n roc_nix_fc_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n {\n-\tif (!roc_nix_is_pf(roc_nix) && !roc_nix_is_lbk(roc_nix) &&\n-\t !roc_nix_is_sdp(roc_nix))\n-\t\treturn 0;\n-\n \tif (fc_cfg->type == ROC_NIX_FC_CQ_CFG)\n \t\treturn nix_fc_cq_config_set(roc_nix, fc_cfg);\n+\telse if (fc_cfg->type == ROC_NIX_FC_RQ_CFG)\n+\t\treturn nix_fc_rq_config_set(roc_nix, fc_cfg);\n \telse if (fc_cfg->type == ROC_NIX_FC_RXCHAN_CFG)\n \t\treturn nix_fc_rxchan_bpid_set(roc_nix,\n \t\t\t\t\t fc_cfg->rxchan_cfg.enable);\n@@ -320,8 +402,8 @@ roc_nix_fc_mode_set(struct roc_nix *roc_nix, enum roc_nix_fc_mode mode)\n }\n \n void\n-rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n-\t\t uint8_t force)\n+roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n+\t\t uint8_t force, uint8_t tc)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct npa_lf *lf = idev_npa_obj_get();\n@@ -329,6 +411,7 @@ rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \tstruct npa_aq_enq_rsp *rsp;\n \tstruct mbox *mbox;\n \tuint32_t limit;\n+\tuint64_t shift;\n \tint rc;\n \n \tif (roc_nix_is_sdp(roc_nix))\n@@ -351,8 +434,10 @@ rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \t\treturn;\n \n \tlimit = rsp->aura.limit;\n+\tshift = rsp->aura.shift;\n+\n \t/* BP is already enabled. */\n-\tif (rsp->aura.bp_ena) {\n+\tif (rsp->aura.bp_ena && ena) {\n \t\tuint16_t bpid;\n \t\tbool nix1;\n \n@@ -363,12 +448,15 @@ rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \t\t\tbpid = rsp->aura.nix0_bpid;\n \n \t\t/* If BP ids don't match disable BP. */\n-\t\tif (((nix1 != nix->is_nix1) || (bpid != nix->bpid[0])) &&\n+\t\tif (((nix1 != nix->is_nix1) || (bpid != nix->bpid[tc])) &&\n \t\t !force) {\n \t\t\treq = mbox_alloc_msg_npa_aq_enq(mbox);\n \t\t\tif (req == NULL)\n \t\t\t\treturn;\n \n+\t\t\tplt_info(\"Disabling BP/FC on aura 0x%\" PRIx64\n+\t\t\t\t \" as it shared across ports or tc\",\n+\t\t\t\t pool_id);\n \t\t\treq->aura_id = roc_npa_aura_handle_to_aura(pool_id);\n \t\t\treq->ctype = NPA_AQ_CTYPE_AURA;\n \t\t\treq->op = NPA_AQ_INSTOP_WRITE;\n@@ -378,11 +466,15 @@ rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \n \t\t\tmbox_process(mbox);\n \t\t}\n+\n+\t\tif ((nix1 != nix->is_nix1) || (bpid != nix->bpid[tc]))\n+\t\t\tplt_info(\"Ignoring aura 0x%\" PRIx64 \"->%u bpid mapping\",\n+\t\t\t\t pool_id, nix->bpid[tc]);\n \t\treturn;\n \t}\n \n \t/* BP was previously enabled but now disabled skip. */\n-\tif (rsp->aura.bp)\n+\tif (rsp->aura.bp && ena)\n \t\treturn;\n \n \treq = mbox_alloc_msg_npa_aq_enq(mbox);\n@@ -395,14 +487,16 @@ rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \n \tif (ena) {\n \t\tif (nix->is_nix1) {\n-\t\t\treq->aura.nix1_bpid = nix->bpid[0];\n+\t\t\treq->aura.nix1_bpid = nix->bpid[tc];\n \t\t\treq->aura_mask.nix1_bpid = ~(req->aura_mask.nix1_bpid);\n \t\t} else {\n-\t\t\treq->aura.nix0_bpid = nix->bpid[0];\n+\t\t\treq->aura.nix0_bpid = nix->bpid[tc];\n \t\t\treq->aura_mask.nix0_bpid = ~(req->aura_mask.nix0_bpid);\n \t\t}\n-\t\treq->aura.bp = NIX_RQ_AURA_THRESH(\n-\t\t\tlimit > 128 ? 256 : limit); /* 95% of size*/\n+\t\treq->aura.bp = NIX_RQ_AURA_THRESH(limit >> shift);\n+\t\treq->aura_mask.bp = ~(req->aura_mask.bp);\n+\t} else {\n+\t\treq->aura.bp = 0;\n \t\treq->aura_mask.bp = ~(req->aura_mask.bp);\n \t}\n \ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex cc69d71..5e865f8 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -357,6 +357,8 @@ nix_tm_tree2str(enum roc_nix_tm_tree tree)\n \t\treturn \"Default Tree\";\n \telse if (tree == ROC_NIX_TM_RLIMIT)\n \t\treturn \"Rate Limit Tree\";\n+\telse if (tree == ROC_NIX_TM_PFC)\n+\t\treturn \"PFC Tree\";\n \telse if (tree == ROC_NIX_TM_USER)\n \t\treturn \"User Tree\";\n \treturn \"???\";\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 76c049c..fa4c954 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -94,6 +94,53 @@ roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable)\n }\n \n int\n+roc_nix_rq_is_sso_enable(struct roc_nix *roc_nix, uint32_t qid)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tstruct mbox *mbox = dev->mbox;\n+\tbool sso_enable;\n+\tint rc;\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tstruct nix_aq_enq_rsp *rsp;\n+\t\tstruct nix_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n+\t\taq->qidx = qid;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tsso_enable = rsp->rq.sso_ena;\n+\t} else {\n+\t\tstruct nix_cn10k_aq_enq_rsp *rsp;\n+\t\tstruct nix_cn10k_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n+\t\taq->qidx = qid;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tsso_enable = rsp->rq.sso_ena;\n+\t}\n+\n+\treturn sso_enable ? true : false;\n+}\n+\n+int\n nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,\n \t\tbool cfg, bool ena)\n {\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex 7fd54ef..151e217 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -98,7 +98,6 @@ int\n nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree)\n {\n \tstruct nix_tm_node_list *list;\n-\tbool is_pf_or_lbk = false;\n \tstruct nix_tm_node *node;\n \tbool skip_bp = false;\n \tuint32_t hw_lvl;\n@@ -106,9 +105,6 @@ nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree)\n \n \tlist = nix_tm_node_list(nix, tree);\n \n-\tif ((!dev_is_vf(&nix->dev) || nix->lbk_link) && !nix->sdp_link)\n-\t\tis_pf_or_lbk = true;\n-\n \tfor (hw_lvl = 0; hw_lvl <= nix->tm_root_lvl; hw_lvl++) {\n \t\tTAILQ_FOREACH(node, list, node) {\n \t\t\tif (node->hw_lvl != hw_lvl)\n@@ -118,7 +114,7 @@ nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree)\n \t\t\t * set per channel only for PF or lbk vf.\n \t\t\t */\n \t\t\tnode->bp_capa = 0;\n-\t\t\tif (is_pf_or_lbk && !skip_bp &&\n+\t\t\tif (!nix->sdp_link && !skip_bp &&\n \t\t\t node->hw_lvl == nix->tm_link_cfg_lvl) {\n \t\t\t\tnode->bp_capa = 1;\n \t\t\t\tskip_bp = false;\n@@ -329,6 +325,7 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \tstruct nix_tm_node *sq_node;\n \tstruct nix_tm_node *parent;\n \tstruct nix_tm_node *node;\n+\tuint8_t parent_lvl;\n \tuint8_t k = 0;\n \tint rc = 0;\n \n@@ -336,9 +333,12 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \tif (!sq_node)\n \t\treturn -ENOENT;\n \n+\tparent_lvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH2 :\n+\t\t ROC_TM_LVL_SCH1);\n+\n \tparent = sq_node->parent;\n \twhile (parent) {\n-\t\tif (parent->lvl == ROC_TM_LVL_SCH2)\n+\t\tif (parent->lvl == parent_lvl)\n \t\t\tbreak;\n \n \t\tparent = parent->parent;\n@@ -1469,16 +1469,18 @@ int\n roc_nix_tm_pfc_prepare_tree(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint8_t leaf_lvl, lvl, lvl_start, lvl_end;\n \tuint32_t nonleaf_id = nix->nb_tx_queues;\n \tstruct nix_tm_node *node = NULL;\n-\tuint8_t leaf_lvl, lvl, lvl_end;\n \tuint32_t tl2_node_id;\n \tuint32_t parent, i;\n \tint rc = -ENOMEM;\n \n \tparent = ROC_NIX_TM_NODE_ID_INVALID;\n-\tlvl_end = ROC_TM_LVL_SCH3;\n-\tleaf_lvl = ROC_TM_LVL_QUEUE;\n+\tlvl_end = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH3 :\n+\t\t ROC_TM_LVL_SCH2);\n+\tleaf_lvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_QUEUE :\n+\t\t ROC_TM_LVL_SCH4);\n \n \t/* TL1 node */\n \tnode = nix_tm_node_alloc();\n@@ -1501,31 +1503,37 @@ roc_nix_tm_pfc_prepare_tree(struct roc_nix *roc_nix)\n \tparent = nonleaf_id;\n \tnonleaf_id++;\n \n-\t/* TL2 node */\n-\trc = -ENOMEM;\n-\tnode = nix_tm_node_alloc();\n-\tif (!node)\n-\t\tgoto error;\n+\tlvl_start = ROC_TM_LVL_SCH1;\n+\tif (roc_nix_is_pf(roc_nix)) {\n+\t\t/* TL2 node */\n+\t\trc = -ENOMEM;\n+\t\tnode = nix_tm_node_alloc();\n+\t\tif (!node)\n+\t\t\tgoto error;\n \n-\tnode->id = nonleaf_id;\n-\tnode->parent_id = parent;\n-\tnode->priority = 0;\n-\tnode->weight = NIX_TM_DFLT_RR_WT;\n-\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n-\tnode->lvl = ROC_TM_LVL_SCH1;\n-\tnode->tree = ROC_NIX_TM_PFC;\n-\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n+\t\tnode->id = nonleaf_id;\n+\t\tnode->parent_id = parent;\n+\t\tnode->priority = 0;\n+\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\t\tnode->lvl = ROC_TM_LVL_SCH1;\n+\t\tnode->tree = ROC_NIX_TM_PFC;\n+\t\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n \n-\trc = nix_tm_node_add(roc_nix, node);\n-\tif (rc)\n-\t\tgoto error;\n+\t\trc = nix_tm_node_add(roc_nix, node);\n+\t\tif (rc)\n+\t\t\tgoto error;\n \n-\ttl2_node_id = nonleaf_id;\n-\tnonleaf_id++;\n+\t\tlvl_start = ROC_TM_LVL_SCH2;\n+\t\ttl2_node_id = nonleaf_id;\n+\t\tnonleaf_id++;\n+\t} else {\n+\t\ttl2_node_id = parent;\n+\t}\n \n \tfor (i = 0; i < nix->nb_tx_queues; i++) {\n \t\tparent = tl2_node_id;\n-\t\tfor (lvl = ROC_TM_LVL_SCH2; lvl <= lvl_end; lvl++) {\n+\t\tfor (lvl = lvl_start; lvl <= lvl_end; lvl++) {\n \t\t\trc = -ENOMEM;\n \t\t\tnode = nix_tm_node_alloc();\n \t\t\tif (!node)\n@@ -1549,7 +1557,8 @@ roc_nix_tm_pfc_prepare_tree(struct roc_nix *roc_nix)\n \t\t\tnonleaf_id++;\n \t\t}\n \n-\t\tlvl = ROC_TM_LVL_SCH4;\n+\t\tlvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH4 :\n+\t\t ROC_TM_LVL_SCH3);\n \n \t\trc = -ENOMEM;\n \t\tnode = nix_tm_node_alloc();\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 1ba5b4f..27e81f2 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -122,7 +122,7 @@ INTERNAL {\n \troc_nix_fc_config_set;\n \troc_nix_fc_mode_set;\n \troc_nix_fc_mode_get;\n-\trox_nix_fc_npa_bp_cfg;\n+\troc_nix_fc_npa_bp_cfg;\n \troc_nix_get_base_chan;\n \troc_nix_get_pf;\n \troc_nix_get_pf_func;\n@@ -220,6 +220,7 @@ INTERNAL {\n \troc_nix_rq_ena_dis;\n \troc_nix_rq_fini;\n \troc_nix_rq_init;\n+\troc_nix_rq_is_sso_enable;\n \troc_nix_rq_modify;\n \troc_nix_rss_default_setup;\n \troc_nix_rss_flowkey_set;\ndiff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c\nindex cf5b1dd..8fcc377 100644\n--- a/drivers/event/cnxk/cnxk_eventdev_adptr.c\n+++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c\n@@ -250,9 +250,11 @@ cnxk_sso_rx_adapter_queue_add(\n \t\t\t\trc |= roc_nix_rx_drop_re_set(&cnxk_eth_dev->nix,\n \t\t\t\t\t\t\t false);\n \t\t}\n-\t\trox_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix,\n-\t\t\t\t rxq_sp->qconf.mp->pool_id, true,\n-\t\t\t\t dev->force_ena_bp);\n+\n+\t\tif (rxq_sp->tx_pause)\n+\t\t\troc_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix,\n+\t\t\t\t\t rxq_sp->qconf.mp->pool_id, true,\n+\t\t\t\t\t dev->force_ena_bp, rxq_sp->tc);\n \t\tcnxk_eth_dev->nb_rxq_sso++;\n \t}\n \n@@ -293,9 +295,9 @@ cnxk_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,\n \t\trxq_sp = cnxk_eth_rxq_to_sp(\n \t\t\teth_dev->data->rx_queues[rx_queue_id]);\n \t\trc = cnxk_sso_rxq_disable(cnxk_eth_dev, (uint16_t)rx_queue_id);\n-\t\trox_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix,\n+\t\troc_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix,\n \t\t\t\t rxq_sp->qconf.mp->pool_id, false,\n-\t\t\t\t dev->force_ena_bp);\n+\t\t\t\t dev->force_ena_bp, 0);\n \t\tcnxk_eth_dev->nb_rxq_sso--;\n \n \t\t/* Enable drop_re if it was disabled earlier */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex e992302..0400d73 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -443,6 +443,8 @@ struct cnxk_eth_rxq_sp {\n \tstruct cnxk_eth_dev *dev;\n \tstruct cnxk_eth_qconf qconf;\n \tuint16_t qid;\n+\tuint8_t tx_pause;\n+\tuint8_t tc;\n } __plt_cache_aligned;\n \n struct cnxk_eth_txq_sp {\n", "prefixes": [ "03/12" ] }