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{
    "id": 114766,
    "url": "http://patchwork.dpdk.org/api/patches/114766/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220809184908.24030-1-ndabilpuram@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220809184908.24030-1-ndabilpuram@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220809184908.24030-1-ndabilpuram@marvell.com",
    "date": "2022-08-09T18:48:45",
    "name": "[01/23] common/cnxk: fix part value for cn10k",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "fe656909673f6e84852e1d4a45ab33f712a2826c",
    "submitter": {
        "id": 1202,
        "url": "http://patchwork.dpdk.org/api/people/1202/?format=api",
        "name": "Nithin Dabilpuram",
        "email": "ndabilpuram@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patchwork.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220809184908.24030-1-ndabilpuram@marvell.com/mbox/",
    "series": [
        {
            "id": 24239,
            "url": "http://patchwork.dpdk.org/api/series/24239/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=24239",
            "date": "2022-08-09T18:48:45",
            "name": "[01/23] common/cnxk: fix part value for cn10k",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/24239/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/114766/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/114766/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        ],
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        "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>",
        "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>",
        "CC": "<jerinj@marvell.com>, <dev@dpdk.org>, Harman Kalra <hkalra@marvell.com>",
        "Subject": "[PATCH 01/23] common/cnxk: fix part value for cn10k",
        "Date": "Wed, 10 Aug 2022 00:18:45 +0530",
        "Message-ID": "<20220809184908.24030-1-ndabilpuram@marvell.com>",
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    },
    "content": "From: Harman Kalra <hkalra@marvell.com>\n\nUpdating the logic for getting part and pass value for cn10k family,\nas device tree compatible logic does not work in VMs.\nScanning all the PCI device and detect first RVU device, subsystem\ndevice file gives part no and revision file provide pass information.\n\nFixes: 014a9e222bac (\"common/cnxk: add model init and IO handling API\")\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n\nDepends-on: series-23650(\"[v2] event/cnxk: add eth port specific PTP enable\")\nDepends-on: series-24029(\"[1/4] cnxk/net: add fc check in vector event Tx path\")\n\n drivers/common/cnxk/roc_model.c    | 152 +++++++++++++++++++++++++++----------\n drivers/common/cnxk/roc_platform.h |   3 +\n 2 files changed, 113 insertions(+), 42 deletions(-)",
    "diff": "diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c\nindex a68baa6..791ffa6 100644\n--- a/drivers/common/cnxk/roc_model.c\n+++ b/drivers/common/cnxk/roc_model.c\n@@ -2,6 +2,7 @@\n  * Copyright(C) 2021 Marvell.\n  */\n \n+#include <dirent.h>\n #include <fcntl.h>\n #include <unistd.h>\n \n@@ -40,6 +41,16 @@ struct roc_model *roc_model;\n #define MODEL_MINOR_SHIFT 0\n #define MODEL_MINOR_MASK  ((1 << MODEL_MINOR_BITS) - 1)\n \n+#define MODEL_CN10K_PART_SHIFT\t8\n+#define MODEL_CN10K_PASS_BITS\t4\n+#define MODEL_CN10K_PASS_MASK\t((1 << MODEL_CN10K_PASS_BITS) - 1)\n+#define MODEL_CN10K_MAJOR_BITS\t2\n+#define MODEL_CN10K_MAJOR_SHIFT 2\n+#define MODEL_CN10K_MAJOR_MASK\t((1 << MODEL_CN10K_MAJOR_BITS) - 1)\n+#define MODEL_CN10K_MINOR_BITS\t2\n+#define MODEL_CN10K_MINOR_SHIFT 0\n+#define MODEL_CN10K_MINOR_MASK\t((1 << MODEL_CN10K_MINOR_BITS) - 1)\n+\n static const struct model_db {\n \tuint32_t impl;\n \tuint32_t part;\n@@ -66,55 +77,101 @@ static const struct model_db {\n \t{VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,\n \t \"cnf95xxmm_a0\"}};\n \n-static uint32_t\n-cn10k_part_get(void)\n+/* Detect if RVU device */\n+static bool\n+is_rvu_device(unsigned long val)\n {\n-\tuint32_t soc = 0x0;\n-\tchar buf[BUFSIZ];\n-\tchar *ptr;\n-\tFILE *fd;\n-\n-\t/* Read the CPU compatible variant */\n-\tfd = fopen(\"/proc/device-tree/compatible\", \"r\");\n-\tif (!fd) {\n-\t\tplt_err(\"Failed to open /proc/device-tree/compatible\");\n-\t\tgoto err;\n-\t}\n+\treturn (val == PCI_DEVID_CNXK_RVU_PF || val == PCI_DEVID_CNXK_RVU_VF ||\n+\t\tval == PCI_DEVID_CNXK_RVU_AF ||\n+\t\tval == PCI_DEVID_CNXK_RVU_AF_VF ||\n+\t\tval == PCI_DEVID_CNXK_RVU_NPA_PF ||\n+\t\tval == PCI_DEVID_CNXK_RVU_NPA_VF ||\n+\t\tval == PCI_DEVID_CNXK_RVU_SSO_TIM_PF ||\n+\t\tval == PCI_DEVID_CNXK_RVU_SSO_TIM_VF ||\n+\t\tval == PCI_DEVID_CN10K_RVU_CPT_PF ||\n+\t\tval == PCI_DEVID_CN10K_RVU_CPT_VF);\n+}\n \n-\tif (fgets(buf, sizeof(buf), fd) == NULL) {\n-\t\tplt_err(\"Failed to read from /proc/device-tree/compatible\");\n-\t\tgoto fclose;\n-\t}\n-\tptr = strchr(buf, ',');\n-\tif (!ptr) {\n-\t\tplt_err(\"Malformed 'CPU compatible': <%s>\", buf);\n-\t\tgoto fclose;\n-\t}\n-\tptr++;\n-\tif (strcmp(\"cn10ka\", ptr) == 0) {\n-\t\tsoc = PART_106xx;\n-\t} else if (strcmp(\"cnf10ka\", ptr) == 0) {\n-\t\tsoc = PART_105xx;\n-\t} else if (strcmp(\"cnf10kb\", ptr) == 0) {\n-\t\tsoc = PART_105xxN;\n-\t} else if (strcmp(\"cn10kb\", ptr) == 0) {\n-\t\tsoc = PART_103xx;\n-\t} else {\n-\t\tplt_err(\"Unidentified 'CPU compatible': <%s>\", ptr);\n-\t\tgoto fclose;\n+static int\n+rvu_device_lookup(const char *dirname, uint32_t *part, uint32_t *pass)\n+{\n+\tchar filename[PATH_MAX];\n+\tunsigned long val;\n+\n+\t/* Check if vendor id is cavium */\n+\tsnprintf(filename, sizeof(filename), \"%s/vendor\", dirname);\n+\tif (plt_sysfs_value_parse(filename, &val) < 0)\n+\t\tgoto error;\n+\n+\tif (val != PCI_VENDOR_ID_CAVIUM)\n+\t\tgoto error;\n+\n+\t/* Get device id  */\n+\tsnprintf(filename, sizeof(filename), \"%s/device\", dirname);\n+\tif (plt_sysfs_value_parse(filename, &val) < 0)\n+\t\tgoto error;\n+\n+\t/* Check if device ID belongs to any RVU device */\n+\tif (!is_rvu_device(val))\n+\t\tgoto error;\n+\n+\t/* Get subsystem_device id */\n+\tsnprintf(filename, sizeof(filename), \"%s/subsystem_device\", dirname);\n+\tif (plt_sysfs_value_parse(filename, &val) < 0)\n+\t\tgoto error;\n+\n+\t*part = val >> MODEL_CN10K_PART_SHIFT;\n+\n+\t/* Get revision for pass value*/\n+\tsnprintf(filename, sizeof(filename), \"%s/revision\", dirname);\n+\tif (plt_sysfs_value_parse(filename, &val) < 0)\n+\t\tgoto error;\n+\n+\t*pass = val & MODEL_CN10K_PASS_MASK;\n+\n+\treturn 0;\n+error:\n+\treturn -EINVAL;\n+}\n+\n+/* Scans through all PCI devices, detects RVU device and returns\n+ * subsystem_device\n+ */\n+static int\n+cn10k_part_pass_get(uint32_t *part, uint32_t *pass)\n+{\n+#define SYSFS_PCI_DEVICES \"/sys/bus/pci/devices\"\n+\tchar dirname[PATH_MAX];\n+\tstruct dirent *e;\n+\tDIR *dir;\n+\n+\tdir = opendir(SYSFS_PCI_DEVICES);\n+\tif (dir == NULL) {\n+\t\tplt_err(\"%s(): opendir failed: %s\\n\", __func__,\n+\t\t\tstrerror(errno));\n+\t\treturn -errno;\n \t}\n \n-fclose:\n-\tfclose(fd);\n+\twhile ((e = readdir(dir)) != NULL) {\n+\t\tif (e->d_name[0] == '.')\n+\t\t\tcontinue;\n+\n+\t\tsnprintf(dirname, sizeof(dirname), \"%s/%s\", SYSFS_PCI_DEVICES,\n+\t\t\t e->d_name);\n+\n+\t\t/* Lookup for rvu device and get part pass information */\n+\t\tif (!rvu_device_lookup(dirname, part, pass))\n+\t\t\tbreak;\n+\t}\n \n-err:\n-\treturn soc;\n+\tclosedir(dir);\n+\treturn 0;\n }\n \n static bool\n populate_model(struct roc_model *model, uint32_t midr)\n {\n-\tuint32_t impl, major, part, minor;\n+\tuint32_t impl, major, part, minor, pass;\n \tbool found = false;\n \tsize_t i;\n \n@@ -124,8 +181,19 @@ populate_model(struct roc_model *model, uint32_t midr)\n \tminor = (midr >> MODEL_MINOR_SHIFT) & MODEL_MINOR_MASK;\n \n \t/* Update part number for cn10k from device-tree */\n-\tif (part == SOC_PART_CN10K)\n-\t\tpart = cn10k_part_get();\n+\tif (part == SOC_PART_CN10K) {\n+\t\tif (cn10k_part_pass_get(&part, &pass))\n+\t\t\tgoto not_found;\n+\t\t/*\n+\t\t * Pass value format:\n+\t\t * Bits 0..1: minor pass\n+\t\t * Bits 3..2: major pass\n+\t\t */\n+\t\tminor = (pass >> MODEL_CN10K_MINOR_SHIFT) &\n+\t\t\tMODEL_CN10K_MINOR_MASK;\n+\t\tmajor = (pass >> MODEL_CN10K_MAJOR_SHIFT) &\n+\t\t\tMODEL_CN10K_MAJOR_MASK;\n+\t}\n \n \tfor (i = 0; i < PLT_DIM(model_db); i++)\n \t\tif (model_db[i].impl == impl && model_db[i].part == part &&\n@@ -136,7 +204,7 @@ populate_model(struct roc_model *model, uint32_t midr)\n \t\t\tfound = true;\n \t\t\tbreak;\n \t\t}\n-\n+not_found:\n \tif (!found) {\n \t\tmodel->flag = 0;\n \t\tstrncpy(model->name, \"unknown\", ROC_MODEL_STR_LEN_MAX - 1);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 502f243..3e7adfc 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -24,6 +24,8 @@\n #include <rte_tailq.h>\n #include <rte_telemetry.h>\n \n+#include \"eal_filesystem.h\"\n+\n #include \"roc_bits.h\"\n \n #if defined(__ARM_FEATURE_SVE)\n@@ -94,6 +96,7 @@\n #define plt_pci_device\t\t    rte_pci_device\n #define plt_pci_read_config\t    rte_pci_read_config\n #define plt_pci_find_ext_capability rte_pci_find_ext_capability\n+#define plt_sysfs_value_parse\t    eal_parse_sysfs_value\n \n #define plt_log2_u32\t rte_log2_u32\n #define plt_cpu_to_be_16 rte_cpu_to_be_16\n",
    "prefixes": [
        "01/23"
    ]
}