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GET /api/patches/114771/?format=api
{ "id": 114771, "url": "http://patchwork.dpdk.org/api/patches/114771/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220809184908.24030-11-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220809184908.24030-11-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220809184908.24030-11-ndabilpuram@marvell.com", "date": "2022-08-09T18:48:55", "name": "[11/23] net/cnxk: support for zero aura for inline meta", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "24957d11bce350a12ad4b8b462d8f37864af6641", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220809184908.24030-11-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 24239, "url": "http://patchwork.dpdk.org/api/series/24239/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=24239", "date": "2022-08-09T18:48:45", "name": "[01/23] common/cnxk: fix part value for cn10k", "version": 1, "mbox": "http://patchwork.dpdk.org/series/24239/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/114771/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/114771/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AA0CAA04FD;\n\tTue, 9 Aug 2022 20:50:28 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 95A2042BF0;\n\tTue, 9 Aug 2022 20:50:28 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id EC94A42BE6\n for <dev@dpdk.org>; Tue, 9 Aug 2022 20:50:26 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 279D65ar015667\n for <dev@dpdk.org>; Tue, 9 Aug 2022 11:50:26 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3huds2ukub-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 09 Aug 2022 11:50:26 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 9 Aug 2022 11:50:24 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 9 Aug 2022 11:50:24 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id B3C543F710A;\n Tue, 9 Aug 2022 11:50:11 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=BMuD9MHVYqex+60Y7IBQHMsHwLmjLxQRpYAgWukFois=;\n b=GSk5IG/O2nt80k5HwbPAm2+j+4twKmxaaW+jjW3nv3KVhNsF/ZhHnrhpLbm44H3mnL+B\n RUbIZXS3nE/9CQUZXF+HtxwjXjqvt4LEBL43j4POgdtNkg7nd2UG8bkQYfmRV0o9z29K\n +8YUpI15RwyXi8372NvGjVNSVFyA1qKDnokhdbvYAzU3JQA/Z8cfWcfDqmybeabWOKMg\n qiIhPRxHmbjm5nZgI3uI7H/cpM2n/0PHVDmoomAHCu/AsYu9Soz0CGr4vjY1y72wPjwE\n s1bP6/VDWwIh8wdSO3ffT0JAmWHTmt+JujlMNvrTu0gl+35B+mdGWwMg/nO5SHURGl2J 2w==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Pavan Nikhilesh <pbhagavatula@marvell.com>, Shijith Thotton\n <sthotton@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 11/23] net/cnxk: support for zero aura for inline meta", "Date": "Wed, 10 Aug 2022 00:18:55 +0530", "Message-ID": "<20220809184908.24030-11-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220809184908.24030-1-ndabilpuram@marvell.com>", "References": "<20220809184908.24030-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "LugDM89iE3ddNJ7pkX4AJo7mT2IQ7S9H", "X-Proofpoint-GUID": "LugDM89iE3ddNJ7pkX4AJo7mT2IQ7S9H", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1\n definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for zero aura for inline meta pkts and register\ncallback to ROC to create meta pool via mempool. Also\nadd devargs to override meta buffer count and size.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/event/cnxk/cn10k_eventdev.c | 8 ++-\n drivers/event/cnxk/cn10k_worker.h | 32 ++++++-----\n drivers/event/cnxk/cnxk_eventdev.h | 1 +\n drivers/event/cnxk/cnxk_eventdev_adptr.c | 2 +-\n drivers/net/cnxk/cn10k_ethdev.c | 8 ++-\n drivers/net/cnxk/cn10k_ethdev.h | 2 +-\n drivers/net/cnxk/cn10k_rx.h | 35 +++++++-----\n drivers/net/cnxk/cnxk_ethdev.c | 3 +\n drivers/net/cnxk/cnxk_ethdev.h | 2 +\n drivers/net/cnxk/cnxk_ethdev_sec.c | 97 +++++++++++++++++++++++++++++++-\n 10 files changed, 154 insertions(+), 36 deletions(-)", "diff": "diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex db61606..0651b2d 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -694,7 +694,7 @@ cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,\n }\n \n static void\n-cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem)\n+cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem, uint64_t meta_aura)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tint i;\n@@ -703,6 +703,8 @@ cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem)\n \t\tstruct cn10k_sso_hws *ws = event_dev->data->ports[i];\n \t\tws->lookup_mem = lookup_mem;\n \t\tws->tstamp = dev->tstamp;\n+\t\tif (meta_aura)\n+\t\t\tws->meta_aura = meta_aura;\n \t}\n }\n \n@@ -713,6 +715,7 @@ cn10k_sso_rx_adapter_queue_add(\n \tconst struct rte_event_eth_rx_adapter_queue_conf *queue_conf)\n {\n \tstruct cn10k_eth_rxq *rxq;\n+\tuint64_t meta_aura;\n \tvoid *lookup_mem;\n \tint rc;\n \n@@ -726,7 +729,8 @@ cn10k_sso_rx_adapter_queue_add(\n \t\treturn -EINVAL;\n \trxq = eth_dev->data->rx_queues[0];\n \tlookup_mem = rxq->lookup_mem;\n-\tcn10k_sso_set_priv_mem(event_dev, lookup_mem);\n+\tmeta_aura = rxq->meta_aura;\n+\tcn10k_sso_set_priv_mem(event_dev, lookup_mem, meta_aura);\n \tcn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);\n \n \treturn 0;\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex db56d96..47ce423 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -127,12 +127,14 @@ cn10k_sso_process_tstamp(uint64_t u64, uint64_t mbuf,\n }\n \n static __rte_always_inline void\n-cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,\n-\t\t void *lookup_mem, void *tstamp, uintptr_t lbase)\n+cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, struct cn10k_sso_hws *ws)\n {\n \tuint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM;\n+\tstruct cnxk_timesync_info *tstamp = ws->tstamp[port_id];\n+\tvoid *lookup_mem = ws->lookup_mem;\n+\tuintptr_t lbase = ws->lmt_base;\n \tstruct rte_event_vector *vec;\n-\tuint64_t aura_handle, laddr;\n+\tuint64_t meta_aura, laddr;\n \tuint16_t nb_mbufs, non_vec;\n \tuint16_t lmt_id, d_off;\n \tstruct rte_mbuf **wqe;\n@@ -153,25 +155,31 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,\n \tif (flags & NIX_RX_OFFLOAD_TSTAMP_F && tstamp)\n \t\tmbuf_init |= 8;\n \n+\tmeta_aura = ws->meta_aura;\n \tnb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);\n \tnb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, wqe, nb_mbufs,\n-\t\t\t\t\t flags | NIX_RX_VWQE_F, lookup_mem,\n-\t\t\t\t\t tstamp, lbase);\n+\t\t\t\t\t flags | NIX_RX_VWQE_F,\n+\t\t\t\t\t lookup_mem, tstamp,\n+\t\t\t\t\t lbase, meta_aura);\n \twqe += nb_mbufs;\n \tnon_vec = vec->nb_elem - nb_mbufs;\n \n \tif (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) {\n+\t\tuint64_t sg_w1;\n+\n \t\tmbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] -\n \t\t\t\t\t sizeof(struct rte_mbuf));\n \t\t/* Pick first mbuf's aura handle assuming all\n \t\t * mbufs are from a vec and are from same RQ.\n \t\t */\n-\t\taura_handle = mbuf->pool->pool_id;\n+\t\tmeta_aura = ws->meta_aura;\n+\t\tif (!meta_aura)\n+\t\t\tmeta_aura = mbuf->pool->pool_id;\n \t\tROC_LMT_BASE_ID_GET(lbase, lmt_id);\n \t\tladdr = lbase;\n \t\tladdr += 8;\n-\t\td_off = ((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf);\n-\t\td_off += (mbuf_init & 0xFFFF);\n+\t\tsg_w1 = *(uint64_t *)(((uintptr_t)wqe[0]) + 72);\n+\t\td_off = sg_w1 - (uintptr_t)mbuf;\n \t\tsa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem);\n \t\tsa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);\n \t}\n@@ -208,7 +216,7 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,\n \n \t/* Free remaining meta buffers if any */\n \tif (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {\n-\t\tnix_sec_flush_meta(laddr, lmt_id, loff, aura_handle);\n+\t\tnix_sec_flush_meta(laddr, lmt_id, loff, meta_aura);\n \t\tplt_io_wmb();\n \t}\n }\n@@ -241,8 +249,7 @@ cn10k_sso_hws_post_process(struct cn10k_sso_hws *ws, uint64_t *u64,\n \t\t\tuint64_t cq_w5;\n \n \t\t\tm = (struct rte_mbuf *)mbuf;\n-\t\t\td_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m;\n-\t\t\td_off += RTE_PKTMBUF_HEADROOM;\n+\t\t\td_off = (*(uint64_t *)(u64[1] + 72)) - (uintptr_t)m;\n \n \t\t\tcq_w1 = *(uint64_t *)(u64[1] + 8);\n \t\t\tcq_w5 = *(uint64_t *)(u64[1] + 40);\n@@ -273,8 +280,7 @@ cn10k_sso_hws_post_process(struct cn10k_sso_hws *ws, uint64_t *u64,\n \t\tvwqe_hdr = ((vwqe_hdr >> 64) & 0xFFF) | BIT_ULL(31) |\n \t\t\t ((vwqe_hdr & 0xFFFF) << 48) | ((uint64_t)port << 32);\n \t\t*(uint64_t *)u64[1] = (uint64_t)vwqe_hdr;\n-\t\tcn10k_process_vwqe(u64[1], port, flags, ws->lookup_mem,\n-\t\t\t\t ws->tstamp[port], ws->lmt_base);\n+\t\tcn10k_process_vwqe(u64[1], port, flags, ws);\n \t\t/* Mark vector mempool object as get */\n \t\tRTE_MEMPOOL_CHECK_COOKIES(rte_mempool_from_obj((void *)u64[1]),\n \t\t\t\t\t (void **)&u64[1], 1, 1);\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex fae4484..d61e60d 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -148,6 +148,7 @@ struct cn10k_sso_hws {\n \tuint8_t hws_id;\n \t/* PTP timestamp */\n \tstruct cnxk_timesync_info **tstamp;\n+\tuint64_t meta_aura;\n \t/* Add Work Fastpath data */\n \tuint64_t xaq_lmt __rte_cache_aligned;\n \tuint64_t *fc_mem;\ndiff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c\nindex 7937cad..5f51c50 100644\n--- a/drivers/event/cnxk/cnxk_eventdev_adptr.c\n+++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c\n@@ -194,7 +194,7 @@ cnxk_sso_rx_adapter_vwqe_enable(struct cnxk_eth_dev *cnxk_eth_dev,\n \n \trq->vwqe_ena = 1;\n \trq->vwqe_first_skip = 0;\n-\trq->vwqe_aura_handle = roc_npa_aura_handle_to_aura(vmp->pool_id);\n+\trq->vwqe_aura_handle = vmp->pool_id;\n \trq->vwqe_max_sz_exp = rte_log2_u32(sz);\n \trq->vwqe_wait_tmo =\n \t\ttmo_ns /\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c\nindex 80c5c0e..e8faeeb 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.c\n+++ b/drivers/net/cnxk/cn10k_ethdev.c\n@@ -282,9 +282,13 @@ cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\trxq->lmt_base = dev->nix.lmt_base;\n \t\trxq->sa_base = roc_nix_inl_inb_sa_base_get(&dev->nix,\n \t\t\t\t\t\t\t dev->inb.inl_dev);\n+\t\trxq->meta_aura = rq->meta_aura_handle;\n+\t\trxq_sp = cnxk_eth_rxq_to_sp(rxq);\n+\t\t/* Assume meta packet from normal aura if meta aura is not setup\n+\t\t */\n+\t\tif (!rxq->meta_aura)\n+\t\t\trxq->meta_aura = rxq_sp->qconf.mp->pool_id;\n \t}\n-\trxq_sp = cnxk_eth_rxq_to_sp(rxq);\n-\trxq->aura_handle = rxq_sp->qconf.mp->pool_id;\n \n \t/* Lookup mem */\n \trxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h\nindex acfdbb6..d0a5b13 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.h\n+++ b/drivers/net/cnxk/cn10k_ethdev.h\n@@ -39,7 +39,7 @@ struct cn10k_eth_rxq {\n \tuint16_t data_off;\n \tuint64_t sa_base;\n \tuint64_t lmt_base;\n-\tuint64_t aura_handle;\n+\tuint64_t meta_aura;\n \tuint16_t rq;\n \tstruct cnxk_timesync_info *tstamp;\n } __plt_cache_aligned;\ndiff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex 0f8790b..2cd297e 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -877,7 +877,7 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \tnb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n \n \tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n-\t\taura_handle = rxq->aura_handle;\n+\t\taura_handle = rxq->meta_aura;\n \t\tsa_base = rxq->sa_base;\n \t\tsa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);\n \t\tROC_LMT_BASE_ID_GET(lbase, lmt_id);\n@@ -984,7 +984,7 @@ static __rte_always_inline uint16_t\n cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t const uint16_t flags, void *lookup_mem,\n \t\t\t struct cnxk_timesync_info *tstamp,\n-\t\t\t uintptr_t lmt_base)\n+\t\t\t uintptr_t lmt_base, uint64_t meta_aura)\n {\n \tstruct cn10k_eth_rxq *rxq = args;\n \tconst uint64_t mbuf_initializer = (flags & NIX_RX_VWQE_F) ?\n@@ -1003,10 +1003,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \tuint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer);\n \tuint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);\n \tstruct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n-\tuint64_t aura_handle, lbase, laddr;\n \tuint8_t loff = 0, lnum = 0, shft = 0;\n \tuint8x16_t f0, f1, f2, f3;\n \tuint16_t lmt_id, d_off;\n+\tuint64_t lbase, laddr;\n \tuint16_t packets = 0;\n \tuint16_t pkts_left;\n \tuintptr_t sa_base;\n@@ -1035,6 +1035,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \n \tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n \t\tif (flags & NIX_RX_VWQE_F) {\n+\t\t\tuint64_t sg_w1;\n \t\t\tuint16_t port;\n \n \t\t\tmbuf0 = (struct rte_mbuf *)((uintptr_t)mbufs[0] -\n@@ -1042,10 +1043,15 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t/* Pick first mbuf's aura handle assuming all\n \t\t\t * mbufs are from a vec and are from same RQ.\n \t\t\t */\n-\t\t\taura_handle = mbuf0->pool->pool_id;\n+\t\t\tif (!meta_aura)\n+\t\t\t\tmeta_aura = mbuf0->pool->pool_id;\n \t\t\t/* Calculate offset from mbuf to actual data area */\n-\t\t\td_off = ((uintptr_t)mbuf0->buf_addr - (uintptr_t)mbuf0);\n-\t\t\td_off += (mbuf_initializer & 0xFFFF);\n+\t\t\t/* Zero aura's first skip i.e mbuf setup might not match the actual\n+\t\t\t * offset as first skip is taken from second pass RQ. So compute\n+\t\t\t * using diff b/w first SG pointer and mbuf addr.\n+\t\t\t */\n+\t\t\tsg_w1 = *(uint64_t *)((uintptr_t)mbufs[0] + 72);\n+\t\t\td_off = (sg_w1 - (uint64_t)mbuf0);\n \n \t\t\t/* Get SA Base from lookup tbl using port_id */\n \t\t\tport = mbuf_initializer >> 48;\n@@ -1053,7 +1059,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \n \t\t\tlbase = lmt_base;\n \t\t} else {\n-\t\t\taura_handle = rxq->aura_handle;\n+\t\t\tmeta_aura = rxq->meta_aura;\n \t\t\td_off = rxq->data_off;\n \t\t\tsa_base = rxq->sa_base;\n \t\t\tlbase = rxq->lmt_base;\n@@ -1721,7 +1727,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\t/* Update aura handle */\n \t\t\t\t*(uint64_t *)(laddr - 8) =\n \t\t\t\t\t(((uint64_t)(15 & 0x1) << 32) |\n-\t\t\t\t roc_npa_aura_handle_to_aura(aura_handle));\n+\t\t\t\t roc_npa_aura_handle_to_aura(meta_aura));\n \t\t\t\tloff = loff - 15;\n \t\t\t\tshft += 3;\n \n@@ -1744,14 +1750,14 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\t/* Update aura handle */\n \t\t\t\t*(uint64_t *)(laddr - 8) =\n \t\t\t\t\t(((uint64_t)(loff & 0x1) << 32) |\n-\t\t\t\t roc_npa_aura_handle_to_aura(aura_handle));\n+\t\t\t\t roc_npa_aura_handle_to_aura(meta_aura));\n \n \t\t\t\tdata = (data & ~(0x7UL << shft)) |\n \t\t\t\t (((uint64_t)loff >> 1) << shft);\n \n \t\t\t\t/* Send up to 16 lmt lines of pointers */\n \t\t\t\tnix_sec_flush_meta_burst(lmt_id, data, lnum + 1,\n-\t\t\t\t\t\t\t aura_handle);\n+\t\t\t\t\t\t\t meta_aura);\n \t\t\t\trte_io_wmb();\n \t\t\t\tlnum = 0;\n \t\t\t\tloff = 0;\n@@ -1769,13 +1775,13 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t/* Update aura handle */\n \t\t*(uint64_t *)(laddr - 8) =\n \t\t\t(((uint64_t)(loff & 0x1) << 32) |\n-\t\t\t roc_npa_aura_handle_to_aura(aura_handle));\n+\t\t\t roc_npa_aura_handle_to_aura(meta_aura));\n \n \t\tdata = (data & ~(0x7UL << shft)) |\n \t\t (((uint64_t)loff >> 1) << shft);\n \n \t\t/* Send up to 16 lmt lines of pointers */\n-\t\tnix_sec_flush_meta_burst(lmt_id, data, lnum + 1, aura_handle);\n+\t\tnix_sec_flush_meta_burst(lmt_id, data, lnum + 1, meta_aura);\n \t\tif (flags & NIX_RX_VWQE_F)\n \t\t\tplt_io_wmb();\n \t}\n@@ -1803,7 +1809,7 @@ static inline uint16_t\n cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t const uint16_t flags, void *lookup_mem,\n \t\t\t struct cnxk_timesync_info *tstamp,\n-\t\t\t uintptr_t lmt_base)\n+\t\t\t uintptr_t lmt_base, uint64_t meta_aura)\n {\n \tRTE_SET_USED(args);\n \tRTE_SET_USED(mbufs);\n@@ -1812,6 +1818,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \tRTE_SET_USED(lookup_mem);\n \tRTE_SET_USED(tstamp);\n \tRTE_SET_USED(lmt_base);\n+\tRTE_SET_USED(meta_aura);\n \n \treturn 0;\n }\n@@ -2038,7 +2045,7 @@ NIX_RX_FASTPATH_MODES\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n \t{ \\\n \t\treturn cn10k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \\\n-\t\t\t\t\t\t (flags), NULL, NULL, 0); \\\n+\t\t\t\t\t\t (flags), NULL, NULL, 0, 0); \\\n \t}\n \n #define NIX_RX_RECV_VEC_MSEG(fn, flags) \\\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex b3af2f8..02416ad 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -1732,6 +1732,9 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)\n \troc_nix_mac_link_info_get_cb_register(nix,\n \t\t\t\t\t cnxk_eth_dev_link_status_get_cb);\n \n+\t/* Register callback for inline meta pool create */\n+\troc_nix_inl_meta_pool_cb_register(cnxk_nix_inl_meta_pool_cb);\n+\n \tdev->eth_dev = eth_dev;\n \tdev->configured = 0;\n \tdev->ptype_disable = 0;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 4cb7c9e..be5cecd 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -641,6 +641,8 @@ struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev,\n struct cnxk_eth_sec_sess *\n cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,\n \t\t\t struct rte_security_session *sess);\n+int cnxk_nix_inl_meta_pool_cb(uint64_t *aura_handle, uint32_t buf_sz, uint32_t nb_bufs,\n+\t\t\t bool destroy);\n \n /* Other private functions */\n int nix_recalc_mtu(struct rte_eth_dev *eth_dev);\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c\nindex 1de3454..9304b14 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_sec.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c\n@@ -4,10 +4,14 @@\n \n #include <cnxk_ethdev.h>\n \n+#define CNXK_NIX_INL_META_POOL_NAME \"NIX_INL_META_POOL\"\n+\n #define CNXK_NIX_INL_SELFTEST\t \"selftest\"\n #define CNXK_NIX_INL_IPSEC_IN_MIN_SPI \"ipsec_in_min_spi\"\n #define CNXK_NIX_INL_IPSEC_IN_MAX_SPI \"ipsec_in_max_spi\"\n #define CNXK_INL_CPT_CHANNEL\t \"inl_cpt_channel\"\n+#define CNXK_NIX_INL_NB_META_BUFS \"nb_meta_bufs\"\n+#define CNXK_NIX_INL_META_BUF_SZ \"meta_buf_sz\"\n \n struct inl_cpt_channel {\n \tbool is_multi_channel;\n@@ -29,6 +33,85 @@ bitmap_ctzll(uint64_t slab)\n }\n \n int\n+cnxk_nix_inl_meta_pool_cb(uint64_t *aura_handle, uint32_t buf_sz, uint32_t nb_bufs, bool destroy)\n+{\n+\tconst char *mp_name = CNXK_NIX_INL_META_POOL_NAME;\n+\tstruct rte_pktmbuf_pool_private mbp_priv;\n+\tstruct npa_aura_s *aura;\n+\tstruct rte_mempool *mp;\n+\tuint16_t first_skip;\n+\tint rc;\n+\n+\t/* Destroy the mempool if requested */\n+\tif (destroy) {\n+\t\tmp = rte_mempool_lookup(mp_name);\n+\t\tif (!mp)\n+\t\t\treturn -ENOENT;\n+\n+\t\tif (mp->pool_id != *aura_handle) {\n+\t\t\tplt_err(\"Meta pool aura mismatch\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tplt_free(mp->pool_config);\n+\t\trte_mempool_free(mp);\n+\n+\t\t*aura_handle = 0;\n+\t\treturn 0;\n+\t}\n+\n+\t/* Need to make it similar to rte_pktmbuf_pool() for sake of OOP\n+\t * support.\n+\t */\n+\tmp = rte_mempool_create_empty(mp_name, nb_bufs, buf_sz, 0,\n+\t\t\t\t sizeof(struct rte_pktmbuf_pool_private),\n+\t\t\t\t SOCKET_ID_ANY, 0);\n+\tif (!mp) {\n+\t\tplt_err(\"Failed to create inline meta pool\");\n+\t\treturn -EIO;\n+\t}\n+\n+\t/* Indicate to allocate zero aura */\n+\taura = plt_zmalloc(sizeof(struct npa_aura_s), 0);\n+\tif (!aura) {\n+\t\trc = -ENOMEM;\n+\t\tgoto free_mp;\n+\t}\n+\taura->ena = 1;\n+\taura->pool_addr = 0x0;\n+\n+\trc = rte_mempool_set_ops_byname(mp, rte_mbuf_platform_mempool_ops(),\n+\t\t\t\t\taura);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to setup mempool ops for meta, rc=%d\", rc);\n+\t\tgoto free_aura;\n+\t}\n+\n+\t/* Init mempool private area */\n+\tfirst_skip = sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM;\n+\tmemset(&mbp_priv, 0, sizeof(mbp_priv));\n+\tmbp_priv.mbuf_data_room_size = (buf_sz - first_skip +\n+\t\t\t\t\tRTE_PKTMBUF_HEADROOM);\n+\trte_pktmbuf_pool_init(mp, &mbp_priv);\n+\n+\t/* Populate buffer */\n+\trc = rte_mempool_populate_default(mp);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to create inline meta pool, rc=%d\", rc);\n+\t\tgoto free_aura;\n+\t}\n+\n+\trte_mempool_obj_iter(mp, rte_pktmbuf_init, NULL);\n+\t*aura_handle = mp->pool_id;\n+\treturn 0;\n+free_aura:\n+\tplt_free(aura);\n+free_mp:\n+\trte_mempool_free(mp);\n+\treturn rc;\n+}\n+\n+int\n cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev, uint32_t *idx_p,\n \t\t\t uint32_t spi)\n {\n@@ -128,7 +211,7 @@ struct rte_security_ops cnxk_eth_sec_ops = {\n };\n \n static int\n-parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args)\n+parse_val_u32(const char *key, const char *value, void *extra_args)\n {\n \tRTE_SET_USED(key);\n \tuint32_t val;\n@@ -184,6 +267,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,\n \tuint32_t ipsec_in_min_spi = 0;\n \tstruct inl_cpt_channel cpt_channel;\n \tstruct rte_kvargs *kvlist;\n+\tuint32_t nb_meta_bufs = 0;\n+\tuint32_t meta_buf_sz = 0;\n \tuint8_t selftest = 0;\n \n \tmemset(&cpt_channel, 0, sizeof(cpt_channel));\n@@ -198,11 +283,15 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,\n \trte_kvargs_process(kvlist, CNXK_NIX_INL_SELFTEST, &parse_selftest,\n \t\t\t &selftest);\n \trte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MIN_SPI,\n-\t\t\t &parse_ipsec_in_spi_range, &ipsec_in_min_spi);\n+\t\t\t &parse_val_u32, &ipsec_in_min_spi);\n \trte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MAX_SPI,\n-\t\t\t &parse_ipsec_in_spi_range, &ipsec_in_max_spi);\n+\t\t\t &parse_val_u32, &ipsec_in_max_spi);\n \trte_kvargs_process(kvlist, CNXK_INL_CPT_CHANNEL, &parse_inl_cpt_channel,\n \t\t\t &cpt_channel);\n+\trte_kvargs_process(kvlist, CNXK_NIX_INL_NB_META_BUFS, &parse_val_u32,\n+\t\t\t &nb_meta_bufs);\n+\trte_kvargs_process(kvlist, CNXK_NIX_INL_META_BUF_SZ, &parse_val_u32,\n+\t\t\t &meta_buf_sz);\n \trte_kvargs_free(kvlist);\n \n null_devargs:\n@@ -212,6 +301,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,\n \tinl_dev->channel = cpt_channel.channel;\n \tinl_dev->chan_mask = cpt_channel.mask;\n \tinl_dev->is_multi_channel = cpt_channel.is_multi_channel;\n+\tinl_dev->nb_meta_bufs = nb_meta_bufs;\n+\tinl_dev->meta_buf_sz = meta_buf_sz;\n \treturn 0;\n exit:\n \treturn -EINVAL;\n", "prefixes": [ "11/23" ] }