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GET /api/patches/117578/?format=api
{ "id": 117578, "url": "http://patchwork.dpdk.org/api/patches/117578/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221007172921.3325250-4-andrew.rybchenko@oktetlabs.ru/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221007172921.3325250-4-andrew.rybchenko@oktetlabs.ru>", "list_archive_url": "https://inbox.dpdk.org/dev/20221007172921.3325250-4-andrew.rybchenko@oktetlabs.ru", "date": "2022-10-07T17:29:20", "name": "[v8,3/4] net/cnxk: support mulitiple mbuf pools per Rx queue", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f6061dd2a35bf9b05017a93762bf46c061d03a06", "submitter": { "id": 2013, "url": "http://patchwork.dpdk.org/api/people/2013/?format=api", "name": "Andrew Rybchenko", "email": "Andrew.Rybchenko@oktetlabs.ru" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221007172921.3325250-4-andrew.rybchenko@oktetlabs.ru/mbox/", "series": [ { "id": 25036, "url": "http://patchwork.dpdk.org/api/series/25036/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25036", "date": "2022-10-07T17:29:17", "name": "ethdev: support mulitiple mbuf pools per Rx queue", "version": 8, "mbox": "http://patchwork.dpdk.org/series/25036/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/117578/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/117578/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 874F9A00C4;\n\tFri, 7 Oct 2022 19:29:40 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3B86742802;\n\tFri, 7 Oct 2022 19:29:29 +0200 (CEST)", "from shelob.oktetlabs.ru (shelob.oktetlabs.ru [91.220.146.113])\n by mails.dpdk.org (Postfix) with ESMTP id 58EA042670\n for <dev@dpdk.org>; Fri, 7 Oct 2022 19:29:25 +0200 (CEST)", "by shelob.oktetlabs.ru (Postfix, from userid 115)\n id 2006799; Fri, 7 Oct 2022 20:29:25 +0300 (MSK)", "from aros.oktetlabs.ru (aros.oktetlabs.ru [192.168.38.17])\n by shelob.oktetlabs.ru (Postfix) with ESMTP id 40DE188;\n Fri, 7 Oct 2022 20:29:23 +0300 (MSK)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on mail1.oktetlabs.ru", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.8 required=5.0 tests=ALL_TRUSTED,\n DKIM_ADSP_DISCARD,\n URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6", "DKIM-Filter": "OpenDKIM Filter v2.11.0 shelob.oktetlabs.ru 40DE188", "Authentication-Results": "shelob.oktetlabs.ru/40DE188; dkim=none;\n dkim-atps=neutral", "From": "Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>,\n Kiran Kumar K <kirankumark@marvell.com>,\n Sunil Kumar Kori <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>", "Cc": "dev@dpdk.org,\n\tHanumanth Pothula <hpothula@marvell.com>", "Subject": "[PATCH v8 3/4] net/cnxk: support mulitiple mbuf pools per Rx queue", "Date": "Fri, 7 Oct 2022 20:29:20 +0300", "Message-Id": "<20221007172921.3325250-4-andrew.rybchenko@oktetlabs.ru>", "X-Mailer": "git-send-email 2.30.2", "In-Reply-To": "<20221007172921.3325250-1-andrew.rybchenko@oktetlabs.ru>", "References": "<20221006170126.1322852-1-hpothula@marvell.com>\n <20221007172921.3325250-1-andrew.rybchenko@oktetlabs.ru>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Hanumanth Pothula <hpothula@marvell.com>\n\nPresently, HW is programmed only to receive packets from LPB pool.\nMaking all packets received from LPB pool.\n\nBut, CNXK HW supports two pools,\n - SPB -> packets with smaller size (less than 4K)\n - LPB -> packets with bigger size (greater than 4K)\n\nPatch enables multiple mempool capability, pool is selected based\non the packet's length. So, basically, PMD programs HW for receiving\npackets from both SPB and LPB pools based on the packet's length.\n\nThis is achieved by enabling rx multiple mempool offload,\nRTE_ETH_RX_OFFLOAD_MUL_MEMPOOL. This allows the application to send\nmore than one pool(in our case two) to the driver, with different\nsegment(packet) lengths, which helps the driver to configure both\npools based on segment lengths.\n\nThis is often useful for saving the memory where the application\ncan create a different pool to steer the specific size of the\npacket, thus enabling effective use of memory.\n\nSigned-off-by: Hanumanth Pothula <hpothula@marvell.com>\n---\n drivers/net/cnxk/cnxk_ethdev.c | 84 ++++++++++++++++++++++++++----\n drivers/net/cnxk/cnxk_ethdev.h | 2 +\n drivers/net/cnxk/cnxk_ethdev_ops.c | 3 ++\n 3 files changed, 80 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 2cb48ba152..bb27cc87fd 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -541,6 +541,58 @@ cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)\n \tplt_free(txq_sp);\n }\n \n+static int\n+cnxk_nix_process_rx_conf(const struct rte_eth_rxconf *rx_conf,\n+\t\t\t struct rte_mempool **lpb_pool,\n+\t\t\t struct rte_mempool **spb_pool)\n+{\n+\tstruct rte_mempool *pool0;\n+\tstruct rte_mempool *pool1;\n+\tstruct rte_mempool **mp = rx_conf->rx_mempools;\n+\tconst char *platform_ops;\n+\tstruct rte_mempool_ops *ops;\n+\n+\tif (*lpb_pool ||\n+\t rx_conf->rx_nmempool != CNXK_NIX_NUM_POOLS_MAX) {\n+\t\tplt_err(\"invalid arguments\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (mp == NULL || mp[0] == NULL || mp[1] == NULL) {\n+\t\tplt_err(\"invalid memory pools\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpool0 = mp[0];\n+\tpool1 = mp[1];\n+\n+\tif (pool0->elt_size > pool1->elt_size) {\n+\t\t*lpb_pool = pool0;\n+\t\t*spb_pool = pool1;\n+\n+\t} else {\n+\t\t*lpb_pool = pool1;\n+\t\t*spb_pool = pool0;\n+\t}\n+\n+\tif ((*spb_pool)->pool_id == 0) {\n+\t\tplt_err(\"Invalid pool_id\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tplatform_ops = rte_mbuf_platform_mempool_ops();\n+\tops = rte_mempool_get_ops((*spb_pool)->ops_index);\n+\tif (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {\n+\t\tplt_err(\"mempool ops should be of cnxk_npa type\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tplt_info(\"spb_pool:%s lpb_pool:%s lpb_len:%u spb_len:%u\\n\", (*spb_pool)->name,\n+\t\t (*lpb_pool)->name, (*lpb_pool)->elt_size, (*spb_pool)->elt_size);\n+\n+\treturn 0;\n+}\n+\n int\n cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\t\tuint32_t nb_desc, uint16_t fp_rx_q_sz,\n@@ -557,6 +609,8 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tuint16_t first_skip;\n \tint rc = -EINVAL;\n \tsize_t rxq_sz;\n+\tstruct rte_mempool *lpb_pool = mp;\n+\tstruct rte_mempool *spb_pool = NULL;\n \n \t/* Sanity checks */\n \tif (rx_conf->rx_deferred_start == 1) {\n@@ -564,15 +618,21 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\tgoto fail;\n \t}\n \n+\tif (rx_conf->rx_nmempool > 0) {\n+\t\trc = cnxk_nix_process_rx_conf(rx_conf, &lpb_pool, &spb_pool);\n+\t\tif (rc)\n+\t\t\tgoto fail;\n+\t}\n+\n \tplatform_ops = rte_mbuf_platform_mempool_ops();\n \t/* This driver needs cnxk_npa mempool ops to work */\n-\tops = rte_mempool_get_ops(mp->ops_index);\n+\tops = rte_mempool_get_ops(lpb_pool->ops_index);\n \tif (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {\n \t\tplt_err(\"mempool ops should be of cnxk_npa type\");\n \t\tgoto fail;\n \t}\n \n-\tif (mp->pool_id == 0) {\n+\tif (lpb_pool->pool_id == 0) {\n \t\tplt_err(\"Invalid pool_id\");\n \t\tgoto fail;\n \t}\n@@ -589,13 +649,13 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t/* Its a no-op when inline device is not used */\n \tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY ||\n \t dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)\n-\t\troc_nix_inl_dev_xaq_realloc(mp->pool_id);\n+\t\troc_nix_inl_dev_xaq_realloc(lpb_pool->pool_id);\n \n \t/* Increase CQ size to Aura size to avoid CQ overflow and\n \t * then CPT buffer leak.\n \t */\n \tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)\n-\t\tnb_desc = nix_inl_cq_sz_clamp_up(nix, mp, nb_desc);\n+\t\tnb_desc = nix_inl_cq_sz_clamp_up(nix, lpb_pool, nb_desc);\n \n \t/* Setup ROC CQ */\n \tcq = &dev->cqs[qid];\n@@ -611,17 +671,17 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \trq = &dev->rqs[qid];\n \trq->qid = qid;\n \trq->cqid = cq->qid;\n-\trq->aura_handle = mp->pool_id;\n+\trq->aura_handle = lpb_pool->pool_id;\n \trq->flow_tag_width = 32;\n \trq->sso_ena = false;\n \n \t/* Calculate first mbuf skip */\n \tfirst_skip = (sizeof(struct rte_mbuf));\n \tfirst_skip += RTE_PKTMBUF_HEADROOM;\n-\tfirst_skip += rte_pktmbuf_priv_size(mp);\n+\tfirst_skip += rte_pktmbuf_priv_size(lpb_pool);\n \trq->first_skip = first_skip;\n \trq->later_skip = sizeof(struct rte_mbuf);\n-\trq->lpb_size = mp->elt_size;\n+\trq->lpb_size = lpb_pool->elt_size;\n \tif (roc_errata_nix_no_meta_aura())\n \t\trq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);\n \n@@ -629,6 +689,12 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tif (roc_nix_inl_inb_is_enabled(nix))\n \t\trq->ipsech_ena = true;\n \n+\tif (spb_pool) {\n+\t\trq->spb_ena = 1;\n+\t\trq->spb_aura_handle = spb_pool->pool_id;\n+\t\trq->spb_size = spb_pool->elt_size;\n+\t}\n+\n \trc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);\n \tif (rc) {\n \t\tplt_err(\"Failed to init roc rq for rq=%d, rc=%d\", qid, rc);\n@@ -651,7 +717,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t/* Queue config should reflect global offloads */\n \trxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;\n \trxq_sp->qconf.nb_desc = nb_desc;\n-\trxq_sp->qconf.mp = mp;\n+\trxq_sp->qconf.mp = lpb_pool;\n \trxq_sp->tc = 0;\n \trxq_sp->tx_pause = (dev->fc_cfg.mode == RTE_ETH_FC_FULL ||\n \t\t\t dev->fc_cfg.mode == RTE_ETH_FC_TX_PAUSE);\n@@ -670,7 +736,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\t\tgoto free_mem;\n \t}\n \n-\tplt_nix_dbg(\"rq=%d pool=%s nb_desc=%d->%d\", qid, mp->name, nb_desc,\n+\tplt_nix_dbg(\"rq=%d pool=%s nb_desc=%d->%d\", qid, lpb_pool->name, nb_desc,\n \t\t cq->nb_desc);\n \n \t/* Store start of fast path area */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 5204c46244..d282f79a9a 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -44,6 +44,8 @@\n #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096\n /* Max supported SQB count */\n #define CNXK_NIX_TX_MAX_SQB 512\n+/* LPB & SPB */\n+#define CNXK_NIX_NUM_POOLS_MAX 2\n \n /* If PTP is enabled additional SEND MEM DESC is required which\n * takes 2 words, hence max 7 iova address are possible\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c\nindex 30d169f799..8f7287161b 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_ops.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c\n@@ -69,6 +69,9 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)\n \tdevinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |\n \t\t\t RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP |\n \t\t\t RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;\n+\n+\tdevinfo->max_rx_mempools = CNXK_NIX_NUM_POOLS_MAX;\n+\n \treturn 0;\n }\n \n", "prefixes": [ "v8", "3/4" ] }