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GET /api/patches/118751/?format=api
{ "id": 118751, "url": "http://patchwork.dpdk.org/api/patches/118751/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221020062951.645121-13-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221020062951.645121-13-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221020062951.645121-13-junfeng.guo@intel.com", "date": "2022-10-20T06:29:49", "name": "[v8,12/14] net/idpf: add support for write back based on ITR expire", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5fb59d950c29e8b5578ac79e691c9ee5d9c3698c", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 3961, "url": "http://patchwork.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221020062951.645121-13-junfeng.guo@intel.com/mbox/", "series": [ { "id": 25330, "url": "http://patchwork.dpdk.org/api/series/25330/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25330", "date": "2022-10-20T06:29:37", "name": "add support for idpf PMD in DPDK", "version": 8, "mbox": "http://patchwork.dpdk.org/series/25330/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/118751/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/118751/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 31C38A0A02;\n\tThu, 20 Oct 2022 08:34:24 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A7FFC42D30;\n\tThu, 20 Oct 2022 08:32:18 +0200 (CEST)", "from mga06.intel.com (mga06b.intel.com [134.134.136.31])\n by mails.dpdk.org (Postfix) with ESMTP id 955EA42CD6\n for <dev@dpdk.org>; Thu, 20 Oct 2022 08:32:14 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 Oct 2022 23:32:14 -0700", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by orsmga006.jf.intel.com with ESMTP; 19 Oct 2022 23:32:12 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1666247534; x=1697783534;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=vjFddImf6OZw155uNBA/HlLWoRnen/nB+AV/Ljui+Wc=;\n b=USpp+e6qRlIIJp/7Z9q7hHTyryLEBrpkWFNtzr4fU9LHDfMpZicqDIjI\n QpTP9P7+3LZj4zrilG7jlYzNJq8DV9CMiql6kcuMo97asZrdVw3GXtzG6\n rWxr9wOihbLorpa9vbCXlXhj3nlj9HoPEI2He0Tiz3Ol6NzjMAuo8Xx9J\n /9sLlXmA/MAR50sEKZeVw4/OOi1sm6jrLwevyvOt//4ZwDfTfjS6rfJGu\n qaM5iGG0egef1nlCqCQCiEAWD54XWSn2t+0HZQmFj1ZBsLHcAVk33EzUx\n 5SzKzrW1eG/ivjtRbe0OjbfNRYUd5x2ergvl33v0NnsvCnPKvTey34UDv g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10505\"; a=\"368667233\"", "E=Sophos;i=\"5.95,198,1661842800\"; d=\"scan'208\";a=\"368667233\"", "E=McAfee;i=\"6500,9779,10505\"; a=\"607481708\"", "E=Sophos;i=\"5.95,198,1661842800\"; d=\"scan'208\";a=\"607481708\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "andrew.rybchenko@oktetlabs.ru, qi.z.zhang@intel.com,\n jingjing.wu@intel.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org,\n\tJunfeng Guo <junfeng.guo@intel.com>", "Subject": "[PATCH v8 12/14] net/idpf: add support for write back based on ITR\n expire", "Date": "Thu, 20 Oct 2022 14:29:49 +0800", "Message-Id": "<20221020062951.645121-13-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20221020062951.645121-1-junfeng.guo@intel.com>", "References": "<20221020024135.338280-15-junfeng.guo@intel.com>\n <20221020062951.645121-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Force write-backs by setting WB_ON_ITR bit in DYN_CTL register,\nso that the packets can be received once at a time.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n drivers/net/idpf/idpf_ethdev.c | 119 +++++++++++++++++++++++++++++++++\n drivers/net/idpf/idpf_ethdev.h | 8 +++\n drivers/net/idpf/idpf_vchnl.c | 107 +++++++++++++++++++++++++++++\n 3 files changed, 234 insertions(+)", "diff": "diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c\nindex 803c0d7e12..ac70c029b0 100644\n--- a/drivers/net/idpf/idpf_ethdev.c\n+++ b/drivers/net/idpf/idpf_ethdev.c\n@@ -404,6 +404,90 @@ idpf_dev_configure(struct rte_eth_dev *dev)\n \treturn ret;\n }\n \n+static int\n+idpf_config_rx_queues_irqs(struct rte_eth_dev *dev)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct virtchnl2_queue_vector *qv_map;\n+\tstruct idpf_hw *hw = &adapter->hw;\n+\tuint32_t dynctl_reg_start;\n+\tuint32_t itrn_reg_start;\n+\tuint32_t dynctl_val, itrn_val;\n+\tuint16_t i;\n+\n+\tqv_map = rte_zmalloc(\"qv_map\",\n+\t\t\tdev->data->nb_rx_queues *\n+\t\t\tsizeof(struct virtchnl2_queue_vector), 0);\n+\tif (!qv_map) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate %d queue-vector map\",\n+\t\t\t dev->data->nb_rx_queues);\n+\t\tgoto qv_map_alloc_err;\n+\t}\n+\n+\t/* Rx interrupt disabled, Map interrupt only for writeback */\n+\n+\t/* The capability flags adapter->caps->other_caps here should be\n+\t * compared with bit VIRTCHNL2_CAP_WB_ON_ITR. The if condition should\n+\t * be updated when the FW can return correct flag bits.\n+\t */\n+\tif (adapter->caps->other_caps) {\n+\t\tdynctl_reg_start =\n+\t\t\tvport->recv_vectors->vchunks.vchunks->dynctl_reg_start;\n+\t\titrn_reg_start =\n+\t\t\tvport->recv_vectors->vchunks.vchunks->itrn_reg_start;\n+\t\tdynctl_val = IDPF_READ_REG(hw, dynctl_reg_start);\n+\t\tPMD_DRV_LOG(DEBUG, \"Value of dynctl_reg_start is 0x%x\",\n+\t\t\t dynctl_val);\n+\t\titrn_val = IDPF_READ_REG(hw, itrn_reg_start);\n+\t\tPMD_DRV_LOG(DEBUG, \"Value of itrn_reg_start is 0x%x\", itrn_val);\n+\t\t/* Force write-backs by setting WB_ON_ITR bit in DYN_CTL\n+\t\t * register. WB_ON_ITR and INTENA are mutually exclusive\n+\t\t * bits. Setting WB_ON_ITR bits means TX and RX Descs\n+\t\t * are written back based on ITR expiration irrespective\n+\t\t * of INTENA setting.\n+\t\t */\n+\t\t/* TBD: need to tune INTERVAL value for better performance. */\n+\t\tif (itrn_val)\n+\t\t\tIDPF_WRITE_REG(hw,\n+\t\t\t\t dynctl_reg_start,\n+\t\t\t\t VIRTCHNL2_ITR_IDX_0 <<\n+\t\t\t\t PF_GLINT_DYN_CTL_ITR_INDX_S |\n+\t\t\t\t PF_GLINT_DYN_CTL_WB_ON_ITR_M |\n+\t\t\t\t itrn_val <<\n+\t\t\t\t PF_GLINT_DYN_CTL_INTERVAL_S);\n+\t\telse\n+\t\t\tIDPF_WRITE_REG(hw,\n+\t\t\t\t dynctl_reg_start,\n+\t\t\t\t VIRTCHNL2_ITR_IDX_0 <<\n+\t\t\t\t PF_GLINT_DYN_CTL_ITR_INDX_S |\n+\t\t\t\t PF_GLINT_DYN_CTL_WB_ON_ITR_M |\n+\t\t\t\t IDPF_DFLT_INTERVAL <<\n+\t\t\t\t PF_GLINT_DYN_CTL_INTERVAL_S);\n+\t}\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\t/* map all queues to the same vector */\n+\t\tqv_map[i].queue_id = vport->chunks_info.rx_start_qid + i;\n+\t\tqv_map[i].vector_id =\n+\t\t\tvport->recv_vectors->vchunks.vchunks->start_vector_id;\n+\t}\n+\tvport->qv_map = qv_map;\n+\n+\tif (idpf_vc_config_irq_map_unmap(vport, true)) {\n+\t\tPMD_DRV_LOG(ERR, \"config interrupt mapping failed\");\n+\t\tgoto config_irq_map_err;\n+\t}\n+\n+\treturn 0;\n+\n+config_irq_map_err:\n+\trte_free(vport->qv_map);\n+\tvport->qv_map = NULL;\n+\n+qv_map_alloc_err:\n+\treturn -1;\n+}\n+\n static int\n idpf_start_queues(struct rte_eth_dev *dev)\n {\n@@ -441,6 +525,10 @@ static int\n idpf_dev_start(struct rte_eth_dev *dev)\n {\n \tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tuint16_t num_allocated_vectors =\n+\t\tadapter->caps->num_allocated_vectors;\n+\tuint16_t req_vecs_num;\n \n \tPMD_INIT_FUNC_TRACE();\n \n@@ -453,6 +541,23 @@ idpf_dev_start(struct rte_eth_dev *dev)\n \n \tvport->max_pkt_len = dev->data->mtu + IDPF_ETH_OVERHEAD;\n \n+\treq_vecs_num = IDPF_DFLT_Q_VEC_NUM;\n+\tif (req_vecs_num + adapter->used_vecs_num > num_allocated_vectors) {\n+\t\tPMD_DRV_LOG(ERR, \"The accumulated request vectors' number should be less than %d\",\n+\t\t\t num_allocated_vectors);\n+\t\tgoto err_mtu;\n+\t}\n+\tif (idpf_vc_alloc_vectors(vport, req_vecs_num)) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate interrupt vectors\");\n+\t\tgoto err_mtu;\n+\t}\n+\tadapter->used_vecs_num += req_vecs_num;\n+\n+\tif (idpf_config_rx_queues_irqs(dev)) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to configure irqs\");\n+\t\tgoto err_mtu;\n+\t}\n+\n \tif (idpf_start_queues(dev)) {\n \t\tPMD_DRV_LOG(ERR, \"Failed to start queues\");\n \t\tgoto err_mtu;\n@@ -489,6 +594,12 @@ idpf_dev_stop(struct rte_eth_dev *dev)\n \n \tidpf_stop_queues(dev);\n \n+\tif (idpf_vc_config_irq_map_unmap(vport, false))\n+\t\tPMD_DRV_LOG(ERR, \"config interrupt unmapping failed\");\n+\n+\tif (idpf_vc_dealloc_vectors(vport))\n+\t\tPMD_DRV_LOG(ERR, \"deallocate interrupt vectors failed\");\n+\n \tvport->stopped = 1;\n \tdev->data->dev_started = 0;\n \n@@ -513,6 +624,12 @@ idpf_dev_close(struct rte_eth_dev *dev)\n \trte_free(vport->rss_key);\n \tvport->rss_key = NULL;\n \n+\trte_free(vport->recv_vectors);\n+\tvport->recv_vectors = NULL;\n+\n+\trte_free(vport->qv_map);\n+\tvport->qv_map = NULL;\n+\n \tadapter->cur_vports &= ~BIT(vport->devarg_id);\n \n \trte_free(vport);\n@@ -864,6 +981,8 @@ idpf_adapter_init(struct rte_pci_device *pci_dev, struct idpf_adapter *adapter)\n \tadapter->cur_vports = 0;\n \tadapter->cur_vport_nb = 0;\n \n+\tadapter->used_vecs_num = 0;\n+\n \treturn ret;\n \n err_vports:\ndiff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h\nindex bba8223cc4..505b3f36e3 100644\n--- a/drivers/net/idpf/idpf_ethdev.h\n+++ b/drivers/net/idpf/idpf_ethdev.h\n@@ -130,6 +130,11 @@ struct idpf_vport {\n \tuint8_t *rss_key;\n \tuint64_t rss_hf;\n \n+\t/* MSIX info*/\n+\tstruct virtchnl2_queue_vector *qv_map; /* queue vector mapping */\n+\tuint16_t max_vectors;\n+\tstruct virtchnl2_alloc_vectors *recv_vectors;\n+\n \t/* Chunk info */\n \tstruct idpf_chunks_info chunks_info;\n \n@@ -248,6 +253,9 @@ int idpf_switch_queue(struct idpf_vport *vport, uint16_t qid,\n \t\t bool rx, bool on);\n int idpf_vc_ena_dis_queues(struct idpf_vport *vport, bool enable);\n int idpf_vc_ena_dis_vport(struct idpf_vport *vport, bool enable);\n+int idpf_vc_config_irq_map_unmap(struct idpf_vport *vport, bool map);\n+int idpf_vc_alloc_vectors(struct idpf_vport *vport, uint16_t num_vectors);\n+int idpf_vc_dealloc_vectors(struct idpf_vport *vport);\n int idpf_vc_query_ptype_info(struct idpf_adapter *adapter);\n int idpf_read_one_msg(struct idpf_adapter *adapter, uint32_t ops,\n \t\t uint16_t buf_len, uint8_t *buf);\ndiff --git a/drivers/net/idpf/idpf_vchnl.c b/drivers/net/idpf/idpf_vchnl.c\nindex 8f447046b1..1b5f021834 100644\n--- a/drivers/net/idpf/idpf_vchnl.c\n+++ b/drivers/net/idpf/idpf_vchnl.c\n@@ -1136,6 +1136,113 @@ idpf_vc_config_txq(struct idpf_vport *vport, uint16_t txq_id)\n \treturn err;\n }\n \n+int\n+idpf_vc_config_irq_map_unmap(struct idpf_vport *vport, bool map)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct virtchnl2_queue_vector_maps *map_info;\n+\tstruct virtchnl2_queue_vector *vecmap;\n+\tuint16_t nb_rxq = vport->dev_data->nb_rx_queues;\n+\tstruct idpf_cmd_info args;\n+\tint len, i, err = 0;\n+\n+\tlen = sizeof(struct virtchnl2_queue_vector_maps) +\n+\t\t(nb_rxq - 1) * sizeof(struct virtchnl2_queue_vector);\n+\n+\tmap_info = rte_zmalloc(\"map_info\", len, 0);\n+\tif (!map_info)\n+\t\treturn -ENOMEM;\n+\n+\tmap_info->vport_id = vport->vport_id;\n+\tmap_info->num_qv_maps = nb_rxq;\n+\tfor (i = 0; i < nb_rxq; i++) {\n+\t\tvecmap = &map_info->qv_maps[i];\n+\t\tvecmap->queue_id = vport->qv_map[i].queue_id;\n+\t\tvecmap->vector_id = vport->qv_map[i].vector_id;\n+\t\tvecmap->itr_idx = VIRTCHNL2_ITR_IDX_0;\n+\t\tvecmap->queue_type = VIRTCHNL2_QUEUE_TYPE_RX;\n+\t}\n+\n+\targs.ops = map ? VIRTCHNL2_OP_MAP_QUEUE_VECTOR :\n+\t\tVIRTCHNL2_OP_UNMAP_QUEUE_VECTOR;\n+\targs.in_args = (u8 *)map_info;\n+\targs.in_args_size = len;\n+\targs.out_buffer = adapter->mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\terr = idpf_execute_vc_cmd(adapter, &args);\n+\tif (err)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_%s_QUEUE_VECTOR\",\n+\t\t\t map ? \"MAP\" : \"UNMAP\");\n+\n+\trte_free(map_info);\n+\treturn err;\n+}\n+\n+int\n+idpf_vc_alloc_vectors(struct idpf_vport *vport, uint16_t num_vectors)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct virtchnl2_alloc_vectors *alloc_vec;\n+\tstruct idpf_cmd_info args;\n+\tint err, len;\n+\n+\tlen = sizeof(struct virtchnl2_alloc_vectors) +\n+\t\t(num_vectors - 1) * sizeof(struct virtchnl2_vector_chunk);\n+\talloc_vec = rte_zmalloc(\"alloc_vec\", len, 0);\n+\tif (!alloc_vec)\n+\t\treturn -ENOMEM;\n+\n+\talloc_vec->num_vectors = num_vectors;\n+\n+\targs.ops = VIRTCHNL2_OP_ALLOC_VECTORS;\n+\targs.in_args = (u8 *)alloc_vec;\n+\targs.in_args_size = sizeof(struct virtchnl2_alloc_vectors);\n+\targs.out_buffer = adapter->mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\terr = idpf_execute_vc_cmd(adapter, &args);\n+\tif (err)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to execute command VIRTCHNL2_OP_ALLOC_VECTORS\");\n+\n+\tif (!vport->recv_vectors) {\n+\t\tvport->recv_vectors = rte_zmalloc(\"recv_vectors\", len, 0);\n+\t\tif (!vport->recv_vectors) {\n+\t\t\trte_free(alloc_vec);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n+\trte_memcpy(vport->recv_vectors, args.out_buffer, len);\n+\trte_free(alloc_vec);\n+\treturn err;\n+}\n+\n+int\n+idpf_vc_dealloc_vectors(struct idpf_vport *vport)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct virtchnl2_alloc_vectors *alloc_vec;\n+\tstruct virtchnl2_vector_chunks *vcs;\n+\tstruct idpf_cmd_info args;\n+\tint err, len;\n+\n+\talloc_vec = vport->recv_vectors;\n+\tvcs = &alloc_vec->vchunks;\n+\n+\tlen = sizeof(struct virtchnl2_vector_chunks) +\n+\t\t(vcs->num_vchunks - 1) * sizeof(struct virtchnl2_vector_chunk);\n+\n+\targs.ops = VIRTCHNL2_OP_DEALLOC_VECTORS;\n+\targs.in_args = (u8 *)vcs;\n+\targs.in_args_size = len;\n+\targs.out_buffer = adapter->mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\terr = idpf_execute_vc_cmd(adapter, &args);\n+\tif (err)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to execute command VIRTCHNL2_OP_DEALLOC_VECTORS\");\n+\n+\treturn err;\n+}\n+\n static int\n idpf_vc_ena_dis_one_queue(struct idpf_vport *vport, uint16_t qid,\n \t\t\t uint32_t type, bool on)\n", "prefixes": [ "v8", "12/14" ] }