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GET /api/patches/118780/?format=api
{ "id": 118780, "url": "http://patchwork.dpdk.org/api/patches/118780/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221020111453.1982947-2-ktejasree@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221020111453.1982947-2-ktejasree@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221020111453.1982947-2-ktejasree@marvell.com", "date": "2022-10-20T11:14:48", "name": "[08/13] common/cnxk: add opad ipad gen for md5", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9560af4a547c2f3f5e2fcdb96668c2055b0780bf", "submitter": { "id": 1789, "url": "http://patchwork.dpdk.org/api/people/1789/?format=api", "name": "Tejasree Kondoj", "email": "ktejasree@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221020111453.1982947-2-ktejasree@marvell.com/mbox/", "series": [ { "id": 25341, "url": "http://patchwork.dpdk.org/api/series/25341/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25341", "date": "2022-10-20T11:14:47", "name": "fixes and improvements to cnxk crypto PMD", "version": 1, "mbox": "http://patchwork.dpdk.org/series/25341/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/118780/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/118780/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id ADF88A0552;\n\tThu, 20 Oct 2022 13:15:04 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EF0EA42D3F;\n\tThu, 20 Oct 2022 13:15:01 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id BA83442D3A\n for <dev@dpdk.org>; Thu, 20 Oct 2022 13:15:00 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 29K8Klck022018\n for <dev@dpdk.org>; Thu, 20 Oct 2022 04:14:59 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3kb2qx8jc0-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 20 Oct 2022 04:14:59 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 20 Oct 2022 04:14:58 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 20 Oct 2022 04:14:58 -0700", "from hyd1554.marvell.com (unknown [10.29.57.11])\n by maili.marvell.com (Postfix) with ESMTP id 4AFD33F7079;\n Thu, 20 Oct 2022 04:14:56 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=K/Pyv0NAxP12p02y/+Wtey8xZcw3mfomvzv9AnlJuIE=;\n b=dBpKIMK0L6WoxAOI36KVOG5d1ZkuxhFW4JQZkS2qXVb0jUKmpB9ISwrOUHDvc5Qn3Kx0\n 8+4CR6qBFL5rFJeWAObH67bFeP2xM5AxwtAFzmeQ/cn4v+H54CNHrN/4w8BZc2MlzdmB\n GBfQsLwZPkQT2XlA8e64QwagbdaUzflTjJFtKwwj+ktCQyD7/7yfSV5bvfliQYjybkE/\n tSZ4R57lXTR5wBJmwF2mUIa9n+ARiBxqsOTkOb63KMUNeN7Sti9+XmLSVH4MLppgAIav\n MhRpg5oM1yDJUNGMpKZ0VLWc9JeEZ/LodwZOZzN0fSVTW5bI9pKj9NtDQJ53ydCno6Cr nQ==", "From": "Tejasree Kondoj <ktejasree@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>", "CC": "Vidya Sagar Velumuri <vvelumuri@marvell.com>, Anoob Joseph\n <anoobj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 08/13] common/cnxk: add opad ipad gen for md5", "Date": "Thu, 20 Oct 2022 16:44:48 +0530", "Message-ID": "<20221020111453.1982947-2-ktejasree@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221020111453.1982947-1-ktejasree@marvell.com>", "References": "<20221020111453.1982947-1-ktejasree@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "IkTC_V_JvVIT0ZmemOpBRWkUdZN_x6Ab", "X-Proofpoint-ORIG-GUID": "IkTC_V_JvVIT0ZmemOpBRWkUdZN_x6Ab", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-10-20_03,2022-10-20_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n\nAdd support to generate ipad and opad for md5.\nSkip the call to additional command WRITE_SA during SA creation.\nInstead use the software defined function to generate opad and ipad.\n\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n---\n drivers/common/cnxk/cnxk_security.c | 49 ++++-----\n drivers/common/cnxk/roc_cpt.c | 95 -----------------\n drivers/common/cnxk/roc_cpt.h | 3 -\n drivers/common/cnxk/roc_hash.c | 155 ++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_hash.h | 1 +\n drivers/common/cnxk/roc_ie_on.h | 2 -\n drivers/common/cnxk/roc_nix_inl.c | 6 --\n drivers/common/cnxk/version.map | 2 +-\n drivers/crypto/cnxk/cn9k_ipsec.c | 7 --\n drivers/net/cnxk/cn9k_ethdev_sec.c | 8 --\n 10 files changed, 178 insertions(+), 150 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c\nindex f220d2577f..68ed0d08b4 100644\n--- a/drivers/common/cnxk/cnxk_security.c\n+++ b/drivers/common/cnxk/cnxk_security.c\n@@ -28,6 +28,10 @@ ipsec_hmac_opad_ipad_gen(struct rte_crypto_sym_xform *auth_xform,\n \t * per packet computation\n \t */\n \tswitch (auth_xform->auth.algo) {\n+\tcase RTE_CRYPTO_AUTH_MD5_HMAC:\n+\t\troc_hash_md5_gen(opad, (uint32_t *)&hmac_opad_ipad[0]);\n+\t\troc_hash_md5_gen(ipad, (uint32_t *)&hmac_opad_ipad[24]);\n+\t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n \t\troc_hash_sha1_gen(opad, (uint32_t *)&hmac_opad_ipad[0]);\n \t\troc_hash_sha1_gen(ipad, (uint32_t *)&hmac_opad_ipad[24]);\n@@ -1218,9 +1222,7 @@ cnxk_on_ipsec_outb_sa_create(struct rte_security_ipsec_xform *ipsec,\n \tstruct roc_ie_on_sa_ctl *ctl;\n \tstruct rte_ipv6_hdr *ip6;\n \tstruct rte_ipv4_hdr *ip4;\n-\tconst uint8_t *auth_key;\n \tuint16_t sport, dport;\n-\tint auth_key_len = 0;\n \tsize_t ctx_len;\n \tint ret;\n \n@@ -1343,29 +1345,14 @@ cnxk_on_ipsec_outb_sa_create(struct rte_security_ipsec_xform *ipsec,\n \tctx_len += RTE_ALIGN_CEIL(ctx_len, 8);\n \n \tif (crypto_xform->type != RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tauth_key = auth_xform->auth.key.data;\n-\t\tauth_key_len = auth_xform->auth.key.length;\n+\t\tuint8_t *hmac_opad_ipad = (uint8_t *)&out_sa->sha2;\n \n-\t\tswitch (auth_xform->auth.algo) {\n-\t\tcase RTE_CRYPTO_AUTH_AES_GMAC:\n-\t\tcase RTE_CRYPTO_AUTH_NULL:\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_MD5_HMAC:\n-\t\tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n-\t\t\tmemcpy(out_sa->sha1.hmac_key, auth_key, auth_key_len);\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA256_HMAC:\n-\t\tcase RTE_CRYPTO_AUTH_SHA384_HMAC:\n-\t\tcase RTE_CRYPTO_AUTH_SHA512_HMAC:\n-\t\t\tmemcpy(out_sa->sha2.hmac_key, auth_key, auth_key_len);\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_AES_XCBC_MAC:\n-\t\t\tmemcpy(out_sa->aes_xcbc.key, auth_key, auth_key_len);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tplt_err(\"Unsupported auth algorithm %u\",\n-\t\t\t\tauth_xform->auth.algo);\n-\t\t\treturn -ENOTSUP;\n+\t\tif (auth_xform->auth.algo == RTE_CRYPTO_AUTH_AES_XCBC_MAC) {\n+\t\t\tconst uint8_t *auth_key = auth_xform->auth.key.data;\n+\n+\t\t\troc_aes_xcbc_key_derive(auth_key, hmac_opad_ipad);\n+\t\t} else if (auth_xform->auth.algo != RTE_CRYPTO_AUTH_NULL) {\n+\t\t\tipsec_hmac_opad_ipad_gen(auth_xform, hmac_opad_ipad);\n \t\t}\n \t}\n \n@@ -1390,9 +1377,9 @@ cnxk_on_ipsec_inb_sa_create(struct rte_security_ipsec_xform *ipsec,\n \tif (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD ||\n \t auth_xform->auth.algo == RTE_CRYPTO_AUTH_NULL ||\n \t auth_xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {\n-\t\tctx_len = offsetof(struct roc_ie_on_inb_sa,\n-\t\t\t\t sha1_or_gcm.hmac_key[0]);\n+\t\tctx_len = offsetof(struct roc_ie_on_inb_sa, sha1_or_gcm.hmac_key[0]);\n \t} else {\n+\t\tuint8_t *hmac_opad_ipad = (uint8_t *)&in_sa->sha2;\n \t\tauth_key = auth_xform->auth.key.data;\n \t\tauth_key_len = auth_xform->auth.key.length;\n \n@@ -1419,10 +1406,16 @@ cnxk_on_ipsec_inb_sa_create(struct rte_security_ipsec_xform *ipsec,\n \t\t\t\t\t aes_xcbc.selector);\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tplt_err(\"Unsupported auth algorithm %u\",\n-\t\t\t\tauth_xform->auth.algo);\n+\t\t\tplt_err(\"Unsupported auth algorithm %u\", auth_xform->auth.algo);\n \t\t\treturn -ENOTSUP;\n \t\t}\n+\t\tif (auth_xform->auth.algo == RTE_CRYPTO_AUTH_AES_XCBC_MAC) {\n+\t\t\tconst uint8_t *auth_key = auth_xform->auth.key.data;\n+\n+\t\t\troc_aes_xcbc_key_derive(auth_key, hmac_opad_ipad);\n+\t\t} else if (auth_xform->auth.algo != RTE_CRYPTO_AUTH_NULL) {\n+\t\t\tipsec_hmac_opad_ipad_gen(auth_xform, hmac_opad_ipad);\n+\t\t}\n \t}\n \n \treturn ctx_len;\ndiff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nindex 311f0a08c4..fb97ec89b2 100644\n--- a/drivers/common/cnxk/roc_cpt.c\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -1079,98 +1079,3 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr,\n \n \treturn 0;\n }\n-\n-int\n-roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, bool inb,\n-\t\t uint16_t ctx_len, uint8_t egrp)\n-{\n-\tunion cpt_res_s res, *hw_res;\n-\tstruct cpt_inst_s inst;\n-\tuint64_t lmt_status;\n-\tint ret = 0;\n-\n-\thw_res = plt_zmalloc(sizeof(*hw_res), ROC_CPT_RES_ALIGN);\n-\tif (unlikely(hw_res == NULL)) {\n-\t\tplt_err(\"Couldn't allocate memory for result address\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\thw_res->cn9k.compcode = CPT_COMP_NOT_DONE;\n-\n-\tinst.w4.s.opcode_major = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_OUTBOUND;\n-\tif (inb)\n-\t\tinst.w4.s.opcode_major = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_INBOUND;\n-\tinst.w4.s.opcode_minor = ctx_len >> 3;\n-\tinst.w4.s.param1 = 0;\n-\tinst.w4.s.param2 = 0;\n-\tinst.w4.s.dlen = ctx_len;\n-\tinst.dptr = sa;\n-\tinst.rptr = 0;\n-\tinst.w7.s.cptr = sa;\n-\tinst.w7.s.egrp = egrp;\n-\n-\tinst.w0.u64 = 0;\n-\tinst.w2.u64 = 0;\n-\tinst.w3.u64 = 0;\n-\tinst.res_addr = (uintptr_t)hw_res;\n-\n-\tplt_io_wmb();\n-\n-\tdo {\n-\t\t/* Copy CPT command to LMTLINE */\n-\t\troc_lmt_mov64((void *)lf->lmt_base, &inst);\n-\t\tlmt_status = roc_lmt_submit_ldeor(lf->io_addr);\n-\t} while (lmt_status == 0);\n-\n-\tconst uint64_t timeout = plt_tsc_cycles() + 60 * plt_tsc_hz();\n-\n-\t/* Wait until CPT instruction completes */\n-\tdo {\n-\t\tres.u64[0] = __atomic_load_n(&hw_res->u64[0], __ATOMIC_RELAXED);\n-\t\tif (unlikely(plt_tsc_cycles() > timeout)) {\n-\t\t\tplt_err(\"Request timed out\");\n-\t\t\tret = -ETIMEDOUT;\n-\t\t\tgoto free;\n-\t\t}\n-\t} while (res.cn9k.compcode == CPT_COMP_NOT_DONE);\n-\n-\tif (unlikely(res.cn9k.compcode != CPT_COMP_GOOD)) {\n-\t\tret = res.cn9k.compcode;\n-\t\tswitch (ret) {\n-\t\tcase CPT_COMP_INSTERR:\n-\t\t\tplt_err(\"Request failed with instruction error\");\n-\t\t\tbreak;\n-\t\tcase CPT_COMP_FAULT:\n-\t\t\tplt_err(\"Request failed with DMA fault\");\n-\t\t\tbreak;\n-\t\tcase CPT_COMP_HWERR:\n-\t\t\tplt_err(\"Request failed with hardware error\");\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tplt_err(\"Request failed with unknown hardware completion code : 0x%x\",\n-\t\t\t\tret);\n-\t\t}\n-\t\tret = -EINVAL;\n-\t\tgoto free;\n-\t}\n-\n-\tif (unlikely(res.cn9k.uc_compcode != ROC_IE_ON_UCC_SUCCESS)) {\n-\t\tret = res.cn9k.uc_compcode;\n-\t\tswitch (ret) {\n-\t\tcase ROC_IE_ON_AUTH_UNSUPPORTED:\n-\t\t\tplt_err(\"Invalid auth type\");\n-\t\t\tbreak;\n-\t\tcase ROC_IE_ON_ENCRYPT_UNSUPPORTED:\n-\t\t\tplt_err(\"Invalid encrypt type\");\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tplt_err(\"Request failed with unknown microcode completion code : 0x%x\",\n-\t\t\t\tret);\n-\t\t}\n-\t\tret = -ENOTSUP;\n-\t}\n-\n-free:\n-\tplt_free(hw_res);\n-\treturn ret;\n-}\ndiff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h\nindex 57e9bea83a..bc9cc19edd 100644\n--- a/drivers/common/cnxk/roc_cpt.h\n+++ b/drivers/common/cnxk/roc_cpt.h\n@@ -174,7 +174,4 @@ int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt,\n void __roc_api roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth);\n int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr,\n \t\t\t\tvoid *sa_cptr, uint16_t sa_len);\n-\n-int __roc_api roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, bool inb,\n-\t\t\t\t uint16_t ctx_len, uint8_t egrp);\n #endif /* _ROC_CPT_H_ */\ndiff --git a/drivers/common/cnxk/roc_hash.c b/drivers/common/cnxk/roc_hash.c\nindex 4a34c7fbf8..1b9030e693 100644\n--- a/drivers/common/cnxk/roc_hash.c\n+++ b/drivers/common/cnxk/roc_hash.c\n@@ -9,6 +9,161 @@\n #define lrot64(bits, word) (((word) << (bits)) | ((word) >> (64 - (bits))))\n #define rrot64(bits, word) lrot64(64 - (bits), word)\n \n+#define S11 7\n+#define S12 12\n+#define S13 17\n+#define S14 22\n+#define S21 5\n+#define S22 9\n+#define S23 14\n+#define S24 20\n+#define S31 4\n+#define S32 11\n+#define S33 16\n+#define S34 23\n+#define S41 6\n+#define S42 10\n+#define S43 15\n+#define S44 21\n+\n+#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))\n+#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))\n+#define H(x, y, z) ((x) ^ (y) ^ (z))\n+#define I(x, y, z) ((y) ^ ((x) | (~z)))\n+\n+#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32 - (n))))\n+\n+/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4.\n+ * Rotation is separate from addition to prevent recomputation.\n+ */\n+\n+#define FF(a, b, c, d, x, s, ac) \\\n+\t{ \\\n+\t\t(a) += F((b), (c), (d)) + (x) + (uint32_t)(ac); \\\n+\t\t(a) = ROTATE_LEFT((a), (s)); \\\n+\t\t(a) += (b); \\\n+\t}\n+\n+#define GG(a, b, c, d, x, s, ac) \\\n+\t{ \\\n+\t\t(a) += G((b), (c), (d)) + (x) + (uint32_t)(ac); \\\n+\t\t(a) = ROTATE_LEFT((a), (s)); \\\n+\t\t(a) += (b); \\\n+\t}\n+\n+#define HH(a, b, c, d, x, s, ac) \\\n+\t{ \\\n+\t\t(a) += H((b), (c), (d)) + (x) + (uint32_t)(ac); \\\n+\t\t(a) = ROTATE_LEFT((a), (s)); \\\n+\t\t(a) += (b); \\\n+\t}\n+\n+#define II(a, b, c, d, x, s, ac) \\\n+\t{ \\\n+\t\t(a) += I((b), (c), (d)) + (x) + (uint32_t)(ac); \\\n+\t\t(a) = ROTATE_LEFT((a), (s)); \\\n+\t\t(a) += (b); \\\n+\t}\n+\n+/*\n+ * Compute a partial hash with the assumption that msg is the first block.\n+ * Based on implementation from RFC 1321\n+ */\n+void\n+roc_hash_md5_gen(uint8_t *msg, uint32_t *hash)\n+{\n+\tuint32_t state[4] = {0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476};\n+\tuint32_t a = state[0];\n+\tuint32_t b = state[1];\n+\tuint32_t c = state[2];\n+\tuint32_t d = state[3];\n+\tuint32_t x[16];\n+\n+\tmemcpy(x, msg, 64);\n+\n+\t/* Round 1 */\n+\tFF(a, b, c, d, x[0], S11, 0xd76aa478);\t/* 1 */\n+\tFF(d, a, b, c, x[1], S12, 0xe8c7b756);\t/* 2 */\n+\tFF(c, d, a, b, x[2], S13, 0x242070db);\t/* 3 */\n+\tFF(b, c, d, a, x[3], S14, 0xc1bdceee);\t/* 4 */\n+\tFF(a, b, c, d, x[4], S11, 0xf57c0faf);\t/* 5 */\n+\tFF(d, a, b, c, x[5], S12, 0x4787c62a);\t/* 6 */\n+\tFF(c, d, a, b, x[6], S13, 0xa8304613);\t/* 7 */\n+\tFF(b, c, d, a, x[7], S14, 0xfd469501);\t/* 8 */\n+\tFF(a, b, c, d, x[8], S11, 0x698098d8);\t/* 9 */\n+\tFF(d, a, b, c, x[9], S12, 0x8b44f7af);\t/* 10 */\n+\tFF(c, d, a, b, x[10], S13, 0xffff5bb1); /* 11 */\n+\tFF(b, c, d, a, x[11], S14, 0x895cd7be); /* 12 */\n+\tFF(a, b, c, d, x[12], S11, 0x6b901122); /* 13 */\n+\tFF(d, a, b, c, x[13], S12, 0xfd987193); /* 14 */\n+\tFF(c, d, a, b, x[14], S13, 0xa679438e); /* 15 */\n+\tFF(b, c, d, a, x[15], S14, 0x49b40821); /* 16 */\n+\n+\t/* Round 2 */\n+\tGG(a, b, c, d, x[1], S21, 0xf61e2562);\t/* 17 */\n+\tGG(d, a, b, c, x[6], S22, 0xc040b340);\t/* 18 */\n+\tGG(c, d, a, b, x[11], S23, 0x265e5a51); /* 19 */\n+\tGG(b, c, d, a, x[0], S24, 0xe9b6c7aa);\t/* 20 */\n+\tGG(a, b, c, d, x[5], S21, 0xd62f105d);\t/* 21 */\n+\tGG(d, a, b, c, x[10], S22, 0x2441453);\t/* 22 */\n+\tGG(c, d, a, b, x[15], S23, 0xd8a1e681); /* 23 */\n+\tGG(b, c, d, a, x[4], S24, 0xe7d3fbc8);\t/* 24 */\n+\tGG(a, b, c, d, x[9], S21, 0x21e1cde6);\t/* 25 */\n+\tGG(d, a, b, c, x[14], S22, 0xc33707d6); /* 26 */\n+\tGG(c, d, a, b, x[3], S23, 0xf4d50d87);\t/* 27 */\n+\tGG(b, c, d, a, x[8], S24, 0x455a14ed);\t/* 28 */\n+\tGG(a, b, c, d, x[13], S21, 0xa9e3e905); /* 29 */\n+\tGG(d, a, b, c, x[2], S22, 0xfcefa3f8);\t/* 30 */\n+\tGG(c, d, a, b, x[7], S23, 0x676f02d9);\t/* 31 */\n+\tGG(b, c, d, a, x[12], S24, 0x8d2a4c8a); /* 32 */\n+\n+\t/* Round 3 */\n+\tHH(a, b, c, d, x[5], S31, 0xfffa3942);\t/* 33 */\n+\tHH(d, a, b, c, x[8], S32, 0x8771f681);\t/* 34 */\n+\tHH(c, d, a, b, x[11], S33, 0x6d9d6122); /* 35 */\n+\tHH(b, c, d, a, x[14], S34, 0xfde5380c); /* 36 */\n+\tHH(a, b, c, d, x[1], S31, 0xa4beea44);\t/* 37 */\n+\tHH(d, a, b, c, x[4], S32, 0x4bdecfa9);\t/* 38 */\n+\tHH(c, d, a, b, x[7], S33, 0xf6bb4b60);\t/* 39 */\n+\tHH(b, c, d, a, x[10], S34, 0xbebfbc70); /* 40 */\n+\tHH(a, b, c, d, x[13], S31, 0x289b7ec6); /* 41 */\n+\tHH(d, a, b, c, x[0], S32, 0xeaa127fa);\t/* 42 */\n+\tHH(c, d, a, b, x[3], S33, 0xd4ef3085);\t/* 43 */\n+\tHH(b, c, d, a, x[6], S34, 0x4881d05);\t/* 44 */\n+\tHH(a, b, c, d, x[9], S31, 0xd9d4d039);\t/* 45 */\n+\tHH(d, a, b, c, x[12], S32, 0xe6db99e5); /* 46 */\n+\tHH(c, d, a, b, x[15], S33, 0x1fa27cf8); /* 47 */\n+\tHH(b, c, d, a, x[2], S34, 0xc4ac5665);\t/* 48 */\n+\n+\t/* Round 4 */\n+\tII(a, b, c, d, x[0], S41, 0xf4292244);\t/* 49 */\n+\tII(d, a, b, c, x[7], S42, 0x432aff97);\t/* 50 */\n+\tII(c, d, a, b, x[14], S43, 0xab9423a7); /* 51 */\n+\tII(b, c, d, a, x[5], S44, 0xfc93a039);\t/* 52 */\n+\tII(a, b, c, d, x[12], S41, 0x655b59c3); /* 53 */\n+\tII(d, a, b, c, x[3], S42, 0x8f0ccc92);\t/* 54 */\n+\tII(c, d, a, b, x[10], S43, 0xffeff47d); /* 55 */\n+\tII(b, c, d, a, x[1], S44, 0x85845dd1);\t/* 56 */\n+\tII(a, b, c, d, x[8], S41, 0x6fa87e4f);\t/* 57 */\n+\tII(d, a, b, c, x[15], S42, 0xfe2ce6e0); /* 58 */\n+\tII(c, d, a, b, x[6], S43, 0xa3014314);\t/* 59 */\n+\tII(b, c, d, a, x[13], S44, 0x4e0811a1); /* 60 */\n+\tII(a, b, c, d, x[4], S41, 0xf7537e82);\t/* 61 */\n+\tII(d, a, b, c, x[11], S42, 0xbd3af235); /* 62 */\n+\tII(c, d, a, b, x[2], S43, 0x2ad7d2bb);\t/* 63 */\n+\tII(b, c, d, a, x[9], S44, 0xeb86d391);\t/* 64 */\n+\n+\tstate[0] += a;\n+\tstate[1] += b;\n+\tstate[2] += c;\n+\tstate[3] += d;\n+\n+\thash[0] = state[0];\n+\thash[1] = state[1];\n+\thash[2] = state[2];\n+\thash[3] = state[3];\n+}\n+\n /*\n * Compute a partial hash with the assumption that msg is the first block.\n * Based on implementation from RFC 3174\ndiff --git a/drivers/common/cnxk/roc_hash.h b/drivers/common/cnxk/roc_hash.h\nindex 1bc9222445..8940faa6eb 100644\n--- a/drivers/common/cnxk/roc_hash.h\n+++ b/drivers/common/cnxk/roc_hash.h\n@@ -9,6 +9,7 @@\n * Compute a partial hash with the assumption that msg is the first block.\n * Based on implementation from RFC 3174\n */\n+void __roc_api roc_hash_md5_gen(uint8_t *msg, uint32_t *hash);\n void __roc_api roc_hash_sha1_gen(uint8_t *msg, uint32_t *hash);\n void __roc_api roc_hash_sha256_gen(uint8_t *msg, uint32_t *hash);\n void __roc_api roc_hash_sha512_gen(uint8_t *msg, uint64_t *hash, int hash_size);\ndiff --git a/drivers/common/cnxk/roc_ie_on.h b/drivers/common/cnxk/roc_ie_on.h\nindex 5d02684e34..057ff95362 100644\n--- a/drivers/common/cnxk/roc_ie_on.h\n+++ b/drivers/common/cnxk/roc_ie_on.h\n@@ -8,8 +8,6 @@\n /* CN9K IPsec LA */\n \n /* CN9K IPsec LA opcodes */\n-#define ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_OUTBOUND\t 0x20\n-#define ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_INBOUND\t 0x21\n #define ROC_IE_ON_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x23\n #define ROC_IE_ON_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x24\n \ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex cdf31b1f0c..669236c5af 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -1301,12 +1301,6 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr,\n \n \t/* Nothing much to do on cn9k */\n \tif (roc_model_is_cn9k()) {\n-\t\tnix = roc_nix_to_nix_priv(roc_nix);\n-\t\toutb_lf = nix->cpt_lf_base;\n-\t\trc = roc_on_cpt_ctx_write(outb_lf, (uint64_t)sa_dptr, inb,\n-\t\t\t\t\t sa_len, ROC_CPT_DFLT_ENG_GRP_SE_IE);\n-\t\tif (rc)\n-\t\t\treturn rc;\n \t\treturn 0;\n \t}\n \ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 276fec3660..8358fb5979 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -78,13 +78,13 @@ INTERNAL {\n \troc_cpt_parse_hdr_dump;\n \troc_cpt_rxc_time_cfg;\n \troc_cpt_ctx_write;\n-\troc_on_cpt_ctx_write;\n \troc_dpi_configure;\n \troc_dpi_dev_fini;\n \troc_dpi_dev_init;\n \troc_dpi_disable;\n \troc_dpi_enable;\n \troc_error_msg_get;\n+\troc_hash_md5_gen;\n \troc_hash_sha1_gen;\n \troc_hash_sha256_gen;\n \troc_hash_sha512_gen;\ndiff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c\nindex 9ae7c73b37..fa00c428e6 100644\n--- a/drivers/crypto/cnxk/cn9k_ipsec.c\n+++ b/drivers/crypto/cnxk/cn9k_ipsec.c\n@@ -81,10 +81,6 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp,\n \n \tctx_len = ret;\n \tegrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE];\n-\tret = roc_on_cpt_ctx_write(&qp->lf, (uintptr_t)sa, false, ctx_len, egrp);\n-\n-\tif (ret)\n-\t\treturn ret;\n \n \tw4.u64 = 0;\n \tw4.s.opcode_major = ROC_IE_ON_MAJOR_OP_PROCESS_OUTBOUND_IPSEC | ROC_IE_ON_INPLACE_BIT;\n@@ -169,9 +165,6 @@ cn9k_ipsec_inb_sa_create(struct cnxk_cpt_qp *qp,\n \n \tctx_len = ret;\n \tegrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE];\n-\tret = roc_on_cpt_ctx_write(&qp->lf, (uint64_t)sa, true, ctx_len, egrp);\n-\tif (ret)\n-\t\treturn ret;\n \n \tw4.u64 = 0;\n \tw4.s.opcode_major = ROC_IE_ON_MAJOR_OP_PROCESS_INBOUND_IPSEC | ROC_IE_ON_INPLACE_BIT;\ndiff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c\nindex af3f74046a..67966a4e49 100644\n--- a/drivers/net/cnxk/cn9k_ethdev_sec.c\n+++ b/drivers/net/cnxk/cn9k_ethdev_sec.c\n@@ -600,14 +600,6 @@ cn9k_eth_sec_session_create(void *device,\n \t\t}\n \n \t\tctx_len = rc;\n-\t\trc = roc_nix_inl_ctx_write(&dev->nix, inb_sa, inb_sa, inbound,\n-\t\t\t\t\t ctx_len);\n-\t\tif (rc) {\n-\t\t\tsnprintf(tbuf, sizeof(tbuf),\n-\t\t\t\t \"Failed to create inbound sa, rc=%d\", rc);\n-\t\t\tgoto err;\n-\t\t}\n-\n \t\tinb_priv = roc_nix_inl_on_ipsec_inb_sa_sw_rsvd(inb_sa);\n \t\t/* Back pointer to get eth_sec */\n \t\tinb_priv->eth_sec = eth_sec;\n", "prefixes": [ "08/13" ] }