get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/118781/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 118781,
    "url": "http://patchwork.dpdk.org/api/patches/118781/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221020111453.1982947-3-ktejasree@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20221020111453.1982947-3-ktejasree@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20221020111453.1982947-3-ktejasree@marvell.com",
    "date": "2022-10-20T11:14:49",
    "name": "[09/13] crypto/cnxk: support PDCP AAD in CPT PMD",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "ec3c0cc71f00db9cb83694f512e21fdd74c21cef",
    "submitter": {
        "id": 1789,
        "url": "http://patchwork.dpdk.org/api/people/1789/?format=api",
        "name": "Tejasree Kondoj",
        "email": "ktejasree@marvell.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patchwork.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221020111453.1982947-3-ktejasree@marvell.com/mbox/",
    "series": [
        {
            "id": 25341,
            "url": "http://patchwork.dpdk.org/api/series/25341/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25341",
            "date": "2022-10-20T11:14:47",
            "name": "fixes and improvements to cnxk crypto PMD",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/25341/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/118781/comments/",
    "check": "pending",
    "checks": "http://patchwork.dpdk.org/api/patches/118781/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 79F4EA0552;\n\tThu, 20 Oct 2022 13:15:12 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0ACF442D52;\n\tThu, 20 Oct 2022 13:15:04 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id E8D1642D4F\n for <dev@dpdk.org>; Thu, 20 Oct 2022 13:15:02 +0200 (CEST)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 29K6Qiaw010176\n for <dev@dpdk.org>; Thu, 20 Oct 2022 04:15:02 -0700",
            "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kb1258whv-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 20 Oct 2022 04:15:02 -0700",
            "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 20 Oct 2022 04:15:00 -0700",
            "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 20 Oct 2022 04:15:00 -0700",
            "from hyd1554.marvell.com (unknown [10.29.57.11])\n by maili.marvell.com (Postfix) with ESMTP id 517373F7044;\n Thu, 20 Oct 2022 04:14:58 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=rM/k8TjWNl6+Vzq5ch8nh23/Q/oKk84kCAnyLbjW0C4=;\n b=ZggHuFAn6GQQMW7fhtcwa5FNaBmrZ2c25SdlPaCpKAsl8ZqJ0VcpdFKE6r/tZocBk+Wd\n qw/KPt/p5jCd/0/vIzluxSEXUFayhi+FK0btoGIIa2TY3cTdE/2rdbcNx0kIMAbKsFS3\n dWJUewp81XqsgaWfR8jiTLg3u3FYIHpc8s7Z6ZbqsGj1vJ/OLgVdgEsgD0mEjQMnfvT4\n KFfTqmBIJfF3c+uRsHtaWesShmE4Ey3FySHOYT0pMHsQTOs9hZntsnkR5KHBpxiUzYdj\n mO3Nfi/2FOVd22I9Vjm0Ak/oi2cAq8Onnrl9sLM4BmUMG5dfhX+98qbmGjkp9zoDCzsU ng==",
        "From": "Tejasree Kondoj <ktejasree@marvell.com>",
        "To": "Akhil Goyal <gakhil@marvell.com>",
        "CC": "Anoob Joseph <anoobj@marvell.com>, Vidya Sagar Velumuri\n <vvelumuri@marvell.com>, <dev@dpdk.org>",
        "Subject": "[PATCH 09/13] crypto/cnxk: support PDCP AAD in CPT PMD",
        "Date": "Thu, 20 Oct 2022 16:44:49 +0530",
        "Message-ID": "<20221020111453.1982947-3-ktejasree@marvell.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20221020111453.1982947-1-ktejasree@marvell.com>",
        "References": "<20221020111453.1982947-1-ktejasree@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-GUID": "Y6rKopHhGFYxf_0-etxK-fHjJx71rZ1x",
        "X-Proofpoint-ORIG-GUID": "Y6rKopHhGFYxf_0-etxK-fHjJx71rZ1x",
        "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-10-20_03,2022-10-20_01,2022-06-22_01",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Adding support for PDCP AAD in 96xx crypto pmd.\n\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 10 +--\n drivers/crypto/cnxk/cnxk_cryptodev_ops.h |  4 +-\n drivers/crypto/cnxk/cnxk_se.h            | 86 +++++++++++-------------\n 3 files changed, 48 insertions(+), 52 deletions(-)",
    "diff": "diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\nindex e0ceaa32d5..a9c42205e6 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n@@ -27,11 +27,13 @@ cnxk_cpt_get_mlen(void)\n \tlen = 2 * sizeof(uint64_t);\n \tlen += ROC_SE_MAX_MAC_LEN * sizeof(uint8_t);\n \n+\t/* For PDCP_CHAIN passthrough alignment */\n+\tlen += 8;\n \tlen += ROC_SE_OFF_CTRL_LEN + ROC_CPT_AES_CBC_IV_LEN;\n-\tlen += RTE_ALIGN_CEIL((ROC_SE_SG_LIST_HDR_SIZE +\n-\t\t\t       (RTE_ALIGN_CEIL(ROC_SE_MAX_SG_IN_OUT_CNT, 4) >>\n-\t\t\t\t2) * ROC_SE_SG_ENTRY_SIZE),\n-\t\t\t      8);\n+\tlen += RTE_ALIGN_CEIL(\n+\t\t(ROC_SE_SG_LIST_HDR_SIZE +\n+\t\t (RTE_ALIGN_CEIL(ROC_SE_MAX_SG_IN_OUT_CNT, 4) >> 2) * ROC_SE_SG_ENTRY_SIZE),\n+\t\t8);\n \n \treturn len;\n }\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\nindex 2064120505..13c90444d6 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n@@ -10,8 +10,8 @@\n \n #include \"roc_api.h\"\n \n-#define CNXK_CPT_MIN_HEADROOM_REQ 24\n-#define CNXK_CPT_MIN_TAILROOM_REQ 102\n+#define CNXK_CPT_MIN_HEADROOM_REQ\t 32\n+#define CNXK_CPT_MIN_TAILROOM_REQ\t 102\n \n /* Default command timeout in seconds */\n #define DEFAULT_COMMAND_TIMEOUT 4\ndiff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h\nindex 9ce75c07e0..abb9965d3e 100644\n--- a/drivers/crypto/cnxk/cnxk_se.h\n+++ b/drivers/crypto/cnxk/cnxk_se.h\n@@ -1393,12 +1393,11 @@ cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \n static __rte_always_inline int\n cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n-\t\t\tstruct roc_se_fc_params *params,\n-\t\t\tstruct cpt_inst_s *inst)\n+\t\t\tstruct roc_se_fc_params *params, struct cpt_inst_s *inst)\n {\n+\tuint32_t encr_data_len, auth_data_len, aad_len, passthr_len, pad_len, hdr_len;\n \tuint32_t encr_offset, auth_offset, iv_offset = 0;\n \tuint8_t *auth_iv = NULL, *cipher_iv = NULL;\n-\tuint32_t encr_data_len, auth_data_len;\n \tuint8_t pdcp_ci_alg, pdcp_auth_alg;\n \tunion cpt_inst_w4 cpt_inst_w4;\n \tstruct roc_se_ctx *se_ctx;\n@@ -1413,12 +1412,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \tencr_offset = ROC_SE_ENCR_OFFSET(d_offs);\n \tauth_offset = ROC_SE_AUTH_OFFSET(d_offs);\n \n-\tif (auth_offset != encr_offset) {\n-\t\tplt_dp_err(\"encr_offset and auth_offset are not same\");\n-\t\tplt_dp_err(\"enc_offset: %d\", encr_offset);\n-\t\tplt_dp_err(\"auth_offset: %d\", auth_offset);\n-\t\treturn -1;\n-\t}\n+\taad_len = encr_offset - auth_offset;\n \n \tif (unlikely(encr_offset >> 16)) {\n \t\tplt_dp_err(\"Offset not supported\");\n@@ -1433,12 +1427,16 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \n \tencr_data_len = ROC_SE_ENCR_DLEN(d_lens);\n \tauth_data_len = ROC_SE_AUTH_DLEN(d_lens);\n+\tauth_data_len -= aad_len;\n+\n+\tencr_offset += iv_len;\n+\tauth_offset = encr_offset - aad_len;\n+\tpassthr_len = RTE_ALIGN_CEIL(auth_offset, 8);\n \n-\tif ((auth_data_len + mac_len) != encr_data_len) {\n-\t\tplt_dp_err(\"(auth_data_len + mac_len) != encr_data_len\");\n-\t\tplt_dp_err(\"auth_data_len: %d\", auth_data_len);\n-\t\tplt_dp_err(\"encr_data_len: %d\", encr_data_len);\n-\t\tplt_dp_err(\"mac_len: %d\", mac_len);\n+\tif (unlikely((aad_len >> 16) || (passthr_len >> 8))) {\n+\t\tplt_dp_err(\"Length not supported\");\n+\t\tplt_dp_err(\"AAD_len: %d\", aad_len);\n+\t\tplt_dp_err(\"Passthrough_len: %d\", passthr_len);\n \t\treturn -1;\n \t}\n \n@@ -1454,12 +1452,15 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \tif (likely(params->cipher_iv_len))\n \t\tcipher_iv = params->iv_buf;\n \n-\tencr_offset += iv_len;\n+\tpad_len = passthr_len - auth_offset;\n+\thdr_len = iv_len + pad_len;\n \n \tif (se_ctx->auth_then_ciph)\n-\t\tinputlen = encr_offset + auth_data_len;\n+\t\tinputlen = auth_data_len;\n \telse\n-\t\tinputlen = encr_offset + encr_data_len;\n+\t\tinputlen = encr_data_len;\n+\n+\tinputlen += (encr_offset + pad_len);\n \n \tif (likely(((req_flags & ROC_SE_SINGLE_BUF_INPLACE)) &&\n \t\t   ((req_flags & ROC_SE_SINGLE_BUF_HEADROOM)))) {\n@@ -1468,19 +1469,18 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \n \t\t/* Use Direct mode */\n \n-\t\toffset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -\n-\t\t\t\t\t    ROC_SE_OFF_CTRL_LEN - iv_len);\n+\t\toffset_vaddr = PLT_PTR_SUB(dm_vaddr, ROC_SE_OFF_CTRL_LEN + hdr_len);\n \n \t\t/* DPTR */\n \t\tinst->dptr = (uint64_t)offset_vaddr;\n \t\t/* RPTR should just exclude offset control word */\n-\t\tinst->rptr = (uint64_t)dm_vaddr - iv_len;\n+\t\tinst->rptr = (uint64_t)PLT_PTR_SUB(dm_vaddr, hdr_len);\n \n \t\tcpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;\n \n \t\t*(uint64_t *)offset_vaddr =\n-\t\t\trte_cpu_to_be_64(((uint64_t)(iv_offset) << 16) |\n-\t\t\t\t\t ((uint64_t)(encr_offset)));\n+\t\t\trte_cpu_to_be_64(((uint64_t)(aad_len) << 16) |\n+\t\t\t\t\t ((uint64_t)(iv_offset) << 8) | ((uint64_t)(passthr_len)));\n \n \t\tiv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN);\n \t\tpdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv);\n@@ -1499,8 +1499,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \t\t/* save space for IV */\n \t\toffset_vaddr = m_vaddr;\n \n-\t\tm_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN +\n-\t\t\t  RTE_ALIGN_CEIL(iv_len, 8);\n+\t\tm_vaddr = PLT_PTR_ADD(m_vaddr, ROC_SE_OFF_CTRL_LEN + RTE_ALIGN_CEIL(hdr_len, 8));\n \n \t\tcpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;\n \n@@ -1519,11 +1518,11 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \t\t/* Offset control word followed by iv */\n \n \t\ti = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,\n-\t\t\t\t ROC_SE_OFF_CTRL_LEN + iv_len);\n+\t\t\t\t ROC_SE_OFF_CTRL_LEN + hdr_len);\n \n \t\t*(uint64_t *)offset_vaddr =\n-\t\t\trte_cpu_to_be_64(((uint64_t)(iv_offset) << 16) |\n-\t\t\t\t\t ((uint64_t)(encr_offset)));\n+\t\t\trte_cpu_to_be_64(((uint64_t)(aad_len) << 16) |\n+\t\t\t\t\t ((uint64_t)(iv_offset) << 8) | ((uint64_t)(passthr_len)));\n \n \t\tiv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN);\n \t\tpdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv);\n@@ -1532,11 +1531,10 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \t\tpdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv);\n \n \t\t/* input data */\n-\t\tsize = inputlen - iv_len;\n+\t\tsize = inputlen - hdr_len;\n \t\tif (size) {\n-\t\t\ti = fill_sg_comp_from_iov(gather_comp, i,\n-\t\t\t\t\t\t  params->src_iov, 0, &size,\n-\t\t\t\t\t\t  NULL, 0);\n+\t\t\ti = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, 0, &size, NULL,\n+\t\t\t\t\t\t  0);\n \t\t\tif (unlikely(size)) {\n \t\t\t\tplt_dp_err(\"Insufficient buffer space,\"\n \t\t\t\t\t   \" size %d needed\",\n@@ -1553,29 +1551,25 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \t\t */\n \n \t\ti = 0;\n-\t\tscatter_comp =\n-\t\t\t(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +\n-\t\t\t\t\t\t      g_size_bytes);\n+\t\tscatter_comp = (struct roc_se_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes);\n \n-\t\tif (iv_len) {\n+\t\tif ((hdr_len)) {\n \t\t\ti = fill_sg_comp(scatter_comp, i,\n-\t\t\t\t\t (uint64_t)offset_vaddr +\n-\t\t\t\t\t\t ROC_SE_OFF_CTRL_LEN,\n-\t\t\t\t\t iv_len);\n+\t\t\t\t\t (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN, hdr_len);\n \t\t}\n \n \t\t/* Add output data */\n-\t\tif (se_ctx->ciph_then_auth &&\n-\t\t    (req_flags & ROC_SE_VALID_MAC_BUF))\n-\t\t\tsize = inputlen - iv_len;\n+\t\tif (se_ctx->ciph_then_auth && (req_flags & ROC_SE_VALID_MAC_BUF))\n+\t\t\tsize = inputlen;\n \t\telse\n \t\t\t/* Output including mac */\n-\t\t\tsize = inputlen - iv_len + mac_len;\n+\t\t\tsize = inputlen + mac_len;\n+\n+\t\tsize -= hdr_len;\n \n \t\tif (size) {\n-\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n-\t\t\t\t\t\t  params->dst_iov, 0, &size,\n-\t\t\t\t\t\t  NULL, 0);\n+\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i, params->dst_iov, 0, &size, NULL,\n+\t\t\t\t\t\t  0);\n \n \t\t\tif (unlikely(size)) {\n \t\t\t\tplt_dp_err(\"Insufficient buffer space,\"\n@@ -2399,7 +2393,7 @@ prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,\n \n \t\t*flags |= ROC_SE_SINGLE_BUF_INPLACE;\n \t\theadroom = rte_pktmbuf_headroom(pkt);\n-\t\tif (likely(headroom >= 24))\n+\t\tif (likely(headroom >= CNXK_CPT_MIN_HEADROOM_REQ))\n \t\t\t*flags |= ROC_SE_SINGLE_BUF_HEADROOM;\n \n \t\tparam->bufs[0].vaddr = seg_data;\n",
    "prefixes": [
        "09/13"
    ]
}