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{
    "id": 119201,
    "url": "http://patchwork.dpdk.org/api/patches/119201/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221027054505.1369248-7-junfeng.guo@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20221027054505.1369248-7-junfeng.guo@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20221027054505.1369248-7-junfeng.guo@intel.com",
    "date": "2022-10-27T05:44:53",
    "name": "[v13,06/18] net/idpf: add support for queue start",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "897eb53361629625f09aac659dbfc4d326ef34e4",
    "submitter": {
        "id": 1785,
        "url": "http://patchwork.dpdk.org/api/people/1785/?format=api",
        "name": "Junfeng Guo",
        "email": "junfeng.guo@intel.com"
    },
    "delegate": {
        "id": 3961,
        "url": "http://patchwork.dpdk.org/api/users/3961/?format=api",
        "username": "arybchenko",
        "first_name": "Andrew",
        "last_name": "Rybchenko",
        "email": "andrew.rybchenko@oktetlabs.ru"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221027054505.1369248-7-junfeng.guo@intel.com/mbox/",
    "series": [
        {
            "id": 25450,
            "url": "http://patchwork.dpdk.org/api/series/25450/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25450",
            "date": "2022-10-27T05:44:47",
            "name": "add support for idpf PMD in DPDK",
            "version": 13,
            "mbox": "http://patchwork.dpdk.org/series/25450/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/119201/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/119201/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 081F442BC5;\n\tThu, 27 Oct 2022 07:47:14 +0200 (CEST)",
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        ],
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            "E=McAfee;i=\"6500,9779,10512\"; a=\"309831063\"",
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            "E=Sophos;i=\"5.95,215,1661842800\"; d=\"scan'208\";a=\"583429245\""
        ],
        "X-ExtLoop1": "1",
        "From": "Junfeng Guo <junfeng.guo@intel.com>",
        "To": "andrew.rybchenko@oktetlabs.ru, qi.z.zhang@intel.com,\n jingjing.wu@intel.com,\n beilei.xing@intel.com",
        "Cc": "dev@dpdk.org, Junfeng Guo <junfeng.guo@intel.com>,\n Xiaoyun Li <xiaoyun.li@intel.com>",
        "Subject": "[PATCH v13 06/18] net/idpf: add support for queue start",
        "Date": "Thu, 27 Oct 2022 13:44:53 +0800",
        "Message-Id": "<20221027054505.1369248-7-junfeng.guo@intel.com>",
        "X-Mailer": "git-send-email 2.34.1",
        "In-Reply-To": "<20221027054505.1369248-1-junfeng.guo@intel.com>",
        "References": "<20221026101027.240583-2-junfeng.guo@intel.com>\n <20221027054505.1369248-1-junfeng.guo@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Add support for these device ops:\n - rx_queue_start\n - tx_queue_start\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\nSigned-off-by: Xiaoyun Li <xiaoyun.li@intel.com>\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n drivers/net/idpf/idpf_ethdev.c |  40 ++-\n drivers/net/idpf/idpf_ethdev.h |   9 +\n drivers/net/idpf/idpf_rxtx.c   | 237 +++++++++++++++--\n drivers/net/idpf/idpf_rxtx.h   |   6 +\n drivers/net/idpf/idpf_vchnl.c  | 447 +++++++++++++++++++++++++++++++++\n 5 files changed, 718 insertions(+), 21 deletions(-)",
    "diff": "diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c\nindex 3430d00e92..abbf519977 100644\n--- a/drivers/net/idpf/idpf_ethdev.c\n+++ b/drivers/net/idpf/idpf_ethdev.c\n@@ -58,6 +58,8 @@ static const struct eth_dev_ops idpf_eth_dev_ops = {\n \t.dev_start\t\t\t= idpf_dev_start,\n \t.dev_stop\t\t\t= idpf_dev_stop,\n \t.dev_close\t\t\t= idpf_dev_close,\n+\t.rx_queue_start\t\t\t= idpf_rx_queue_start,\n+\t.tx_queue_start\t\t\t= idpf_tx_queue_start,\n \t.rx_queue_setup\t\t\t= idpf_rx_queue_setup,\n \t.tx_queue_setup\t\t\t= idpf_tx_queue_setup,\n \t.dev_infos_get\t\t\t= idpf_dev_info_get,\n@@ -305,6 +307,39 @@ idpf_dev_configure(struct rte_eth_dev *dev)\n \treturn 0;\n }\n \n+static int\n+idpf_start_queues(struct rte_eth_dev *dev)\n+{\n+\tstruct idpf_rx_queue *rxq;\n+\tstruct idpf_tx_queue *txq;\n+\tint err = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\ttxq = dev->data->tx_queues[i];\n+\t\tif (txq == NULL || txq->tx_deferred_start)\n+\t\t\tcontinue;\n+\t\terr = idpf_tx_queue_start(dev, i);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to start Tx queue %u\", i);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\trxq = dev->data->rx_queues[i];\n+\t\tif (rxq == NULL || rxq->rx_deferred_start)\n+\t\t\tcontinue;\n+\t\terr = idpf_rx_queue_start(dev, i);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to start Rx queue %u\", i);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\treturn err;\n+}\n+\n static int\n idpf_dev_start(struct rte_eth_dev *dev)\n {\n@@ -317,7 +352,10 @@ idpf_dev_start(struct rte_eth_dev *dev)\n \n \tvport->max_pkt_len = dev->data->mtu + IDPF_ETH_OVERHEAD;\n \n-\t/* TODO: start queues */\n+\tif (idpf_start_queues(dev) != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to start queues\");\n+\t\treturn -1;\n+\t}\n \n \tif (idpf_vc_ena_dis_vport(vport, true) != 0) {\n \t\tPMD_DRV_LOG(ERR, \"Failed to enable vport\");\ndiff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h\nindex 84ae6641e2..96c22009e9 100644\n--- a/drivers/net/idpf/idpf_ethdev.h\n+++ b/drivers/net/idpf/idpf_ethdev.h\n@@ -24,7 +24,9 @@\n #define IDPF_DEFAULT_TXQ_NUM\t16\n \n #define IDPF_INVALID_VPORT_IDX\t0xffff\n+#define IDPF_TXQ_PER_GRP\t1\n #define IDPF_TX_COMPLQ_PER_GRP\t1\n+#define IDPF_RXQ_PER_GRP\t1\n #define IDPF_RX_BUFQ_PER_GRP\t2\n \n #define IDPF_CTLQ_ID\t\t-1\n@@ -182,6 +184,13 @@ int idpf_vc_check_api_version(struct idpf_adapter *adapter);\n int idpf_vc_get_caps(struct idpf_adapter *adapter);\n int idpf_vc_create_vport(struct idpf_adapter *adapter);\n int idpf_vc_destroy_vport(struct idpf_vport *vport);\n+int idpf_vc_config_rxqs(struct idpf_vport *vport);\n+int idpf_vc_config_rxq(struct idpf_vport *vport, uint16_t rxq_id);\n+int idpf_vc_config_txqs(struct idpf_vport *vport);\n+int idpf_vc_config_txq(struct idpf_vport *vport, uint16_t txq_id);\n+int idpf_switch_queue(struct idpf_vport *vport, uint16_t qid,\n+\t\t      bool rx, bool on);\n+int idpf_vc_ena_dis_queues(struct idpf_vport *vport, bool enable);\n int idpf_vc_ena_dis_vport(struct idpf_vport *vport, bool enable);\n int idpf_read_one_msg(struct idpf_adapter *adapter, uint32_t ops,\n \t\t      uint16_t buf_len, uint8_t *buf);\ndiff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c\nindex 3528d2f2c7..6d954afd9d 100644\n--- a/drivers/net/idpf/idpf_rxtx.c\n+++ b/drivers/net/idpf/idpf_rxtx.c\n@@ -334,11 +334,6 @@ idpf_rx_split_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \tif (check_rx_thresh(nb_desc, rx_free_thresh) != 0)\n \t\treturn -EINVAL;\n \n-\tif (rx_conf->rx_deferred_start) {\n-\t\tPMD_INIT_LOG(ERR, \"Queue start is not supported currently.\");\n-\t\treturn -EINVAL;\n-\t}\n-\n \t/* Setup Rx description queue */\n \trxq = rte_zmalloc_socket(\"idpf rxq\",\n \t\t\t\t sizeof(struct idpf_rx_queue),\n@@ -354,6 +349,7 @@ idpf_rx_split_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \trxq->rx_free_thresh = rx_free_thresh;\n \trxq->queue_id = vport->chunks_info.rx_start_qid + queue_idx;\n \trxq->port_id = dev->data->port_id;\n+\trxq->rx_deferred_start = rx_conf->rx_deferred_start;\n \trxq->rx_hdr_len = 0;\n \trxq->adapter = adapter;\n \trxq->offloads = offloads;\n@@ -470,11 +466,6 @@ idpf_rx_single_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \tif (check_rx_thresh(nb_desc, rx_free_thresh) != 0)\n \t\treturn -EINVAL;\n \n-\tif (rx_conf->rx_deferred_start) {\n-\t\tPMD_INIT_LOG(ERR, \"Queue start is not supported currently.\");\n-\t\treturn -EINVAL;\n-\t}\n-\n \t/* Setup Rx description queue */\n \trxq = rte_zmalloc_socket(\"idpf rxq\",\n \t\t\t\t sizeof(struct idpf_rx_queue),\n@@ -490,6 +481,7 @@ idpf_rx_single_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \trxq->rx_free_thresh = rx_free_thresh;\n \trxq->queue_id = vport->chunks_info.rx_start_qid + queue_idx;\n \trxq->port_id = dev->data->port_id;\n+\trxq->rx_deferred_start = rx_conf->rx_deferred_start;\n \trxq->rx_hdr_len = 0;\n \trxq->adapter = adapter;\n \trxq->offloads = offloads;\n@@ -579,11 +571,6 @@ idpf_tx_split_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \tif (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)\n \t\treturn -EINVAL;\n \n-\tif (tx_conf->tx_deferred_start) {\n-\t\tPMD_INIT_LOG(ERR, \"Queue start is not supported currently.\");\n-\t\treturn -EINVAL;\n-\t}\n-\n \t/* Allocate the TX queue data structure. */\n \ttxq = rte_zmalloc_socket(\"idpf split txq\",\n \t\t\t\t sizeof(struct idpf_tx_queue),\n@@ -600,6 +587,7 @@ idpf_tx_split_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \ttxq->queue_id = vport->chunks_info.tx_start_qid + queue_idx;\n \ttxq->port_id = dev->data->port_id;\n \ttxq->offloads = offloads;\n+\ttxq->tx_deferred_start = tx_conf->tx_deferred_start;\n \n \t/* Allocate software ring */\n \ttxq->sw_nb_desc = 2 * nb_desc;\n@@ -706,11 +694,6 @@ idpf_tx_single_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \tif (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)\n \t\treturn -EINVAL;\n \n-\tif (tx_conf->tx_deferred_start) {\n-\t\tPMD_INIT_LOG(ERR, \"Queue start is not supported currently.\");\n-\t\treturn -EINVAL;\n-\t}\n-\n \t/* Allocate the TX queue data structure. */\n \ttxq = rte_zmalloc_socket(\"idpf txq\",\n \t\t\t\t sizeof(struct idpf_tx_queue),\n@@ -729,6 +712,7 @@ idpf_tx_single_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \ttxq->queue_id = vport->chunks_info.tx_start_qid + queue_idx;\n \ttxq->port_id = dev->data->port_id;\n \ttxq->offloads = offloads;\n+\ttxq->tx_deferred_start = tx_conf->tx_deferred_start;\n \n \t/* Allocate software ring */\n \ttxq->sw_ring =\n@@ -782,3 +766,216 @@ idpf_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\treturn idpf_tx_split_queue_setup(dev, queue_idx, nb_desc,\n \t\t\t\t\t\t socket_id, tx_conf);\n }\n+static int\n+idpf_alloc_single_rxq_mbufs(struct idpf_rx_queue *rxq)\n+{\n+\tvolatile struct virtchnl2_singleq_rx_buf_desc *rxd;\n+\tstruct rte_mbuf *mbuf = NULL;\n+\tuint64_t dma_addr;\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n+\t\tmbuf = rte_mbuf_raw_alloc(rxq->mp);\n+\t\tif (unlikely(mbuf == NULL)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate mbuf for RX\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\trte_mbuf_refcnt_set(mbuf, 1);\n+\t\tmbuf->next = NULL;\n+\t\tmbuf->data_off = RTE_PKTMBUF_HEADROOM;\n+\t\tmbuf->nb_segs = 1;\n+\t\tmbuf->port = rxq->port_id;\n+\n+\t\tdma_addr =\n+\t\t\trte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));\n+\n+\t\trxd = &((volatile struct virtchnl2_singleq_rx_buf_desc *)(rxq->rx_ring))[i];\n+\t\trxd->pkt_addr = dma_addr;\n+\t\trxd->hdr_addr = 0;\n+\t\trxd->rsvd1 = 0;\n+\t\trxd->rsvd2 = 0;\n+\t\trxq->sw_ring[i] = mbuf;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+idpf_alloc_split_rxq_mbufs(struct idpf_rx_queue *rxq)\n+{\n+\tvolatile struct virtchnl2_splitq_rx_buf_desc *rxd;\n+\tstruct rte_mbuf *mbuf = NULL;\n+\tuint64_t dma_addr;\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n+\t\tmbuf = rte_mbuf_raw_alloc(rxq->mp);\n+\t\tif (unlikely(mbuf == NULL)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate mbuf for RX\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\trte_mbuf_refcnt_set(mbuf, 1);\n+\t\tmbuf->next = NULL;\n+\t\tmbuf->data_off = RTE_PKTMBUF_HEADROOM;\n+\t\tmbuf->nb_segs = 1;\n+\t\tmbuf->port = rxq->port_id;\n+\n+\t\tdma_addr =\n+\t\t\trte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));\n+\n+\t\trxd = &((volatile struct virtchnl2_splitq_rx_buf_desc *)(rxq->rx_ring))[i];\n+\t\trxd->qword0.buf_id = i;\n+\t\trxd->qword0.rsvd0 = 0;\n+\t\trxd->qword0.rsvd1 = 0;\n+\t\trxd->pkt_addr = dma_addr;\n+\t\trxd->hdr_addr = 0;\n+\t\trxd->rsvd2 = 0;\n+\n+\t\trxq->sw_ring[i] = mbuf;\n+\t}\n+\n+\trxq->nb_rx_hold = 0;\n+\trxq->rx_tail = rxq->nb_rx_desc - 1;\n+\n+\treturn 0;\n+}\n+\n+int\n+idpf_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n+{\n+\tstruct idpf_rx_queue *rxq;\n+\tint err;\n+\n+\tif (rx_queue_id >= dev->data->nb_rx_queues)\n+\t\treturn -EINVAL;\n+\n+\trxq = dev->data->rx_queues[rx_queue_id];\n+\n+\tif (rxq == NULL || !rxq->q_set) {\n+\t\tPMD_DRV_LOG(ERR, \"RX queue %u not available or setup\",\n+\t\t\t\t\trx_queue_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rxq->bufq1 == NULL) {\n+\t\t/* Single queue */\n+\t\terr = idpf_alloc_single_rxq_mbufs(rxq);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX queue mbuf\");\n+\t\t\treturn err;\n+\t\t}\n+\n+\t\trte_wmb();\n+\n+\t\t/* Init the RX tail register. */\n+\t\tIDPF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);\n+\t} else {\n+\t\t/* Split queue */\n+\t\terr = idpf_alloc_split_rxq_mbufs(rxq->bufq1);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX buffer queue mbuf\");\n+\t\t\treturn err;\n+\t\t}\n+\t\terr = idpf_alloc_split_rxq_mbufs(rxq->bufq2);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX buffer queue mbuf\");\n+\t\t\treturn err;\n+\t\t}\n+\n+\t\trte_wmb();\n+\n+\t\t/* Init the RX tail register. */\n+\t\tIDPF_PCI_REG_WRITE(rxq->bufq1->qrx_tail, rxq->bufq1->rx_tail);\n+\t\tIDPF_PCI_REG_WRITE(rxq->bufq2->qrx_tail, rxq->bufq2->rx_tail);\n+\t}\n+\n+\treturn err;\n+}\n+\n+int\n+idpf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct idpf_rx_queue *rxq =\n+\t\tdev->data->rx_queues[rx_queue_id];\n+\tint err = 0;\n+\n+\terr = idpf_vc_config_rxq(vport, rx_queue_id);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Fail to configure Rx queue %u\", rx_queue_id);\n+\t\treturn err;\n+\t}\n+\n+\terr = idpf_rx_queue_init(dev, rx_queue_id);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to init RX queue %u\",\n+\t\t\t    rx_queue_id);\n+\t\treturn err;\n+\t}\n+\n+\t/* Ready to switch the queue on */\n+\terr = idpf_switch_queue(vport, rx_queue_id, true, true);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to switch RX queue %u on\",\n+\t\t\t    rx_queue_id);\n+\t} else {\n+\t\trxq->q_started = true;\n+\t\tdev->data->rx_queue_state[rx_queue_id] =\n+\t\t\tRTE_ETH_QUEUE_STATE_STARTED;\n+\t}\n+\n+\treturn err;\n+}\n+\n+int\n+idpf_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct idpf_tx_queue *txq;\n+\n+\tif (tx_queue_id >= dev->data->nb_tx_queues)\n+\t\treturn -EINVAL;\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\n+\t/* Init the RX tail register. */\n+\tIDPF_PCI_REG_WRITE(txq->qtx_tail, 0);\n+\n+\treturn 0;\n+}\n+\n+int\n+idpf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct idpf_tx_queue *txq =\n+\t\tdev->data->tx_queues[tx_queue_id];\n+\tint err = 0;\n+\n+\terr = idpf_vc_config_txq(vport, tx_queue_id);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Fail to configure Tx queue %u\", tx_queue_id);\n+\t\treturn err;\n+\t}\n+\n+\terr = idpf_tx_queue_init(dev, tx_queue_id);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to init TX queue %u\",\n+\t\t\t    tx_queue_id);\n+\t\treturn err;\n+\t}\n+\n+\t/* Ready to switch the queue on */\n+\terr = idpf_switch_queue(vport, tx_queue_id, false, true);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to switch TX queue %u on\",\n+\t\t\t    tx_queue_id);\n+\t} else {\n+\t\ttxq->q_started = true;\n+\t\tdev->data->tx_queue_state[tx_queue_id] =\n+\t\t\tRTE_ETH_QUEUE_STATE_STARTED;\n+\t}\n+\n+\treturn err;\n+}\ndiff --git a/drivers/net/idpf/idpf_rxtx.h b/drivers/net/idpf/idpf_rxtx.h\nindex 3f3932c3eb..ab9b3830fd 100644\n--- a/drivers/net/idpf/idpf_rxtx.h\n+++ b/drivers/net/idpf/idpf_rxtx.h\n@@ -50,6 +50,7 @@ struct idpf_rx_queue {\n \n \tbool q_set;             /* if rx queue has been configured */\n \tbool q_started;         /* if rx queue has been started */\n+\tbool rx_deferred_start; /* don't start this queue in dev start */\n \n \t/* only valid for split queue mode */\n \tuint8_t expected_gen_id;\n@@ -95,6 +96,7 @@ struct idpf_tx_queue {\n \n \tbool q_set;\t\t/* if tx queue has been configured */\n \tbool q_started;\t\t/* if tx queue has been started */\n+\tbool tx_deferred_start; /* don't start this queue in dev start */\n \n \t/* only valid for split queue mode */\n \tuint16_t sw_nb_desc;\n@@ -109,8 +111,12 @@ int idpf_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\t\tuint16_t nb_desc, unsigned int socket_id,\n \t\t\tconst struct rte_eth_rxconf *rx_conf,\n \t\t\tstruct rte_mempool *mp);\n+int idpf_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n+int idpf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n int idpf_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\t\tuint16_t nb_desc, unsigned int socket_id,\n \t\t\tconst struct rte_eth_txconf *tx_conf);\n+int idpf_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+int idpf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n \n #endif /* _IDPF_RXTX_H_ */\ndiff --git a/drivers/net/idpf/idpf_vchnl.c b/drivers/net/idpf/idpf_vchnl.c\nindex 4dae1a0b36..11d915cf4e 100644\n--- a/drivers/net/idpf/idpf_vchnl.c\n+++ b/drivers/net/idpf/idpf_vchnl.c\n@@ -21,6 +21,7 @@\n #include <rte_dev.h>\n \n #include \"idpf_ethdev.h\"\n+#include \"idpf_rxtx.h\"\n \n static int\n idpf_vc_clean(struct idpf_adapter *adapter)\n@@ -223,6 +224,10 @@ idpf_execute_vc_cmd(struct idpf_adapter *adapter, struct idpf_cmd_info *args)\n \tcase VIRTCHNL2_OP_GET_CAPS:\n \tcase VIRTCHNL2_OP_CREATE_VPORT:\n \tcase VIRTCHNL2_OP_DESTROY_VPORT:\n+\tcase VIRTCHNL2_OP_CONFIG_RX_QUEUES:\n+\tcase VIRTCHNL2_OP_CONFIG_TX_QUEUES:\n+\tcase VIRTCHNL2_OP_ENABLE_QUEUES:\n+\tcase VIRTCHNL2_OP_DISABLE_QUEUES:\n \tcase VIRTCHNL2_OP_ENABLE_VPORT:\n \tcase VIRTCHNL2_OP_DISABLE_VPORT:\n \t\t/* for init virtchnl ops, need to poll the response */\n@@ -440,6 +445,448 @@ idpf_vc_destroy_vport(struct idpf_vport *vport)\n \treturn err;\n }\n \n+#define IDPF_RX_BUF_STRIDE\t\t64\n+int\n+idpf_vc_config_rxqs(struct idpf_vport *vport)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct idpf_rx_queue **rxq =\n+\t\t(struct idpf_rx_queue **)vport->dev_data->rx_queues;\n+\tstruct virtchnl2_config_rx_queues *vc_rxqs = NULL;\n+\tstruct virtchnl2_rxq_info *rxq_info;\n+\tstruct idpf_cmd_info args;\n+\tuint16_t total_qs, num_qs;\n+\tint size, i, j;\n+\tint err = 0;\n+\tint k = 0;\n+\n+\ttotal_qs = vport->num_rx_q + vport->num_rx_bufq;\n+\twhile (total_qs) {\n+\t\tif (total_qs > adapter->max_rxq_per_msg) {\n+\t\t\tnum_qs = adapter->max_rxq_per_msg;\n+\t\t\ttotal_qs -= adapter->max_rxq_per_msg;\n+\t\t} else {\n+\t\t\tnum_qs = total_qs;\n+\t\t\ttotal_qs = 0;\n+\t\t}\n+\n+\t\tsize = sizeof(*vc_rxqs) + (num_qs - 1) *\n+\t\t\tsizeof(struct virtchnl2_rxq_info);\n+\t\tvc_rxqs = rte_zmalloc(\"cfg_rxqs\", size, 0);\n+\t\tif (vc_rxqs == NULL) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate virtchnl2_config_rx_queues\");\n+\t\t\terr = -ENOMEM;\n+\t\t\tbreak;\n+\t\t}\n+\t\tvc_rxqs->vport_id = vport->vport_id;\n+\t\tvc_rxqs->num_qinfo = num_qs;\n+\t\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n+\t\t\tfor (i = 0; i < num_qs; i++, k++) {\n+\t\t\t\trxq_info = &vc_rxqs->qinfo[i];\n+\t\t\t\trxq_info->dma_ring_addr = rxq[k]->rx_ring_phys_addr;\n+\t\t\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX;\n+\t\t\t\trxq_info->queue_id = rxq[k]->queue_id;\n+\t\t\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SINGLE;\n+\t\t\t\trxq_info->data_buffer_size = rxq[k]->rx_buf_len;\n+\t\t\t\trxq_info->max_pkt_size = vport->max_pkt_len;\n+\n+\t\t\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M;\n+\t\t\t\trxq_info->qflags |= VIRTCHNL2_RX_DESC_SIZE_32BYTE;\n+\n+\t\t\t\trxq_info->ring_len = rxq[k]->nb_rx_desc;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tfor (i = 0; i < num_qs / 3; i++, k++) {\n+\t\t\t\t/* Rx queue */\n+\t\t\t\trxq_info = &vc_rxqs->qinfo[i * 3];\n+\t\t\t\trxq_info->dma_ring_addr =\n+\t\t\t\t\trxq[k]->rx_ring_phys_addr;\n+\t\t\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX;\n+\t\t\t\trxq_info->queue_id = rxq[k]->queue_id;\n+\t\t\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\t\t\trxq_info->data_buffer_size = rxq[k]->rx_buf_len;\n+\t\t\t\trxq_info->max_pkt_size = vport->max_pkt_len;\n+\n+\t\t\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;\n+\t\t\t\trxq_info->qflags |= VIRTCHNL2_RX_DESC_SIZE_32BYTE;\n+\n+\t\t\t\trxq_info->ring_len = rxq[k]->nb_rx_desc;\n+\t\t\t\trxq_info->rx_bufq1_id = rxq[k]->bufq1->queue_id;\n+\t\t\t\trxq_info->rx_bufq2_id = rxq[k]->bufq2->queue_id;\n+\t\t\t\trxq_info->rx_buffer_low_watermark = 64;\n+\n+\t\t\t\t/* Buffer queue */\n+\t\t\t\tfor (j = 1; j <= IDPF_RX_BUFQ_PER_GRP; j++) {\n+\t\t\t\t\tstruct idpf_rx_queue *bufq = j == 1 ?\n+\t\t\t\t\t\trxq[k]->bufq1 : rxq[k]->bufq2;\n+\t\t\t\t\trxq_info = &vc_rxqs->qinfo[i * 3 + j];\n+\t\t\t\t\trxq_info->dma_ring_addr =\n+\t\t\t\t\t\tbufq->rx_ring_phys_addr;\n+\t\t\t\t\trxq_info->type =\n+\t\t\t\t\t\tVIRTCHNL2_QUEUE_TYPE_RX_BUFFER;\n+\t\t\t\t\trxq_info->queue_id = bufq->queue_id;\n+\t\t\t\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\t\t\t\trxq_info->data_buffer_size = bufq->rx_buf_len;\n+\t\t\t\t\trxq_info->desc_ids =\n+\t\t\t\t\t\tVIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;\n+\t\t\t\t\trxq_info->ring_len = bufq->nb_rx_desc;\n+\n+\t\t\t\t\trxq_info->buffer_notif_stride =\n+\t\t\t\t\t\tIDPF_RX_BUF_STRIDE;\n+\t\t\t\t\trxq_info->rx_buffer_low_watermark = 64;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\tmemset(&args, 0, sizeof(args));\n+\t\targs.ops = VIRTCHNL2_OP_CONFIG_RX_QUEUES;\n+\t\targs.in_args = (uint8_t *)vc_rxqs;\n+\t\targs.in_args_size = size;\n+\t\targs.out_buffer = adapter->mbx_resp;\n+\t\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\n+\t\terr = idpf_execute_vc_cmd(adapter, &args);\n+\t\trte_free(vc_rxqs);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_CONFIG_RX_QUEUES\");\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn err;\n+}\n+\n+int\n+idpf_vc_config_rxq(struct idpf_vport *vport, uint16_t rxq_id)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct idpf_rx_queue **rxq =\n+\t\t(struct idpf_rx_queue **)vport->dev_data->rx_queues;\n+\tstruct virtchnl2_config_rx_queues *vc_rxqs = NULL;\n+\tstruct virtchnl2_rxq_info *rxq_info;\n+\tstruct idpf_cmd_info args;\n+\tuint16_t num_qs;\n+\tint size, err, i;\n+\n+\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE)\n+\t\tnum_qs = IDPF_RXQ_PER_GRP;\n+\telse\n+\t\tnum_qs = IDPF_RXQ_PER_GRP + IDPF_RX_BUFQ_PER_GRP;\n+\n+\tsize = sizeof(*vc_rxqs) + (num_qs - 1) *\n+\t\tsizeof(struct virtchnl2_rxq_info);\n+\tvc_rxqs = rte_zmalloc(\"cfg_rxqs\", size, 0);\n+\tif (vc_rxqs == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate virtchnl2_config_rx_queues\");\n+\t\terr = -ENOMEM;\n+\t\treturn err;\n+\t}\n+\tvc_rxqs->vport_id = vport->vport_id;\n+\tvc_rxqs->num_qinfo = num_qs;\n+\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n+\t\trxq_info = &vc_rxqs->qinfo[0];\n+\t\trxq_info->dma_ring_addr = rxq[rxq_id]->rx_ring_phys_addr;\n+\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX;\n+\t\trxq_info->queue_id = rxq[rxq_id]->queue_id;\n+\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SINGLE;\n+\t\trxq_info->data_buffer_size = rxq[rxq_id]->rx_buf_len;\n+\t\trxq_info->max_pkt_size = vport->max_pkt_len;\n+\n+\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M;\n+\t\trxq_info->qflags |= VIRTCHNL2_RX_DESC_SIZE_32BYTE;\n+\n+\t\trxq_info->ring_len = rxq[rxq_id]->nb_rx_desc;\n+\t}  else {\n+\t\t/* Rx queue */\n+\t\trxq_info = &vc_rxqs->qinfo[0];\n+\t\trxq_info->dma_ring_addr = rxq[rxq_id]->rx_ring_phys_addr;\n+\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX;\n+\t\trxq_info->queue_id = rxq[rxq_id]->queue_id;\n+\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\trxq_info->data_buffer_size = rxq[rxq_id]->rx_buf_len;\n+\t\trxq_info->max_pkt_size = vport->max_pkt_len;\n+\n+\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;\n+\t\trxq_info->qflags |= VIRTCHNL2_RX_DESC_SIZE_32BYTE;\n+\n+\t\trxq_info->ring_len = rxq[rxq_id]->nb_rx_desc;\n+\t\trxq_info->rx_bufq1_id = rxq[rxq_id]->bufq1->queue_id;\n+\t\trxq_info->rx_bufq2_id = rxq[rxq_id]->bufq2->queue_id;\n+\t\trxq_info->rx_buffer_low_watermark = 64;\n+\n+\t\t/* Buffer queue */\n+\t\tfor (i = 1; i <= IDPF_RX_BUFQ_PER_GRP; i++) {\n+\t\t\tstruct idpf_rx_queue *bufq =\n+\t\t\t\ti == 1 ? rxq[rxq_id]->bufq1 : rxq[rxq_id]->bufq2;\n+\t\t\trxq_info = &vc_rxqs->qinfo[i];\n+\t\t\trxq_info->dma_ring_addr = bufq->rx_ring_phys_addr;\n+\t\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX_BUFFER;\n+\t\t\trxq_info->queue_id = bufq->queue_id;\n+\t\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\t\trxq_info->data_buffer_size = bufq->rx_buf_len;\n+\t\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;\n+\t\t\trxq_info->ring_len = bufq->nb_rx_desc;\n+\n+\t\t\trxq_info->buffer_notif_stride = IDPF_RX_BUF_STRIDE;\n+\t\t\trxq_info->rx_buffer_low_watermark = 64;\n+\t\t}\n+\t}\n+\n+\tmemset(&args, 0, sizeof(args));\n+\targs.ops = VIRTCHNL2_OP_CONFIG_RX_QUEUES;\n+\targs.in_args = (uint8_t *)vc_rxqs;\n+\targs.in_args_size = size;\n+\targs.out_buffer = adapter->mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\n+\terr = idpf_execute_vc_cmd(adapter, &args);\n+\trte_free(vc_rxqs);\n+\tif (err != 0)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_CONFIG_RX_QUEUES\");\n+\n+\treturn err;\n+}\n+\n+int\n+idpf_vc_config_txqs(struct idpf_vport *vport)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct idpf_tx_queue **txq =\n+\t\t(struct idpf_tx_queue **)vport->dev_data->tx_queues;\n+\tstruct virtchnl2_config_tx_queues *vc_txqs = NULL;\n+\tstruct virtchnl2_txq_info *txq_info;\n+\tstruct idpf_cmd_info args;\n+\tuint16_t total_qs, num_qs;\n+\tint size, i;\n+\tint err = 0;\n+\tint k = 0;\n+\n+\ttotal_qs = vport->num_tx_q + vport->num_tx_complq;\n+\twhile (total_qs) {\n+\t\tif (total_qs > adapter->max_txq_per_msg) {\n+\t\t\tnum_qs = adapter->max_txq_per_msg;\n+\t\t\ttotal_qs -= adapter->max_txq_per_msg;\n+\t\t} else {\n+\t\t\tnum_qs = total_qs;\n+\t\t\ttotal_qs = 0;\n+\t\t}\n+\t\tsize = sizeof(*vc_txqs) + (num_qs - 1) *\n+\t\t\tsizeof(struct virtchnl2_txq_info);\n+\t\tvc_txqs = rte_zmalloc(\"cfg_txqs\", size, 0);\n+\t\tif (vc_txqs == NULL) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate virtchnl2_config_tx_queues\");\n+\t\t\terr = -ENOMEM;\n+\t\t\tbreak;\n+\t\t}\n+\t\tvc_txqs->vport_id = vport->vport_id;\n+\t\tvc_txqs->num_qinfo = num_qs;\n+\t\tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n+\t\t\tfor (i = 0; i < num_qs; i++, k++) {\n+\t\t\t\ttxq_info = &vc_txqs->qinfo[i];\n+\t\t\t\ttxq_info->dma_ring_addr = txq[k]->tx_ring_phys_addr;\n+\t\t\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX;\n+\t\t\t\ttxq_info->queue_id = txq[k]->queue_id;\n+\t\t\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SINGLE;\n+\t\t\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_QUEUE;\n+\t\t\t\ttxq_info->ring_len = txq[k]->nb_tx_desc;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tfor (i = 0; i < num_qs / 2; i++, k++) {\n+\t\t\t\t/* txq info */\n+\t\t\t\ttxq_info = &vc_txqs->qinfo[2 * i];\n+\t\t\t\ttxq_info->dma_ring_addr = txq[k]->tx_ring_phys_addr;\n+\t\t\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX;\n+\t\t\t\ttxq_info->queue_id = txq[k]->queue_id;\n+\t\t\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\t\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;\n+\t\t\t\ttxq_info->ring_len = txq[k]->nb_tx_desc;\n+\t\t\t\ttxq_info->tx_compl_queue_id =\n+\t\t\t\t\ttxq[k]->complq->queue_id;\n+\t\t\t\ttxq_info->relative_queue_id = txq_info->queue_id;\n+\n+\t\t\t\t/* tx completion queue info */\n+\t\t\t\ttxq_info = &vc_txqs->qinfo[2 * i + 1];\n+\t\t\t\ttxq_info->dma_ring_addr =\n+\t\t\t\t\ttxq[k]->complq->tx_ring_phys_addr;\n+\t\t\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION;\n+\t\t\t\ttxq_info->queue_id = txq[k]->complq->queue_id;\n+\t\t\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\t\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;\n+\t\t\t\ttxq_info->ring_len = txq[k]->complq->nb_tx_desc;\n+\t\t\t}\n+\t\t}\n+\n+\t\tmemset(&args, 0, sizeof(args));\n+\t\targs.ops = VIRTCHNL2_OP_CONFIG_TX_QUEUES;\n+\t\targs.in_args = (uint8_t *)vc_txqs;\n+\t\targs.in_args_size = size;\n+\t\targs.out_buffer = adapter->mbx_resp;\n+\t\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\n+\t\terr = idpf_execute_vc_cmd(adapter, &args);\n+\t\trte_free(vc_txqs);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_CONFIG_TX_QUEUES\");\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn err;\n+}\n+\n+int\n+idpf_vc_config_txq(struct idpf_vport *vport, uint16_t txq_id)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct idpf_tx_queue **txq =\n+\t\t(struct idpf_tx_queue **)vport->dev_data->tx_queues;\n+\tstruct virtchnl2_config_tx_queues *vc_txqs = NULL;\n+\tstruct virtchnl2_txq_info *txq_info;\n+\tstruct idpf_cmd_info args;\n+\tuint16_t num_qs;\n+\tint size, err;\n+\n+\tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE)\n+\t\tnum_qs = IDPF_TXQ_PER_GRP;\n+\telse\n+\t\tnum_qs = IDPF_TXQ_PER_GRP + IDPF_TX_COMPLQ_PER_GRP;\n+\n+\tsize = sizeof(*vc_txqs) + (num_qs - 1) *\n+\t\tsizeof(struct virtchnl2_txq_info);\n+\tvc_txqs = rte_zmalloc(\"cfg_txqs\", size, 0);\n+\tif (vc_txqs == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate virtchnl2_config_tx_queues\");\n+\t\terr = -ENOMEM;\n+\t\treturn err;\n+\t}\n+\tvc_txqs->vport_id = vport->vport_id;\n+\tvc_txqs->num_qinfo = num_qs;\n+\n+\tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n+\t\ttxq_info = &vc_txqs->qinfo[0];\n+\t\ttxq_info->dma_ring_addr = txq[txq_id]->tx_ring_phys_addr;\n+\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX;\n+\t\ttxq_info->queue_id = txq[txq_id]->queue_id;\n+\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SINGLE;\n+\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_QUEUE;\n+\t\ttxq_info->ring_len = txq[txq_id]->nb_tx_desc;\n+\t} else {\n+\t\t/* txq info */\n+\t\ttxq_info = &vc_txqs->qinfo[0];\n+\t\ttxq_info->dma_ring_addr = txq[txq_id]->tx_ring_phys_addr;\n+\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX;\n+\t\ttxq_info->queue_id = txq[txq_id]->queue_id;\n+\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;\n+\t\ttxq_info->ring_len = txq[txq_id]->nb_tx_desc;\n+\t\ttxq_info->tx_compl_queue_id = txq[txq_id]->complq->queue_id;\n+\t\ttxq_info->relative_queue_id = txq_info->queue_id;\n+\n+\t\t/* tx completion queue info */\n+\t\ttxq_info = &vc_txqs->qinfo[1];\n+\t\ttxq_info->dma_ring_addr = txq[txq_id]->complq->tx_ring_phys_addr;\n+\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION;\n+\t\ttxq_info->queue_id = txq[txq_id]->complq->queue_id;\n+\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;\n+\t\ttxq_info->ring_len = txq[txq_id]->complq->nb_tx_desc;\n+\t}\n+\n+\tmemset(&args, 0, sizeof(args));\n+\targs.ops = VIRTCHNL2_OP_CONFIG_TX_QUEUES;\n+\targs.in_args = (uint8_t *)vc_txqs;\n+\targs.in_args_size = size;\n+\targs.out_buffer = adapter->mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\n+\terr = idpf_execute_vc_cmd(adapter, &args);\n+\trte_free(vc_txqs);\n+\tif (err != 0)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_CONFIG_TX_QUEUES\");\n+\n+\treturn err;\n+}\n+\n+static int\n+idpf_vc_ena_dis_one_queue(struct idpf_vport *vport, uint16_t qid,\n+\t\t\t  uint32_t type, bool on)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct virtchnl2_del_ena_dis_queues *queue_select;\n+\tstruct virtchnl2_queue_chunk *queue_chunk;\n+\tstruct idpf_cmd_info args;\n+\tint err, len;\n+\n+\tlen = sizeof(struct virtchnl2_del_ena_dis_queues);\n+\tqueue_select = rte_zmalloc(\"queue_select\", len, 0);\n+\tif (queue_select == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tqueue_chunk = queue_select->chunks.chunks;\n+\tqueue_select->chunks.num_chunks = 1;\n+\tqueue_select->vport_id = vport->vport_id;\n+\n+\tqueue_chunk->type = type;\n+\tqueue_chunk->start_queue_id = qid;\n+\tqueue_chunk->num_queues = 1;\n+\n+\targs.ops = on ? VIRTCHNL2_OP_ENABLE_QUEUES :\n+\t\tVIRTCHNL2_OP_DISABLE_QUEUES;\n+\targs.in_args = (u8 *)queue_select;\n+\targs.in_args_size = len;\n+\targs.out_buffer = adapter->mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\terr = idpf_execute_vc_cmd(adapter, &args);\n+\tif (err != 0)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_%s_QUEUES\",\n+\t\t\t    on ? \"ENABLE\" : \"DISABLE\");\n+\n+\trte_free(queue_select);\n+\treturn err;\n+}\n+\n+int\n+idpf_switch_queue(struct idpf_vport *vport, uint16_t qid,\n+\t\t     bool rx, bool on)\n+{\n+\tuint32_t type;\n+\tint err, queue_id;\n+\n+\t/* switch txq/rxq */\n+\ttype = rx ? VIRTCHNL2_QUEUE_TYPE_RX : VIRTCHNL2_QUEUE_TYPE_TX;\n+\n+\tif (type == VIRTCHNL2_QUEUE_TYPE_RX)\n+\t\tqueue_id = vport->chunks_info.rx_start_qid + qid;\n+\telse\n+\t\tqueue_id = vport->chunks_info.tx_start_qid + qid;\n+\terr = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\t/* switch tx completion queue */\n+\tif (!rx && vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n+\t\ttype = VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION;\n+\t\tqueue_id = vport->chunks_info.tx_compl_start_qid + qid;\n+\t\terr = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);\n+\t\tif (err != 0)\n+\t\t\treturn err;\n+\t}\n+\n+\t/* switch rx buffer queue */\n+\tif (rx && vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n+\t\ttype = VIRTCHNL2_QUEUE_TYPE_RX_BUFFER;\n+\t\tqueue_id = vport->chunks_info.rx_buf_start_qid + 2 * qid;\n+\t\terr = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);\n+\t\tif (err != 0)\n+\t\t\treturn err;\n+\t\tqueue_id++;\n+\t\terr = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);\n+\t\tif (err != 0)\n+\t\t\treturn err;\n+\t}\n+\n+\treturn err;\n+}\n+\n int\n idpf_vc_ena_dis_vport(struct idpf_vport *vport, bool enable)\n {\n",
    "prefixes": [
        "v13",
        "06/18"
    ]
}