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GET /api/patches/119206/?format=api
{ "id": 119206, "url": "http://patchwork.dpdk.org/api/patches/119206/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221027054505.1369248-12-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221027054505.1369248-12-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221027054505.1369248-12-junfeng.guo@intel.com", "date": "2022-10-27T05:44:58", "name": "[v13,11/18] net/idpf: add support for basic Tx datapath", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a376f83e408647c104825cafbded822bdf1e1431", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 3961, "url": "http://patchwork.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221027054505.1369248-12-junfeng.guo@intel.com/mbox/", "series": [ { "id": 25450, "url": "http://patchwork.dpdk.org/api/series/25450/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25450", "date": "2022-10-27T05:44:47", "name": "add support for idpf PMD in DPDK", "version": 13, "mbox": "http://patchwork.dpdk.org/series/25450/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/119206/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/119206/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E5DD8A00C5;\n\tThu, 27 Oct 2022 07:48:12 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0717E42BE2;\n\tThu, 27 Oct 2022 07:47:27 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id 64DE542BF0\n for <dev@dpdk.org>; Thu, 27 Oct 2022 07:47:16 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Oct 2022 22:47:16 -0700", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by orsmga003.jf.intel.com with ESMTP; 26 Oct 2022 22:47:13 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1666849636; x=1698385636;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=BcVw0ZsUci71pnmSIKX0jMeXfG6a0ply1YSpxb8/grU=;\n b=L48lf2NXrUzo1HD34uCK4kHTLN5mH2UupclEhMRwTAgim7TN+ApVu3AU\n 39UaVlfzjj49FggV2p8sh/4vcNAVN02TeiscHhoQfr1GYQ0wsQHp94rHL\n csqZn1JuOSf6aWfuJEwpH8pnZpBQ9aGLeC0mkufqJlqRNEWYRQs2MSQq7\n 78lWn5mcikQGefjhqS2+FGu/UeVSDA2cWfxArYce1JhrVOCopkNjxH9UB\n ekX9NqIEChUC6nrd8C+cRvW5z8KZ8i9aWAUUvpjHsIyZfiolLeNVVkpDW\n d0J+YrUJy65lkec2KuGCQtd3m7uIMuZwUdydCayFOFMzt0X7a2T6pU3x8 w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10512\"; a=\"309831082\"", "E=Sophos;i=\"5.95,215,1661842800\"; d=\"scan'208\";a=\"309831082\"", "E=McAfee;i=\"6500,9779,10512\"; a=\"583429289\"", "E=Sophos;i=\"5.95,215,1661842800\"; d=\"scan'208\";a=\"583429289\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "andrew.rybchenko@oktetlabs.ru, qi.z.zhang@intel.com,\n jingjing.wu@intel.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, Junfeng Guo <junfeng.guo@intel.com>,\n Xiaoyun Li <xiaoyun.li@intel.com>", "Subject": "[PATCH v13 11/18] net/idpf: add support for basic Tx datapath", "Date": "Thu, 27 Oct 2022 13:44:58 +0800", "Message-Id": "<20221027054505.1369248-12-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20221027054505.1369248-1-junfeng.guo@intel.com>", "References": "<20221026101027.240583-2-junfeng.guo@intel.com>\n <20221027054505.1369248-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add basic Tx support in split queue mode and single queue mode.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\nSigned-off-by: Xiaoyun Li <xiaoyun.li@intel.com>\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n drivers/net/idpf/idpf_ethdev.c | 3 +\n drivers/net/idpf/idpf_ethdev.h | 1 +\n drivers/net/idpf/idpf_rxtx.c | 357 +++++++++++++++++++++++++++++++++\n drivers/net/idpf/idpf_rxtx.h | 10 +\n 4 files changed, 371 insertions(+)", "diff": "diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c\nindex df2a760673..6fb56e584d 100644\n--- a/drivers/net/idpf/idpf_ethdev.c\n+++ b/drivers/net/idpf/idpf_ethdev.c\n@@ -88,6 +88,8 @@ idpf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \n \tdev_info->max_mac_addrs = IDPF_NUM_MACADDR_MAX;\n \n+\tdev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS;\n+\n \tdev_info->default_txconf = (struct rte_eth_txconf) {\n \t\t.tx_free_thresh = IDPF_DEFAULT_TX_FREE_THRESH,\n \t\t.tx_rs_thresh = IDPF_DEFAULT_TX_RS_THRESH,\n@@ -376,6 +378,7 @@ idpf_dev_start(struct rte_eth_dev *dev)\n \t}\n \n \tidpf_set_rx_function(dev);\n+\tidpf_set_tx_function(dev);\n \n \tif (idpf_vc_ena_dis_vport(vport, true) != 0) {\n \t\tPMD_DRV_LOG(ERR, \"Failed to enable vport\");\ndiff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h\nindex 96c22009e9..af0a8e2970 100644\n--- a/drivers/net/idpf/idpf_ethdev.h\n+++ b/drivers/net/idpf/idpf_ethdev.h\n@@ -35,6 +35,7 @@\n \n #define IDPF_MIN_BUF_SIZE\t1024\n #define IDPF_MAX_FRAME_SIZE\t9728\n+#define IDPF_MIN_FRAME_SIZE\t14\n \n #define IDPF_NUM_MACADDR_MAX\t64\n \ndiff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c\nindex ea499c4d37..f55d2143b9 100644\n--- a/drivers/net/idpf/idpf_rxtx.c\n+++ b/drivers/net/idpf/idpf_rxtx.c\n@@ -1365,6 +1365,148 @@ idpf_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \treturn nb_rx;\n }\n \n+static inline void\n+idpf_split_tx_free(struct idpf_tx_queue *cq)\n+{\n+\tvolatile struct idpf_splitq_tx_compl_desc *compl_ring = cq->compl_ring;\n+\tvolatile struct idpf_splitq_tx_compl_desc *txd;\n+\tuint16_t next = cq->tx_tail;\n+\tstruct idpf_tx_entry *txe;\n+\tstruct idpf_tx_queue *txq;\n+\tuint16_t gen, qid, q_head;\n+\tuint8_t ctype;\n+\n+\ttxd = &compl_ring[next];\n+\tgen = (rte_le_to_cpu_16(txd->qid_comptype_gen) &\n+\t\tIDPF_TXD_COMPLQ_GEN_M) >> IDPF_TXD_COMPLQ_GEN_S;\n+\tif (gen != cq->expected_gen_id)\n+\t\treturn;\n+\n+\tctype = (rte_le_to_cpu_16(txd->qid_comptype_gen) &\n+\t\tIDPF_TXD_COMPLQ_COMPL_TYPE_M) >> IDPF_TXD_COMPLQ_COMPL_TYPE_S;\n+\tqid = (rte_le_to_cpu_16(txd->qid_comptype_gen) &\n+\t\tIDPF_TXD_COMPLQ_QID_M) >> IDPF_TXD_COMPLQ_QID_S;\n+\tq_head = rte_le_to_cpu_16(txd->q_head_compl_tag.compl_tag);\n+\ttxq = cq->txqs[qid - cq->tx_start_qid];\n+\n+\tswitch (ctype) {\n+\tcase IDPF_TXD_COMPLT_RE:\n+\t\tif (q_head == 0)\n+\t\t\ttxq->last_desc_cleaned = txq->nb_tx_desc - 1;\n+\t\telse\n+\t\t\ttxq->last_desc_cleaned = q_head - 1;\n+\t\tif (unlikely((txq->last_desc_cleaned % 32) == 0)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"unexpected desc (head = %u) completion.\",\n+\t\t\t\t\t\tq_head);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tbreak;\n+\tcase IDPF_TXD_COMPLT_RS:\n+\t\ttxq->nb_free++;\n+\t\ttxq->nb_used--;\n+\t\ttxe = &txq->sw_ring[q_head];\n+\t\tif (txe->mbuf != NULL) {\n+\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n+\t\t\ttxe->mbuf = NULL;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"unknown completion type.\");\n+\t\treturn;\n+\t}\n+\n+\tif (++next == cq->nb_tx_desc) {\n+\t\tnext = 0;\n+\t\tcq->expected_gen_id ^= 1;\n+\t}\n+\n+\tcq->tx_tail = next;\n+}\n+\n+uint16_t\n+idpf_splitq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tstruct idpf_tx_queue *txq = (struct idpf_tx_queue *)tx_queue;\n+\tvolatile struct idpf_flex_tx_sched_desc *txr;\n+\tvolatile struct idpf_flex_tx_sched_desc *txd;\n+\tstruct idpf_tx_entry *sw_ring;\n+\tstruct idpf_tx_entry *txe, *txn;\n+\tuint16_t nb_used, tx_id, sw_id;\n+\tstruct rte_mbuf *tx_pkt;\n+\tuint16_t nb_to_clean;\n+\tuint16_t nb_tx = 0;\n+\n+\tif (unlikely(txq == NULL) || unlikely(!txq->q_started))\n+\t\treturn nb_tx;\n+\n+\ttxr = txq->desc_ring;\n+\tsw_ring = txq->sw_ring;\n+\ttx_id = txq->tx_tail;\n+\tsw_id = txq->sw_tail;\n+\ttxe = &sw_ring[sw_id];\n+\n+\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n+\t\ttx_pkt = tx_pkts[nb_tx];\n+\n+\t\tif (txq->nb_free <= txq->free_thresh) {\n+\t\t\t/* TODO: Need to refine\n+\t\t\t * 1. free and clean: Better to decide a clean destination instead of\n+\t\t\t * loop times. And don't free mbuf when RS got immediately, free when\n+\t\t\t * transmit or according to the clean destination.\n+\t\t\t * Now, just ignore the RE write back, free mbuf when get RS\n+\t\t\t * 2. out-of-order rewrite back haven't be supported, SW head and HW head\n+\t\t\t * need to be separated.\n+\t\t\t **/\n+\t\t\tnb_to_clean = 2 * txq->rs_thresh;\n+\t\t\twhile (nb_to_clean--)\n+\t\t\t\tidpf_split_tx_free(txq->complq);\n+\t\t}\n+\n+\t\tif (txq->nb_free < tx_pkt->nb_segs)\n+\t\t\tbreak;\n+\t\tnb_used = tx_pkt->nb_segs;\n+\n+\t\tdo {\n+\t\t\ttxd = &txr[tx_id];\n+\t\t\ttxn = &sw_ring[txe->next_id];\n+\t\t\ttxe->mbuf = tx_pkt;\n+\n+\t\t\t/* Setup TX descriptor */\n+\t\t\ttxd->buf_addr =\n+\t\t\t\trte_cpu_to_le_64(rte_mbuf_data_iova(tx_pkt));\n+\t\t\ttxd->qw1.cmd_dtype =\n+\t\t\t\trte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE);\n+\t\t\ttxd->qw1.rxr_bufsize = tx_pkt->data_len;\n+\t\t\ttxd->qw1.compl_tag = sw_id;\n+\t\t\ttx_id++;\n+\t\t\tif (tx_id == txq->nb_tx_desc)\n+\t\t\t\ttx_id = 0;\n+\t\t\tsw_id = txe->next_id;\n+\t\t\ttxe = txn;\n+\t\t\ttx_pkt = tx_pkt->next;\n+\t\t} while (tx_pkt);\n+\n+\t\t/* fill the last descriptor with End of Packet (EOP) bit */\n+\t\ttxd->qw1.cmd_dtype |= IDPF_TXD_FLEX_FLOW_CMD_EOP;\n+\n+\t\tif (unlikely((tx_id % 32) == 0))\n+\t\t\ttxd->qw1.cmd_dtype |= IDPF_TXD_FLEX_FLOW_CMD_RE;\n+\t\ttxq->nb_free = (uint16_t)(txq->nb_free - nb_used);\n+\t\ttxq->nb_used = (uint16_t)(txq->nb_used + nb_used);\n+\t}\n+\n+\t/* update the tail pointer if any packets were processed */\n+\tif (likely(nb_tx > 0)) {\n+\t\tIDPF_PCI_REG_WRITE(txq->qtx_tail, tx_id);\n+\t\ttxq->tx_tail = tx_id;\n+\t\ttxq->sw_tail = sw_id;\n+\t}\n+\n+\treturn nb_tx;\n+}\n+\n static inline void\n idpf_update_rx_tail(struct idpf_rx_queue *rxq, uint16_t nb_hold,\n \t\t uint16_t rx_id)\n@@ -1471,6 +1613,208 @@ idpf_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \treturn nb_rx;\n }\n \n+static inline int\n+idpf_xmit_cleanup(struct idpf_tx_queue *txq)\n+{\n+\tuint16_t last_desc_cleaned = txq->last_desc_cleaned;\n+\tstruct idpf_tx_entry *sw_ring = txq->sw_ring;\n+\tuint16_t nb_tx_desc = txq->nb_tx_desc;\n+\tuint16_t desc_to_clean_to;\n+\tuint16_t nb_tx_to_clean;\n+\tuint16_t i;\n+\n+\tvolatile struct idpf_flex_tx_desc *txd = txq->tx_ring;\n+\n+\tdesc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);\n+\tif (desc_to_clean_to >= nb_tx_desc)\n+\t\tdesc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);\n+\n+\tdesc_to_clean_to = sw_ring[desc_to_clean_to].last_id;\n+\t/* In the writeback Tx desccriptor, the only significant fields are the 4-bit DTYPE */\n+\tif ((txd[desc_to_clean_to].qw1.cmd_dtype &\n+\t\t\trte_cpu_to_le_16(IDPF_TXD_QW1_DTYPE_M)) !=\n+\t\t\trte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_DESC_DONE)) {\n+\t\tPMD_TX_LOG(DEBUG, \"TX descriptor %4u is not done \"\n+\t\t\t \"(port=%d queue=%d)\", desc_to_clean_to,\n+\t\t\t txq->port_id, txq->queue_id);\n+\t\treturn -1;\n+\t}\n+\n+\tif (last_desc_cleaned > desc_to_clean_to)\n+\t\tnb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +\n+\t\t\t\t\t desc_to_clean_to);\n+\telse\n+\t\tnb_tx_to_clean = (uint16_t)(desc_to_clean_to -\n+\t\t\t\t\tlast_desc_cleaned);\n+\n+\ttxd[desc_to_clean_to].qw1.cmd_dtype = 0;\n+\ttxd[desc_to_clean_to].qw1.buf_size = 0;\n+\tfor (i = 0; i < RTE_DIM(txd[desc_to_clean_to].qw1.flex.raw); i++)\n+\t\ttxd[desc_to_clean_to].qw1.flex.raw[i] = 0;\n+\n+\ttxq->last_desc_cleaned = desc_to_clean_to;\n+\ttxq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);\n+\n+\treturn 0;\n+}\n+\n+/* TX function */\n+uint16_t\n+idpf_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tvolatile struct idpf_flex_tx_desc *txd;\n+\tvolatile struct idpf_flex_tx_desc *txr;\n+\tstruct idpf_tx_entry *txe, *txn;\n+\tstruct idpf_tx_entry *sw_ring;\n+\tstruct idpf_tx_queue *txq;\n+\tstruct rte_mbuf *tx_pkt;\n+\tstruct rte_mbuf *m_seg;\n+\tuint64_t buf_dma_addr;\n+\tuint16_t tx_last;\n+\tuint16_t nb_used;\n+\tuint16_t td_cmd;\n+\tuint16_t tx_id;\n+\tuint16_t nb_tx;\n+\tuint16_t slen;\n+\n+\tnb_tx = 0;\n+\ttxq = tx_queue;\n+\n+\tif (unlikely(txq == NULL) || unlikely(!txq->q_started))\n+\t\treturn nb_tx;\n+\n+\tsw_ring = txq->sw_ring;\n+\ttxr = txq->tx_ring;\n+\ttx_id = txq->tx_tail;\n+\ttxe = &sw_ring[tx_id];\n+\n+\t/* Check if the descriptor ring needs to be cleaned. */\n+\tif (txq->nb_free < txq->free_thresh)\n+\t\t(void)idpf_xmit_cleanup(txq);\n+\n+\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n+\t\ttd_cmd = 0;\n+\n+\t\ttx_pkt = *tx_pkts++;\n+\t\tRTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);\n+\n+\t\t/* The number of descriptors that must be allocated for\n+\t\t * a packet equals to the number of the segments of that\n+\t\t * packet plus 1 context descriptor if needed.\n+\t\t */\n+\t\tnb_used = (uint16_t)(tx_pkt->nb_segs);\n+\t\ttx_last = (uint16_t)(tx_id + nb_used - 1);\n+\n+\t\t/* Circular ring */\n+\t\tif (tx_last >= txq->nb_tx_desc)\n+\t\t\ttx_last = (uint16_t)(tx_last - txq->nb_tx_desc);\n+\n+\t\tPMD_TX_LOG(DEBUG, \"port_id=%u queue_id=%u\"\n+\t\t\t \" tx_first=%u tx_last=%u\",\n+\t\t\t txq->port_id, txq->queue_id, tx_id, tx_last);\n+\n+\t\tif (nb_used > txq->nb_free) {\n+\t\t\tif (idpf_xmit_cleanup(txq) != 0) {\n+\t\t\t\tif (nb_tx == 0)\n+\t\t\t\t\treturn 0;\n+\t\t\t\tgoto end_of_tx;\n+\t\t\t}\n+\t\t\tif (unlikely(nb_used > txq->rs_thresh)) {\n+\t\t\t\twhile (nb_used > txq->nb_free) {\n+\t\t\t\t\tif (idpf_xmit_cleanup(txq) != 0) {\n+\t\t\t\t\t\tif (nb_tx == 0)\n+\t\t\t\t\t\t\treturn 0;\n+\t\t\t\t\t\tgoto end_of_tx;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tm_seg = tx_pkt;\n+\t\tdo {\n+\t\t\ttxd = &txr[tx_id];\n+\t\t\ttxn = &sw_ring[txe->next_id];\n+\n+\t\t\tif (txe->mbuf != NULL)\n+\t\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n+\t\t\ttxe->mbuf = m_seg;\n+\n+\t\t\t/* Setup TX Descriptor */\n+\t\t\tslen = m_seg->data_len;\n+\t\t\tbuf_dma_addr = rte_mbuf_data_iova(m_seg);\n+\t\t\ttxd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);\n+\t\t\ttxd->qw1.buf_size = slen;\n+\t\t\ttxd->qw1.cmd_dtype = rte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_FLEX_DATA <<\n+\t\t\t\t\t\t\t IDPF_FLEX_TXD_QW1_DTYPE_S);\n+\n+\t\t\ttxe->last_id = tx_last;\n+\t\t\ttx_id = txe->next_id;\n+\t\t\ttxe = txn;\n+\t\t\tm_seg = m_seg->next;\n+\t\t} while (m_seg);\n+\n+\t\t/* The last packet data descriptor needs End Of Packet (EOP) */\n+\t\ttd_cmd |= IDPF_TX_FLEX_DESC_CMD_EOP;\n+\t\ttxq->nb_used = (uint16_t)(txq->nb_used + nb_used);\n+\t\ttxq->nb_free = (uint16_t)(txq->nb_free - nb_used);\n+\n+\t\tif (txq->nb_used >= txq->rs_thresh) {\n+\t\t\tPMD_TX_LOG(DEBUG, \"Setting RS bit on TXD id=\"\n+\t\t\t\t \"%4u (port=%d queue=%d)\",\n+\t\t\t\t tx_last, txq->port_id, txq->queue_id);\n+\n+\t\t\ttd_cmd |= IDPF_TX_FLEX_DESC_CMD_RS;\n+\n+\t\t\t/* Update txq RS bit counters */\n+\t\t\ttxq->nb_used = 0;\n+\t\t}\n+\n+\t\ttxd->qw1.cmd_dtype |= rte_cpu_to_le_16(td_cmd << IDPF_FLEX_TXD_QW1_CMD_S);\n+\t}\n+\n+end_of_tx:\n+\trte_wmb();\n+\n+\tPMD_TX_LOG(DEBUG, \"port_id=%u queue_id=%u tx_tail=%u nb_tx=%u\",\n+\t\t txq->port_id, txq->queue_id, tx_id, nb_tx);\n+\n+\tIDPF_PCI_REG_WRITE(txq->qtx_tail, tx_id);\n+\ttxq->tx_tail = tx_id;\n+\n+\treturn nb_tx;\n+}\n+\n+/* TX prep functions */\n+uint16_t\n+idpf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t uint16_t nb_pkts)\n+{\n+\tint i;\n+\tuint64_t ol_flags;\n+\tstruct rte_mbuf *m;\n+\n+\tfor (i = 0; i < nb_pkts; i++) {\n+\t\tm = tx_pkts[i];\n+\t\tol_flags = m->ol_flags;\n+\n+\t\t/* Check condition for nb_segs > IDPF_TX_MAX_MTU_SEG. */\n+\t\tif ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) == 0) {\n+\t\t\tif (m->nb_segs > IDPF_TX_MAX_MTU_SEG) {\n+\t\t\t\trte_errno = EINVAL;\n+\t\t\t\treturn i;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (m->pkt_len < IDPF_MIN_FRAME_SIZE) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn i;\n+\t\t}\n+\t}\n+\n+\treturn i;\n+}\n+\n void\n idpf_set_rx_function(struct rte_eth_dev *dev)\n {\n@@ -1481,3 +1825,16 @@ idpf_set_rx_function(struct rte_eth_dev *dev)\n \telse\n \t\tdev->rx_pkt_burst = idpf_singleq_recv_pkts;\n }\n+\n+void\n+idpf_set_tx_function(struct rte_eth_dev *dev)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n+\t\tdev->tx_pkt_burst = idpf_splitq_xmit_pkts;\n+\t\tdev->tx_pkt_prepare = idpf_prep_pkts;\n+\t} else {\n+\t\tdev->tx_pkt_burst = idpf_singleq_xmit_pkts;\n+\t\tdev->tx_pkt_prepare = idpf_prep_pkts;\n+\t}\n+}\ndiff --git a/drivers/net/idpf/idpf_rxtx.h b/drivers/net/idpf/idpf_rxtx.h\nindex 650c6c1c3a..30dc94b3dd 100644\n--- a/drivers/net/idpf/idpf_rxtx.h\n+++ b/drivers/net/idpf/idpf_rxtx.h\n@@ -21,6 +21,8 @@\n #define IDPF_DEFAULT_TX_RS_THRESH\t32\n #define IDPF_DEFAULT_TX_FREE_THRESH\t32\n \n+#define IDPF_TX_MAX_MTU_SEG\t10\n+\n struct idpf_rx_queue {\n \tstruct idpf_adapter *adapter; /* the adapter this queue belongs to */\n \tstruct rte_mempool *mp; /* mbuf pool to populate Rx ring */\n@@ -137,7 +139,15 @@ uint16_t idpf_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t\tuint16_t nb_pkts);\n uint16_t idpf_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t uint16_t nb_pkts);\n+uint16_t idpf_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t\tuint16_t nb_pkts);\n+uint16_t idpf_splitq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts);\n+uint16_t idpf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\tuint16_t nb_pkts);\n+\n void idpf_stop_queues(struct rte_eth_dev *dev);\n \n void idpf_set_rx_function(struct rte_eth_dev *dev);\n+void idpf_set_tx_function(struct rte_eth_dev *dev);\n #endif /* _IDPF_RXTX_H_ */\n", "prefixes": [ "v13", "11/18" ] }