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GET /api/patches/119820/?format=api
{ "id": 119820, "url": "http://patchwork.dpdk.org/api/patches/119820/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221114105321.163430-2-rbhansali@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221114105321.163430-2-rbhansali@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221114105321.163430-2-rbhansali@marvell.com", "date": "2022-11-14T10:53:21", "name": "[2/2] net/cnxk: update IPsec completion code handling", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "4071a9bf0662fe6abd190622327c6f0095bec795", "submitter": { "id": 2436, "url": "http://patchwork.dpdk.org/api/people/2436/?format=api", "name": "Rahul Bhansali", "email": "rbhansali@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221114105321.163430-2-rbhansali@marvell.com/mbox/", "series": [ { "id": 25751, "url": "http://patchwork.dpdk.org/api/series/25751/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25751", "date": "2022-11-14T10:53:20", "name": "[1/2] common/cnxk: update IPsec completion codes", "version": 1, "mbox": "http://patchwork.dpdk.org/series/25751/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/119820/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/119820/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 60725A0032;\n\tMon, 14 Nov 2022 11:53:51 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5095042D0C;\n\tMon, 14 Nov 2022 11:53:51 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 928C742C29\n for <dev@dpdk.org>; Mon, 14 Nov 2022 11:53:50 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 2AE6h1Yd008489 for <dev@dpdk.org>; Mon, 14 Nov 2022 02:53:50 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kugnb0rf0-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 14 Nov 2022 02:53:49 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 14 Nov 2022 02:53:47 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 14 Nov 2022 02:53:47 -0800", "from localhost.localdomain (unknown [10.28.36.158])\n by maili.marvell.com (Postfix) with ESMTP id EABDB5C68E9;\n Mon, 14 Nov 2022 02:53:44 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=WDf8uCiMBsnWClgmjR7/ccBPwj5DlbHMYRgBu3AQ0Bw=;\n b=a+3AIOEojYah+sQaf8/Nez80gVpE8kIkhDJzieK5Hjq8I0+NvpyXd/eTQjNq3Sq+CXlt\n pKISk0XzLzbkEYmmDCSDuhlvveVMNgE77AolgRO5VdUDGYZcaRTB7viL0CXbwmu8/kr6\n cVWNGQiY6Izb0XTE7cU0ZPGxpMNG32AtTmtxyurX1ujq5mVqo2+dG31UTPeIcbjxKC1M\n B/M223Pkwy1Okgo96jBznn9xThVu9wew8g/2mgn3qletvxxAd4abm3zTC5ZexTL1ZNzs\n UluRjPP3Yi05QnVdasceyFGMMFWoXMEyn5TT+VMhm0mJY4Z/J8nVI+32obW3tNh04qfn QQ==", "From": "Rahul Bhansali <rbhansali@marvell.com>", "To": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, Rahul Bhansali <rbhansali@marvell.com>", "Subject": "[PATCH 2/2] net/cnxk: update IPsec completion code handling", "Date": "Mon, 14 Nov 2022 16:23:21 +0530", "Message-ID": "<20221114105321.163430-2-rbhansali@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221114105321.163430-1-rbhansali@marvell.com>", "References": "<20221114105321.163430-1-rbhansali@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "wlkcssh_z1hhEHI2gRtdofmvsRGJCOha", "X-Proofpoint-GUID": "wlkcssh_z1hhEHI2gRtdofmvsRGJCOha", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-11-14_10,2022-11-11_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Update IPsec handling with reference from UCODE version\nOCPT-04-IE-IPSEC-MC-30-01-28-00\n\nSigned-off-by: Rahul Bhansali <rbhansali@marvell.com>\n---\n drivers/net/cnxk/cn10k_rx.h | 170 ++++++++++++++++++++----------------\n 1 file changed, 95 insertions(+), 75 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex 4e22ceda02..ff01c2d8b3 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -42,17 +42,12 @@\n \t\t (uint64_t *)(((uintptr_t)((uint64_t *)(b))[i]) - (o)) : \\\n \t\t (uint64_t *)(((uintptr_t)(b)) + CQE_SZ(i) - (o)))\n \n-#define NIX_RX_SEC_UCC_CONST \\\n-\t((RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1) << 8 | \\\n-\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \\\n-\t\t << 24 | \\\n-\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1) \\\n-\t\t << 32 | \\\n-\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \\\n-\t\t << 40 | \\\n-\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \\\n-\t\t << 48 | \\\n-\t (RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1) << 56)\n+#define NIX_RX_SEC_UCC_CONST \\\n+\t((RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1) | \\\n+\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) << 8 | \\\n+\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1) << 16 | \\\n+\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) << 32 | \\\n+\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) << 48)\n \n #ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n static inline void\n@@ -475,16 +470,23 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, const uint64_t sa_base,\n \t\t\tinner->data_len = len;\n \t\t\t*(uint64_t *)(&inner->rearm_data) = mbuf_init;\n \n-\t\t\tinner->ol_flags = ((ucc == CPT_COMP_WARN) ?\n+\t\t\tinner->ol_flags = ((CPT_COMP_HWGOOD_MASK & (1U << ucc)) ?\n \t\t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD :\n \t\t\t\t\t (RTE_MBUF_F_RX_SEC_OFFLOAD |\n \t\t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED));\n \n \t\t\tucc = hdr->w3.uc_ccode;\n-\t\t\tinner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?\n-\t\t\t\t((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3))\n-\t\t\t\t & 0xFF) << 1 : 0;\n-\t\t} else if (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) {\n+\n+\t\t\tif (ucc && ucc < 0xED) {\n+\t\t\t\tinner->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;\n+\t\t\t} else {\n+\t\t\t\tucc += 3; /* To make codes in 0xFx series except 0 */\n+\t\t\t\tinner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?\n+\t\t\t\t\t\t ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3))\n+\t\t\t\t\t\t & 0xFF) << 1 : RTE_MBUF_F_RX_IP_CKSUM_GOOD;\n+\t\t\t}\n+\t\t} else if ((!(hdr->w0.err_sum) || roc_ie_ot_ucc_is_success(hdr->w3.uc_ccode)) &&\n+\t\t\t !(hdr->w0.reas_sts)) {\n \t\t\t/* Reassembly success */\n \t\t\tinner = nix_sec_reassemble_frags(hdr, cq_w1, cq_w5,\n \t\t\t\t\t\t\t mbuf_init);\n@@ -541,15 +543,21 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, const uint64_t sa_base,\n \t\tinner->data_len = len;\n \t\t*(uint64_t *)(&inner->rearm_data) = mbuf_init;\n \n-\t\tinner->ol_flags = ((ucc == CPT_COMP_WARN) ?\n+\t\tinner->ol_flags = ((CPT_COMP_HWGOOD_MASK & (1U << ucc)) ?\n \t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD :\n \t\t\t\t (RTE_MBUF_F_RX_SEC_OFFLOAD |\n \t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED));\n \n \t\tucc = hdr->w3.uc_ccode;\n-\t\tinner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?\n-\t\t\t((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3))\n-\t\t\t & 0xFF) << 1 : 0;\n+\n+\t\tif (ucc && ucc < 0xED) {\n+\t\t\tinner->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;\n+\t\t} else {\n+\t\t\tucc += 3; /* To make codes in 0xFx series except 0 */\n+\t\t\tinner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?\n+\t\t\t\t\t ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3))\n+\t\t\t\t\t & 0xFF) << 1 : RTE_MBUF_F_RX_IP_CKSUM_GOOD;\n+\t\t}\n \n \t\t/* Store meta in lmtline to free\n \t\t * Assume all meta's from same aura.\n@@ -596,7 +604,8 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uint64_t cq_w5, uintptr_t inb_sa,\n \tRTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&inner, 1, 1);\n \n \tif (flags & NIX_RX_REAS_F && hdr->w0.num_frags) {\n-\t\tif (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) {\n+\t\tif ((!(hdr->w0.err_sum) || roc_ie_ot_ucc_is_success(hdr->w3.uc_ccode)) &&\n+\t\t !(hdr->w0.reas_sts)) {\n \t\t\t/* Reassembly success */\n \t\t\tnix_sec_reassemble_frags(hdr, cq_w1, cq_w5, mbuf_init);\n \n@@ -1317,6 +1326,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\tuintptr_t cpth1 = (uintptr_t)mbuf1 + d_off;\n \t\t\tuintptr_t cpth2 = (uintptr_t)mbuf2 + d_off;\n \t\t\tuintptr_t cpth3 = (uintptr_t)mbuf3 + d_off;\n+\t\t\tuint8_t code;\n \n \t\t\tuint64x2_t inner0, inner1, inner2, inner3;\n \t\t\tuint64x2_t wqe01, wqe23, sa01, sa23;\n@@ -1352,42 +1362,46 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\tsa01 = vaddq_u64(sa01, vdupq_n_u64(sa_base));\n \t\t\tsa23 = vaddq_u64(sa23, vdupq_n_u64(sa_base));\n \n-\t\t\tconst uint8x16_t tbl = {\n-\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST */\n-\t\t\t\t0,\n-\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM */\n-\t\t\t\tRTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,\n-\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_AGAIN */\n-\t\t\t\t0,\n-\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM */\n-\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n-\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,\n-\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM */\n-\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n-\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,\n-\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM */\n-\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n-\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,\n-\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_UDP_ZEROCSUM */\n-\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n-\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,\n-\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM */\n-\t\t\t\tRTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1,\n-\t\t\t\t/* HW_CCODE -> RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED */\n-\t\t\t\t1, 0, 1, 1, 1, 1, 0, 1,\n-\t\t\t};\n-\n-\t\t\tconst int8x8_t err_off = {\n-\t\t\t\t/* UCC of significance starts from 0xF0 */\n-\t\t\t\t0xF0,\n-\t\t\t\t/* Move HW_CCODE from 0:6 -> 8:14 */\n-\t\t\t\t-8,\n-\t\t\t\t0xF0,\n-\t\t\t\t-8,\n-\t\t\t\t0xF0,\n-\t\t\t\t-8,\n-\t\t\t\t0xF0,\n-\t\t\t\t-8,\n+\t\t\tconst uint8x16x2_t tbl = {{\n+\t\t\t\t{\n+\t\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM */\n+\t\t\t\t\tRTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,\n+\t\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM */\n+\t\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n+\t\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,\n+\t\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM */\n+\t\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n+\t\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,\n+\t\t\t\t\t1,\n+\t\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM */\n+\t\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n+\t\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,\n+\t\t\t\t\t1,\n+\t\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_UDP_ZEROCSUM */\n+\t\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n+\t\t\t\t\tRTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,\n+\t\t\t\t\t3, 1, 3, 3, 3, 3, 1, 3, 1,\n+\t\t\t\t},\n+\t\t\t\t{\n+\t\t\t\t\t1, 1, 1,\n+\t\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM */\n+\t\t\t\t\tRTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1,\n+\t\t\t\t\t/* Rest 0 to indicate RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED */\n+\t\t\t\t\t0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t\t\t},\n+\t\t\t}};\n+\n+\t\t\tconst uint8x8_t err_off = {\n+\t\t\t\t/* UCC */\n+\t\t\t\t0xED,\n+\t\t\t\t/* HW_CCODE 0:6 -> 7:D */\n+\t\t\t\t-7,\n+\t\t\t\t0xED,\n+\t\t\t\t-7,\n+\t\t\t\t0xED,\n+\t\t\t\t-7,\n+\t\t\t\t0xED,\n+\t\t\t\t-7,\n \t\t\t};\n \n \t\t\tucc = vdup_n_u8(0);\n@@ -1395,8 +1409,13 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\tucc = vset_lane_u16(*(uint16_t *)(cpth1 + 30), ucc, 1);\n \t\t\tucc = vset_lane_u16(*(uint16_t *)(cpth2 + 30), ucc, 2);\n \t\t\tucc = vset_lane_u16(*(uint16_t *)(cpth3 + 30), ucc, 3);\n-\t\t\tucc = vsub_s8(ucc, err_off);\n-\t\t\tucc = vqtbl1_u8(tbl, ucc);\n+\t\t\tucc = vsub_u8(ucc, err_off);\n+\n+\t\t\t/* Table lookup to get the corresponding flags, Out of the range\n+\t\t\t * from this lookup will have value 0 and consider as\n+\t\t\t * RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED.\n+\t\t\t */\n+\t\t\tucc = vqtbl2_u8(tbl, ucc);\n \n \t\t\tRTE_BUILD_BUG_ON(NPC_LT_LC_IP != 2);\n \t\t\tRTE_BUILD_BUG_ON(NPC_LT_LC_IP_OPT != 3);\n@@ -1478,10 +1497,11 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\tnix_sec_meta_to_mbuf(cq0_w1, cq0_w5, sa, cpth0,\n \t\t\t\t\t\t mbuf0, &f0, &ol_flags0,\n \t\t\t\t\t\t flags, &rearm0);\n-\t\t\t\tol_flags0 |= ((uint64_t)vget_lane_u8(ucc, 0))\n-\t\t\t\t\t << 1;\n-\t\t\t\tol_flags0 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |\n-\t\t\t\t\t(uint64_t)vget_lane_u8(ucc, 1) << 19);\n+\t\t\t\tcode = vget_lane_u8(ucc, 0);\n+\t\t\t\tol_flags0 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :\n+\t\t\t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;\n+\n+\t\t\t\tol_flags0 |= ((uint64_t)(vget_lane_u8(ucc, 1)) << 18);\n \t\t\t}\n \n \t\t\tif (cq1_w1 & BIT(11)) {\n@@ -1502,10 +1522,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\tnix_sec_meta_to_mbuf(cq1_w1, cq1_w5, sa, cpth1,\n \t\t\t\t\t\t mbuf1, &f1, &ol_flags1,\n \t\t\t\t\t\t flags, &rearm1);\n-\t\t\t\tol_flags1 |= ((uint64_t)vget_lane_u8(ucc, 2))\n-\t\t\t\t\t << 1;\n-\t\t\t\tol_flags1 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |\n-\t\t\t\t\t(uint64_t)vget_lane_u8(ucc, 3) << 19);\n+\t\t\t\tcode = vget_lane_u8(ucc, 2);\n+\t\t\t\tol_flags1 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :\n+\t\t\t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;\n+\t\t\t\tol_flags1 |= ((uint64_t)(vget_lane_u8(ucc, 3)) << 18);\n \t\t\t}\n \n \t\t\tif (cq2_w1 & BIT(11)) {\n@@ -1526,10 +1546,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\tnix_sec_meta_to_mbuf(cq2_w1, cq2_w5, sa, cpth2,\n \t\t\t\t\t\t mbuf2, &f2, &ol_flags2,\n \t\t\t\t\t\t flags, &rearm2);\n-\t\t\t\tol_flags2 |= ((uint64_t)vget_lane_u8(ucc, 4))\n-\t\t\t\t\t << 1;\n-\t\t\t\tol_flags2 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |\n-\t\t\t\t\t(uint64_t)vget_lane_u8(ucc, 5) << 19);\n+\t\t\t\tcode = vget_lane_u8(ucc, 4);\n+\t\t\t\tol_flags2 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :\n+\t\t\t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;\n+\t\t\t\tol_flags2 |= ((uint64_t)(vget_lane_u8(ucc, 5)) << 18);\n \t\t\t}\n \n \t\t\tif (cq3_w1 & BIT(11)) {\n@@ -1550,10 +1570,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\tnix_sec_meta_to_mbuf(cq3_w1, cq3_w5, sa, cpth3,\n \t\t\t\t\t\t mbuf3, &f3, &ol_flags3,\n \t\t\t\t\t\t flags, &rearm3);\n-\t\t\t\tol_flags3 |= ((uint64_t)vget_lane_u8(ucc, 6))\n-\t\t\t\t\t << 1;\n-\t\t\t\tol_flags3 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |\n-\t\t\t\t\t(uint64_t)vget_lane_u8(ucc, 7) << 19);\n+\t\t\t\tcode = vget_lane_u8(ucc, 6);\n+\t\t\t\tol_flags3 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :\n+\t\t\t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;\n+\t\t\t\tol_flags3 |= ((uint64_t)(vget_lane_u8(ucc, 7)) << 18);\n \t\t\t}\n \t\t}\n \n", "prefixes": [ "2/2" ] }