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GET /api/patches/122226/?format=api
{ "id": 122226, "url": "http://patchwork.dpdk.org/api/patches/122226/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230118025347.1567078-2-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230118025347.1567078-2-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230118025347.1567078-2-junfeng.guo@intel.com", "date": "2023-01-18T02:53:40", "name": "[RFC,1/8] net/gve: add Rx queue setup for DQO", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "16d4f867d6f418f3291a96e99e4b2929c767b508", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230118025347.1567078-2-junfeng.guo@intel.com/mbox/", "series": [ { "id": 26583, "url": "http://patchwork.dpdk.org/api/series/26583/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=26583", "date": "2023-01-18T02:53:39", "name": "gve PMD enhancement", "version": 1, "mbox": "http://patchwork.dpdk.org/series/26583/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/122226/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/122226/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1F4AD42407;\n\tWed, 18 Jan 2023 03:59:04 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1EB5242D16;\n\tWed, 18 Jan 2023 03:59:01 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id E56EE427EE\n for <dev@dpdk.org>; Wed, 18 Jan 2023 03:58:59 +0100 (CET)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Jan 2023 18:58:59 -0800", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by fmsmga008.fm.intel.com with ESMTP; 17 Jan 2023 18:58:56 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1674010740; x=1705546740;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=bmbOnResrsGUARKiW6/0WBWMPkVIAQTKhSz5uoXeLAs=;\n b=O0xykWfsW7NPjfWhQVTMboBL7kECxolrcjqo7kgQjlOEWhf5kaFGzN/k\n GIagv/y/28rBidqihWsmU/1keMaGt6Gk6w7obZwr+IfQxCF6OrPqc9qhj\n 7Mj6Al+1jg7U4yTN4J9PaHOC54C9X3aJBfHzKhkvmzVhfDmLU67/vqmJZ\n deXF/wV0d5dPQi6eJOrLhzWO5rfNSxvRS7XJZkbH7bMS6oyMuebdG5rAk\n Puxc1fT3YvUChSDtKThdPMDBScn1iytf5y5TazdCAcFBBUgYxTQbHRgnK\n lhTA6gdj7DIhnN5Bb59oHPxYMJ7XDmfvfOh3IkAIhVPgIZoq9ANtUyAO7 g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10593\"; a=\"322575455\"", "E=Sophos;i=\"5.97,224,1669104000\"; d=\"scan'208\";a=\"322575455\"", "E=McAfee;i=\"6500,9779,10593\"; a=\"722911134\"", "E=Sophos;i=\"5.97,224,1669104000\"; d=\"scan'208\";a=\"722911134\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@amd.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, xiaoyun.li@intel.com, helin.zhang@intel.com,\n Junfeng Guo <junfeng.guo@intel.com>, Rushil Gupta <rushilg@google.com>,\n Jordan Kimbrough <jrkim@google.com>, Jeroen de Borst <jeroendb@google.com>", "Subject": "[RFC 1/8] net/gve: add Rx queue setup for DQO", "Date": "Wed, 18 Jan 2023 10:53:40 +0800", "Message-Id": "<20230118025347.1567078-2-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230118025347.1567078-1-junfeng.guo@intel.com>", "References": "<20230118025347.1567078-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for rx_queue_setup_dqo ops.\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nSigned-off-by: Rushil Gupta <rushilg@google.com>\nSigned-off-by: Jordan Kimbrough <jrkim@google.com>\nSigned-off-by: Jeroen de Borst <jeroendb@google.com>\n---\n drivers/net/gve/gve_ethdev.c | 1 +\n drivers/net/gve/gve_ethdev.h | 14 ++++\n drivers/net/gve/gve_rx_dqo.c | 148 +++++++++++++++++++++++++++++++++++\n drivers/net/gve/meson.build | 1 +\n 4 files changed, 164 insertions(+)\n create mode 100644 drivers/net/gve/gve_rx_dqo.c", "diff": "diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex d03f2fba92..26182b0422 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -366,6 +366,7 @@ gve_eth_dev_ops_override(struct eth_dev_ops *local_eth_dev_ops)\n {\n \t/* override eth_dev ops for DQO */\n \tlocal_eth_dev_ops->tx_queue_setup = gve_tx_queue_setup_dqo;\n+\tlocal_eth_dev_ops->rx_queue_setup = gve_rx_queue_setup_dqo;\n }\n \n static void\ndiff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex 2dfcef6893..0adfc90554 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -145,6 +145,7 @@ struct gve_rx_queue {\n \tuint16_t nb_rx_desc;\n \tuint16_t expected_seqno; /* the next expected seqno */\n \tuint16_t free_thresh;\n+\tuint16_t nb_rx_hold;\n \tuint32_t next_avail;\n \tuint32_t nb_avail;\n \n@@ -163,6 +164,14 @@ struct gve_rx_queue {\n \tuint16_t ntfy_id;\n \tuint16_t rx_buf_len;\n \n+\t/* newly added for DQO*/\n+\tvolatile struct gve_rx_desc_dqo *rx_ring;\n+\tstruct gve_rx_compl_desc_dqo *compl_ring;\n+\tconst struct rte_memzone *compl_ring_mz;\n+\tuint64_t compl_ring_phys_addr;\n+\tuint8_t cur_gen_bit;\n+\tuint16_t bufq_tail;\n+\n \t/* Only valid for DQO_RDA queue format */\n \tstruct gve_rx_queue *bufq;\n \n@@ -334,6 +343,11 @@ gve_tx_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n \n /* Below functions are used for DQO */\n \n+int\n+gve_rx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n+\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t const struct rte_eth_rxconf *conf,\n+\t\t struct rte_mempool *pool);\n int\n gve_tx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n \t\t uint16_t nb_desc, unsigned int socket_id,\ndiff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c\nnew file mode 100644\nindex 0000000000..e8a6d575fc\n--- /dev/null\n+++ b/drivers/net/gve/gve_rx_dqo.c\n@@ -0,0 +1,148 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Intel Corporation\n+ */\n+\n+#include \"gve_ethdev.h\"\n+#include \"base/gve_adminq.h\"\n+\n+static void\n+gve_reset_rxq_dqo(struct gve_rx_queue *rxq)\n+{\n+\tstruct rte_mbuf **sw_ring;\n+\tuint32_t size, i;\n+\n+\tif (rxq == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"pointer to rxq is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tsize = rxq->nb_rx_desc * sizeof(struct gve_rx_desc_dqo);\n+\tfor (i = 0; i < size; i++)\n+\t\t((volatile char *)rxq->rx_ring)[i] = 0;\n+\n+\tsize = rxq->nb_rx_desc * sizeof(struct gve_rx_compl_desc_dqo);\n+\tfor (i = 0; i < size; i++)\n+\t\t((volatile char *)rxq->compl_ring)[i] = 0;\n+\n+\tsw_ring = rxq->sw_ring;\n+\tfor (i = 0; i < rxq->nb_rx_desc; i++)\n+\t\tsw_ring[i] = NULL;\n+\n+\trxq->bufq_tail = 0;\n+\trxq->next_avail = 0;\n+\trxq->nb_rx_hold = rxq->nb_rx_desc - 1;\n+\n+\trxq->rx_tail = 0;\n+\trxq->cur_gen_bit = 1;\n+}\n+\n+int\n+gve_rx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n+\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t const struct rte_eth_rxconf *conf,\n+\t\t struct rte_mempool *pool)\n+{\n+\tstruct gve_priv *hw = dev->data->dev_private;\n+\tconst struct rte_memzone *mz;\n+\tstruct gve_rx_queue *rxq;\n+\tuint16_t free_thresh;\n+\tint err = 0;\n+\n+\tif (nb_desc != hw->rx_desc_cnt) {\n+\t\tPMD_DRV_LOG(WARNING, \"gve doesn't support nb_desc config, use hw nb_desc %u.\",\n+\t\t\t hw->rx_desc_cnt);\n+\t}\n+\tnb_desc = hw->rx_desc_cnt;\n+\n+\t/* Allocate the RX queue data structure. */\n+\trxq = rte_zmalloc_socket(\"gve rxq\",\n+\t\t\t\t sizeof(struct gve_rx_queue),\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t socket_id);\n+\tif (rxq == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for rx queue structure\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* check free_thresh here */\n+\tfree_thresh = conf->rx_free_thresh ?\n+\t\t\tconf->rx_free_thresh : GVE_DEFAULT_RX_FREE_THRESH;\n+\tif (free_thresh >= nb_desc) {\n+\t\tPMD_DRV_LOG(ERR, \"rx_free_thresh (%u) must be less than nb_desc (%u).\",\n+\t\t\t free_thresh, rxq->nb_rx_desc);\n+\t\terr = -EINVAL;\n+\t\tgoto err_rxq;\n+\t}\n+\n+\trxq->nb_rx_desc = nb_desc;\n+\trxq->free_thresh = free_thresh;\n+\trxq->queue_id = queue_id;\n+\trxq->port_id = dev->data->port_id;\n+\trxq->ntfy_id = hw->num_ntfy_blks / 2 + queue_id;\n+\n+\trxq->mpool = pool;\n+\trxq->hw = hw;\n+\trxq->ntfy_addr = &hw->db_bar2[rte_be_to_cpu_32(hw->irq_dbs[rxq->ntfy_id].id)];\n+\n+\trxq->rx_buf_len =\n+\t\trte_pktmbuf_data_room_size(rxq->mpool) - RTE_PKTMBUF_HEADROOM;\n+\n+\t/* Allocate software ring */\n+\trxq->sw_ring = rte_zmalloc_socket(\"gve rx sw ring\",\n+\t\t\t\t\t nb_desc * sizeof(struct rte_mbuf *),\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (rxq->sw_ring == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for SW RX ring\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err_rxq;\n+\t}\n+\n+\t/* Allocate RX buffer queue */\n+\tmz = rte_eth_dma_zone_reserve(dev, \"rx_ring\", queue_id,\n+\t\t\t\t nb_desc * sizeof(struct gve_rx_desc_dqo),\n+\t\t\t\t PAGE_SIZE, socket_id);\n+\tif (mz == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to reserve DMA memory for RX buffer queue\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err_rxq;\n+\t}\n+\trxq->rx_ring = (struct gve_rx_desc_dqo *)mz->addr;\n+\trxq->rx_ring_phys_addr = mz->iova;\n+\trxq->mz = mz;\n+\n+\t/* Allocate RX completion queue */\n+\tmz = rte_eth_dma_zone_reserve(dev, \"compl_ring\", queue_id,\n+\t\t\t\t nb_desc * sizeof(struct gve_rx_compl_desc_dqo),\n+\t\t\t\t PAGE_SIZE, socket_id);\n+\tif (mz == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to reserve DMA memory for RX completion queue\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err_rxq;\n+\t}\n+\t/* Zero all the descriptors in the ring */\n+\tmemset(mz->addr, 0, nb_desc * sizeof(struct gve_rx_compl_desc_dqo));\n+\trxq->compl_ring = (struct gve_rx_compl_desc_dqo *)mz->addr;\n+\trxq->compl_ring_phys_addr = mz->iova;\n+\trxq->compl_ring_mz = mz;\n+\n+\tmz = rte_eth_dma_zone_reserve(dev, \"rxq_res\", queue_id,\n+\t\t\t\t sizeof(struct gve_queue_resources),\n+\t\t\t\t PAGE_SIZE, socket_id);\n+\tif (mz == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to reserve DMA memory for RX resource\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err_rxq;\n+\t}\n+\trxq->qres = (struct gve_queue_resources *)mz->addr;\n+\trxq->qres_mz = mz;\n+\n+\tgve_reset_rxq_dqo(rxq);\n+\n+\tdev->data->rx_queues[queue_id] = rxq;\n+\n+\treturn 0;\n+\n+err_rxq:\n+\trte_free(rxq);\n+\treturn err;\n+}\ndiff --git a/drivers/net/gve/meson.build b/drivers/net/gve/meson.build\nindex 2ddb0cbf9e..c9d87903f9 100644\n--- a/drivers/net/gve/meson.build\n+++ b/drivers/net/gve/meson.build\n@@ -11,6 +11,7 @@ sources = files(\n 'base/gve_adminq.c',\n 'gve_rx.c',\n 'gve_tx.c',\n+ 'gve_rx_dqo.c',\n 'gve_tx_dqo.c',\n 'gve_ethdev.c',\n )\n", "prefixes": [ "RFC", "1/8" ] }