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GET /api/patches/122656/?format=api
{ "id": 122656, "url": "http://patchwork.dpdk.org/api/patches/122656/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230130062642.3337239-6-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230130062642.3337239-6-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230130062642.3337239-6-junfeng.guo@intel.com", "date": "2023-01-30T06:26:38", "name": "[RFC,v2,5/9] net/gve: support basic Tx data path for DQO", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fdc3149f524355cdfc6c66fe0c36698d8f21111b", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230130062642.3337239-6-junfeng.guo@intel.com/mbox/", "series": [ { "id": 26684, "url": "http://patchwork.dpdk.org/api/series/26684/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=26684", "date": "2023-01-30T06:26:33", "name": "gve PMD enhancement", "version": 2, "mbox": "http://patchwork.dpdk.org/series/26684/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/122656/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/122656/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D1AD7424BA;\n\tMon, 30 Jan 2023 07:32:47 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6A21E427E9;\n\tMon, 30 Jan 2023 07:32:33 +0100 (CET)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id D90CC410FB\n for <dev@dpdk.org>; Mon, 30 Jan 2023 07:32:31 +0100 (CET)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 29 Jan 2023 22:32:31 -0800", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by orsmga004.jf.intel.com with ESMTP; 29 Jan 2023 22:32:27 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1675060352; x=1706596352;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=EXYWc2RPYgYWSMwm0jcddbYfXxkRmCR3DDtmVgl770Q=;\n b=kndWCNET6Nkch2fiy+wHqazeChAjgUyFoEP/CYT33XJIbjgGxOYP3Mg4\n KYd3dcmAdjtzRO0waEk+yqw7YmvIB5U8dF3hhQpojRN2ZJvph3Xc/4Qpf\n 5mt23ZCQ5be1BFI7aYlehrbSu6fvz6guR6jBEtx8vxgcGNCvM81yGSVjk\n +sfp/4G1/hEiTQngngDRXbibAQWmoBdNXz9cHv0ZsgGh2Gr15UFJozlDn\n W+HnyTEiSLFMu9o3UTesML4UfnG1SzPWO2hFOGy7aJNLRM700BTLXNwAR\n hA9Q6G7vO0VkdwkUuLQ0NxNTcFp8ERr8WXN550d+NWOy32DGfVFvB/vrR g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10605\"; a=\"392035698\"", "E=Sophos;i=\"5.97,257,1669104000\"; d=\"scan'208\";a=\"392035698\"", "E=McAfee;i=\"6500,9779,10605\"; a=\"787906469\"", "E=Sophos;i=\"5.97,257,1669104000\"; d=\"scan'208\";a=\"787906469\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@amd.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, xiaoyun.li@intel.com, helin.zhang@intel.com,\n Junfeng Guo <junfeng.guo@intel.com>, Rushil Gupta <rushilg@google.com>,\n Jordan Kimbrough <jrkim@google.com>, Jeroen de Borst <jeroendb@google.com>", "Subject": "[RFC v2 5/9] net/gve: support basic Tx data path for DQO", "Date": "Mon, 30 Jan 2023 14:26:38 +0800", "Message-Id": "<20230130062642.3337239-6-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230130062642.3337239-1-junfeng.guo@intel.com>", "References": "<20230118025347.1567078-1-junfeng.guo@intel.com>\n <20230130062642.3337239-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add basic Tx data path support for DQO.\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nSigned-off-by: Rushil Gupta <rushilg@google.com>\nSigned-off-by: Jordan Kimbrough <jrkim@google.com>\nSigned-off-by: Jeroen de Borst <jeroendb@google.com>\n---\n drivers/net/gve/gve_ethdev.c | 1 +\n drivers/net/gve/gve_ethdev.h | 4 +\n drivers/net/gve/gve_tx_dqo.c | 141 +++++++++++++++++++++++++++++++++++\n 3 files changed, 146 insertions(+)", "diff": "diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex 7c4be3a1cb..512a038968 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -703,6 +703,7 @@ gve_dev_init(struct rte_eth_dev *eth_dev)\n \t} else {\n \t\t/* override Tx/Rx setup/release eth_dev ops */\n \t\tgve_eth_dev_ops_override(&gve_local_eth_dev_ops);\n+\t\teth_dev->tx_pkt_burst = gve_tx_burst_dqo;\n \t}\n \n \teth_dev->dev_ops = &gve_local_eth_dev_ops;\ndiff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex 93314f2db3..ba657dd6c1 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -125,6 +125,7 @@ struct gve_tx_queue {\n \tuint8_t cur_gen_bit;\n \tuint32_t last_desc_cleaned;\n \tvoid **txqs;\n+\tuint16_t re_cnt;\n \n \t/* Only valid for DQO_RDA queue format */\n \tstruct gve_tx_queue *complq;\n@@ -365,4 +366,7 @@ gve_stop_tx_queues_dqo(struct rte_eth_dev *dev);\n void\n gve_stop_rx_queues_dqo(struct rte_eth_dev *dev);\n \n+uint16_t\n+gve_tx_burst_dqo(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n+\n #endif /* _GVE_ETHDEV_H_ */\ndiff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c\nindex e2e4153f27..3583c82246 100644\n--- a/drivers/net/gve/gve_tx_dqo.c\n+++ b/drivers/net/gve/gve_tx_dqo.c\n@@ -5,6 +5,147 @@\n #include \"gve_ethdev.h\"\n #include \"base/gve_adminq.h\"\n \n+static inline void\n+gve_tx_clean_dqo(struct gve_tx_queue *txq)\n+{\n+\tstruct gve_tx_compl_desc *compl_ring;\n+\tstruct gve_tx_compl_desc *compl_desc;\n+\tstruct gve_tx_queue *aim_txq;\n+\tuint16_t nb_desc_clean;\n+\tstruct rte_mbuf *txe;\n+\tuint16_t compl_tag;\n+\tuint16_t next;\n+\n+\tnext = txq->complq_tail;\n+\tcompl_ring = txq->compl_ring;\n+\tcompl_desc = &compl_ring[next];\n+\n+\tif (compl_desc->generation != txq->cur_gen_bit)\n+\t\treturn;\n+\n+\tcompl_tag = rte_le_to_cpu_16(compl_desc->completion_tag);\n+\n+\taim_txq = txq->txqs[compl_desc->id];\n+\n+\tswitch (compl_desc->type) {\n+\tcase GVE_COMPL_TYPE_DQO_DESC:\n+\t\t/* need to clean Descs from last_cleaned to compl_tag */\n+\t\tif (aim_txq->last_desc_cleaned > compl_tag)\n+\t\t\tnb_desc_clean = aim_txq->nb_tx_desc - aim_txq->last_desc_cleaned +\n+\t\t\t\t\tcompl_tag;\n+\t\telse\n+\t\t\tnb_desc_clean = compl_tag - aim_txq->last_desc_cleaned;\n+\t\taim_txq->nb_free += nb_desc_clean;\n+\t\taim_txq->last_desc_cleaned = compl_tag;\n+\t\tbreak;\n+\tcase GVE_COMPL_TYPE_DQO_REINJECTION:\n+\t\tPMD_DRV_LOG(DEBUG, \"GVE_COMPL_TYPE_DQO_REINJECTION !!!\");\n+\t\t/* FALLTHROUGH */\n+\tcase GVE_COMPL_TYPE_DQO_PKT:\n+\t\ttxe = aim_txq->sw_ring[compl_tag];\n+\t\tif (txe != NULL) {\n+\t\t\trte_pktmbuf_free_seg(txe);\n+\t\t\ttxe = NULL;\n+\t\t}\n+\t\tbreak;\n+\tcase GVE_COMPL_TYPE_DQO_MISS:\n+\t\trte_delay_us_sleep(1);\n+\t\tPMD_DRV_LOG(DEBUG, \"GVE_COMPL_TYPE_DQO_MISS ignored !!!\");\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"unknown completion type.\");\n+\t\treturn;\n+\t}\n+\n+\tnext++;\n+\tif (next == txq->nb_tx_desc * DQO_TX_MULTIPLIER) {\n+\t\tnext = 0;\n+\t\ttxq->cur_gen_bit ^= 1;\n+\t}\n+\n+\ttxq->complq_tail = next;\n+}\n+\n+uint16_t\n+gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct gve_tx_queue *txq = tx_queue;\n+\tvolatile union gve_tx_desc_dqo *txr;\n+\tvolatile union gve_tx_desc_dqo *txd;\n+\tstruct rte_mbuf **sw_ring;\n+\tstruct rte_mbuf *tx_pkt;\n+\tuint16_t mask, sw_mask;\n+\tuint16_t nb_to_clean;\n+\tuint16_t nb_tx = 0;\n+\tuint16_t nb_used;\n+\tuint16_t tx_id;\n+\tuint16_t sw_id;\n+\n+\tsw_ring = txq->sw_ring;\n+\ttxr = txq->tx_ring;\n+\n+\tmask = txq->nb_tx_desc - 1;\n+\tsw_mask = txq->sw_size - 1;\n+\ttx_id = txq->tx_tail;\n+\tsw_id = txq->sw_tail;\n+\n+\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n+\t\ttx_pkt = tx_pkts[nb_tx];\n+\n+\t\tif (txq->nb_free <= txq->free_thresh) {\n+\t\t\tnb_to_clean = DQO_TX_MULTIPLIER * txq->rs_thresh;\n+\t\t\twhile (nb_to_clean--)\n+\t\t\t\tgve_tx_clean_dqo(txq);\n+\t\t}\n+\n+\t\tif (txq->nb_free < tx_pkt->nb_segs)\n+\t\t\tbreak;\n+\n+\t\tnb_used = tx_pkt->nb_segs;\n+\n+\t\tdo {\n+\t\t\ttxd = &txr[tx_id];\n+\n+\t\t\tsw_ring[sw_id] = tx_pkt;\n+\n+\t\t\t/* fill Tx descriptor */\n+\t\t\ttxd->pkt.buf_addr = rte_cpu_to_le_64(rte_mbuf_data_iova(tx_pkt));\n+\t\t\ttxd->pkt.dtype = GVE_TX_PKT_DESC_DTYPE_DQO;\n+\t\t\ttxd->pkt.compl_tag = rte_cpu_to_le_16(sw_id);\n+\t\t\ttxd->pkt.buf_size = RTE_MIN(tx_pkt->data_len, GVE_TX_MAX_BUF_SIZE_DQO);\n+\n+\t\t\t/* size of desc_ring and sw_ring could be different */\n+\t\t\ttx_id = (tx_id + 1) & mask;\n+\t\t\tsw_id = (sw_id + 1) & sw_mask;\n+\n+\t\t\ttx_pkt = tx_pkt->next;\n+\t\t} while (tx_pkt);\n+\n+\t\t/* fill the last descriptor with End of Packet (EOP) bit */\n+\t\ttxd->pkt.end_of_packet = 1;\n+\n+\t\ttxq->nb_free -= nb_used;\n+\t\ttxq->nb_used += nb_used;\n+\t}\n+\n+\t/* update the tail pointer if any packets were processed */\n+\tif (nb_tx > 0) {\n+\t\t/* Request a descriptor completion on the last descriptor */\n+\t\ttxq->re_cnt += nb_tx;\n+\t\tif (txq->re_cnt >= GVE_TX_MIN_RE_INTERVAL) {\n+\t\t\ttxd = &txr[(tx_id - 1) & mask];\n+\t\t\ttxd->pkt.report_event = true;\n+\t\t\ttxq->re_cnt = 0;\n+\t\t}\n+\n+\t\trte_write32(tx_id, txq->qtx_tail);\n+\t\ttxq->tx_tail = tx_id;\n+\t\ttxq->sw_tail = sw_id;\n+\t}\n+\n+\treturn nb_tx;\n+}\n+\n static inline void\n gve_release_txq_mbufs_dqo(struct gve_tx_queue *txq)\n {\n", "prefixes": [ "RFC", "v2", "5/9" ] }