Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/124765/?format=api
{ "id": 124765, "url": "http://patchwork.dpdk.org/api/patches/124765/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230303081013.589868-8-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230303081013.589868-8-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230303081013.589868-8-ndabilpuram@marvell.com", "date": "2023-03-03T08:10:06", "name": "[08/15] net/cnxk: check flow control config per queue on dev start", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6749d908b3d17418491deadb4472586b9a0f2adf", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230303081013.589868-8-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 27237, "url": "http://patchwork.dpdk.org/api/series/27237/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27237", "date": "2023-03-03T08:09:59", "name": "[01/15] net/cnxk: resolve sefgault caused during transmit completion", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27237/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/124765/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/124765/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0E69241DC3;\n\tFri, 3 Mar 2023 09:11:43 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7753342D37;\n\tFri, 3 Mar 2023 09:11:13 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id A4C0642C76\n for <dev@dpdk.org>; Fri, 3 Mar 2023 09:11:11 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3234WuWW024918 for <dev@dpdk.org>; Fri, 3 Mar 2023 00:11:11 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p1wr9xbjk-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 03 Mar 2023 00:11:10 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Fri, 3 Mar 2023 00:11:08 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Fri, 3 Mar 2023 00:11:08 -0800", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id B16673F7053;\n Fri, 3 Mar 2023 00:11:06 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=TmDaYmpoKff8n+r9HFlFYXTiz5Ia2ZuW1kWVxEmfUJA=;\n b=IgqgmzZfj1p2+FW7hY4XG27Aza1CPamf62ZAs09nw/ykBhRr23CXVINd7N7+w3SJKeCd\n 07obJgaZtSf3sqRs//Q4wFSyM01trHob+qFHzjvKJqvRDp0DxFOavSkxoKFRjSAzvTKJ\n TzyvX6x3AWKrceEa0wPYRwFrUN6KrF11XJQuk683fyd9ovbjzdA8bpuZrzaUaMNkGu6B\n I22aneC+08+zYdliEvIEiuqOSZ7ujtMVWW4YRblp9j+y6z2Ns/8vr8zkL0+gldszRCCq\n oq0DI7YDqZaIofCXPs8b3AyYZ6QUcLfuVLS5L3UeURYDaWtF7PUP9dMB7TukrAg7E41Z Xw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 08/15] net/cnxk: check flow control config per queue on dev\n start", "Date": "Fri, 3 Mar 2023 13:40:06 +0530", "Message-ID": "<20230303081013.589868-8-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230303081013.589868-1-ndabilpuram@marvell.com>", "References": "<20230303081013.589868-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "FfcZC8hYtcvHT8zeGmjBsjKqRy9PPe_V", "X-Proofpoint-GUID": "FfcZC8hYtcvHT8zeGmjBsjKqRy9PPe_V", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-03-03_01,2023-03-02_02,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Check and enable/disable flow control config per queue on\ndevice start to handle cases like SSO enablement, TM changes etc.\nModify flow control config get to get status per RQ/SQ.\n\nAlso disallow changes to flow control config when device\nis in started state.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/cnxk/cnxk_ethdev.c | 9 +-\n drivers/net/cnxk/cnxk_ethdev_ops.c | 198 ++++++++++++++++-------------\n 2 files changed, 113 insertions(+), 94 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex e99335b117..d8ccd307a8 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -363,7 +363,7 @@ nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)\n \tstruct cnxk_fc_cfg *fc = &dev->fc_cfg;\n \tint rc;\n \n-\tif (roc_nix_is_vf_or_sdp(&dev->nix))\n+\tif (roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix))\n \t\treturn 0;\n \n \t/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */\n@@ -388,7 +388,11 @@ nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)\n \tstruct cnxk_fc_cfg *fc = &dev->fc_cfg;\n \tstruct rte_eth_fc_conf fc_cfg = {0};\n \n-\tif (roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix))\n+\tif (roc_nix_is_sdp(&dev->nix))\n+\t\treturn 0;\n+\n+\t/* Don't do anything if PFC is enabled */\n+\tif (dev->pfc_cfg.rx_pause_en || dev->pfc_cfg.tx_pause_en)\n \t\treturn 0;\n \n \tfc_cfg.mode = fc->mode;\n@@ -481,7 +485,6 @@ cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tsq->qid = qid;\n \tsq->nb_desc = nb_desc;\n \tsq->max_sqe_sz = nix_sq_max_sqe_sz(dev);\n-\tsq->tc = ROC_NIX_PFC_CLASS_INVALID;\n \n \tif (nix->tx_compl_ena) {\n \t\tsq->cqid = sq->qid + dev->nb_rxq;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c\nindex a6ab493626..5df7927d7b 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_ops.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c\n@@ -205,12 +205,15 @@ cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,\n \t\t struct rte_eth_fc_conf *fc_conf)\n {\n \tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n-\tenum rte_eth_fc_mode mode_map[] = {\n-\t\t\t\t\t RTE_ETH_FC_NONE, RTE_ETH_FC_RX_PAUSE,\n-\t\t\t\t\t RTE_ETH_FC_TX_PAUSE, RTE_ETH_FC_FULL\n-\t\t\t\t\t };\n+\tenum rte_eth_fc_mode mode_map[2][2] = {\n+\t\t[0][0] = RTE_ETH_FC_NONE,\n+\t\t[0][1] = RTE_ETH_FC_TX_PAUSE,\n+\t\t[1][0] = RTE_ETH_FC_RX_PAUSE,\n+\t\t[1][1] = RTE_ETH_FC_FULL,\n+\t};\n \tstruct roc_nix *nix = &dev->nix;\n-\tint mode;\n+\tuint8_t rx_pause, tx_pause;\n+\tint mode, i;\n \n \tif (roc_nix_is_sdp(nix))\n \t\treturn 0;\n@@ -219,32 +222,25 @@ cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,\n \tif (mode < 0)\n \t\treturn mode;\n \n+\trx_pause = (mode == ROC_NIX_FC_FULL) || (mode == ROC_NIX_FC_RX);\n+\ttx_pause = (mode == ROC_NIX_FC_FULL) || (mode == ROC_NIX_FC_TX);\n+\n+\t/* Report flow control as disabled even if one RQ/SQ has it disabled */\n+\tfor (i = 0; i < dev->nb_rxq; i++) {\n+\t\tif (dev->rqs[i].tc == ROC_NIX_PFC_CLASS_INVALID)\n+\t\t\ttx_pause = 0;\n+\t}\n+\n+\tfor (i = 0; i < dev->nb_txq; i++) {\n+\t\tif (dev->sqs[i].tc == ROC_NIX_PFC_CLASS_INVALID)\n+\t\t\trx_pause = 0;\n+\t}\n+\n \tmemset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));\n-\tfc_conf->mode = mode_map[mode];\n+\tfc_conf->mode = mode_map[rx_pause][tx_pause];\n \treturn 0;\n }\n \n-static int\n-nix_fc_cq_config_set(struct cnxk_eth_dev *dev, uint16_t qid, bool enable)\n-{\n-\tstruct roc_nix *nix = &dev->nix;\n-\tstruct roc_nix_fc_cfg fc_cfg;\n-\tstruct roc_nix_cq *cq;\n-\tstruct roc_nix_rq *rq;\n-\n-\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n-\trq = &dev->rqs[qid];\n-\tcq = &dev->cqs[qid];\n-\tfc_cfg.type = ROC_NIX_FC_RQ_CFG;\n-\tfc_cfg.rq_cfg.enable = enable;\n-\tfc_cfg.rq_cfg.tc = 0;\n-\tfc_cfg.rq_cfg.rq = qid;\n-\tfc_cfg.rq_cfg.pool = rq->aura_handle;\n-\tfc_cfg.rq_cfg.cq_drop = cq->drop_thresh;\n-\n-\treturn roc_nix_fc_config_set(nix, &fc_cfg);\n-}\n-\n int\n cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \t\t struct rte_eth_fc_conf *fc_conf)\n@@ -260,68 +256,90 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \tstruct cnxk_eth_rxq_sp *rxq;\n \tstruct cnxk_eth_txq_sp *txq;\n \tuint8_t rx_pause, tx_pause;\n+\tstruct roc_nix_sq *sq;\n+\tstruct roc_nix_cq *cq;\n+\tstruct roc_nix_rq *rq;\n+\tuint8_t tc;\n \tint rc, i;\n \n \tif (roc_nix_is_sdp(nix))\n \t\treturn 0;\n \n+\tif (dev->pfc_cfg.rx_pause_en || dev->pfc_cfg.tx_pause_en) {\n+\t\tplt_err(\"Disable PFC before configuring Flow Control\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tif (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time ||\n \t fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) {\n \t\tplt_info(\"Only MODE configuration is supported\");\n \t\treturn -EINVAL;\n \t}\n \n-\n-\trx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) ||\n-\t\t (fc_conf->mode == RTE_ETH_FC_RX_PAUSE);\n-\ttx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) ||\n-\t\t (fc_conf->mode == RTE_ETH_FC_TX_PAUSE);\n-\n-\tif (fc_conf->mode == fc->mode) {\n-\t\tfc->rx_pause = rx_pause;\n-\t\tfc->tx_pause = tx_pause;\n-\t\treturn 0;\n+\t/* Disallow flow control changes when device is in started state */\n+\tif (data->dev_started) {\n+\t\tplt_info(\"Stop the port=%d for setting flow control\", data->port_id);\n+\t\treturn -EBUSY;\n \t}\n \n+\trx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) || (fc_conf->mode == RTE_ETH_FC_RX_PAUSE);\n+\ttx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) || (fc_conf->mode == RTE_ETH_FC_TX_PAUSE);\n+\n \t/* Check if TX pause frame is already enabled or not */\n-\tif (fc->tx_pause ^ tx_pause) {\n-\t\tif (roc_model_is_cn96_ax() && data->dev_started) {\n-\t\t\t/* On Ax, CQ should be in disabled state\n-\t\t\t * while setting flow control configuration.\n-\t\t\t */\n-\t\t\tplt_info(\"Stop the port=%d for setting flow control\",\n-\t\t\t\t data->port_id);\n-\t\t\treturn 0;\n-\t\t}\n+\ttc = tx_pause ? 0 : ROC_NIX_PFC_CLASS_INVALID;\n+\tfor (i = 0; i < data->nb_rx_queues; i++) {\n+\t\tstruct roc_nix_fc_cfg fc_cfg;\n \n-\t\tfor (i = 0; i < data->nb_rx_queues; i++) {\n-\t\t\tstruct roc_nix_fc_cfg fc_cfg;\n+\t\t/* Skip if RQ does not exist */\n+\t\tif (!data->rx_queues[i])\n+\t\t\tcontinue;\n \n-\t\t\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n-\t\t\trxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[i]) -\n-\t\t\t 1;\n-\t\t\trxq->tx_pause = !!tx_pause;\n-\t\t\trc = nix_fc_cq_config_set(dev, rxq->qid, !!tx_pause);\n-\t\t\tif (rc)\n-\t\t\t\treturn rc;\n-\t\t}\n+\t\trxq = cnxk_eth_rxq_to_sp(data->rx_queues[i]);\n+\t\trq = &dev->rqs[rxq->qid];\n+\t\tcq = &dev->cqs[rxq->qid];\n+\n+\t\t/* Skip if RQ is in expected state */\n+\t\tif (fc->tx_pause == tx_pause && rq->tc == tc)\n+\t\t\tcontinue;\n+\n+\t\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n+\t\tfc_cfg.type = ROC_NIX_FC_RQ_CFG;\n+\t\tfc_cfg.rq_cfg.enable = !!tx_pause;\n+\t\tfc_cfg.rq_cfg.tc = 0;\n+\t\tfc_cfg.rq_cfg.rq = rq->qid;\n+\t\tfc_cfg.rq_cfg.pool = rq->aura_handle;\n+\t\tfc_cfg.rq_cfg.cq_drop = cq->drop_thresh;\n+\n+\t\trc = roc_nix_fc_config_set(nix, &fc_cfg);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t\trxq->tx_pause = !!tx_pause;\n \t}\n \n \t/* Check if RX pause frame is enabled or not */\n-\tif (fc->rx_pause ^ rx_pause) {\n-\t\tfor (i = 0; i < data->nb_tx_queues; i++) {\n-\t\t\tstruct roc_nix_fc_cfg fc_cfg;\n-\n-\t\t\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n-\t\t\ttxq = ((struct cnxk_eth_txq_sp *)data->tx_queues[i]) -\n-\t\t\t 1;\n-\t\t\tfc_cfg.type = ROC_NIX_FC_TM_CFG;\n-\t\t\tfc_cfg.tm_cfg.sq = txq->qid;\n-\t\t\tfc_cfg.tm_cfg.enable = !!rx_pause;\n-\t\t\trc = roc_nix_fc_config_set(nix, &fc_cfg);\n-\t\t\tif (rc)\n-\t\t\t\treturn rc;\n-\t\t}\n+\ttc = rx_pause ? 0 : ROC_NIX_PFC_CLASS_INVALID;\n+\tfor (i = 0; i < data->nb_tx_queues; i++) {\n+\t\tstruct roc_nix_fc_cfg fc_cfg;\n+\n+\t\t/* Skip if SQ does not exist */\n+\t\tif (!data->tx_queues[i])\n+\t\t\tcontinue;\n+\n+\t\ttxq = cnxk_eth_txq_to_sp(data->tx_queues[i]);\n+\t\tsq = &dev->sqs[txq->qid];\n+\n+\t\t/* Skip if SQ is in expected state */\n+\t\tif (fc->rx_pause == rx_pause && sq->tc == tc)\n+\t\t\tcontinue;\n+\n+\t\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n+\t\tfc_cfg.type = ROC_NIX_FC_TM_CFG;\n+\t\tfc_cfg.tm_cfg.sq = txq->qid;\n+\t\tfc_cfg.tm_cfg.tc = 0;\n+\t\tfc_cfg.tm_cfg.enable = !!rx_pause;\n+\t\trc = roc_nix_fc_config_set(nix, &fc_cfg);\n+\t\tif (rc && rc != EEXIST)\n+\t\t\treturn rc;\n \t}\n \n \trc = roc_nix_fc_mode_set(nix, mode_map[fc_conf->mode]);\n@@ -350,6 +368,7 @@ cnxk_nix_priority_flow_ctrl_queue_config(struct rte_eth_dev *eth_dev,\n \t\t\t\t struct rte_eth_pfc_queue_conf *pfc_conf)\n {\n \tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n \tstruct roc_nix *nix = &dev->nix;\n \tenum rte_eth_fc_mode mode;\n \tuint8_t en, tc;\n@@ -366,6 +385,12 @@ cnxk_nix_priority_flow_ctrl_queue_config(struct rte_eth_dev *eth_dev,\n \t\treturn -ENOTSUP;\n \t}\n \n+\t/* Disallow flow control changes when device is in started state */\n+\tif (data->dev_started) {\n+\t\tplt_info(\"Stop the port=%d for setting PFC\", data->port_id);\n+\t\treturn -EBUSY;\n+\t}\n+\n \tmode = pfc_conf->mode;\n \n \t/* Perform Tx pause configuration on RQ */\n@@ -1094,7 +1119,7 @@ nix_priority_flow_ctrl_rq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tenum roc_nix_fc_mode mode;\n \tstruct roc_nix_rq *rq;\n \tstruct roc_nix_cq *cq;\n-\tint rc;\n+\tint rc, i;\n \n \tif (roc_model_is_cn96_ax() && data->dev_started) {\n \t\t/* On Ax, CQ should be in disabled state\n@@ -1127,15 +1152,13 @@ nix_priority_flow_ctrl_rq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tif (rc)\n \t\treturn rc;\n \n-\tif (rxq->tx_pause != tx_pause) {\n-\t\tif (tx_pause)\n-\t\t\tpfc->tx_pause_en++;\n-\t\telse\n-\t\t\tpfc->tx_pause_en--;\n-\t}\n-\n \trxq->tx_pause = !!tx_pause;\n \trxq->tc = tc;\n+\t/* Recheck number of RQ's that have PFC enabled */\n+\tpfc->tx_pause_en = 0;\n+\tfor (i = 0; i < dev->nb_rxq; i++)\n+\t\tif (dev->rqs[i].tc != ROC_NIX_PFC_CLASS_INVALID)\n+\t\t\tpfc->tx_pause_en++;\n \n \t/* Skip if PFC already enabled in mac */\n \tif (pfc->tx_pause_en > 1)\n@@ -1168,7 +1191,7 @@ nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tstruct cnxk_eth_txq_sp *txq;\n \tenum roc_nix_fc_mode mode;\n \tstruct roc_nix_sq *sq;\n-\tint rc;\n+\tint rc, i;\n \n \tif (data->tx_queues == NULL)\n \t\treturn -EINVAL;\n@@ -1212,18 +1235,11 @@ nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tif (rc)\n \t\treturn rc;\n \n-\t/* Maintaining a count for SQs which are configured for PFC. This is\n-\t * required to handle disabling of a particular SQ without affecting\n-\t * PFC on other SQs.\n-\t */\n-\tif (!fc_cfg.tm_cfg.enable && sq->tc != ROC_NIX_PFC_CLASS_INVALID) {\n-\t\tsq->tc = ROC_NIX_PFC_CLASS_INVALID;\n-\t\tpfc->rx_pause_en--;\n-\t} else if (fc_cfg.tm_cfg.enable &&\n-\t\t sq->tc == ROC_NIX_PFC_CLASS_INVALID) {\n-\t\tsq->tc = tc;\n-\t\tpfc->rx_pause_en++;\n-\t}\n+\t/* Recheck number of SQ's that have PFC enabled */\n+\tpfc->rx_pause_en = 0;\n+\tfor (i = 0; i < dev->nb_txq; i++)\n+\t\tif (dev->sqs[i].tc != ROC_NIX_PFC_CLASS_INVALID)\n+\t\t\tpfc->rx_pause_en++;\n \n \tif (pfc->rx_pause_en > 1)\n \t\tgoto exit;\n", "prefixes": [ "08/15" ] }