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GET /api/patches/125907/?format=api
{ "id": 125907, "url": "http://patchwork.dpdk.org/api/patches/125907/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230411091144.1087887-2-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230411091144.1087887-2-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230411091144.1087887-2-ndabilpuram@marvell.com", "date": "2023-04-11T09:11:25", "name": "[02/21] common/cnxk: add pool BPID to RQ while using common pool", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "5b637de36d89bf51048803ca56245e0c472635ac", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230411091144.1087887-2-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 27660, "url": "http://patchwork.dpdk.org/api/series/27660/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27660", "date": "2023-04-11T09:11:24", "name": "[01/21] common/cnxk: allocate dynamic BPIDs", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27660/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/125907/comments/", "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/125907/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B15594291B;\n\tTue, 11 Apr 2023 11:12:11 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 519AD4111C;\n\tTue, 11 Apr 2023 11:12:10 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id B5F084111C\n for <dev@dpdk.org>; Tue, 11 Apr 2023 11:12:08 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33B8Ak4d021460 for <dev@dpdk.org>; Tue, 11 Apr 2023 02:12:07 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pvt73b1rs-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 11 Apr 2023 02:12:07 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 11 Apr 2023 02:12:05 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 11 Apr 2023 02:12:05 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 96F1E3F7070;\n Tue, 11 Apr 2023 02:12:03 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=neXng+rYrw9NupGtmYLeVT/1o0SPimp/xruAiRk00aM=;\n b=CXtmkmGnxM4A4vHqJDoHTbgilPHFXl/djaAssrm08dXX9ZY9jLc/ePPIqvMBDFJJBxhi\n JWV5TIurH4IG4bwI8r0qDH9y1Mj1/tbhEWCH6BciYvJKYHIRvHkw6usLAeOLUtvuDZ92\n s0FHsta9UeGLZ/bmqv0uaUBD+SjMwZnzI0EPDcU592itFr7SnlPBT7ouYdyiADQCrMfR\n /NrKsyTS/7iT4PbXf+x68/M7rTpDIk+7jg+0JglPCywdQ742TER+eYPdIuUTJ5+pM+Lp\n +uKYgKhDkZCtncRdFCx7D58+9s4PMX0wQWY0gMCq9RND3KwkfGTT56olM1szV61hwHsX pg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>, Shijith Thotton\n <sthotton@marvell.com>", "Subject": "[PATCH 02/21] common/cnxk: add pool BPID to RQ while using common\n pool", "Date": "Tue, 11 Apr 2023 14:41:25 +0530", "Message-ID": "<20230411091144.1087887-2-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "References": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "DeCGUzl7Y0YlDHh58dYya_tHwkbnB3sG", "X-Proofpoint-ORIG-GUID": "DeCGUzl7Y0YlDHh58dYya_tHwkbnB3sG", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nWhen RQs of two different traffic classes are using the same mempool,\nBPIDs could differ between the RQs and BPID of only one RQ can be\nconfigured per pool. In such cases, a new BPID is configured on both RQs\nand pool or pool back-pressure is disabled.\n\nCN103xx and CN106xx B0 supports configuring multiple BPID per RQ.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/common/cnxk/roc_idev.c | 12 +++\n drivers/common/cnxk/roc_idev.h | 1 +\n drivers/common/cnxk/roc_idev_priv.h | 1 +\n drivers/common/cnxk/roc_nix.c | 5 +\n drivers/common/cnxk/roc_nix.h | 3 +\n drivers/common/cnxk/roc_nix_fc.c | 156 ++++++++++++++++------------\n drivers/common/cnxk/roc_npa.c | 48 +++++++++\n drivers/common/cnxk/roc_npa.h | 2 +\n drivers/common/cnxk/version.map | 2 +\n 9 files changed, 166 insertions(+), 64 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c\nindex 62a4fd8880..f420f0158d 100644\n--- a/drivers/common/cnxk/roc_idev.c\n+++ b/drivers/common/cnxk/roc_idev.c\n@@ -39,6 +39,7 @@ idev_set_defaults(struct idev_cfg *idev)\n \tidev->bphy = NULL;\n \tidev->cpt = NULL;\n \tidev->nix_inl_dev = NULL;\n+\tTAILQ_INIT(&idev->roc_nix_list);\n \tplt_spinlock_init(&idev->nix_inl_dev_lock);\n \tplt_spinlock_init(&idev->npa_dev_lock);\n \t__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);\n@@ -201,6 +202,17 @@ roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix)\n \treturn (uint64_t *)&inl_dev->sa_soft_exp_ring[nix->outb_se_ring_base];\n }\n \n+struct roc_nix_list *\n+roc_idev_nix_list_get(void)\n+{\n+\tstruct idev_cfg *idev;\n+\n+\tidev = idev_get_cfg();\n+\tif (idev != NULL)\n+\t\treturn &idev->roc_nix_list;\n+\treturn NULL;\n+}\n+\n void\n roc_idev_cpt_set(struct roc_cpt *cpt)\n {\ndiff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h\nindex 926aac0634..640ca97708 100644\n--- a/drivers/common/cnxk/roc_idev.h\n+++ b/drivers/common/cnxk/roc_idev.h\n@@ -17,5 +17,6 @@ void __roc_api roc_idev_cpt_set(struct roc_cpt *cpt);\n \n struct roc_nix *__roc_api roc_idev_npa_nix_get(void);\n uint64_t __roc_api roc_idev_nix_inl_meta_aura_get(void);\n+struct roc_nix_list *__roc_api roc_idev_nix_list_get(void);\n \n #endif /* _ROC_IDEV_H_ */\ndiff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h\nindex b97d2936a2..d83522799f 100644\n--- a/drivers/common/cnxk/roc_idev_priv.h\n+++ b/drivers/common/cnxk/roc_idev_priv.h\n@@ -32,6 +32,7 @@ struct idev_cfg {\n \tstruct roc_sso *sso;\n \tstruct nix_inl_dev *nix_inl_dev;\n \tstruct idev_nix_inl_cfg inl_cfg;\n+\tstruct roc_nix_list roc_nix_list;\n \tplt_spinlock_t nix_inl_dev_lock;\n \tplt_spinlock_t npa_dev_lock;\n };\ndiff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex 97ef1c7133..39943e4ba7 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -417,6 +417,7 @@ roc_nix_dev_init(struct roc_nix *roc_nix)\n \tnix = roc_nix_to_nix_priv(roc_nix);\n \tpci_dev = roc_nix->pci_dev;\n \tdev = &nix->dev;\n+\tTAILQ_INSERT_TAIL(roc_idev_nix_list_get(), roc_nix, next);\n \n \tif (nix->dev.drv_inited)\n \t\treturn 0;\n@@ -425,6 +426,10 @@ roc_nix_dev_init(struct roc_nix *roc_nix)\n \t\tgoto skip_dev_init;\n \n \tmemset(nix, 0, sizeof(*nix));\n+\n+\t/* Since 0 is a valid BPID, use -1 to represent invalid value. */\n+\tmemset(nix->bpid, -1, sizeof(nix->bpid));\n+\n \t/* Initialize device */\n \trc = dev_init(dev, pci_dev);\n \tif (rc) {\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 2737bb9517..188b8800d3 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -425,6 +425,8 @@ typedef void (*q_err_get_t)(struct roc_nix *roc_nix, void *data);\n typedef void (*link_info_get_t)(struct roc_nix *roc_nix,\n \t\t\t\tstruct roc_nix_link_info *link);\n \n+TAILQ_HEAD(roc_nix_list, roc_nix);\n+\n struct roc_nix {\n \t/* Input parameters */\n \tstruct plt_pci_device *pci_dev;\n@@ -456,6 +458,7 @@ struct roc_nix {\n \tuint32_t buf_sz;\n \tuint64_t meta_aura_handle;\n \tuintptr_t meta_mempool;\n+\tTAILQ_ENTRY(roc_nix) next;\n \n #define ROC_NIX_MEM_SZ (6 * 1056)\n \tuint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned;\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex 3b726673a6..8b7659fb9a 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -428,17 +428,64 @@ roc_nix_fc_mode_set(struct roc_nix *roc_nix, enum roc_nix_fc_mode mode)\n \treturn rc;\n }\n \n+static int\n+nix_rx_chan_multi_bpid_cfg(struct roc_nix *roc_nix, uint8_t chan, uint16_t bpid, uint16_t *bpid_new)\n+{\n+\tstruct roc_nix *roc_nix_tmp, *roc_nix_pre = NULL;\n+\tuint8_t chan_pre;\n+\n+\tif (!roc_feature_nix_has_rxchan_multi_bpid())\n+\t\treturn -ENOTSUP;\n+\n+\t/* Find associated NIX RX channel if Aura BPID is of that of a NIX. */\n+\tTAILQ_FOREACH (roc_nix_tmp, roc_idev_nix_list_get(), next) {\n+\t\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix_tmp);\n+\t\tint i;\n+\n+\t\tfor (i = 0; i < NIX_MAX_CHAN; i++) {\n+\t\t\tif (nix->bpid[i] == bpid)\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (i < NIX_MAX_CHAN) {\n+\t\t\troc_nix_pre = roc_nix_tmp;\n+\t\t\tchan_pre = i;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* Alloc and configure a new BPID if Aura BPID is that of a NIX. */\n+\tif (roc_nix_pre) {\n+\t\tif (roc_nix_bpids_alloc(roc_nix, ROC_NIX_INTF_TYPE_SSO, 1, bpid_new) <= 0)\n+\t\t\treturn -ENOSPC;\n+\n+\t\tif (roc_nix_chan_bpid_set(roc_nix_pre, chan_pre, *bpid_new, 1, false) < 0)\n+\t\t\treturn -ENOSPC;\n+\n+\t\tif (roc_nix_chan_bpid_set(roc_nix, chan, *bpid_new, 1, false) < 0)\n+\t\t\treturn -ENOSPC;\n+\n+\t\treturn 0;\n+\t} else {\n+\t\treturn roc_nix_chan_bpid_set(roc_nix, chan, bpid, 1, false);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+#define NIX_BPID_INVALID 0xFFFF\n+\n void\n roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \t\t uint8_t force, uint8_t tc)\n {\n+\tuint32_t aura_id = roc_npa_aura_handle_to_aura(pool_id);\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct npa_lf *lf = idev_npa_obj_get();\n \tstruct npa_aq_enq_req *req;\n \tstruct npa_aq_enq_rsp *rsp;\n+\tuint8_t bp_thresh, bp_intf;\n \tstruct mbox *mbox;\n-\tuint32_t limit;\n-\tuint64_t shift;\n \tint rc;\n \n \tif (roc_nix_is_sdp(roc_nix))\n@@ -446,93 +493,74 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \n \tif (!lf)\n \t\treturn;\n-\tmbox = mbox_get(lf->mbox);\n \n-\treq = mbox_alloc_msg_npa_aq_enq(mbox);\n-\tif (req == NULL)\n-\t\tgoto exit;\n+\tmbox = lf->mbox;\n+\treq = mbox_alloc_msg_npa_aq_enq(mbox_get(mbox));\n+\tif (req == NULL) {\n+\t\tmbox_put(mbox);\n+\t\treturn;\n+\t}\n \n-\treq->aura_id = roc_npa_aura_handle_to_aura(pool_id);\n+\treq->aura_id = aura_id;\n \treq->ctype = NPA_AQ_CTYPE_AURA;\n \treq->op = NPA_AQ_INSTOP_READ;\n \n \trc = mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\tgoto exit;\n+\tmbox_put(mbox);\n+\tif (rc) {\n+\t\tplt_nix_dbg(\"Failed to read context of aura 0x%\" PRIx64, pool_id);\n+\t\treturn;\n+\t}\n \n-\tlimit = rsp->aura.limit;\n-\tshift = rsp->aura.shift;\n+\tbp_intf = 1 << nix->is_nix1;\n+\tbp_thresh = NIX_RQ_AURA_THRESH(rsp->aura.limit >> rsp->aura.shift);\n \n \t/* BP is already enabled. */\n \tif (rsp->aura.bp_ena && ena) {\n-\t\tuint16_t bpid;\n-\t\tbool nix1;\n+\t\tuint16_t bpid =\n+\t\t\t(rsp->aura.bp_ena & 0x1) ? rsp->aura.nix0_bpid : rsp->aura.nix1_bpid;\n \n-\t\tnix1 = !!(rsp->aura.bp_ena & 0x2);\n-\t\tif (nix1)\n-\t\t\tbpid = rsp->aura.nix1_bpid;\n-\t\telse\n-\t\t\tbpid = rsp->aura.nix0_bpid;\n+\t\t/* Disable BP if BPIDs don't match and couldn't add new BPID. */\n+\t\tif (bpid != nix->bpid[tc]) {\n+\t\t\tuint16_t bpid_new = NIX_BPID_INVALID;\n \n-\t\t/* If BP ids don't match disable BP. */\n-\t\tif (((nix1 != nix->is_nix1) || (bpid != nix->bpid[tc])) &&\n-\t\t !force) {\n-\t\t\treq = mbox_alloc_msg_npa_aq_enq(mbox);\n-\t\t\tif (req == NULL)\n-\t\t\t\tgoto exit;\n+\t\t\tif ((nix_rx_chan_multi_bpid_cfg(roc_nix, tc, bpid, &bpid_new) < 0) &&\n+\t\t\t !force) {\n+\t\t\t\tplt_info(\"Disabling BP/FC on aura 0x%\" PRIx64\n+\t\t\t\t\t \" as it shared across ports or tc\",\n+\t\t\t\t\t pool_id);\n \n-\t\t\tplt_info(\"Disabling BP/FC on aura 0x%\" PRIx64\n-\t\t\t\t \" as it shared across ports or tc\",\n-\t\t\t\t pool_id);\n-\t\t\treq->aura_id = roc_npa_aura_handle_to_aura(pool_id);\n-\t\t\treq->ctype = NPA_AQ_CTYPE_AURA;\n-\t\t\treq->op = NPA_AQ_INSTOP_WRITE;\n+\t\t\t\tif (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false))\n+\t\t\t\t\tplt_nix_dbg(\n+\t\t\t\t\t\t\"Disabling backpressue failed on aura 0x%\" PRIx64,\n+\t\t\t\t\t\tpool_id);\n+\t\t\t}\n \n-\t\t\treq->aura.bp_ena = 0;\n-\t\t\treq->aura_mask.bp_ena = ~(req->aura_mask.bp_ena);\n-\n-\t\t\tmbox_process(mbox);\n+\t\t\t/* Configure Aura with new BPID if it is allocated. */\n+\t\t\tif (bpid_new != NIX_BPID_INVALID) {\n+\t\t\t\tif (roc_npa_aura_bp_configure(pool_id, bpid_new, bp_intf, bp_thresh,\n+\t\t\t\t\t\t\t true))\n+\t\t\t\t\tplt_nix_dbg(\n+\t\t\t\t\t\t\"Enabling backpressue failed on aura 0x%\" PRIx64,\n+\t\t\t\t\t\tpool_id);\n+\t\t\t}\n \t\t}\n \n-\t\tif ((nix1 != nix->is_nix1) || (bpid != nix->bpid[tc]))\n-\t\t\tplt_info(\"Ignoring aura 0x%\" PRIx64 \"->%u bpid mapping\",\n-\t\t\t\t pool_id, nix->bpid[tc]);\n-\t\tgoto exit;\n+\t\treturn;\n \t}\n \n \t/* BP was previously enabled but now disabled skip. */\n \tif (rsp->aura.bp && ena)\n-\t\tgoto exit;\n-\n-\treq = mbox_alloc_msg_npa_aq_enq(mbox);\n-\tif (req == NULL)\n-\t\tgoto exit;\n-\n-\treq->aura_id = roc_npa_aura_handle_to_aura(pool_id);\n-\treq->ctype = NPA_AQ_CTYPE_AURA;\n-\treq->op = NPA_AQ_INSTOP_WRITE;\n+\t\treturn;\n \n \tif (ena) {\n-\t\tif (nix->is_nix1) {\n-\t\t\treq->aura.nix1_bpid = nix->bpid[tc];\n-\t\t\treq->aura_mask.nix1_bpid = ~(req->aura_mask.nix1_bpid);\n-\t\t} else {\n-\t\t\treq->aura.nix0_bpid = nix->bpid[tc];\n-\t\t\treq->aura_mask.nix0_bpid = ~(req->aura_mask.nix0_bpid);\n-\t\t}\n-\t\treq->aura.bp = NIX_RQ_AURA_THRESH(limit >> shift);\n-\t\treq->aura_mask.bp = ~(req->aura_mask.bp);\n+\t\tif (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true))\n+\t\t\tplt_nix_dbg(\"Enabling backpressue failed on aura 0x%\" PRIx64, pool_id);\n \t} else {\n-\t\treq->aura.bp = 0;\n-\t\treq->aura_mask.bp = ~(req->aura_mask.bp);\n+\t\tif (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false))\n+\t\t\tplt_nix_dbg(\"Disabling backpressue failed on aura 0x%\" PRIx64, pool_id);\n \t}\n \n-\treq->aura.bp_ena = (!!ena << nix->is_nix1);\n-\treq->aura_mask.bp_ena = ~(req->aura_mask.bp_ena);\n-\n-\tmbox_process(mbox);\n-exit:\n-\tmbox_put(mbox);\n \treturn;\n }\n \ndiff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex 42846ac4ec..d6a97e49c9 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -882,6 +882,54 @@ roc_npa_zero_aura_handle(void)\n \treturn 0;\n }\n \n+int\n+roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf, uint8_t bp_thresh,\n+\t\t\t bool enable)\n+{\n+\tuint32_t aura_id = roc_npa_aura_handle_to_aura(aura_handle);\n+\tstruct npa_lf *lf = idev_npa_obj_get();\n+\tstruct npa_aq_enq_req *req;\n+\tstruct mbox *mbox;\n+\tint rc = 0;\n+\n+\tif (lf == NULL)\n+\t\treturn NPA_ERR_PARAM;\n+\n+\tmbox = mbox_get(lf->mbox);\n+\treq = mbox_alloc_msg_npa_aq_enq(mbox);\n+\tif (req == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tgoto fail;\n+\t}\n+\n+\treq->aura_id = aura_id;\n+\treq->ctype = NPA_AQ_CTYPE_AURA;\n+\treq->op = NPA_AQ_INSTOP_WRITE;\n+\n+\tif (enable) {\n+\t\tif (bp_intf & 0x1) {\n+\t\t\treq->aura.nix0_bpid = bpid;\n+\t\t\treq->aura_mask.nix0_bpid = ~(req->aura_mask.nix0_bpid);\n+\t\t} else {\n+\t\t\treq->aura.nix1_bpid = bpid;\n+\t\t\treq->aura_mask.nix1_bpid = ~(req->aura_mask.nix1_bpid);\n+\t\t}\n+\t\treq->aura.bp = bp_thresh;\n+\t\treq->aura_mask.bp = ~(req->aura_mask.bp);\n+\t} else {\n+\t\treq->aura.bp = 0;\n+\t\treq->aura_mask.bp = ~(req->aura_mask.bp);\n+\t}\n+\n+\treq->aura.bp_ena = bp_intf;\n+\treq->aura_mask.bp_ena = ~(req->aura_mask.bp_ena);\n+\n+\tmbox_process(mbox);\n+fail:\n+\tmbox_put(mbox);\n+\treturn rc;\n+}\n+\n static inline int\n npa_attach(struct mbox *m_box)\n {\ndiff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h\nindex 21608a40d9..546b7c93d9 100644\n--- a/drivers/common/cnxk/roc_npa.h\n+++ b/drivers/common/cnxk/roc_npa.h\n@@ -746,6 +746,8 @@ uint64_t __roc_api roc_npa_zero_aura_handle(void);\n int __roc_api roc_npa_buf_type_update(uint64_t aura_handle, enum roc_npa_buf_type type, int cnt);\n uint64_t __roc_api roc_npa_buf_type_mask(uint64_t aura_handle);\n uint64_t __roc_api roc_npa_buf_type_limit_get(uint64_t type_mask);\n+int __roc_api roc_npa_aura_bp_configure(uint64_t aura_id, uint16_t bpid, uint8_t bp_intf,\n+\t\t\t\t\tuint8_t bp_thresh, bool enable);\n \n /* Init callbacks */\n typedef int (*roc_npa_lf_init_cb_t)(struct plt_pci_device *pci_dev);\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex e7c6f6bce5..d740d9df81 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -99,6 +99,7 @@ INTERNAL {\n \troc_idev_npa_nix_get;\n \troc_idev_num_lmtlines_get;\n \troc_idev_nix_inl_meta_aura_get;\n+\troc_idev_nix_list_get;\n \troc_ml_reg_read64;\n \troc_ml_reg_write64;\n \troc_ml_reg_read32;\n@@ -361,6 +362,7 @@ INTERNAL {\n \troc_npa_aura_limit_modify;\n \troc_npa_aura_op_range_get;\n \troc_npa_aura_op_range_set;\n+\troc_npa_aura_bp_configure;\n \troc_npa_ctx_dump;\n \troc_npa_dev_fini;\n \troc_npa_dev_init;\n", "prefixes": [ "02/21" ] }