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GET /api/patches/125981/?format=api
{ "id": 125981, "url": "http://patchwork.dpdk.org/api/patches/125981/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230413061650.796940-2-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230413061650.796940-2-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230413061650.796940-2-junfeng.guo@intel.com", "date": "2023-04-13T06:16:41", "name": "[01/10] net/gve: add Tx queue setup for DQO", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "65cda8eb402397ddb30694b9b1a40acc7a736235", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230413061650.796940-2-junfeng.guo@intel.com/mbox/", "series": [ { "id": 27687, "url": "http://patchwork.dpdk.org/api/series/27687/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27687", "date": "2023-04-13T06:16:40", "name": "gve PMD enhancement", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27687/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/125981/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/125981/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 991994292F;\n\tThu, 13 Apr 2023 08:17:16 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5C38C410F9;\n\tThu, 13 Apr 2023 08:17:15 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 9502D410F9\n for <dev@dpdk.org>; Thu, 13 Apr 2023 08:17:13 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Apr 2023 23:17:13 -0700", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by fmsmga007.fm.intel.com with ESMTP; 12 Apr 2023 23:17:10 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1681366633; x=1712902633;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=yklh252yNfNFvwLC1eLbai6xmuqwdL5eWDwjKlKEtHk=;\n b=GCCo/++g4cyUMBC6SnDUD3V0n7u+cm1+4lzjjT/LzyCReqvxaainDp9o\n 5n+iyfUvYecKZLWuG/TRfgBhPeuU7yiMICamy9ItxiyZAuDi3uvDj0pyp\n pHdO9cgTFvbYmOq6ZWF0AjhPHWODE3qHUv55et/A++MECuPC4F/8+ZBpx\n iWkGZFMsGcvK6bc7gV66k/sIFnOwX82rgwf335pZ4aYdMvIyPV8kzzhSy\n JwktDbwECyNUrpIKDCWyc2Ob30vjPDUYd9yT62A/xL70K4eLeckTBxAgP\n 1S19HQ7lyvBQJXQ3fekrwJMsqh/M8y52pbehERd1gRMINDWmxXvrgYFeF A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10678\"; a=\"341595338\"", "E=Sophos;i=\"5.98,339,1673942400\"; d=\"scan'208\";a=\"341595338\"", "E=McAfee;i=\"6600,9927,10678\"; a=\"691824250\"", "E=Sophos;i=\"5.98,339,1673942400\"; d=\"scan'208\";a=\"691824250\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@amd.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, Junfeng Guo <junfeng.guo@intel.com>,\n Rushil Gupta <rushilg@google.com>, Joshua Washington <joshwash@google.com>,\n Jeroen de Borst <jeroendb@google.com>", "Subject": "[PATCH 01/10] net/gve: add Tx queue setup for DQO", "Date": "Thu, 13 Apr 2023 14:16:41 +0800", "Message-Id": "<20230413061650.796940-2-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230413061650.796940-1-junfeng.guo@intel.com>", "References": "<20230413061650.796940-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for tx_queue_setup_dqo ops.\n\nDQO format has submission and completion queue pair for each Tx/Rx\nqueue. Note that with DQO format all descriptors and doorbells, as\nwell as counters are written in little-endian.\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nSigned-off-by: Rushil Gupta <rushilg@google.com>\nSigned-off-by: Joshua Washington <joshwash@google.com>\nSigned-off-by: Jeroen de Borst <jeroendb@google.com>\n---\n drivers/net/gve/gve_ethdev.c | 21 +++-\n drivers/net/gve/gve_ethdev.h | 27 ++++-\n drivers/net/gve/gve_tx_dqo.c | 185 +++++++++++++++++++++++++++++++++++\n drivers/net/gve/meson.build | 1 +\n 4 files changed, 230 insertions(+), 4 deletions(-)\n create mode 100644 drivers/net/gve/gve_tx_dqo.c", "diff": "diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex cf28a4a3b7..90345b193d 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -298,6 +298,7 @@ gve_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \n \tdev_info->default_txconf = (struct rte_eth_txconf) {\n \t\t.tx_free_thresh = GVE_DEFAULT_TX_FREE_THRESH,\n+\t\t.tx_rs_thresh = GVE_DEFAULT_TX_RS_THRESH,\n \t\t.offloads = 0,\n \t};\n \n@@ -528,6 +529,21 @@ static const struct eth_dev_ops gve_eth_dev_ops = {\n \t.xstats_get_names = gve_xstats_get_names,\n };\n \n+static const struct eth_dev_ops gve_eth_dev_ops_dqo = {\n+\t.dev_configure = gve_dev_configure,\n+\t.dev_start = gve_dev_start,\n+\t.dev_stop = gve_dev_stop,\n+\t.dev_close = gve_dev_close,\n+\t.dev_infos_get = gve_dev_info_get,\n+\t.tx_queue_setup = gve_tx_queue_setup_dqo,\n+\t.link_update = gve_link_update,\n+\t.stats_get = gve_dev_stats_get,\n+\t.stats_reset = gve_dev_stats_reset,\n+\t.mtu_set = gve_dev_mtu_set,\n+\t.xstats_get = gve_xstats_get,\n+\t.xstats_get_names = gve_xstats_get_names,\n+};\n+\n static void\n gve_free_counter_array(struct gve_priv *priv)\n {\n@@ -770,8 +786,6 @@ gve_dev_init(struct rte_eth_dev *eth_dev)\n \trte_be32_t *db_bar;\n \tint err;\n \n-\teth_dev->dev_ops = &gve_eth_dev_ops;\n-\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n@@ -807,10 +821,11 @@ gve_dev_init(struct rte_eth_dev *eth_dev)\n \t\treturn err;\n \n \tif (gve_is_gqi(priv)) {\n+\t\teth_dev->dev_ops = &gve_eth_dev_ops;\n \t\teth_dev->rx_pkt_burst = gve_rx_burst;\n \t\teth_dev->tx_pkt_burst = gve_tx_burst;\n \t} else {\n-\t\tPMD_DRV_LOG(ERR, \"DQO_RDA is not implemented and will be added in the future\");\n+\t\teth_dev->dev_ops = &gve_eth_dev_ops_dqo;\n \t}\n \n \teth_dev->data->mac_addrs = &priv->dev_addr;\ndiff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex 0b825113f6..6c6defa045 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -28,7 +28,8 @@\n #define PCI_MSIX_FLAGS_QSIZE\t0x07FF\t/* Table size */\n \n #define GVE_DEFAULT_RX_FREE_THRESH 512\n-#define GVE_DEFAULT_TX_FREE_THRESH 256\n+#define GVE_DEFAULT_TX_FREE_THRESH 32\n+#define GVE_DEFAULT_TX_RS_THRESH 32\n #define GVE_TX_MAX_FREE_SZ 512\n \n #define GVE_MIN_BUF_SIZE\t 1024\n@@ -53,6 +54,13 @@ union gve_tx_desc {\n \tstruct gve_tx_seg_desc seg; /* subsequent descs for a packet */\n };\n \n+/* Tx desc for DQO format */\n+union gve_tx_desc_dqo {\n+\tstruct gve_tx_pkt_desc_dqo pkt;\n+\tstruct gve_tx_tso_context_desc_dqo tso_ctx;\n+\tstruct gve_tx_general_context_desc_dqo general_ctx;\n+};\n+\n /* Offload features */\n union gve_tx_offload {\n \tuint64_t data;\n@@ -100,8 +108,10 @@ struct gve_tx_queue {\n \tuint32_t tx_tail;\n \tuint16_t nb_tx_desc;\n \tuint16_t nb_free;\n+\tuint16_t nb_used;\n \tuint32_t next_to_clean;\n \tuint16_t free_thresh;\n+\tuint16_t rs_thresh;\n \n \t/* Only valid for DQO_QPL queue format */\n \tuint16_t sw_tail;\n@@ -128,7 +138,15 @@ struct gve_tx_queue {\n \tstruct gve_queue_resources *qres;\n \n \t/* newly added for DQO */\n+\tvolatile union gve_tx_desc_dqo *tx_ring;\n+\tstruct gve_tx_compl_desc *compl_ring;\n+\tconst struct rte_memzone *compl_ring_mz;\n \tuint64_t compl_ring_phys_addr;\n+\tuint32_t complq_tail;\n+\tuint16_t sw_size;\n+\tuint8_t cur_gen_bit;\n+\tuint32_t last_desc_cleaned;\n+\tvoid **txqs;\n \n \t/* Only valid for DQO_RDA queue format */\n \tstruct gve_tx_queue *complq;\n@@ -342,4 +360,11 @@ gve_rx_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n uint16_t\n gve_tx_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n \n+/* Below functions are used for DQO */\n+\n+int\n+gve_tx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n+\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t const struct rte_eth_txconf *conf);\n+\n #endif /* _GVE_ETHDEV_H_ */\ndiff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c\nnew file mode 100644\nindex 0000000000..22d20ff16f\n--- /dev/null\n+++ b/drivers/net/gve/gve_tx_dqo.c\n@@ -0,0 +1,185 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022-2023 Google LLC\n+ * Copyright (c) 2022-2023 Intel Corporation\n+ */\n+\n+#include \"gve_ethdev.h\"\n+#include \"base/gve_adminq.h\"\n+\n+static int\n+check_tx_thresh_dqo(uint16_t nb_desc, uint16_t tx_rs_thresh,\n+\t\t uint16_t tx_free_thresh)\n+{\n+\tif (tx_rs_thresh >= (nb_desc - 2)) {\n+\t\tPMD_DRV_LOG(ERR, \"tx_rs_thresh (%u) must be less than the \"\n+\t\t\t \"number of TX descriptors (%u) minus 2\",\n+\t\t\t tx_rs_thresh, nb_desc);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (tx_free_thresh >= (nb_desc - 3)) {\n+\t\tPMD_DRV_LOG(ERR, \"tx_free_thresh (%u) must be less than the \"\n+\t\t\t \"number of TX descriptors (%u) minus 3.\",\n+\t\t\t tx_free_thresh, nb_desc);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (tx_rs_thresh > tx_free_thresh) {\n+\t\tPMD_DRV_LOG(ERR, \"tx_rs_thresh (%u) must be less than or \"\n+\t\t\t \"equal to tx_free_thresh (%u).\",\n+\t\t\t tx_rs_thresh, tx_free_thresh);\n+\t\treturn -EINVAL;\n+\t}\n+\tif ((nb_desc % tx_rs_thresh) != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"tx_rs_thresh (%u) must be a divisor of the \"\n+\t\t\t \"number of TX descriptors (%u).\",\n+\t\t\t tx_rs_thresh, nb_desc);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+gve_reset_txq_dqo(struct gve_tx_queue *txq)\n+{\n+\tstruct rte_mbuf **sw_ring;\n+\tuint32_t size, i;\n+\n+\tif (txq == NULL) {\n+\t\tPMD_DRV_LOG(DEBUG, \"Pointer to txq is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tsize = txq->nb_tx_desc * sizeof(union gve_tx_desc_dqo);\n+\tfor (i = 0; i < size; i++)\n+\t\t((volatile char *)txq->tx_ring)[i] = 0;\n+\n+\tsize = txq->sw_size * sizeof(struct gve_tx_compl_desc);\n+\tfor (i = 0; i < size; i++)\n+\t\t((volatile char *)txq->compl_ring)[i] = 0;\n+\n+\tsw_ring = txq->sw_ring;\n+\tfor (i = 0; i < txq->sw_size; i++)\n+\t\tsw_ring[i] = NULL;\n+\n+\ttxq->tx_tail = 0;\n+\ttxq->nb_used = 0;\n+\n+\ttxq->last_desc_cleaned = 0;\n+\ttxq->sw_tail = 0;\n+\ttxq->nb_free = txq->nb_tx_desc - 1;\n+\n+\ttxq->complq_tail = 0;\n+\ttxq->cur_gen_bit = 1;\n+}\n+\n+int\n+gve_tx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n+\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t const struct rte_eth_txconf *conf)\n+{\n+\tstruct gve_priv *hw = dev->data->dev_private;\n+\tconst struct rte_memzone *mz;\n+\tstruct gve_tx_queue *txq;\n+\tuint16_t free_thresh;\n+\tuint16_t rs_thresh;\n+\tuint16_t sw_size;\n+\tint err = 0;\n+\n+\tif (nb_desc != hw->tx_desc_cnt) {\n+\t\tPMD_DRV_LOG(WARNING, \"gve doesn't support nb_desc config, use hw nb_desc %u.\",\n+\t\t\t hw->tx_desc_cnt);\n+\t}\n+\tnb_desc = hw->tx_desc_cnt;\n+\n+\t/* Allocate the TX queue data structure. */\n+\ttxq = rte_zmalloc_socket(\"gve txq\",\n+\t\t\t\t sizeof(struct gve_tx_queue),\n+\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for tx queue structure\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* need to check free_thresh here */\n+\tfree_thresh = conf->tx_free_thresh ?\n+\t\t\tconf->tx_free_thresh : GVE_DEFAULT_TX_FREE_THRESH;\n+\trs_thresh = conf->tx_rs_thresh ?\n+\t\t\tconf->tx_rs_thresh : GVE_DEFAULT_TX_RS_THRESH;\n+\tif (check_tx_thresh_dqo(nb_desc, rs_thresh, free_thresh))\n+\t\treturn -EINVAL;\n+\n+\ttxq->nb_tx_desc = nb_desc;\n+\ttxq->free_thresh = free_thresh;\n+\ttxq->rs_thresh = rs_thresh;\n+\ttxq->queue_id = queue_id;\n+\ttxq->port_id = dev->data->port_id;\n+\ttxq->ntfy_id = queue_id;\n+\ttxq->hw = hw;\n+\ttxq->ntfy_addr = &hw->db_bar2[rte_be_to_cpu_32(hw->irq_dbs[txq->ntfy_id].id)];\n+\n+\t/* Allocate software ring */\n+\tsw_size = nb_desc * DQO_TX_MULTIPLIER;\n+\ttxq->sw_ring = rte_zmalloc_socket(\"gve tx sw ring\",\n+\t\t\t\t\t sw_size * sizeof(struct rte_mbuf *),\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq->sw_ring == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for SW TX ring\");\n+\t\terr = -ENOMEM;\n+\t\tgoto free_txq;\n+\t}\n+\ttxq->sw_size = sw_size;\n+\n+\t/* Allocate TX hardware ring descriptors. */\n+\tmz = rte_eth_dma_zone_reserve(dev, \"tx_ring\", queue_id,\n+\t\t\t\t nb_desc * sizeof(union gve_tx_desc_dqo),\n+\t\t\t\t PAGE_SIZE, socket_id);\n+\tif (mz == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to reserve DMA memory for TX\");\n+\t\terr = -ENOMEM;\n+\t\tgoto free_txq_sw_ring;\n+\t}\n+\ttxq->tx_ring = (union gve_tx_desc_dqo *)mz->addr;\n+\ttxq->tx_ring_phys_addr = mz->iova;\n+\ttxq->mz = mz;\n+\n+\t/* Allocate TX completion ring descriptors. */\n+\tmz = rte_eth_dma_zone_reserve(dev, \"tx_compl_ring\", queue_id,\n+\t\t\t\t sw_size * sizeof(struct gve_tx_compl_desc),\n+\t\t\t\t PAGE_SIZE, socket_id);\n+\tif (mz == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to reserve DMA memory for TX completion queue\");\n+\t\terr = -ENOMEM;\n+\t\tgoto free_txq_mz;\n+\t}\n+\ttxq->compl_ring = (struct gve_tx_compl_desc *)mz->addr;\n+\ttxq->compl_ring_phys_addr = mz->iova;\n+\ttxq->compl_ring_mz = mz;\n+\ttxq->txqs = dev->data->tx_queues;\n+\n+\tmz = rte_eth_dma_zone_reserve(dev, \"txq_res\", queue_id,\n+\t\t\t\t sizeof(struct gve_queue_resources),\n+\t\t\t\t PAGE_SIZE, socket_id);\n+\tif (mz == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to reserve DMA memory for TX resource\");\n+\t\terr = -ENOMEM;\n+\t\tgoto free_txq_cq_mz;\n+\t}\n+\ttxq->qres = (struct gve_queue_resources *)mz->addr;\n+\ttxq->qres_mz = mz;\n+\n+\tgve_reset_txq_dqo(txq);\n+\n+\tdev->data->tx_queues[queue_id] = txq;\n+\n+\treturn 0;\n+\n+free_txq_cq_mz:\n+\trte_memzone_free(txq->compl_ring_mz);\n+free_txq_mz:\n+\trte_memzone_free(txq->mz);\n+free_txq_sw_ring:\n+\trte_free(txq->sw_ring);\n+free_txq:\n+\trte_free(txq);\n+\treturn err;\n+}\ndiff --git a/drivers/net/gve/meson.build b/drivers/net/gve/meson.build\nindex af0010c01c..2ddb0cbf9e 100644\n--- a/drivers/net/gve/meson.build\n+++ b/drivers/net/gve/meson.build\n@@ -11,6 +11,7 @@ sources = files(\n 'base/gve_adminq.c',\n 'gve_rx.c',\n 'gve_tx.c',\n+ 'gve_tx_dqo.c',\n 'gve_ethdev.c',\n )\n includes += include_directories('base')\n", "prefixes": [ "01/10" ] }