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{
    "id": 125990,
    "url": "http://patchwork.dpdk.org/api/patches/125990/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230413061650.796940-11-junfeng.guo@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230413061650.796940-11-junfeng.guo@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230413061650.796940-11-junfeng.guo@intel.com",
    "date": "2023-04-13T06:16:50",
    "name": "[10/10] net/gve: support jumbo frame for GQI",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "58f9657a46ce2949f8071facf3ddc188eba0bd38",
    "submitter": {
        "id": 1785,
        "url": "http://patchwork.dpdk.org/api/people/1785/?format=api",
        "name": "Junfeng Guo",
        "email": "junfeng.guo@intel.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patchwork.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230413061650.796940-11-junfeng.guo@intel.com/mbox/",
    "series": [
        {
            "id": 27687,
            "url": "http://patchwork.dpdk.org/api/series/27687/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27687",
            "date": "2023-04-13T06:16:40",
            "name": "gve PMD enhancement",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/27687/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/125990/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/125990/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        ],
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            "E=McAfee;i=\"6600,9927,10678\"; a=\"341595417\"",
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            "E=Sophos;i=\"5.98,339,1673942400\"; d=\"scan'208\";a=\"691824321\""
        ],
        "X-ExtLoop1": "1",
        "From": "Junfeng Guo <junfeng.guo@intel.com>",
        "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@amd.com,\n beilei.xing@intel.com",
        "Cc": "dev@dpdk.org, Junfeng Guo <junfeng.guo@intel.com>,\n Rushil Gupta <rushilg@google.com>, Joshua Washington <joshwash@google.com>,\n Jeroen de Borst <jeroendb@google.com>",
        "Subject": "[PATCH 10/10] net/gve: support jumbo frame for GQI",
        "Date": "Thu, 13 Apr 2023 14:16:50 +0800",
        "Message-Id": "<20230413061650.796940-11-junfeng.guo@intel.com>",
        "X-Mailer": "git-send-email 2.34.1",
        "In-Reply-To": "<20230413061650.796940-1-junfeng.guo@intel.com>",
        "References": "<20230413061650.796940-1-junfeng.guo@intel.com>",
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        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Add multi-segment support to enable GQI Rx Jumbo Frame.\n\nSigned-off-by: Rushil Gupta <rushilg@google.com>\nSigned-off-by: Joshua Washington <joshwash@google.com>\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nSigned-off-by: Jeroen de Borst <jeroendb@google.com>\n---\n drivers/net/gve/gve_ethdev.h |   8 ++\n drivers/net/gve/gve_rx.c     | 137 +++++++++++++++++++++++++----------\n 2 files changed, 108 insertions(+), 37 deletions(-)",
    "diff": "diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex 4a0e860afa..53a75044c5 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -159,6 +159,13 @@ struct gve_tx_queue {\n \tuint8_t is_gqi_qpl;\n };\n \n+struct gve_rx_ctx {\n+\tstruct rte_mbuf *mbuf_head;\n+\tstruct rte_mbuf *mbuf_tail;\n+\tuint16_t total_frags;\n+\tbool drop_pkt;\n+};\n+\n struct gve_rx_queue {\n \tvolatile struct gve_rx_desc *rx_desc_ring;\n \tvolatile union gve_rx_data_slot *rx_data_ring;\n@@ -167,6 +174,7 @@ struct gve_rx_queue {\n \tuint64_t rx_ring_phys_addr;\n \tstruct rte_mbuf **sw_ring;\n \tstruct rte_mempool *mpool;\n+\tstruct gve_rx_ctx ctx;\n \n \tuint16_t rx_tail;\n \tuint16_t nb_rx_desc;\ndiff --git a/drivers/net/gve/gve_rx.c b/drivers/net/gve/gve_rx.c\nindex 3dd3f578f9..f2f6202404 100644\n--- a/drivers/net/gve/gve_rx.c\n+++ b/drivers/net/gve/gve_rx.c\n@@ -5,6 +5,8 @@\n #include \"gve_ethdev.h\"\n #include \"base/gve_adminq.h\"\n \n+#define GVE_PKT_CONT_BIT_IS_SET(x) (GVE_RXF_PKT_CONT & (x))\n+\n static inline void\n gve_rx_refill(struct gve_rx_queue *rxq)\n {\n@@ -87,43 +89,72 @@ gve_rx_refill(struct gve_rx_queue *rxq)\n \t}\n }\n \n-uint16_t\n-gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+/*\n+ * This method processes a single rte_mbuf and handles packet segmentation\n+ * In QPL mode it copies data from the mbuf to the gve_rx_queue.\n+ */\n+static void\n+gve_rx_mbuf(struct gve_rx_queue *rxq, struct rte_mbuf *rxe, uint16_t len,\n+\t    uint16_t rx_id)\n {\n-\tvolatile struct gve_rx_desc *rxr, *rxd;\n-\tstruct gve_rx_queue *rxq = rx_queue;\n-\tuint16_t rx_id = rxq->rx_tail;\n-\tstruct rte_mbuf *rxe;\n-\tuint16_t nb_rx, len;\n-\tuint64_t bytes = 0;\n+\tuint16_t padding = 0;\n \tuint64_t addr;\n-\tuint16_t i;\n-\n-\trxr = rxq->rx_desc_ring;\n-\tnb_rx = 0;\n \n-\tfor (i = 0; i < nb_pkts; i++) {\n-\t\trxd = &rxr[rx_id];\n-\t\tif (GVE_SEQNO(rxd->flags_seq) != rxq->expected_seqno)\n-\t\t\tbreak;\n-\n-\t\tif (rxd->flags_seq & GVE_RXF_ERR) {\n-\t\t\trxq->stats.errors++;\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\tlen = rte_be_to_cpu_16(rxd->len) - GVE_RX_PAD;\n-\t\trxe = rxq->sw_ring[rx_id];\n-\t\tif (rxq->is_gqi_qpl) {\n-\t\t\taddr = (uint64_t)(rxq->qpl->mz->addr) + rx_id * PAGE_SIZE + GVE_RX_PAD;\n-\t\t\trte_memcpy((void *)((size_t)rxe->buf_addr + rxe->data_off),\n-\t\t\t\t   (void *)(size_t)addr, len);\n-\t\t}\n+\trxe->data_len = len;\n+\tif (!rxq->ctx.mbuf_head) {\n+\t\trxq->ctx.mbuf_head = rxe;\n+\t\trxq->ctx.mbuf_tail = rxe;\n+\t\trxe->nb_segs = 1;\n \t\trxe->pkt_len = len;\n \t\trxe->data_len = len;\n \t\trxe->port = rxq->port_id;\n \t\trxe->ol_flags = 0;\n+\t\tpadding = GVE_RX_PAD;\n+\t} else {\n+\t\trxq->ctx.mbuf_head->pkt_len += len;\n+\t\trxq->ctx.mbuf_head->nb_segs += 1;\n+\t\trxq->ctx.mbuf_tail->next = rxe;\n+\t\trxq->ctx.mbuf_tail = rxe;\n+\t}\n+\tif (rxq->is_gqi_qpl) {\n+\t\taddr = (uint64_t)(rxq->qpl->mz->addr) + rx_id * PAGE_SIZE + padding;\n+\t\trte_memcpy((void *)((size_t)rxe->buf_addr + rxe->data_off),\n+\t\t\t\t    (void *)(size_t)addr, len);\n+\t}\n+}\n+\n+/*\n+ * This method processes a single packet fragment associated with the\n+ * passed packet descriptor.\n+ * This methods returns whether the fragment is the last fragment\n+ * of a packet.\n+ */\n+static bool\n+gve_rx(struct gve_rx_queue *rxq, volatile struct gve_rx_desc *rxd, uint16_t rx_id)\n+{\n+\tbool is_last_frag = !GVE_PKT_CONT_BIT_IS_SET(rxd->flags_seq);\n+\tuint16_t frag_size = rte_be_to_cpu_16(rxd->len);\n+\tstruct gve_rx_ctx *ctx = &rxq->ctx;\n+\tbool is_first_frag = ctx->total_frags == 0;\n+\tstruct rte_mbuf *rxe;\n+\n+\tif (ctx->drop_pkt)\n+\t\tgoto finish_frag;\n \n+\tif (rxd->flags_seq & GVE_RXF_ERR) {\n+\t\tctx->drop_pkt = true;\n+\t\trxq->stats.errors++;\n+\t\tgoto finish_frag;\n+\t}\n+\n+\tif (is_first_frag)\n+\t\tfrag_size -= GVE_RX_PAD;\n+\n+\trxe = rxq->sw_ring[rx_id];\n+\tgve_rx_mbuf(rxq, rxe, frag_size, rx_id);\n+\trxq->stats.bytes += frag_size;\n+\n+\tif (is_first_frag) {\n \t\tif (rxd->flags_seq & GVE_RXF_TCP)\n \t\t\trxe->packet_type |= RTE_PTYPE_L4_TCP;\n \t\tif (rxd->flags_seq & GVE_RXF_UDP)\n@@ -137,28 +168,60 @@ gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\t\trxe->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;\n \t\t\trxe->hash.rss = rte_be_to_cpu_32(rxd->rss_hash);\n \t\t}\n+\t}\n \n-\t\trxq->expected_seqno = gve_next_seqno(rxq->expected_seqno);\n+finish_frag:\n+\tctx->total_frags++;\n+\treturn is_last_frag;\n+}\n+\n+static void\n+gve_rx_ctx_clear(struct gve_rx_ctx *ctx)\n+{\n+\tctx->mbuf_head = NULL;\n+\tctx->mbuf_tail = NULL;\n+\tctx->drop_pkt = false;\n+\tctx->total_frags = 0;\n+}\n+\n+uint16_t\n+gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tvolatile struct gve_rx_desc *rxr, *rxd;\n+\tstruct gve_rx_queue *rxq = rx_queue;\n+\tstruct gve_rx_ctx *ctx = &rxq->ctx;\n+\tuint16_t rx_id = rxq->rx_tail;\n+\tuint16_t nb_rx;\n+\n+\trxr = rxq->rx_desc_ring;\n+\tnb_rx = 0;\n+\n+\twhile (nb_rx < nb_pkts) {\n+\t\trxd = &rxr[rx_id];\n+\t\tif (GVE_SEQNO(rxd->flags_seq) != rxq->expected_seqno)\n+\t\t\tbreak;\n+\n+\t\tif (gve_rx(rxq, rxd, rx_id)) {\n+\t\t\tif (!ctx->drop_pkt)\n+\t\t\t\trx_pkts[nb_rx++] = ctx->mbuf_head;\n+\t\t\trxq->nb_avail += ctx->total_frags;\n+\t\t\tgve_rx_ctx_clear(ctx);\n+\t\t}\n \n \t\trx_id++;\n \t\tif (rx_id == rxq->nb_rx_desc)\n \t\t\trx_id = 0;\n \n-\t\trx_pkts[nb_rx] = rxe;\n-\t\tbytes += len;\n-\t\tnb_rx++;\n+\t\trxq->expected_seqno = gve_next_seqno(rxq->expected_seqno);\n \t}\n \n-\trxq->nb_avail += nb_rx;\n \trxq->rx_tail = rx_id;\n \n \tif (rxq->nb_avail > rxq->free_thresh)\n \t\tgve_rx_refill(rxq);\n \n-\tif (nb_rx) {\n+\tif (nb_rx)\n \t\trxq->stats.packets += nb_rx;\n-\t\trxq->stats.bytes += bytes;\n-\t}\n \n \treturn nb_rx;\n }\n",
    "prefixes": [
        "10/10"
    ]
}