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GET /api/patches/126779/?format=api
{ "id": 126779, "url": "http://patchwork.dpdk.org/api/patches/126779/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230509030729.2680451-1-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230509030729.2680451-1-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230509030729.2680451-1-junfeng.guo@intel.com", "date": "2023-05-09T03:07:29", "name": "net/gve: support queue start and stop operations", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ad30e7f25b9157ff31a96e20c53437124fdeba96", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230509030729.2680451-1-junfeng.guo@intel.com/mbox/", "series": [ { "id": 27965, "url": "http://patchwork.dpdk.org/api/series/27965/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27965", "date": "2023-05-09T03:07:29", "name": "net/gve: support queue start and stop operations", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27965/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/126779/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/126779/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EDD9942A8C;\n\tTue, 9 May 2023 05:07:51 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 80C13410D7;\n\tTue, 9 May 2023 05:07:51 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id E5E4C410D0\n for <dev@dpdk.org>; Tue, 9 May 2023 05:07:48 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 May 2023 20:07:47 -0700", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.149])\n by fmsmga004.fm.intel.com with ESMTP; 08 May 2023 20:07:44 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1683601669; x=1715137669;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=AuD0+ziV1zCZNVg00xQz8hKT9t3HcoBuX3HRECibNhA=;\n b=NtsMJKCOH9KcdmxYjBx3jcV4LH+CrWrH9ttBPH60+bG/8nbDVWJRXp2A\n fod4GacP7j6ZgkM7nuEhk8FkOI8DO6+irJ6hrjIlGUKBBdwh+T32AneVp\n GcnCPV7lcWyqpZ2rfzrMEBcWdcexK6HIRlskL1YB+I724vCtY/a5oWZkL\n T4Q/4PYcqTST5fj44vYg8UuQMoal4e6tidVL8XbsN7UELb7sM+jy5ysU9\n Cqy7/qdjGv6347rOzfw3VDFLSs/meEgfEZuMl1O6opTBSNxIZsYJezbZR\n HRXGNEQ7FDfKfhAGWa4QnPjvCuIPZCz8KJWrQcvMu9ERLeMrC+JA2yCNJ Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10704\"; a=\"334249846\"", "E=Sophos;i=\"5.99,259,1677571200\"; d=\"scan'208\";a=\"334249846\"", "E=McAfee;i=\"6600,9927,10704\"; a=\"768286131\"", "E=Sophos;i=\"5.99,259,1677571200\"; d=\"scan'208\";a=\"768286131\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com,\n\tferruh.yigit@amd.com,\n\trushilg@google.com", "Cc": "dev@dpdk.org, joshwash@google.com, jeroendb@google.com,\n Junfeng Guo <junfeng.guo@intel.com>", "Subject": "[PATCH] net/gve: support queue start and stop operations", "Date": "Tue, 9 May 2023 11:07:29 +0800", "Message-Id": "<20230509030729.2680451-1-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for queue operations for GQI:\n - gve_rx_queue_start\n - gve_tx_queue_start\n - gve_rx_queue_stop\n - gve_tx_queue_stop\n\nAdd support for queue operations for DQO:\n - gve_rx_queue_start_dqo\n - gve_tx_queue_start_dqo\n - gve_rx_queue_stop_dqo\n - gve_tx_queue_stop_dqo\n\nAlso move the funcs of rxq_mbufs_alloc into the corresponding files.\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n drivers/net/gve/gve_ethdev.c | 166 +++++++++++------------------------\n drivers/net/gve/gve_ethdev.h | 36 ++++++++\n drivers/net/gve/gve_rx.c | 96 ++++++++++++++++++--\n drivers/net/gve/gve_rx_dqo.c | 97 ++++++++++++++++++--\n drivers/net/gve/gve_tx.c | 54 ++++++++++--\n drivers/net/gve/gve_tx_dqo.c | 54 ++++++++++--\n 6 files changed, 364 insertions(+), 139 deletions(-)", "diff": "diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex 8b6861a24f..1dcb3b3a01 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -104,81 +104,6 @@ gve_dev_configure(struct rte_eth_dev *dev)\n \treturn 0;\n }\n \n-static int\n-gve_refill_pages(struct gve_rx_queue *rxq)\n-{\n-\tstruct rte_mbuf *nmb;\n-\tuint16_t i;\n-\tint diag;\n-\n-\tdiag = rte_pktmbuf_alloc_bulk(rxq->mpool, &rxq->sw_ring[0], rxq->nb_rx_desc);\n-\tif (diag < 0) {\n-\t\tfor (i = 0; i < rxq->nb_rx_desc - 1; i++) {\n-\t\t\tnmb = rte_pktmbuf_alloc(rxq->mpool);\n-\t\t\tif (!nmb)\n-\t\t\t\tbreak;\n-\t\t\trxq->sw_ring[i] = nmb;\n-\t\t}\n-\t\tif (i < rxq->nb_rx_desc - 1)\n-\t\t\treturn -ENOMEM;\n-\t}\n-\trxq->nb_avail = 0;\n-\trxq->next_avail = rxq->nb_rx_desc - 1;\n-\n-\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n-\t\tif (rxq->is_gqi_qpl) {\n-\t\t\trxq->rx_data_ring[i].addr = rte_cpu_to_be_64(i * PAGE_SIZE);\n-\t\t} else {\n-\t\t\tif (i == rxq->nb_rx_desc - 1)\n-\t\t\t\tbreak;\n-\t\t\tnmb = rxq->sw_ring[i];\n-\t\t\trxq->rx_data_ring[i].addr = rte_cpu_to_be_64(rte_mbuf_data_iova(nmb));\n-\t\t}\n-\t}\n-\n-\trte_write32(rte_cpu_to_be_32(rxq->next_avail), rxq->qrx_tail);\n-\n-\treturn 0;\n-}\n-\n-static int\n-gve_refill_dqo(struct gve_rx_queue *rxq)\n-{\n-\tstruct rte_mbuf *nmb;\n-\tuint16_t i;\n-\tint diag;\n-\n-\tdiag = rte_pktmbuf_alloc_bulk(rxq->mpool, &rxq->sw_ring[0], rxq->nb_rx_desc);\n-\tif (diag < 0) {\n-\t\trxq->stats.no_mbufs_bulk++;\n-\t\tfor (i = 0; i < rxq->nb_rx_desc - 1; i++) {\n-\t\t\tnmb = rte_pktmbuf_alloc(rxq->mpool);\n-\t\t\tif (!nmb)\n-\t\t\t\tbreak;\n-\t\t\trxq->sw_ring[i] = nmb;\n-\t\t}\n-\t\tif (i < rxq->nb_rx_desc - 1) {\n-\t\t\trxq->stats.no_mbufs += rxq->nb_rx_desc - 1 - i;\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t}\n-\n-\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n-\t\tif (i == rxq->nb_rx_desc - 1)\n-\t\t\tbreak;\n-\t\tnmb = rxq->sw_ring[i];\n-\t\trxq->rx_ring[i].buf_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));\n-\t\trxq->rx_ring[i].buf_id = rte_cpu_to_le_16(i);\n-\t}\n-\n-\trxq->nb_rx_hold = 0;\n-\trxq->bufq_tail = rxq->nb_rx_desc - 1;\n-\n-\trte_write32(rxq->bufq_tail, rxq->qrx_tail);\n-\n-\treturn 0;\n-}\n-\n static int\n gve_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)\n {\n@@ -208,65 +133,68 @@ gve_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)\n }\n \n static int\n-gve_dev_start(struct rte_eth_dev *dev)\n+gve_start_queues(struct rte_eth_dev *dev)\n {\n-\tuint16_t num_queues = dev->data->nb_tx_queues;\n \tstruct gve_priv *priv = dev->data->dev_private;\n-\tstruct gve_tx_queue *txq;\n-\tstruct gve_rx_queue *rxq;\n+\tuint16_t num_queues;\n \tuint16_t i;\n-\tint err;\n+\tint ret;\n \n+\tnum_queues = dev->data->nb_tx_queues;\n \tpriv->txqs = (struct gve_tx_queue **)dev->data->tx_queues;\n-\terr = gve_adminq_create_tx_queues(priv, num_queues);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"failed to create %u tx queues.\", num_queues);\n-\t\treturn err;\n-\t}\n-\tfor (i = 0; i < num_queues; i++) {\n-\t\ttxq = priv->txqs[i];\n-\t\ttxq->qtx_tail =\n-\t\t&priv->db_bar2[rte_be_to_cpu_32(txq->qres->db_index)];\n-\t\ttxq->qtx_head =\n-\t\t&priv->cnt_array[rte_be_to_cpu_32(txq->qres->counter_index)];\n-\n-\t\trte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), txq->ntfy_addr);\n-\t}\n+\tret = gve_adminq_create_tx_queues(priv, num_queues);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to create %u tx queues.\", num_queues);\n+\t\treturn ret;\n+\t}\n+\tfor (i = 0; i < num_queues; i++)\n+\t\tif (gve_tx_queue_start(dev, i) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to start Tx queue %d\", i);\n+\t\t\tgoto err_tx;\n+\t\t}\n \n \tnum_queues = dev->data->nb_rx_queues;\n \tpriv->rxqs = (struct gve_rx_queue **)dev->data->rx_queues;\n-\terr = gve_adminq_create_rx_queues(priv, num_queues);\n-\tif (err) {\n-\t\tPMD_DRV_LOG(ERR, \"failed to create %u rx queues.\", num_queues);\n+\tret = gve_adminq_create_rx_queues(priv, num_queues);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to create %u rx queues.\", num_queues);\n \t\tgoto err_tx;\n \t}\n \tfor (i = 0; i < num_queues; i++) {\n-\t\trxq = priv->rxqs[i];\n-\t\trxq->qrx_tail =\n-\t\t&priv->db_bar2[rte_be_to_cpu_32(rxq->qres->db_index)];\n-\n-\t\trte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), rxq->ntfy_addr);\n-\n \t\tif (gve_is_gqi(priv))\n-\t\t\terr = gve_refill_pages(rxq);\n+\t\t\tret = gve_rx_queue_start(dev, i);\n \t\telse\n-\t\t\terr = gve_refill_dqo(rxq);\n-\t\tif (err) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Failed to refill for RX\");\n+\t\t\tret = gve_rx_queue_start_dqo(dev, i);\n+\t\tif (ret != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to start Rx queue %d\", i);\n \t\t\tgoto err_rx;\n \t\t}\n \t}\n \n-\tdev->data->dev_started = 1;\n-\tgve_link_update(dev, 0);\n-\n \treturn 0;\n \n err_rx:\n \tgve_stop_rx_queues(dev);\n err_tx:\n \tgve_stop_tx_queues(dev);\n-\treturn err;\n+\treturn ret;\n+}\n+\n+static int\n+gve_dev_start(struct rte_eth_dev *dev)\n+{\n+\tint ret;\n+\n+\tret = gve_start_queues(dev);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to start queues\");\n+\t\treturn ret;\n+\t}\n+\n+\tdev->data->dev_started = 1;\n+\tgve_link_update(dev, 0);\n+\n+\treturn 0;\n }\n \n static int\n@@ -573,6 +501,10 @@ static const struct eth_dev_ops gve_eth_dev_ops = {\n \t.tx_queue_setup = gve_tx_queue_setup,\n \t.rx_queue_release = gve_rx_queue_release,\n \t.tx_queue_release = gve_tx_queue_release,\n+\t.rx_queue_start = gve_rx_queue_start,\n+\t.tx_queue_start = gve_tx_queue_start,\n+\t.rx_queue_stop = gve_rx_queue_stop,\n+\t.tx_queue_stop = gve_tx_queue_stop,\n \t.link_update = gve_link_update,\n \t.stats_get = gve_dev_stats_get,\n \t.stats_reset = gve_dev_stats_reset,\n@@ -591,6 +523,10 @@ static const struct eth_dev_ops gve_eth_dev_ops_dqo = {\n \t.tx_queue_setup = gve_tx_queue_setup_dqo,\n \t.rx_queue_release = gve_rx_queue_release_dqo,\n \t.tx_queue_release = gve_tx_queue_release_dqo,\n+\t.rx_queue_start = gve_rx_queue_start_dqo,\n+\t.tx_queue_start = gve_tx_queue_start_dqo,\n+\t.rx_queue_stop = gve_rx_queue_stop_dqo,\n+\t.tx_queue_stop = gve_tx_queue_stop_dqo,\n \t.link_update = gve_link_update,\n \t.stats_get = gve_dev_stats_get,\n \t.stats_reset = gve_dev_stats_reset,\n@@ -877,12 +813,12 @@ gve_dev_init(struct rte_eth_dev *eth_dev)\n \n \tif (gve_is_gqi(priv)) {\n \t\teth_dev->dev_ops = &gve_eth_dev_ops;\n-\t\teth_dev->rx_pkt_burst = gve_rx_burst;\n-\t\teth_dev->tx_pkt_burst = gve_tx_burst;\n+\t\tgve_set_rx_function(eth_dev);\n+\t\tgve_set_tx_function(eth_dev);\n \t} else {\n \t\teth_dev->dev_ops = &gve_eth_dev_ops_dqo;\n-\t\teth_dev->rx_pkt_burst = gve_rx_burst_dqo;\n-\t\teth_dev->tx_pkt_burst = gve_tx_burst_dqo;\n+\t\tgve_set_rx_function_dqo(eth_dev);\n+\t\tgve_set_tx_function_dqo(eth_dev);\n \t}\n \n \teth_dev->data->mac_addrs = &priv->dev_addr;\ndiff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex 53a75044c5..cd62debd22 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -367,6 +367,18 @@ gve_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);\n void\n gve_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);\n \n+int\n+gve_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+\n+int\n+gve_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n+\n+int\n+gve_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+\n+int\n+gve_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n+\n void\n gve_stop_tx_queues(struct rte_eth_dev *dev);\n \n@@ -379,6 +391,12 @@ gve_rx_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n uint16_t\n gve_tx_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n \n+void\n+gve_set_rx_function(struct rte_eth_dev *dev);\n+\n+void\n+gve_set_tx_function(struct rte_eth_dev *dev);\n+\n /* Below functions are used for DQO */\n \n int\n@@ -397,6 +415,18 @@ gve_tx_queue_release_dqo(struct rte_eth_dev *dev, uint16_t qid);\n void\n gve_rx_queue_release_dqo(struct rte_eth_dev *dev, uint16_t qid);\n \n+int\n+gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n+\n+int\n+gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+\n+int\n+gve_rx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n+\n+int\n+gve_tx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+\n void\n gve_stop_tx_queues_dqo(struct rte_eth_dev *dev);\n \n@@ -409,4 +439,10 @@ gve_rx_burst_dqo(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n uint16_t\n gve_tx_burst_dqo(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n \n+void\n+gve_set_rx_function_dqo(struct rte_eth_dev *dev);\n+\n+void\n+gve_set_tx_function_dqo(struct rte_eth_dev *dev);\n+\n #endif /* _GVE_ETHDEV_H_ */\ndiff --git a/drivers/net/gve/gve_rx.c b/drivers/net/gve/gve_rx.c\nindex f2f6202404..b8c92ccda0 100644\n--- a/drivers/net/gve/gve_rx.c\n+++ b/drivers/net/gve/gve_rx.c\n@@ -414,11 +414,91 @@ gve_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,\n \treturn err;\n }\n \n+static int\n+gve_rxq_mbufs_alloc(struct gve_rx_queue *rxq)\n+{\n+\tstruct rte_mbuf *nmb;\n+\tuint16_t i;\n+\tint diag;\n+\n+\tdiag = rte_pktmbuf_alloc_bulk(rxq->mpool, &rxq->sw_ring[0], rxq->nb_rx_desc);\n+\tif (diag < 0) {\n+\t\tfor (i = 0; i < rxq->nb_rx_desc - 1; i++) {\n+\t\t\tnmb = rte_pktmbuf_alloc(rxq->mpool);\n+\t\t\tif (!nmb)\n+\t\t\t\tbreak;\n+\t\t\trxq->sw_ring[i] = nmb;\n+\t\t}\n+\t\tif (i < rxq->nb_rx_desc - 1)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\trxq->nb_avail = 0;\n+\trxq->next_avail = rxq->nb_rx_desc - 1;\n+\n+\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n+\t\tif (rxq->is_gqi_qpl) {\n+\t\t\trxq->rx_data_ring[i].addr = rte_cpu_to_be_64(i * PAGE_SIZE);\n+\t\t} else {\n+\t\t\tif (i == rxq->nb_rx_desc - 1)\n+\t\t\t\tbreak;\n+\t\t\tnmb = rxq->sw_ring[i];\n+\t\t\trxq->rx_data_ring[i].addr = rte_cpu_to_be_64(rte_mbuf_data_iova(nmb));\n+\t\t}\n+\t}\n+\n+\trte_write32(rte_cpu_to_be_32(rxq->next_avail), rxq->qrx_tail);\n+\n+\treturn 0;\n+}\n+\n+int\n+gve_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n+{\n+\tstruct gve_priv *hw = dev->data->dev_private;\n+\tstruct gve_rx_queue *rxq;\n+\tint ret;\n+\n+\tif (rx_queue_id >= dev->data->nb_rx_queues)\n+\t\treturn -EINVAL;\n+\n+\trxq = dev->data->rx_queues[rx_queue_id];\n+\n+\trxq->qrx_tail = &hw->db_bar2[rte_be_to_cpu_32(rxq->qres->db_index)];\n+\n+\trte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), rxq->ntfy_addr);\n+\n+\tret = gve_rxq_mbufs_alloc(rxq);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to alloc Rx queue mbuf\");\n+\t\treturn ret;\n+\t}\n+\n+\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n+\n+\treturn 0;\n+}\n+\n+int\n+gve_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n+{\n+\tstruct gve_rx_queue *rxq;\n+\n+\tif (rx_queue_id >= dev->data->nb_rx_queues)\n+\t\treturn -EINVAL;\n+\n+\trxq = dev->data->rx_queues[rx_queue_id];\n+\tgve_release_rxq_mbufs(rxq);\n+\tgve_reset_rxq(rxq);\n+\n+\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\treturn 0;\n+}\n+\n void\n gve_stop_rx_queues(struct rte_eth_dev *dev)\n {\n \tstruct gve_priv *hw = dev->data->dev_private;\n-\tstruct gve_rx_queue *rxq;\n \tuint16_t i;\n \tint err;\n \n@@ -429,9 +509,13 @@ gve_stop_rx_queues(struct rte_eth_dev *dev)\n \tif (err != 0)\n \t\tPMD_DRV_LOG(WARNING, \"failed to destroy rxqs\");\n \n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n-\t\trxq = dev->data->rx_queues[i];\n-\t\tgve_release_rxq_mbufs(rxq);\n-\t\tgve_reset_rxq(rxq);\n-\t}\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n+\t\tif (gve_rx_queue_stop(dev, i) != 0)\n+\t\t\tPMD_DRV_LOG(WARNING, \"Fail to stop Rx queue %d\", i);\n+}\n+\n+void\n+gve_set_rx_function(struct rte_eth_dev *dev)\n+{\n+\tdev->rx_pkt_burst = gve_rx_burst;\n }\ndiff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c\nindex 1d6b21359c..236aefd2a8 100644\n--- a/drivers/net/gve/gve_rx_dqo.c\n+++ b/drivers/net/gve/gve_rx_dqo.c\n@@ -333,11 +333,92 @@ gve_rx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n \treturn err;\n }\n \n+static int\n+gve_rxq_mbufs_alloc_dqo(struct gve_rx_queue *rxq)\n+{\n+\tstruct rte_mbuf *nmb;\n+\tuint16_t i;\n+\tint diag;\n+\n+\tdiag = rte_pktmbuf_alloc_bulk(rxq->mpool, &rxq->sw_ring[0], rxq->nb_rx_desc);\n+\tif (diag < 0) {\n+\t\trxq->stats.no_mbufs_bulk++;\n+\t\tfor (i = 0; i < rxq->nb_rx_desc - 1; i++) {\n+\t\t\tnmb = rte_pktmbuf_alloc(rxq->mpool);\n+\t\t\tif (!nmb)\n+\t\t\t\tbreak;\n+\t\t\trxq->sw_ring[i] = nmb;\n+\t\t}\n+\t\tif (i < rxq->nb_rx_desc - 1) {\n+\t\t\trxq->stats.no_mbufs += rxq->nb_rx_desc - 1 - i;\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n+\t\tif (i == rxq->nb_rx_desc - 1)\n+\t\t\tbreak;\n+\t\tnmb = rxq->sw_ring[i];\n+\t\trxq->rx_ring[i].buf_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));\n+\t\trxq->rx_ring[i].buf_id = rte_cpu_to_le_16(i);\n+\t}\n+\n+\trxq->nb_rx_hold = 0;\n+\trxq->bufq_tail = rxq->nb_rx_desc - 1;\n+\n+\trte_write32(rxq->bufq_tail, rxq->qrx_tail);\n+\n+\treturn 0;\n+}\n+\n+int\n+gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n+{\n+\tstruct gve_priv *hw = dev->data->dev_private;\n+\tstruct gve_rx_queue *rxq;\n+\tint ret;\n+\n+\tif (rx_queue_id >= dev->data->nb_rx_queues)\n+\t\treturn -EINVAL;\n+\n+\trxq = dev->data->rx_queues[rx_queue_id];\n+\n+\trxq->qrx_tail = &hw->db_bar2[rte_be_to_cpu_32(rxq->qres->db_index)];\n+\n+\trte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), rxq->ntfy_addr);\n+\n+\tret = gve_rxq_mbufs_alloc_dqo(rxq);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to alloc Rx queue mbuf\");\n+\t\treturn ret;\n+\t}\n+\n+\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n+\n+\treturn 0;\n+}\n+\n+int\n+gve_rx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n+{\n+\tstruct gve_rx_queue *rxq;\n+\n+\tif (rx_queue_id >= dev->data->nb_rx_queues)\n+\t\treturn -EINVAL;\n+\n+\trxq = dev->data->rx_queues[rx_queue_id];\n+\tgve_release_rxq_mbufs_dqo(rxq);\n+\tgve_reset_rxq_dqo(rxq);\n+\n+\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\treturn 0;\n+}\n+\n void\n gve_stop_rx_queues_dqo(struct rte_eth_dev *dev)\n {\n \tstruct gve_priv *hw = dev->data->dev_private;\n-\tstruct gve_rx_queue *rxq;\n \tuint16_t i;\n \tint err;\n \n@@ -345,9 +426,13 @@ gve_stop_rx_queues_dqo(struct rte_eth_dev *dev)\n \tif (err != 0)\n \t\tPMD_DRV_LOG(WARNING, \"failed to destroy rxqs\");\n \n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n-\t\trxq = dev->data->rx_queues[i];\n-\t\tgve_release_rxq_mbufs_dqo(rxq);\n-\t\tgve_reset_rxq_dqo(rxq);\n-\t}\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n+\t\tif (gve_rx_queue_stop_dqo(dev, i) != 0)\n+\t\t\tPMD_DRV_LOG(WARNING, \"Fail to stop Rx queue %d\", i);\n+}\n+\n+void\n+gve_set_rx_function_dqo(struct rte_eth_dev *dev)\n+{\n+\tdev->rx_pkt_burst = gve_rx_burst_dqo;\n }\ndiff --git a/drivers/net/gve/gve_tx.c b/drivers/net/gve/gve_tx.c\nindex 13dc807623..2e0d001109 100644\n--- a/drivers/net/gve/gve_tx.c\n+++ b/drivers/net/gve/gve_tx.c\n@@ -664,11 +664,49 @@ gve_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id, uint16_t nb_desc,\n \treturn err;\n }\n \n+int\n+gve_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct gve_priv *hw = dev->data->dev_private;\n+\tstruct gve_tx_queue *txq;\n+\n+\tif (tx_queue_id >= dev->data->nb_tx_queues)\n+\t\treturn -EINVAL;\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\n+\ttxq->qtx_tail = &hw->db_bar2[rte_be_to_cpu_32(txq->qres->db_index)];\n+\ttxq->qtx_head =\n+\t\t&hw->cnt_array[rte_be_to_cpu_32(txq->qres->counter_index)];\n+\n+\trte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), txq->ntfy_addr);\n+\n+\tdev->data->rx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n+\n+\treturn 0;\n+}\n+\n+int\n+gve_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct gve_tx_queue *txq;\n+\n+\tif (tx_queue_id >= dev->data->nb_tx_queues)\n+\t\treturn -EINVAL;\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\tgve_release_txq_mbufs(txq);\n+\tgve_reset_txq(txq);\n+\n+\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\treturn 0;\n+}\n+\n void\n gve_stop_tx_queues(struct rte_eth_dev *dev)\n {\n \tstruct gve_priv *hw = dev->data->dev_private;\n-\tstruct gve_tx_queue *txq;\n \tuint16_t i;\n \tint err;\n \n@@ -679,9 +717,13 @@ gve_stop_tx_queues(struct rte_eth_dev *dev)\n \tif (err != 0)\n \t\tPMD_DRV_LOG(WARNING, \"failed to destroy txqs\");\n \n-\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n-\t\ttxq = dev->data->tx_queues[i];\n-\t\tgve_release_txq_mbufs(txq);\n-\t\tgve_reset_txq(txq);\n-\t}\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n+\t\tif (gve_tx_queue_stop(dev, i) != 0)\n+\t\t\tPMD_DRV_LOG(WARNING, \"Fail to stop Tx queue %d\", i);\n+}\n+\n+void\n+gve_set_tx_function(struct rte_eth_dev *dev)\n+{\n+\tdev->tx_pkt_burst = gve_tx_burst;\n }\ndiff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c\nindex b38eeaea4b..e0d144835b 100644\n--- a/drivers/net/gve/gve_tx_dqo.c\n+++ b/drivers/net/gve/gve_tx_dqo.c\n@@ -373,11 +373,49 @@ gve_tx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n \treturn err;\n }\n \n+int\n+gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct gve_priv *hw = dev->data->dev_private;\n+\tstruct gve_tx_queue *txq;\n+\n+\tif (tx_queue_id >= dev->data->nb_tx_queues)\n+\t\treturn -EINVAL;\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\n+\ttxq->qtx_tail = &hw->db_bar2[rte_be_to_cpu_32(txq->qres->db_index)];\n+\ttxq->qtx_head =\n+\t\t&hw->cnt_array[rte_be_to_cpu_32(txq->qres->counter_index)];\n+\n+\trte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), txq->ntfy_addr);\n+\n+\tdev->data->rx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n+\n+\treturn 0;\n+}\n+\n+int\n+gve_tx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct gve_tx_queue *txq;\n+\n+\tif (tx_queue_id >= dev->data->nb_tx_queues)\n+\t\treturn -EINVAL;\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\tgve_release_txq_mbufs_dqo(txq);\n+\tgve_reset_txq_dqo(txq);\n+\n+\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\treturn 0;\n+}\n+\n void\n gve_stop_tx_queues_dqo(struct rte_eth_dev *dev)\n {\n \tstruct gve_priv *hw = dev->data->dev_private;\n-\tstruct gve_tx_queue *txq;\n \tuint16_t i;\n \tint err;\n \n@@ -385,9 +423,13 @@ gve_stop_tx_queues_dqo(struct rte_eth_dev *dev)\n \tif (err != 0)\n \t\tPMD_DRV_LOG(WARNING, \"failed to destroy txqs\");\n \n-\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n-\t\ttxq = dev->data->tx_queues[i];\n-\t\tgve_release_txq_mbufs_dqo(txq);\n-\t\tgve_reset_txq_dqo(txq);\n-\t}\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n+\t\tif (gve_tx_queue_stop_dqo(dev, i) != 0)\n+\t\t\tPMD_DRV_LOG(WARNING, \"Fail to stop Tx queue %d\", i);\n+}\n+\n+void\n+gve_set_tx_function_dqo(struct rte_eth_dev *dev)\n+{\n+\tdev->tx_pkt_burst = gve_tx_burst_dqo;\n }\n", "prefixes": [] }