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GET /api/patches/127195/?format=api
{ "id": 127195, "url": "http://patchwork.dpdk.org/api/patches/127195/?format=api", "web_url": "http://patchwork.dpdk.org/project/dts/patch/20230523091220.32474-3-tadhg.kearney@intel.com/", "project": { "id": 3, "url": "http://patchwork.dpdk.org/api/projects/3/?format=api", "name": "DTS", "link_name": "dts", "list_id": "dts.dpdk.org", "list_email": "dts@dpdk.org", "web_url": "", "scm_url": "git://dpdk.org/tools/dts", "webscm_url": "http://git.dpdk.org/tools/dts/", "list_archive_url": "https://inbox.dpdk.org/dts", "list_archive_url_format": "https://inbox.dpdk.org/dts/{}", "commit_url_format": "" }, "msgid": "<20230523091220.32474-3-tadhg.kearney@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dts/20230523091220.32474-3-tadhg.kearney@intel.com", "date": "2023-05-23T09:12:20", "name": "[v1,2/2] test_plans/power_intel_uncore: add test_plan for newly added test suite", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "d38acf7a02672a2491d3b86a944ea56db0c10a8d", "submitter": { "id": 2533, "url": "http://patchwork.dpdk.org/api/people/2533/?format=api", "name": "Tadhg Kearney", "email": "tadhg.kearney@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dts/patch/20230523091220.32474-3-tadhg.kearney@intel.com/mbox/", "series": [ { "id": 28126, "url": "http://patchwork.dpdk.org/api/series/28126/?format=api", "web_url": "http://patchwork.dpdk.org/project/dts/list/?series=28126", "date": "2023-05-23T09:12:18", "name": "add new power_intel_uncore testsuite", "version": 1, "mbox": "http://patchwork.dpdk.org/series/28126/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/127195/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/127195/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dts-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 32FBA42B7E;\n\tTue, 23 May 2023 11:12:48 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CF6CA42C54;\n\tTue, 23 May 2023 11:12:47 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 4A18640EE5\n for <dts@dpdk.org>; Tue, 23 May 2023 11:12:45 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 May 2023 02:12:26 -0700", "from silpixa00401183.ir.intel.com ([10.55.129.127])\n by orsmga007.jf.intel.com with ESMTP; 23 May 2023 02:12:25 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1684833165; x=1716369165;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=Vu6271ftM/P8fCR7/FCH1Uo2DY2OUwj10Ud4XAO06oA=;\n b=YTjHodBAZVLJvnJ1CD5RSijDY527KcTeP7Q6Ar5r8zyrWwqdB8QUijFx\n yH4pdhzof97yzz3+i8nbY6jVKOTPtmx8g3K60a004/l+n6kMVD5qgiYGc\n yP6bVDHqeh1XDv9SifCH0OAwbviyAVCwVgJe8O1DKl7HtctP/Z9WhSkLd\n rq5/ISrQAojai5gMVFLEqETFZt/871Xna879N3IGKQ7C2Y3rWlxuXFF7P\n ac2j8glLSk3eq2NwaoHNIHRSkgU02iGwBkmCtp4IevEm63F6Ks3ytV3R6\n RLP12TslNwWeg4d3uTaBYIexsZufxhK8eleAWcskVB/c8kxdobKUydfeW g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10718\"; a=\"439538179\"", "E=Sophos;i=\"6.00,185,1681196400\"; d=\"scan'208\";a=\"439538179\"", "E=McAfee;i=\"6600,9927,10718\"; a=\"697986215\"", "E=Sophos;i=\"6.00,185,1681196400\"; d=\"scan'208\";a=\"697986215\"" ], "X-ExtLoop1": "1", "From": "Tadhg Kearney <tadhg.kearney@intel.com>", "To": "dts@dpdk.org", "Cc": "reshma.pattan@intel.com, karen.kelly@intel.com,\n Tadhg Kearney <tadhg.kearney@intel.com>", "Subject": "[dts][PATCH v1 2/2] test_plans/power_intel_uncore: add test_plan for\n newly added test suite", "Date": "Tue, 23 May 2023 09:12:20 +0000", "Message-Id": "<20230523091220.32474-3-tadhg.kearney@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230523091220.32474-1-tadhg.kearney@intel.com>", "References": "<20230523091220.32474-1-tadhg.kearney@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dts@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "test suite reviews and discussions <dts.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dts>,\n <mailto:dts-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dts/>", "List-Post": "<mailto:dts@dpdk.org>", "List-Help": "<mailto:dts-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dts>,\n <mailto:dts-request@dpdk.org?subject=subscribe>", "Errors-To": "dts-bounces@dpdk.org" }, "content": "Add new test_plan for newly added testsuite power_intel_uncore.\n\nSigned-off-by: Tadhg Kearney <tadhg.kearney@intel.com>\n---\n test_plans/index.rst | 1 +\n test_plans/power_intel_uncore_test_plan.rst | 126 ++++++++++++++++++++\n 2 files changed, 127 insertions(+)\n create mode 100644 test_plans/power_intel_uncore_test_plan.rst", "diff": "diff --git a/test_plans/index.rst b/test_plans/index.rst\nindex 2008f50b..c43ee002 100644\n--- a/test_plans/index.rst\n+++ b/test_plans/index.rst\n@@ -212,6 +212,7 @@ The following are the test plans for the DPDK DTS automated test system.\n power_bidirection_channel_test_plan\n power_branch_ratio_test_plan\n power_empty_poll_test_plan\n+ power_intel_uncore_test_plan\n power_pbf_test_plan\n power_pmd_test_plan\n power_pstate_test_plan\ndiff --git a/test_plans/power_intel_uncore_test_plan.rst b/test_plans/power_intel_uncore_test_plan.rst\nnew file mode 100644\nindex 00000000..aff8051c\n--- /dev/null\n+++ b/test_plans/power_intel_uncore_test_plan.rst\n@@ -0,0 +1,126 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2023 Intel Corporation\n+\n+============================\n+Power Intel Uncore Test Plan\n+============================\n+Uncore is a term used by Intel to describe the functions of a microprocessor that are\n+not in the core, but which must be closely connected to the core to achieve high performance;\n+L3 cache, on-die memory controller, etc.\n+L3fwd-power facilitates setting uncores frequency using DPDK Intel Uncore API.\n+\n+There is a test for each of the three options that are available for setting the uncore frequency,\n+along with one final test to check successful exiting of Uncore API.\n+\n+Uncore is changed per socket level, this test suite is designed to change the uncore value \n+for each socket, however only socket 0 is verified to see if a change has been made.\n+To view changed frequency, using MSR can be done on any core of the socket.\n+See \"Useful MSR 0x620 Information\" section for more information.\n+\n+Preperation work\n+================\n+1. Check kernel version to make sure that it's greater than 5.6\n+ uname -r\n+2. Check if uncore is enabled.\n+ cd /sys/devices/system/cpu/intel_uncore_frequency\n+ if not:\n+ check if kernel flag is enabled\n+ cat /boot/config-$(uname -r) | grep -i \"CONFIG_INTEL_UNCORE_FREQ_CONTROL\"\n+ Otherwise add uncore sysfs driver\n+ modprobe intel-uncore-frequency\n+3. Check if MSR driver is built-in or is loaded\n+ modprobe msr\n+\n+Useful MSR 0x620 Information\n+==========================\n+* MSR 0x620 is a seperate register interface to configure uncore P-state ratio\n+ limits and read back the current set uncore ratio limits.\n+* Bits 0:6 are for max ratio and bits 8:14 for min ratio.\n+* MSR 0x620 value is a ratio value, which means it must be multiplied by the base clock \n+ to get the uncore frequency in KHz. In this example 100000.\n+* When reading MSR 0x620 during this test suite core 0 on socket 0 is only checked\n+ for the uncore max and min ratio limits. When no core is specified for rdmsr,\n+ then it defaults to core 0.\n+\n+Test Case 1: Validate_power_uncore_freq_max\n+===========================================\n+Step 1. Check current max set uncore frequency versus max possible frequency\n+\n+ \"rdmsr 0x620 -f 6:0 -d\" * 100000\n+ cat /sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/initial_max_freq_khz\n+\n+ If these are equal, then change the value of each sysfs file by bringing them down 1 bin (100MHz).\n+\n+ echo {lower_uncore_max} > /sys/devices/system/cpu/intel_uncore_frequency/package_XX_die_XX/max_freq_khz\n+\n+Step 2. Run basic l3fwd-power configuration to set min/max uncore frequency to max limit\n+\n+ ./<build_target>/examples/dpdk-l3fwd-power -c 0x6 -n 1 -- -p 0x1 -P --config=\"(0,0,2)\" -U\n+\n+Step 3. Confirm uncore min/max frequencies are set to max limit\n+\n+ \"rdmsr 0x620 -f 6:0 -d\" * 100000\n+ \"rdmsr 0x620 -f 14:8\" * 100000\n+\n+\n+Test Case 2: Validate_power_uncore_freq_min\n+===========================================\n+\n+Step 1. Check current min set uncore frequency versus min possible frequency\n+\n+ \"rdmsr 0x620 -f 14:8\" * 100000\n+ cat /sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/initial_min_freq_khz\n+\n+ If these are equal, then change the value of each sysfs file by bringing them up 1 bin (100MHz) .\n+\n+ echo {higher_uncore_min} > /sys/devices/system/cpu/intel_uncore_frequency/package_XX_die_XX/min_freq_khz\n+\n+Step 2. Run basic l3fwd-power configuration to set min/max uncore frequency to min limit\n+\n+ ./<build_target>/examples/dpdk-l3fwd-power -c 0x6 -n 1 -- -p 0x1 -P --config=\"(0,0,2)\" -u\n+\n+Step 3. Confirm uncore min/max frequencies are set to min limit\n+\n+ \"rdmsr 0x620 -f 14:8\" * 100000\n+ \"rdmsr 0x620 -f 6:0 -d\" * 100000\n+\n+\n+Test Case 3: Validate_power_uncore_freq_idx\n+===========================================\n+\n+Step 1. Check current max uncore frequency versus index 2.\n+ Index 2 is equal to the frequency at index 2.\n+ This is equal to => max possible freq - 200000(2 bin (200MHz)).\n+ For example index range is [2400000, 2300000, 2200000,......,900000,800000], index 2 is 2200000.\n+\n+ \"rdmsr 0x620 -f 6:0 -d\" * 100000\n+ (cat /sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/initial_max_freq_khz) - 200000\n+\n+ If these are equal, then change the value of each sysfs file by bringing them up 1 bin (100MHz).\n+\n+ echo {higher_uncore_idx} > /sys/devices/system/cpu/intel_uncore_frequency/package_XX_die_XX/max_freq_khz\n+\n+Step 2. Run basic l3fwd-power configuration to set min/max uncore frequency to index value\n+\n+ ./<build_target>/examples/dpdk-l3fwd-power -c 0x6 -n 1 -- -p 0x1 -P --config=\"(0,0,2)\" -i 2\n+\n+Step 3. Confirm uncore min/max frequencies are set to index value\n+\n+ \"rdmsr 0x620 -f 6:0 -d\" * 100000\n+ \"rdmsr 0x620 -f 14:8\" * 100000\n+\n+\n+Test Case 4: Validate_power_uncore_exit\n+=======================================\n+\n+Step 1. Run basic l3fwd-power configuration. Doesn't matter just want to get l3fwd-power running\n+\n+ ./<build_target>/examples/dpdk-l3fwd-power -c 0x6 -n 1 -- -p 0x1 -P --config=\"(0,0,2)\" -U\n+\n+Step 2. Exit program and ensure there are no errors/ right output is recieved\n+\n+ Ctrl-C\n+ Check for line \"mode and been set back to the original\"\n+ Which should be the last line the program outputs when exiting correctly.\n+ The start of the line is omitted as it won't be known which mode/which lcore will be set\n+ back to the original.\n", "prefixes": [ "v1", "2/2" ] }