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GET /api/patches/128535/?format=api
{ "id": 128535, "url": "http://patchwork.dpdk.org/api/patches/128535/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230613071614.2259604-2-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230613071614.2259604-2-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230613071614.2259604-2-gakhil@marvell.com", "date": "2023-06-13T07:16:00", "name": "[v3,01/15] common/cnxk: add ROC MACsec initialization", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "42e4aedbec112a1a6a60fa427ce4ee384e2f0c19", "submitter": { "id": 2094, "url": "http://patchwork.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230613071614.2259604-2-gakhil@marvell.com/mbox/", "series": [ { "id": 28472, "url": "http://patchwork.dpdk.org/api/series/28472/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28472", "date": "2023-06-13T07:15:59", "name": "net/cnxk: add MACsec support", "version": 3, "mbox": "http://patchwork.dpdk.org/series/28472/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/128535/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/128535/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2171042CA0;\n\tTue, 13 Jun 2023 09:16:41 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2225A4161A;\n\tTue, 13 Jun 2023 09:16:38 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 3192441149\n for <dev@dpdk.org>; Tue, 13 Jun 2023 09:16:37 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 35D56EGe005611; Tue, 13 Jun 2023 00:16:36 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r650235dd-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 13 Jun 2023 00:16:35 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 13 Jun 2023 00:16:34 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 13 Jun 2023 00:16:34 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id D435C5E6861;\n Tue, 13 Jun 2023 00:16:31 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=T9DEFMci5ixUOmIFDkC/CslVZz8sBxmzvjXU6uHynvQ=;\n b=Ik/xmYzPdlEAR7HKQCFBbQC3rUuKnkmANVM2+znVFhJkJ0PTSWLNGgJoc+FU3hTwt+UD\n 57i9goBhSkmJLr2/1NXETAEtrFm4+++KZdafgLbjCKbYnEYSxPp6/odGuoMpvRkqiMOc\n EGFKJwqdFdgYjezzPNucWyc9ezDe+O8LF4EULRiMSyYnISjM6rQFKEYksjfEHqEm8XGi\n H7/6D6yOyEOzTWzwruDIrqHbla+p9x3wY6Tw3LRC+DvhpyoHhDfTWV36+dzEbRmMJfmE\n Fkh2qNkc5YfPS7GIjvv1ftXz++2XKG6hesJjL8uKPe+fymM0C2yhV8rnu8f2104dElGD dQ==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <vattunuru@marvell.com>, <jerinj@marvell.com>, <adwivedi@marvell.com>,\n <ndabilpuram@marvell.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH v3 01/15] common/cnxk: add ROC MACsec initialization", "Date": "Tue, 13 Jun 2023 12:46:00 +0530", "Message-ID": "<20230613071614.2259604-2-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230613071614.2259604-1-gakhil@marvell.com>", "References": "<20230607152819.226838-1-gakhil@marvell.com>\n <20230613071614.2259604-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "LRZj-NqUeOJ4Ci0j2aIJBlGqyhYMYf4z", "X-Proofpoint-GUID": "LRZj-NqUeOJ4Ci0j2aIJBlGqyhYMYf4z", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-06-13_04,2023-06-12_02,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added ROC init and fini APIs for supporting MACsec.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_features.h | 12 ++\n drivers/common/cnxk/roc_idev.c | 46 ++++++\n drivers/common/cnxk/roc_idev.h | 3 +\n drivers/common/cnxk/roc_idev_priv.h | 1 +\n drivers/common/cnxk/roc_mbox.h | 65 +++++++-\n drivers/common/cnxk/roc_mcs.c | 220 ++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_mcs.h | 41 ++++++\n drivers/common/cnxk/roc_mcs_priv.h | 65 ++++++++\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/roc_utils.c | 5 +\n drivers/common/cnxk/version.map | 7 +\n 13 files changed, 471 insertions(+), 1 deletion(-)\n create mode 100644 drivers/common/cnxk/roc_mcs.c\n create mode 100644 drivers/common/cnxk/roc_mcs.h\n create mode 100644 drivers/common/cnxk/roc_mcs_priv.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 631b594f32..e33c002676 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -26,6 +26,7 @@ sources = files(\n 'roc_irq.c',\n 'roc_ie_ot.c',\n 'roc_mbox.c',\n+ 'roc_mcs.c',\n 'roc_ml.c',\n 'roc_model.c',\n 'roc_nix.c',\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex bbc94ab48e..f630853088 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -114,4 +114,7 @@\n /* ML */\n #include \"roc_ml.h\"\n \n+/* MACsec */\n+#include \"roc_mcs.h\"\n+\n #endif /* _ROC_API_H_ */\ndiff --git a/drivers/common/cnxk/roc_features.h b/drivers/common/cnxk/roc_features.h\nindex 36ef315f5a..815f800e7a 100644\n--- a/drivers/common/cnxk/roc_features.h\n+++ b/drivers/common/cnxk/roc_features.h\n@@ -59,4 +59,16 @@ roc_feature_nix_has_age_drop_stats(void)\n {\n \treturn (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());\n }\n+\n+static inline bool\n+roc_feature_nix_has_macsec(void)\n+{\n+\treturn roc_model_is_cn10kb();\n+}\n+\n+static inline bool\n+roc_feature_bphy_has_macsec(void)\n+{\n+\treturn roc_model_is_cnf10kb();\n+}\n #endif\ndiff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c\nindex f420f0158d..e6c6b34d78 100644\n--- a/drivers/common/cnxk/roc_idev.c\n+++ b/drivers/common/cnxk/roc_idev.c\n@@ -38,6 +38,7 @@ idev_set_defaults(struct idev_cfg *idev)\n \tidev->num_lmtlines = 0;\n \tidev->bphy = NULL;\n \tidev->cpt = NULL;\n+\tTAILQ_INIT(&idev->mcs_list);\n \tidev->nix_inl_dev = NULL;\n \tTAILQ_INIT(&idev->roc_nix_list);\n \tplt_spinlock_init(&idev->nix_inl_dev_lock);\n@@ -187,6 +188,51 @@ roc_idev_cpt_get(void)\n \treturn NULL;\n }\n \n+struct roc_mcs *\n+roc_idev_mcs_get(uint8_t mcs_idx)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct roc_mcs *mcs = NULL;\n+\n+\tif (idev != NULL) {\n+\t\tTAILQ_FOREACH(mcs, &idev->mcs_list, next) {\n+\t\t\tif (mcs->idx == mcs_idx)\n+\t\t\t\treturn mcs;\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+void\n+roc_idev_mcs_set(struct roc_mcs *mcs)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct roc_mcs *mcs_iter = NULL;\n+\n+\tif (idev != NULL) {\n+\t\tTAILQ_FOREACH(mcs_iter, &idev->mcs_list, next) {\n+\t\t\tif (mcs_iter->idx == mcs->idx)\n+\t\t\t\treturn;\n+\t\t}\n+\t\tTAILQ_INSERT_TAIL(&idev->mcs_list, mcs, next);\n+\t}\n+}\n+\n+void\n+roc_idev_mcs_free(struct roc_mcs *mcs)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct roc_mcs *mcs_iter = NULL;\n+\n+\tif (idev != NULL) {\n+\t\tTAILQ_FOREACH(mcs_iter, &idev->mcs_list, next) {\n+\t\t\tif (mcs_iter->idx == mcs->idx)\n+\t\t\t\tTAILQ_REMOVE(&idev->mcs_list, mcs, next);\n+\t\t}\n+\t}\n+}\n+\n uint64_t *\n roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix)\n {\ndiff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h\nindex 640ca97708..aea7f5279d 100644\n--- a/drivers/common/cnxk/roc_idev.h\n+++ b/drivers/common/cnxk/roc_idev.h\n@@ -19,4 +19,7 @@ struct roc_nix *__roc_api roc_idev_npa_nix_get(void);\n uint64_t __roc_api roc_idev_nix_inl_meta_aura_get(void);\n struct roc_nix_list *__roc_api roc_idev_nix_list_get(void);\n \n+struct roc_mcs *__roc_api roc_idev_mcs_get(uint8_t mcs_idx);\n+void __roc_api roc_idev_mcs_set(struct roc_mcs *mcs);\n+void __roc_api roc_idev_mcs_free(struct roc_mcs *mcs);\n #endif /* _ROC_IDEV_H_ */\ndiff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h\nindex 4983578fc6..80f8465e1c 100644\n--- a/drivers/common/cnxk/roc_idev_priv.h\n+++ b/drivers/common/cnxk/roc_idev_priv.h\n@@ -31,6 +31,7 @@ struct idev_cfg {\n \tstruct roc_bphy *bphy;\n \tstruct roc_cpt *cpt;\n \tstruct roc_sso *sso;\n+\tstruct roc_mcs_head mcs_list;\n \tstruct nix_inl_dev *nix_inl_dev;\n \tstruct idev_nix_inl_cfg inl_cfg;\n \tstruct roc_nix_list roc_nix_list;\ndiff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex 93c5451c0f..ef7a7d6513 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -295,7 +295,12 @@ struct mbox_msghdr {\n \t nix_bpids) \\\n \tM(NIX_FREE_BPIDS, 0x8029, nix_free_bpids, nix_bpids, msg_rsp) \\\n \tM(NIX_RX_CHAN_CFG, 0x802a, nix_rx_chan_cfg, nix_rx_chan_cfg, \\\n-\t nix_rx_chan_cfg)\n+\t nix_rx_chan_cfg) \\\n+\t/* MCS mbox IDs (range 0xa000 - 0xbFFF) */ \\\n+\tM(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \\\n+\t mcs_alloc_rsrc_rsp) \\\n+\tM(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \\\n+\tM(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \\\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n #define MBOX_UP_CGX_MESSAGES \\\n@@ -673,6 +678,64 @@ struct cgx_set_link_mode_rsp {\n \tint __io status;\n };\n \n+/* MCS mbox structures */\n+enum mcs_direction {\n+\tMCS_RX,\n+\tMCS_TX,\n+};\n+\n+enum mcs_rsrc_type {\n+\tMCS_RSRC_TYPE_FLOWID,\n+\tMCS_RSRC_TYPE_SECY,\n+\tMCS_RSRC_TYPE_SC,\n+\tMCS_RSRC_TYPE_SA,\n+};\n+\n+struct mcs_alloc_rsrc_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rsrc_type;\n+\tuint8_t __io rsrc_cnt; /* Resources count */\n+\tuint8_t __io mcs_id; /* MCS block ID */\n+\tuint8_t __io dir; /* Macsec ingress or egress side */\n+\tuint8_t __io all; /* Allocate all resource type one each */\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_alloc_rsrc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io flow_ids[128]; /* Index of reserved entries */\n+\tuint8_t __io secy_ids[128];\n+\tuint8_t __io sc_ids[128];\n+\tuint8_t __io sa_ids[256];\n+\tuint8_t __io rsrc_type;\n+\tuint8_t __io rsrc_cnt; /* No of entries reserved */\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint8_t __io all;\n+\tuint8_t __io rsvd[256];\n+};\n+\n+struct mcs_free_rsrc_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rsrc_id; /* Index of the entry to be freed */\n+\tuint8_t __io rsrc_type;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint8_t __io all; /* Free all the cam resources */\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_hw_info {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io num_mcs_blks; /* Number of MCS blocks */\n+\tuint8_t __io tcam_entries; /* RX/TX Tcam entries per mcs block */\n+\tuint8_t __io secy_entries; /* RX/TX SECY entries per mcs block */\n+\tuint8_t __io sc_entries; /* RX/TX SC CAM entries per mcs block */\n+\tuint16_t __io sa_entries; /* PN table entries = SA entries */\n+\tuint64_t __io rsvd[16];\n+};\n+\n+\n /* NPA mbox message formats */\n \n /* NPA mailbox error codes\ndiff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c\nnew file mode 100644\nindex 0000000000..20433eae83\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mcs.c\n@@ -0,0 +1,220 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+int\n+roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info)\n+{\n+\tstruct mcs_hw_info *hw;\n+\tstruct npa_lf *npa;\n+\tint rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (hw_info == NULL)\n+\t\treturn -EINVAL;\n+\n+\t/* Use mbox handler of first probed pci_func for\n+\t * initial mcs mbox communication.\n+\t */\n+\tnpa = idev_npa_obj_get();\n+\tif (!npa)\n+\t\treturn MCS_ERR_DEVICE_NOT_FOUND;\n+\n+\tmbox_alloc_msg_mcs_get_hw_info(npa->mbox);\n+\trc = mbox_process_msg(npa->mbox, (void *)&hw);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\thw_info->num_mcs_blks = hw->num_mcs_blks;\n+\thw_info->tcam_entries = hw->tcam_entries;\n+\thw_info->secy_entries = hw->secy_entries;\n+\thw_info->sc_entries = hw->sc_entries;\n+\thw_info->sa_entries = hw->sa_entries;\n+\n+\treturn rc;\n+}\n+\n+static int\n+mcs_alloc_bmap(uint16_t entries, void **mem, struct plt_bitmap **bmap)\n+{\n+\tsize_t bmap_sz;\n+\tint rc = 0;\n+\n+\tbmap_sz = plt_bitmap_get_memory_footprint(entries);\n+\t*mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);\n+\tif (*mem == NULL)\n+\t\trc = -ENOMEM;\n+\n+\t*bmap = plt_bitmap_init(entries, *mem, bmap_sz);\n+\tif (!*bmap) {\n+\t\tplt_free(*mem);\n+\t\t*mem = NULL;\n+\t\trc = -ENOMEM;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static void\n+rsrc_bmap_free(struct mcs_rsrc *rsrc)\n+{\n+\tplt_bitmap_free(rsrc->tcam_bmap);\n+\tplt_free(rsrc->tcam_bmap_mem);\n+\tplt_bitmap_free(rsrc->secy_bmap);\n+\tplt_free(rsrc->secy_bmap_mem);\n+\tplt_bitmap_free(rsrc->sc_bmap);\n+\tplt_free(rsrc->sc_bmap_mem);\n+\tplt_bitmap_free(rsrc->sa_bmap);\n+\tplt_free(rsrc->sa_bmap_mem);\n+}\n+\n+static int\n+rsrc_bmap_alloc(struct mcs_priv *priv, struct mcs_rsrc *rsrc)\n+{\n+\tint rc;\n+\n+\trc = mcs_alloc_bmap(priv->tcam_entries << 1, &rsrc->tcam_bmap_mem, &rsrc->tcam_bmap);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\trc = mcs_alloc_bmap(priv->secy_entries << 1, &rsrc->secy_bmap_mem, &rsrc->secy_bmap);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\trc = mcs_alloc_bmap(priv->sc_entries << 1, &rsrc->sc_bmap_mem, &rsrc->sc_bmap);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\trc = mcs_alloc_bmap(priv->sa_entries << 1, &rsrc->sa_bmap_mem, &rsrc->sa_bmap);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\treturn rc;\n+exit:\n+\trsrc_bmap_free(rsrc);\n+\n+\treturn rc;\n+}\n+\n+static int\n+mcs_alloc_rsrc_bmap(struct roc_mcs *mcs)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct mcs_hw_info *hw;\n+\tint i, rc;\n+\n+\tmbox_alloc_msg_mcs_get_hw_info(mcs->mbox);\n+\trc = mbox_process_msg(mcs->mbox, (void *)&hw);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tpriv->num_mcs_blks = hw->num_mcs_blks;\n+\tpriv->tcam_entries = hw->tcam_entries;\n+\tpriv->secy_entries = hw->secy_entries;\n+\tpriv->sc_entries = hw->sc_entries;\n+\tpriv->sa_entries = hw->sa_entries;\n+\n+\trc = rsrc_bmap_alloc(priv, &priv->dev_rsrc);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tpriv->port_rsrc = plt_zmalloc(sizeof(struct mcs_rsrc) * 4, 0);\n+\tif (priv->port_rsrc == NULL) {\n+\t\trsrc_bmap_free(&priv->dev_rsrc);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tfor (i = 0; i < MAX_PORTS_PER_MCS; i++) {\n+\t\trc = rsrc_bmap_alloc(priv, &priv->port_rsrc[i]);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\n+\t\tpriv->port_rsrc[i].sc_conf =\n+\t\t\tplt_zmalloc(priv->sc_entries * sizeof(struct mcs_sc_conf), 0);\n+\t\tif (priv->port_rsrc[i].sc_conf == NULL) {\n+\t\t\trsrc_bmap_free(&priv->port_rsrc[i]);\n+\t\t\tgoto exit;\n+\t\t}\n+\t}\n+\n+\treturn rc;\n+\n+exit:\n+\twhile (i--) {\n+\t\trsrc_bmap_free(&priv->port_rsrc[i]);\n+\t\tplt_free(priv->port_rsrc[i].sc_conf);\n+\t}\n+\tplt_free(priv->port_rsrc);\n+\n+\treturn -ENOMEM;\n+}\n+\n+struct roc_mcs *\n+roc_mcs_dev_init(uint8_t mcs_idx)\n+{\n+\tstruct roc_mcs *mcs;\n+\tstruct npa_lf *npa;\n+\n+\tif (!(roc_feature_bphy_has_macsec() || roc_feature_nix_has_macsec()))\n+\t\treturn NULL;\n+\n+\tmcs = roc_idev_mcs_get(mcs_idx);\n+\tif (mcs) {\n+\t\tplt_info(\"Skipping device, mcs device already probed\");\n+\t\tmcs->refcount++;\n+\t\treturn mcs;\n+\t}\n+\n+\tmcs = plt_zmalloc(sizeof(struct roc_mcs), PLT_CACHE_LINE_SIZE);\n+\tif (!mcs)\n+\t\treturn NULL;\n+\n+\tnpa = idev_npa_obj_get();\n+\tif (!npa)\n+\t\tgoto exit;\n+\n+\tmcs->mbox = npa->mbox;\n+\tmcs->idx = mcs_idx;\n+\n+\t/* Add any per mcsv initialization */\n+\tif (mcs_alloc_rsrc_bmap(mcs))\n+\t\tgoto exit;\n+\n+\troc_idev_mcs_set(mcs);\n+\tmcs->refcount++;\n+\n+\treturn mcs;\n+exit:\n+\tplt_free(mcs);\n+\treturn NULL;\n+}\n+\n+void\n+roc_mcs_dev_fini(struct roc_mcs *mcs)\n+{\n+\tstruct mcs_priv *priv;\n+\tint i;\n+\n+\tmcs->refcount--;\n+\tif (mcs->refcount > 0)\n+\t\treturn;\n+\n+\tpriv = roc_mcs_to_mcs_priv(mcs);\n+\n+\trsrc_bmap_free(&priv->dev_rsrc);\n+\n+\tfor (i = 0; i < MAX_PORTS_PER_MCS; i++) {\n+\t\trsrc_bmap_free(&priv->port_rsrc[i]);\n+\t\tplt_free(priv->port_rsrc[i].sc_conf);\n+\t}\n+\n+\tplt_free(priv->port_rsrc);\n+\n+\troc_idev_mcs_free(mcs);\n+\n+\tplt_free(mcs);\n+}\ndiff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h\nnew file mode 100644\nindex 0000000000..2f06ce2659\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mcs.h\n@@ -0,0 +1,41 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Marvell.\n+ */\n+\n+#ifndef _ROC_MCS_H_\n+#define _ROC_MCS_H_\n+\n+#define MCS_AES_GCM_256_KEYLEN 32\n+\n+struct roc_mcs_hw_info {\n+\tuint8_t num_mcs_blks; /* Number of MCS blocks */\n+\tuint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */\n+\tuint8_t secy_entries; /* RX/TX SECY entries per mcs block */\n+\tuint8_t sc_entries; /* RX/TX SC CAM entries per mcs block */\n+\tuint16_t sa_entries; /* PN table entries = SA entries */\n+\tuint64_t rsvd[16];\n+};\n+\n+\n+struct roc_mcs {\n+\tTAILQ_ENTRY(roc_mcs) next;\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct mbox *mbox;\n+\tvoid *userdata;\n+\tuint8_t idx;\n+\tuint8_t refcount;\n+\n+#define ROC_MCS_MEM_SZ (1 * 1024)\n+\tuint8_t reserved[ROC_MCS_MEM_SZ] __plt_cache_aligned;\n+} __plt_cache_aligned;\n+\n+TAILQ_HEAD(roc_mcs_head, roc_mcs);\n+\n+/* Initialization */\n+__roc_api struct roc_mcs *roc_mcs_dev_init(uint8_t mcs_idx);\n+__roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs);\n+/* Get roc mcs dev structure */\n+__roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx);\n+/* HW info get */\n+__roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info);\n+#endif /* _ROC_MCS_H_ */\ndiff --git a/drivers/common/cnxk/roc_mcs_priv.h b/drivers/common/cnxk/roc_mcs_priv.h\nnew file mode 100644\nindex 0000000000..9e0bbe4392\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mcs_priv.h\n@@ -0,0 +1,65 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Marvell.\n+ */\n+\n+#ifndef _ROC_MCS_PRIV_H_\n+#define _ROC_MCS_PRIV_H_\n+\n+#define MAX_PORTS_PER_MCS 4\n+\n+enum mcs_error_status {\n+\tMCS_ERR_PARAM = -900,\n+\tMCS_ERR_HW_NOTSUP = -901,\n+\tMCS_ERR_DEVICE_NOT_FOUND = -902,\n+};\n+\n+#define MCS_SUPPORT_CHECK \\\n+\tdo { \\\n+\t\tif (!(roc_feature_bphy_has_macsec() || roc_feature_nix_has_macsec())) \\\n+\t\t\treturn MCS_ERR_HW_NOTSUP; \\\n+\t} while (0)\n+\n+struct mcs_sc_conf {\n+\tstruct {\n+\t\tuint64_t sci;\n+\t\tuint16_t sa_idx0;\n+\t\tuint16_t sa_idx1;\n+\t\tuint8_t rekey_enb;\n+\t} tx;\n+\tstruct {\n+\t\tuint16_t sa_idx;\n+\t\tuint8_t an;\n+\t} rx;\n+};\n+\n+struct mcs_rsrc {\n+\tstruct plt_bitmap *tcam_bmap;\n+\tvoid *tcam_bmap_mem;\n+\tstruct plt_bitmap *secy_bmap;\n+\tvoid *secy_bmap_mem;\n+\tstruct plt_bitmap *sc_bmap;\n+\tvoid *sc_bmap_mem;\n+\tstruct plt_bitmap *sa_bmap;\n+\tvoid *sa_bmap_mem;\n+\tstruct mcs_sc_conf *sc_conf;\n+};\n+\n+struct mcs_priv {\n+\tstruct mcs_rsrc *port_rsrc;\n+\tstruct mcs_rsrc dev_rsrc;\n+\tuint64_t default_sci;\n+\tuint32_t lmac_bmap;\n+\tuint8_t num_mcs_blks;\n+\tuint8_t tcam_entries;\n+\tuint8_t secy_entries;\n+\tuint8_t sc_entries;\n+\tuint16_t sa_entries;\n+};\n+\n+static inline struct mcs_priv *\n+roc_mcs_to_mcs_priv(struct roc_mcs *roc_mcs)\n+{\n+\treturn (struct mcs_priv *)&roc_mcs->reserved[0];\n+}\n+\n+#endif /* _ROC_MCS_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex 14fe2e452a..254a2d3310 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -44,6 +44,9 @@\n /* DPI */\n #include \"roc_dpi_priv.h\"\n \n+/* MCS */\n+#include \"roc_mcs_priv.h\"\n+\n /* REE */\n #include \"roc_ree_priv.h\"\n \ndiff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c\nindex fe291fce96..9af2ae9b69 100644\n--- a/drivers/common/cnxk/roc_utils.c\n+++ b/drivers/common/cnxk/roc_utils.c\n@@ -16,6 +16,7 @@ roc_error_msg_get(int errorcode)\n \tcase NPA_ERR_PARAM:\n \tcase NPC_ERR_PARAM:\n \tcase SSO_ERR_PARAM:\n+\tcase MCS_ERR_PARAM:\n \tcase UTIL_ERR_PARAM:\n \t\terr_msg = \"Invalid parameter\";\n \t\tbreak;\n@@ -35,6 +36,7 @@ roc_error_msg_get(int errorcode)\n \t\terr_msg = \"Operation not supported\";\n \t\tbreak;\n \tcase NIX_ERR_HW_NOTSUP:\n+\tcase MCS_ERR_HW_NOTSUP:\n \t\terr_msg = \"Hardware does not support\";\n \t\tbreak;\n \tcase NIX_ERR_QUEUE_INVALID_RANGE:\n@@ -223,6 +225,9 @@ roc_error_msg_get(int errorcode)\n \tcase SSO_ERR_DEVICE_NOT_BOUNDED:\n \t\terr_msg = \"SSO pf/vf not found\";\n \t\tbreak;\n+\tcase MCS_ERR_DEVICE_NOT_FOUND:\n+\t\terr_msg = \"MCS device not found\";\n+\t\tbreak;\n \tcase UTIL_ERR_FS:\n \t\terr_msg = \"file operation failed\";\n \t\tbreak;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex e1335e9068..900290b866 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -94,6 +94,9 @@ INTERNAL {\n \troc_idev_cpt_get;\n \troc_idev_cpt_set;\n \troc_idev_lmt_base_addr_get;\n+\troc_idev_mcs_free;\n+\troc_idev_mcs_get;\n+\troc_idev_mcs_set;\n \troc_idev_npa_maxpools_get;\n \troc_idev_npa_maxpools_set;\n \troc_idev_npa_nix_get;\n@@ -132,6 +135,10 @@ INTERNAL {\n \troc_se_auth_key_set;\n \troc_se_ciph_key_set;\n \troc_se_ctx_init;\n+\troc_mcs_dev_init;\n+\troc_mcs_dev_fini;\n+\troc_mcs_dev_get;\n+\troc_mcs_hw_info_get;\n \troc_nix_bpf_alloc;\n \troc_nix_bpf_config;\n \troc_nix_bpf_connect;\n", "prefixes": [ "v3", "01/15" ] }