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GET /api/patches/128796/?format=api
{ "id": 128796, "url": "http://patchwork.dpdk.org/api/patches/128796/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230619124941.3967346-2-ktejasree@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230619124941.3967346-2-ktejasree@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230619124941.3967346-2-ktejasree@marvell.com", "date": "2023-06-19T12:49:40", "name": "[7/8] crypto/cnxk: add support for sm4", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7d117b12b31165c17de4c042a35b656c4fc9f8a6", "submitter": { "id": 1789, "url": "http://patchwork.dpdk.org/api/people/1789/?format=api", "name": "Tejasree Kondoj", "email": "ktejasree@marvell.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230619124941.3967346-2-ktejasree@marvell.com/mbox/", "series": [ { "id": 28566, "url": "http://patchwork.dpdk.org/api/series/28566/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28566", "date": "2023-06-19T12:45:20", "name": "fixes and improvements to CNXK crypto PMD", "version": 1, "mbox": "http://patchwork.dpdk.org/series/28566/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/128796/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/128796/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 644CC42CFA;\n\tMon, 19 Jun 2023 14:49:55 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E0E42410F6;\n\tMon, 19 Jun 2023 14:49:52 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id A491040DF8\n for <dev@dpdk.org>; Mon, 19 Jun 2023 14:49:50 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 35JBcNp4017112 for <dev@dpdk.org>; Mon, 19 Jun 2023 05:49:49 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r9a6n5hxf-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 19 Jun 2023 05:49:49 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Mon, 19 Jun 2023 05:49:48 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Mon, 19 Jun 2023 05:49:47 -0700", "from hyd1554.marvell.com (unknown [10.29.57.11])\n by maili.marvell.com (Postfix) with ESMTP id 00F3E5C68EC;\n Mon, 19 Jun 2023 05:49:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=r2cKLCgS5M1wIALVx/NUag4yRRHUA5jq8H5ccV5fNR4=;\n b=MNZKhTMFrYoUS8F0tyvzRPxE+iPfSB8Idegb+Sjrt8gzrmAkk3k2SO1ddYd8HkzLmtRL\n DYjC6pAxyEnN5hNTjSDcplNfixd0O8bmwEkBMOyM7jaXx5MsepqrTkDiBZI5g0kBpiA1\n bxudAg/K3XSmWFaUzpfBqpNu4JssoqKjprFaGeqTaNbMGgTXB8ZMwpLWGchdEQRo+btb\n i/pGhRj8/G3UyLT2ic3J4PKo4wQ7gtMuGrCUSqvyYTKdkTveE2e46kIq41IAjz5N1hPe\n 5fQQ7EEtYqrHQiPdSrBWHiBfQmhPDHbRkMuvHo61XmipIw8BXLFoRyXnm9KOqnQgC891 iQ==", "From": "Tejasree Kondoj <ktejasree@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>", "CC": "Vidya Sagar Velumuri <vvelumuri@marvell.com>, Anoob Joseph\n <anoobj@marvell.com>, Aakash Sasidharan <asasidharan@marvell.com>,\n Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 7/8] crypto/cnxk: add support for sm4", "Date": "Mon, 19 Jun 2023 18:19:40 +0530", "Message-ID": "<20230619124941.3967346-2-ktejasree@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230619124941.3967346-1-ktejasree@marvell.com>", "References": "<20230619124941.3967346-1-ktejasree@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "f7i2OEDai1XhnBhDQdACKZR6T2Px3MoU", "X-Proofpoint-GUID": "f7i2OEDai1XhnBhDQdACKZR6T2Px3MoU", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26\n definitions=2023-06-19_09,2023-06-16_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n\nAdd support for SM4 cipher\nSupport for modes: SM4_CBC, SM4_ECB, SM4_CTR, SM4_OFB, SM4_CFB\n\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n---\n doc/guides/cryptodevs/cnxk.rst | 1 +\n doc/guides/cryptodevs/features/cn10k.ini | 1 +\n drivers/common/cnxk/hw/cpt.h | 5 +-\n drivers/common/cnxk/roc_se.c | 3 +\n drivers/common/cnxk/roc_se.h | 20 ++\n drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +-\n .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 113 ++++++-\n drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 5 +-\n drivers/crypto/cnxk/cnxk_se.h | 278 +++++++++++++++++-\n 9 files changed, 421 insertions(+), 7 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/cnxk.rst b/doc/guides/cryptodevs/cnxk.rst\nindex 777e8ffb0e..fbe67475be 100644\n--- a/doc/guides/cryptodevs/cnxk.rst\n+++ b/doc/guides/cryptodevs/cnxk.rst\n@@ -41,6 +41,7 @@ Cipher algorithms:\n * ``RTE_CRYPTO_CIPHER_KASUMI_F8``\n * ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``\n * ``RTE_CRYPTO_CIPHER_ZUC_EEA3``\n+* ``RTE_CRYPTO_CIPHER_SM4``\n \n Hash algorithms:\n \ndiff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini\nindex d8844b5c83..7e34e2f870 100644\n--- a/doc/guides/cryptodevs/features/cn10k.ini\n+++ b/doc/guides/cryptodevs/features/cn10k.ini\n@@ -38,6 +38,7 @@ DES CBC = Y\n KASUMI F8 = Y\n SNOW3G UEA2 = Y\n ZUC EEA3 = Y\n+SM4 = Y\n \n ;\n ; Supported authentication algorithms of 'cn10k' crypto driver.\ndiff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h\nindex 82ea076e4c..5e1519e202 100644\n--- a/drivers/common/cnxk/hw/cpt.h\n+++ b/drivers/common/cnxk/hw/cpt.h\n@@ -73,7 +73,10 @@ union cpt_eng_caps {\n \t\tuint64_t __io des : 1;\n \t\tuint64_t __io crc : 1;\n \t\tuint64_t __io mmul : 1;\n-\t\tuint64_t __io reserved_15_33 : 19;\n+\t\tuint64_t __io reserved_15_20 : 6;\n+\t\tuint64_t __io sm3 : 1;\n+\t\tuint64_t __io sm4 : 1;\n+\t\tuint64_t __io reserved_23_33 : 11;\n \t\tuint64_t __io pdcp_chain : 1;\n \t\tuint64_t __io sg_ver2 : 1;\n \t\tuint64_t __io reserved_36_63 : 28;\ndiff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c\nindex f9b6936267..2662297315 100644\n--- a/drivers/common/cnxk/roc_se.c\n+++ b/drivers/common/cnxk/roc_se.c\n@@ -757,6 +757,9 @@ roc_se_ctx_init(struct roc_se_ctx *roc_se_ctx)\n \tcase ROC_SE_PDCP_CHAIN:\n \t\tctx_len = sizeof(struct roc_se_zuc_snow3g_chain_ctx);\n \t\tbreak;\n+\tcase ROC_SE_SM:\n+\t\tctx_len = sizeof(struct roc_se_sm_context);\n+\t\tbreak;\n \tdefault:\n \t\tctx_len = 0;\n \t}\ndiff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h\nindex 1e7abecf8f..008ab31912 100644\n--- a/drivers/common/cnxk/roc_se.h\n+++ b/drivers/common/cnxk/roc_se.h\n@@ -17,6 +17,7 @@\n #define ROC_SE_MAJOR_OP_PDCP\t 0x37\n #define ROC_SE_MAJOR_OP_KASUMI\t 0x38\n #define ROC_SE_MAJOR_OP_PDCP_CHAIN 0x3C\n+#define ROC_SE_MAJOR_OP_SM\t 0x3D\n \n #define ROC_SE_MAJOR_OP_MISC\t\t 0x01ULL\n #define ROC_SE_MISC_MINOR_OP_PASSTHROUGH 0x03ULL\n@@ -28,6 +29,8 @@\n \n #define ROC_SE_OFF_CTRL_LEN 8\n \n+#define ROC_SE_SM4_KEY_LEN 16\n+\n #define ROC_SE_ZS_EA 0x1\n #define ROC_SE_ZS_IA 0x2\n #define ROC_SE_K_F8 0x4\n@@ -38,6 +41,7 @@\n #define ROC_SE_KASUMI\t 0x3\n #define ROC_SE_HASH_HMAC 0x4\n #define ROC_SE_PDCP_CHAIN 0x5\n+#define ROC_SE_SM\t 0x6\n \n #define ROC_SE_OP_CIPHER_ENCRYPT 0x1\n #define ROC_SE_OP_CIPHER_DECRYPT 0x2\n@@ -125,6 +129,14 @@ typedef enum {\n \tROC_SE_DES_DOCSISBPI = 0x96,\n } roc_se_cipher_type;\n \n+typedef enum {\n+\tROC_SM4_ECB = 0x0,\n+\tROC_SM4_CBC = 0x1,\n+\tROC_SM4_CTR = 0x2,\n+\tROC_SM4_CFB = 0x3,\n+\tROC_SM4_OFB = 0x4,\n+} roc_sm_cipher_type;\n+\n typedef enum {\n \t/* Microcode errors */\n \tROC_SE_NO_ERR = 0x00,\n@@ -192,6 +204,13 @@ struct roc_se_context {\n \tstruct roc_se_hmac_context hmac;\n };\n \n+struct roc_se_sm_context {\n+\tuint64_t rsvd_56_60 : 5;\n+\tuint64_t enc_cipher : 3;\n+\tuint64_t rsvd_0_55 : 56;\n+\tuint8_t encr_key[16];\n+};\n+\n struct roc_se_otk_zuc_ctx {\n \tunion {\n \t\tuint64_t u64;\n@@ -325,6 +344,7 @@ struct roc_se_ctx {\n \t\t\tstruct roc_se_zuc_snow3g_ctx zs_ctx;\n \t\t\tstruct roc_se_zuc_snow3g_chain_ctx zs_ch_ctx;\n \t\t\tstruct roc_se_kasumi_ctx k_ctx;\n+\t\t\tstruct roc_se_sm_context sm_ctx;\n \t\t};\n \t} se_ctx __plt_aligned(ROC_ALIGN);\n \tuint8_t *auth_key;\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h\nindex ce45f5d01b..09f5ba0650 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev.h\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev.h\n@@ -10,7 +10,7 @@\n \n #include \"roc_cpt.h\"\n \n-#define CNXK_CPT_MAX_CAPS\t 49\n+#define CNXK_CPT_MAX_CAPS\t 54\n #define CNXK_SEC_CRYPTO_MAX_CAPS 16\n #define CNXK_SEC_MAX_CAPS\t 9\n #define CNXK_AE_EC_ID_MAX\t 8\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\nindex 8a3b0c48d0..4c6357353e 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\n@@ -1049,6 +1049,109 @@ static const struct rte_cryptodev_capabilities caps_null[] = {\n \t},\n };\n \n+static const struct rte_cryptodev_capabilities caps_sm4[] = {\n+\t{\t/* SM4 CBC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_SM4_CBC,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* SM4 ECB */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_SM4_ECB,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 0,\n+\t\t\t\t\t.max = 0,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* SM4 CTR */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_SM4_CTR,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* SM4 OFB */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_SM4_OFB,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* SM4 CFB */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_SM4_CFB,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+};\n+\n static const struct rte_cryptodev_capabilities caps_end[] = {\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n@@ -1513,9 +1616,13 @@ cn9k_crypto_caps_add(struct rte_cryptodev_capabilities cnxk_caps[], int *cur_pos\n }\n \n static void\n-cn10k_crypto_caps_add(struct rte_cryptodev_capabilities cnxk_caps[], int *cur_pos)\n+cn10k_crypto_caps_add(struct rte_cryptodev_capabilities cnxk_caps[],\n+\t\t union cpt_eng_caps *hw_caps, int *cur_pos)\n {\n-\tcpt_caps_add(cnxk_caps, cur_pos, caps_sm3, RTE_DIM(caps_sm3));\n+\tif (hw_caps->sg_ver2) {\n+\t\tCPT_CAPS_ADD(cnxk_caps, cur_pos, hw_caps, sm3);\n+\t\tCPT_CAPS_ADD(cnxk_caps, cur_pos, hw_caps, sm4);\n+\t}\n }\n \n static void\n@@ -1537,7 +1644,7 @@ crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[],\n \t\tcn9k_crypto_caps_add(cnxk_caps, &cur_pos);\n \n \tif (roc_model_is_cn10k())\n-\t\tcn10k_crypto_caps_add(cnxk_caps, &cur_pos);\n+\t\tcn10k_crypto_caps_add(cnxk_caps, hw_caps, &cur_pos);\n \n \tcpt_caps_add(cnxk_caps, &cur_pos, caps_null, RTE_DIM(caps_null));\n \tcpt_caps_add(cnxk_caps, &cur_pos, caps_end, RTE_DIM(caps_end));\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\nindex d0c99d37e8..50150d3f06 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n@@ -660,7 +660,7 @@ cnxk_cpt_inst_w7_get(struct cnxk_se_sess *sess, struct roc_cpt *roc_cpt)\n \n \t/* Set the engine group */\n \tif (sess->zsk_flag || sess->aes_ctr_eea2 || sess->is_sha3 || sess->is_sm3 ||\n-\t sess->passthrough)\n+\t sess->passthrough || sess->is_sm4)\n \t\tinst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_SE];\n \telse\n \t\tinst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE];\n@@ -704,6 +704,9 @@ sym_session_configure(struct roc_cpt *roc_cpt, struct rte_crypto_sym_xform *xfor\n \t\tcase ROC_SE_PDCP_CHAIN:\n \t\t\tthr_type = CPT_DP_THREAD_TYPE_PDCP_CHAIN;\n \t\t\tbreak;\n+\t\tcase ROC_SE_SM:\n+\t\t\tthr_type = CPT_DP_THREAD_TYPE_SM;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tplt_err(\"Invalid op type\");\n \t\t\tret = -ENOTSUP;\ndiff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h\nindex 9f3bff3e68..3444f2d599 100644\n--- a/drivers/crypto/cnxk/cnxk_se.h\n+++ b/drivers/crypto/cnxk/cnxk_se.h\n@@ -23,6 +23,7 @@ enum cpt_dp_thread_type {\n \tCPT_DP_THREAD_TYPE_PDCP,\n \tCPT_DP_THREAD_TYPE_PDCP_CHAIN,\n \tCPT_DP_THREAD_TYPE_KASUMI,\n+\tCPT_DP_THREAD_TYPE_SM,\n \tCPT_DP_THREAD_AUTH_ONLY,\n \tCPT_DP_THREAD_GENERIC,\n \tCPT_DP_THREAD_TYPE_PT,\n@@ -49,7 +50,8 @@ struct cnxk_se_sess {\n \tuint8_t short_iv : 1;\n \tuint8_t is_sm3 : 1;\n \tuint8_t passthrough : 1;\n-\tuint8_t rsvd : 4;\n+\tuint8_t is_sm4 : 1;\n+\tuint8_t rsvd : 3;\n \tuint8_t mac_len;\n \tuint8_t iv_length;\n \tuint8_t auth_iv_length;\n@@ -1059,6 +1061,100 @@ pdcp_chain_sg2_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx,\n \treturn ret;\n }\n \n+static __rte_always_inline int\n+cpt_sm_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, struct roc_se_fc_params *fc_params,\n+\t struct cpt_inst_s *inst, const bool is_sg_ver2, int decrypt)\n+{\n+\tint32_t inputlen, outputlen, enc_dlen;\n+\tunion cpt_inst_w4 cpt_inst_w4;\n+\tuint32_t passthrough_len = 0;\n+\tstruct roc_se_ctx *se_ctx;\n+\tuint32_t encr_data_len;\n+\tuint32_t encr_offset;\n+\tuint64_t offset_ctrl;\n+\tuint8_t iv_len = 16;\n+\tuint8_t *src = NULL;\n+\tvoid *offset_vaddr;\n+\tint ret;\n+\n+\tencr_offset = ROC_SE_ENCR_OFFSET(d_offs);\n+\tencr_data_len = ROC_SE_ENCR_DLEN(d_lens);\n+\n+\tse_ctx = fc_params->ctx;\n+\tcpt_inst_w4.u64 = se_ctx->template_w4.u64;\n+\n+\tif (unlikely(!(flags & ROC_SE_VALID_IV_BUF)))\n+\t\tiv_len = 0;\n+\n+\tencr_offset += iv_len;\n+\tenc_dlen = encr_data_len + encr_offset;\n+\tenc_dlen = RTE_ALIGN_CEIL(encr_data_len, 8) + encr_offset;\n+\n+\tinputlen = enc_dlen;\n+\toutputlen = enc_dlen;\n+\n+\tcpt_inst_w4.s.param1 = encr_data_len;\n+\n+\tif (unlikely(encr_offset >> 8)) {\n+\t\tplt_dp_err(\"Offset not supported\");\n+\t\tplt_dp_err(\"enc_offset: %d\", encr_offset);\n+\t\treturn -1;\n+\t}\n+\n+\toffset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset);\n+\n+\t/*\n+\t * In cn9k, cn10k since we have a limitation of\n+\t * IV & Offset control word not part of instruction\n+\t * and need to be part of Data Buffer, we check if\n+\t * head room is there and then only do the Direct mode processing\n+\t */\n+\tif (likely((flags & ROC_SE_SINGLE_BUF_INPLACE) && (flags & ROC_SE_SINGLE_BUF_HEADROOM))) {\n+\t\tvoid *dm_vaddr = fc_params->bufs[0].vaddr;\n+\n+\t\t/* Use Direct mode */\n+\n+\t\toffset_vaddr = PLT_PTR_SUB(dm_vaddr, ROC_SE_OFF_CTRL_LEN + iv_len);\n+\t\t*(uint64_t *)offset_vaddr = offset_ctrl;\n+\n+\t\t/* DPTR */\n+\t\tinst->dptr = (uint64_t)offset_vaddr;\n+\n+\t\t/* RPTR should just exclude offset control word */\n+\t\tinst->rptr = (uint64_t)dm_vaddr - iv_len;\n+\n+\t\tcpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tvoid *dst = PLT_PTR_ADD(offset_vaddr, ROC_SE_OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\n+\t\t\trte_memcpy(dst, src, 16);\n+\t\t}\n+\t\tinst->w4.u64 = cpt_inst_w4.u64;\n+\t} else {\n+\t\tif (likely(iv_len))\n+\t\t\tsrc = fc_params->iv_buf;\n+\n+\t\tinst->w4.u64 = cpt_inst_w4.u64;\n+\n+\t\tif (is_sg_ver2)\n+\t\t\tret = sg2_inst_prep(fc_params, inst, offset_ctrl, src, iv_len, 0, 0,\n+\t\t\t\t\t inputlen, outputlen, passthrough_len, flags, 0,\n+\t\t\t\t\t decrypt);\n+\t\telse\n+\t\t\tret = sg_inst_prep(fc_params, inst, offset_ctrl, src, iv_len, 0, 0,\n+\t\t\t\t\t inputlen, outputlen, passthrough_len, flags, 0, decrypt);\n+\n+\t\tif (unlikely(ret)) {\n+\t\t\tplt_dp_err(\"sg prep failed\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n static __rte_always_inline int\n cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \t\t struct roc_se_fc_params *fc_params, struct cpt_inst_s *inst,\n@@ -1899,6 +1995,71 @@ fill_sess_aead(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n \treturn 0;\n }\n \n+static __rte_always_inline int\n+fill_sm_sess_cipher(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n+{\n+\tstruct roc_se_sm_context *sm_ctx = &sess->roc_se_ctx.se_ctx.sm_ctx;\n+\tstruct rte_crypto_cipher_xform *c_form;\n+\troc_sm_cipher_type enc_type = 0;\n+\n+\tc_form = &xform->cipher;\n+\n+\tif (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) {\n+\t\tsess->cpt_op |= ROC_SE_OP_CIPHER_ENCRYPT;\n+\t\tsess->roc_se_ctx.template_w4.s.opcode_minor = ROC_SE_FC_MINOR_OP_ENCRYPT;\n+\t} else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT) {\n+\t\tsess->cpt_op |= ROC_SE_OP_CIPHER_DECRYPT;\n+\t\tsess->roc_se_ctx.template_w4.s.opcode_minor = ROC_SE_FC_MINOR_OP_DECRYPT;\n+\t} else {\n+\t\tplt_dp_err(\"Unknown cipher operation\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tswitch (c_form->algo) {\n+\tcase RTE_CRYPTO_CIPHER_SM4_CBC:\n+\t\tenc_type = ROC_SM4_CBC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_SM4_ECB:\n+\t\tenc_type = ROC_SM4_ECB;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_SM4_CTR:\n+\t\tenc_type = ROC_SM4_CTR;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_SM4_CFB:\n+\t\tenc_type = ROC_SM4_CFB;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_SM4_OFB:\n+\t\tenc_type = ROC_SM4_OFB;\n+\t\tbreak;\n+\tdefault:\n+\t\tplt_dp_err(\"Crypto: Undefined cipher algo %u specified\", c_form->algo);\n+\t\treturn -1;\n+\t}\n+\n+\tsess->iv_offset = c_form->iv.offset;\n+\tsess->iv_length = c_form->iv.length;\n+\n+\tif (c_form->key.length != ROC_SE_SM4_KEY_LEN) {\n+\t\tplt_dp_err(\"Invalid cipher params keylen %u\", c_form->key.length);\n+\t\treturn -1;\n+\t}\n+\n+\tsess->zsk_flag = 0;\n+\tsess->zs_cipher = 0;\n+\tsess->aes_gcm = 0;\n+\tsess->aes_ctr = 0;\n+\tsess->is_null = 0;\n+\tsess->is_sm4 = 1;\n+\tsess->roc_se_ctx.fc_type = ROC_SE_SM;\n+\n+\tsess->roc_se_ctx.template_w4.s.opcode_major = ROC_SE_MAJOR_OP_SM;\n+\n+\tmemcpy(sm_ctx->encr_key, c_form->key.data, ROC_SE_SM4_KEY_LEN);\n+\tsm_ctx->enc_cipher = enc_type;\n+\n+\treturn 0;\n+}\n+\n static __rte_always_inline int\n fill_sess_cipher(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n {\n@@ -1909,6 +2070,13 @@ fill_sess_cipher(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n \n \tc_form = &xform->cipher;\n \n+\tif ((c_form->algo == RTE_CRYPTO_CIPHER_SM4_CBC) ||\n+\t (c_form->algo == RTE_CRYPTO_CIPHER_SM4_ECB) ||\n+\t (c_form->algo == RTE_CRYPTO_CIPHER_SM4_CTR) ||\n+\t (c_form->algo == RTE_CRYPTO_CIPHER_SM4_CFB) ||\n+\t (c_form->algo == RTE_CRYPTO_CIPHER_SM4_OFB))\n+\t\treturn fill_sm_sess_cipher(xform, sess);\n+\n \tif (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)\n \t\tsess->cpt_op |= ROC_SE_OP_CIPHER_ENCRYPT;\n \telse if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT) {\n@@ -2379,6 +2547,110 @@ prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,\n \treturn;\n }\n \n+static __rte_always_inline int\n+fill_sm_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,\n+\t struct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req,\n+\t struct cpt_inst_s *inst, const bool is_sg_ver2)\n+{\n+\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n+\tstruct roc_se_fc_params fc_params;\n+\tstruct rte_mbuf *m_src, *m_dst;\n+\tuint8_t cpt_op = sess->cpt_op;\n+\tuint64_t d_offs, d_lens;\n+\tchar src[SRC_IOV_SIZE];\n+\tchar dst[SRC_IOV_SIZE];\n+\tvoid *mdata = NULL;\n+#ifdef CPT_ALWAYS_USE_SG_MODE\n+\tuint8_t inplace = 0;\n+#else\n+\tuint8_t inplace = 1;\n+#endif\n+\tuint32_t flags = 0;\n+\tint ret;\n+\n+\tuint32_t ci_data_length = sym_op->cipher.data.length;\n+\tuint32_t ci_data_offset = sym_op->cipher.data.offset;\n+\n+\tfc_params.cipher_iv_len = sess->iv_length;\n+\tfc_params.auth_iv_len = 0;\n+\tfc_params.auth_iv_buf = NULL;\n+\tfc_params.iv_buf = NULL;\n+\tfc_params.mac_buf.size = 0;\n+\tfc_params.mac_buf.vaddr = 0;\n+\n+\tif (likely(sess->iv_length)) {\n+\t\tflags |= ROC_SE_VALID_IV_BUF;\n+\t\tfc_params.iv_buf = rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset);\n+\t}\n+\n+\tm_src = sym_op->m_src;\n+\tm_dst = sym_op->m_dst;\n+\n+\td_offs = ci_data_offset;\n+\td_offs = (d_offs << 16);\n+\n+\td_lens = ci_data_length;\n+\td_lens = (d_lens << 32);\n+\n+\tfc_params.ctx = &sess->roc_se_ctx;\n+\n+\tif (likely(!m_dst && inplace)) {\n+\t\tfc_params.dst_iov = fc_params.src_iov = (void *)src;\n+\n+\t\tprepare_iov_from_pkt_inplace(m_src, &fc_params, &flags);\n+\n+\t} else {\n+\t\t/* Out of place processing */\n+\t\tfc_params.src_iov = (void *)src;\n+\t\tfc_params.dst_iov = (void *)dst;\n+\n+\t\t/* Store SG I/O in the api for reuse */\n+\t\tif (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {\n+\t\t\tplt_dp_err(\"Prepare src iov failed\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto err_exit;\n+\t\t}\n+\n+\t\tif (unlikely(m_dst != NULL)) {\n+\t\t\tif (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {\n+\t\t\t\tplt_dp_err(\"Prepare dst iov failed for m_dst %p\", m_dst);\n+\t\t\t\tret = -EINVAL;\n+\t\t\t\tgoto err_exit;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tfc_params.dst_iov = (void *)src;\n+\t\t}\n+\t}\n+\n+\tfc_params.meta_buf.vaddr = NULL;\n+\n+\tif (unlikely(!((flags & ROC_SE_SINGLE_BUF_INPLACE) &&\n+\t\t (flags & ROC_SE_SINGLE_BUF_HEADROOM)))) {\n+\t\tmdata = alloc_op_meta(&fc_params.meta_buf, m_info->mlen, m_info->pool, infl_req);\n+\t\tif (mdata == NULL) {\n+\t\t\tplt_dp_err(\"Error allocating meta buffer for request\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n+\t/* Finally prepare the instruction */\n+\tret = cpt_sm_prep(flags, d_offs, d_lens, &fc_params, inst, is_sg_ver2,\n+\t\t\t !(cpt_op & ROC_SE_OP_ENCODE));\n+\n+\tif (unlikely(ret)) {\n+\t\tplt_dp_err(\"Preparing request failed due to bad input arg\");\n+\t\tgoto free_mdata_and_exit;\n+\t}\n+\n+\treturn 0;\n+\n+free_mdata_and_exit:\n+\tif (infl_req->op_flags & CPT_OP_FLAGS_METABUF)\n+\t\trte_mempool_put(m_info->pool, infl_req->mdata);\n+err_exit:\n+\treturn ret;\n+}\n+\n static __rte_always_inline int\n fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,\n \t struct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req,\n@@ -3068,6 +3340,10 @@ cpt_sym_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, struct cnxk_\n \t\tret = fill_fc_params(op, sess, &qp->meta_info, infl_req, inst, true, false,\n \t\t\t\t is_sg_ver2);\n \t\tbreak;\n+\tcase CPT_DP_THREAD_TYPE_SM:\n+\t\tret = fill_sm_params(op, sess, &qp->meta_info, infl_req, inst, is_sg_ver2);\n+\t\tbreak;\n+\n \tcase CPT_DP_THREAD_AUTH_ONLY:\n \t\tret = fill_digest_params(op, sess, &qp->meta_info, infl_req, inst, is_sg_ver2);\n \t\tbreak;\n", "prefixes": [ "7/8" ] }