Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/128862/?format=api
{ "id": 128862, "url": "http://patchwork.dpdk.org/api/patches/128862/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230620141115.841226-5-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230620141115.841226-5-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230620141115.841226-5-suanmingm@nvidia.com", "date": "2023-06-20T14:11:10", "name": "[v4,4/9] crypto/mlx5: add AES-GCM encryption key", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a146c604a934f14a9ef87d61c9162b565f2eaeb5", "submitter": { "id": 1887, "url": "http://patchwork.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230620141115.841226-5-suanmingm@nvidia.com/mbox/", "series": [ { "id": 28586, "url": "http://patchwork.dpdk.org/api/series/28586/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28586", "date": "2023-06-20T14:11:06", "name": "crypto/mlx5: support AES-GCM", "version": 4, "mbox": "http://patchwork.dpdk.org/series/28586/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/128862/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/128862/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D590C42D09;\n\tTue, 20 Jun 2023 16:12:25 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E487F42D48;\n\tTue, 20 Jun 2023 16:12:06 +0200 (CEST)", "from NAM04-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam04on2074.outbound.protection.outlook.com [40.107.100.74])\n by mails.dpdk.org (Postfix) with ESMTP id 9CD8342C4D\n for <dev@dpdk.org>; Tue, 20 Jun 2023 16:12:05 +0200 (CEST)", "from SJ0PR05CA0047.namprd05.prod.outlook.com (2603:10b6:a03:33f::22)\n by DS0PR12MB7534.namprd12.prod.outlook.com (2603:10b6:8:139::6) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6500.37; Tue, 20 Jun\n 2023 14:12:01 +0000", "from MWH0EPF000989E8.namprd02.prod.outlook.com\n (2603:10b6:a03:33f:cafe::aa) by SJ0PR05CA0047.outlook.office365.com\n (2603:10b6:a03:33f::22) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.21 via Frontend\n Transport; Tue, 20 Jun 2023 14:12:00 +0000", "from mail.nvidia.com (216.228.117.161) by\n MWH0EPF000989E8.mail.protection.outlook.com (10.167.241.135) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6521.17 via Frontend Transport; Tue, 20 Jun 2023 14:12:00 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 20 Jun 2023\n 07:11:43 -0700", "from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 20 Jun\n 2023 07:11:41 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=Vj8gwB0jAIfO8eMmGqYkcvGS1jdFaG9+8a/7xYu6u6sDAUslCBemMea1r52GqpRfUIMv1rMg4CkSbd9ox7O1T3UMw/MQdHZ4nd5UtUl8KBE1L3ER3+GTdPCUWWB/0J5Uw7KidTVHxT9bNpjsSVxOI3pv9ln4gZ1wKkmFO8LC6Hw81QnXg6CNFSazY313cyrBGF+PC8zkCBSPbi9iTX67oFqNKj3hA8Z+tbMq91/BHXm6fIk2GZUoNS/toFBezdq5EdvFnbLjmisNIBWeQ5Cw1G/VLHdPWPBpUZpKz7yDMs/SavHJRAP/WGJnWGnvZMKT2OajCoVFFaHd/0+ItZ9REA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=HlrZnc4TBYinAE5ycix/9UD68IScnM54k3BL9xhW650=;\n b=EtvHgE4nw+EkAgWDhFnLcZEMp1+KO3yTCQWWfv/ZpR6PhhvVtQJSpi1a07AiIO4itrTi4v0Pjl5j6wlsH8wmqlmti6U7DVHRGkJkQlejflVCUSuNI+ZDHDlPRJdZGQ9BVnoNDFGvalIjnWc0QAlrKInrO8+xYX2ngk0G41TUofbX4jPdgp9yRj6s8Z+NIZNZWIEn8aOwOrrjnr8tRWGR1fF7Hp0ZUMdJoxUHX+lroDFnG5Lf0PdYWwWJRhDhOTKyS9WjHeG4aog2x88meT0HPT2x5pYaaxa9KXzv4Nwn5HzPLfnLb9Ay3+woL18HzDvrUbE4yCvN90hyj6tCXQ0ZIw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=marvell.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=HlrZnc4TBYinAE5ycix/9UD68IScnM54k3BL9xhW650=;\n b=Cw7fRa3uG0XOis02NE/ioz1bit8VBFeGCuXjNgeiDkoPNLNQRzIlDEKGULEtPMcUMMNrUu2mNQReZ0uqOtPalTyMezWlFcI6y88FxjLPHxBdHuAOKeeDxn8BK4ODzZk/CJdn/DuTZGoif2EAgPYmD3FXku0vh7ew98EYK5QGiVRWknoleeoh/+1zBglKlxI89mn1VLLOs5CVBTm2+6vh5PnwGEYqXgeemMHu5g/rcnuGq1P28V/uf1asc5kiIMJAiY97/sPODg5ETLI6bURizsxUPOlGKg11xFkqbw0kQm5tuEzZFwymrBbxBHJCbwkduOHWr2rj4cK2guECdxnaug==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<gakhil@marvell.com>, Matan Azrad <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH v4 4/9] crypto/mlx5: add AES-GCM encryption key", "Date": "Tue, 20 Jun 2023 17:11:10 +0300", "Message-ID": "<20230620141115.841226-5-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230620141115.841226-1-suanmingm@nvidia.com>", "References": "<20230418092325.2578712-1-suanmingm@nvidia.com>\n <20230620141115.841226-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000989E8:EE_|DS0PR12MB7534:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0ecde3d5-21f9-45fb-02ae-08db719850bc", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n aEsSxZX3BVCtjRZ5csUO1/xhoQZcJQrINAyoTn7metnnXfyXLu6dy8GSS7VZMatAAw9DfyHyDh4ztvrUZc7m7WTDgFX2EiWYx/gDHDzFHGHb7gWR/4Knazef0WZTNOFhC+4RElGcL8OF1MoYPXlhpvpuok9bQGQ3qH6hYIdCFwBr2Vyrc5CHEBlNCFp6ADFVeqDMzn/60BENixeGPIJrsKP3skyDk8sk7VQwPWdJ/vrruEQwlgElj9Y2hTnPpS5cqYlhUKmLpNJ9ma1t6E4+shYNeL6PzqpWK+pMF/q/ZrccUwAMjHj9wBSkDMrYT1Ka5WOZE79oGxd3s/+t5BhWaAv/LqZeUvmP61OrXLNne5uRwAwfdWtU0PPflV1YXfulupGQxzhs9PonK6ncritpgxjhfP9WDkh8/E7T/BXXrunvDSpgGb9uUZ9UsbpJeAhUTEdkCpUvIdC4VhOKDZPavtmT7yV7+hQtJJ8crdU36gvwqHZnkCtnkOMI3H9lFRzPSyE5tA9JdHXk5mukOgJ8kxTRtGrJtBH5Gj3mGM/ZAQTE9f6sxm6Z4XufdoNkiAENmP+fI1SUu+GdUSGi+MaEIHt9/eYEGkSStLXbtCwuZPC2/l+G4hDRuk4iWmxKlGoZeZa+WaHWI+kil3QHkEf6ufezrEoQR9ZsPgmxCcuPljb8Cr9xY9HY6YZt/bbD+i9EGslvXz26byHqt/HR1IzaB1xTU+DYQYrEDMzsoYG8+0Wtu0qcbpCKqtrEUNKJijze", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(39860400002)(396003)(346002)(376002)(136003)(451199021)(46966006)(40470700004)(36840700001)(83380400001)(47076005)(7696005)(54906003)(6666004)(110136005)(316002)(8676002)(8936002)(2616005)(36756003)(86362001)(26005)(1076003)(4326008)(6286002)(6636002)(16526019)(186003)(426003)(336012)(41300700001)(5660300002)(82310400005)(70586007)(70206006)(356005)(40460700003)(82740400003)(7636003)(55016003)(40480700001)(36860700001)(478600001)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jun 2023 14:12:00.5586 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0ecde3d5-21f9-45fb-02ae-08db719850bc", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000989E8.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS0PR12MB7534", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The crypto device requires the DEK(data encryption key) object for\ndata encryption/decryption operation.\n\nThis commit adds the AES-GCM DEK object management support.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.h | 17 ++++-\n drivers/crypto/mlx5/mlx5_crypto_dek.c | 102 +++++++++++++-------------\n drivers/crypto/mlx5/mlx5_crypto_gcm.c | 33 +++++++++\n drivers/crypto/mlx5/mlx5_crypto_xts.c | 53 ++++++++++++-\n 4 files changed, 150 insertions(+), 55 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 76f368ee91..bb5a557a38 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -86,6 +86,11 @@ struct mlx5_crypto_session {\n \tuint32_t dek_id; /**< DEK ID */\n } __rte_packed;\n \n+struct mlx5_crypto_dek_ctx {\n+\tstruct rte_crypto_sym_xform *xform;\n+\tstruct mlx5_crypto_priv *priv;\n+};\n+\n typedef void *(*mlx5_crypto_mkey_update_t)(struct mlx5_crypto_priv *priv,\n \t\t\t\t\t struct mlx5_crypto_qp *qp,\n \t\t\t\t\t uint32_t idx);\n@@ -106,7 +111,7 @@ mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n \n struct mlx5_crypto_dek *\n mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,\n-\t\t\tstruct rte_crypto_cipher_xform *cipher);\n+\t\t\tstruct rte_crypto_sym_xform *xform);\n \n int\n mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv);\n@@ -120,4 +125,14 @@ mlx5_crypto_xts_init(struct mlx5_crypto_priv *priv);\n int\n mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv);\n \n+int\n+mlx5_crypto_dek_fill_xts_attr(struct mlx5_crypto_dek *dek,\n+\t\t\t struct mlx5_devx_dek_attr *dek_attr,\n+\t\t\t void *cb_ctx);\n+\n+int\n+mlx5_crypto_dek_fill_gcm_attr(struct mlx5_crypto_dek *dek,\n+\t\t\t struct mlx5_devx_dek_attr *dek_attr,\n+\t\t\t void *cb_ctx);\n+\n #endif /* MLX5_CRYPTO_H_ */\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_dek.c b/drivers/crypto/mlx5/mlx5_crypto_dek.c\nindex 7339ef2bd9..716bcc0545 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_dek.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_dek.c\n@@ -13,10 +13,24 @@\n #include \"mlx5_crypto_utils.h\"\n #include \"mlx5_crypto.h\"\n \n-struct mlx5_crypto_dek_ctx {\n-\tstruct rte_crypto_cipher_xform *cipher;\n-\tstruct mlx5_crypto_priv *priv;\n-};\n+static int\n+mlx5_crypto_dek_get_key(struct rte_crypto_sym_xform *xform,\n+\t\t\tconst uint8_t **key,\n+\t\t\tuint16_t *key_len)\n+{\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {\n+\t\t*key = xform->cipher.key.data;\n+\t\t*key_len = xform->cipher.key.length;\n+\t} else if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n+\t\t*key = xform->aead.key.data;\n+\t\t*key_len = xform->aead.key.length;\n+\t} else {\n+\t\tDRV_LOG(ERR, \"Xform dek type not supported.\");\n+\t\trte_errno = -EINVAL;\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n \n int\n mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n@@ -27,19 +41,22 @@ mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n \n struct mlx5_crypto_dek *\n mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,\n-\t\t\tstruct rte_crypto_cipher_xform *cipher)\n+\t\t\tstruct rte_crypto_sym_xform *xform)\n {\n+\tconst uint8_t *key;\n+\tuint16_t key_len;\n \tstruct mlx5_hlist *dek_hlist = priv->dek_hlist;\n \tstruct mlx5_crypto_dek_ctx dek_ctx = {\n-\t\t.cipher = cipher,\n+\t\t.xform = xform,\n \t\t.priv = priv,\n \t};\n-\tstruct rte_crypto_cipher_xform *cipher_ctx = cipher;\n-\tuint64_t key64 = __rte_raw_cksum(cipher_ctx->key.data,\n-\t\t\t\t\t cipher_ctx->key.length, 0);\n-\tstruct mlx5_list_entry *entry = mlx5_hlist_register(dek_hlist,\n-\t\t\t\t\t\t\t key64, &dek_ctx);\n+\tuint64_t key64;\n+\tstruct mlx5_list_entry *entry;\n \n+\tif (mlx5_crypto_dek_get_key(xform, &key, &key_len))\n+\t\treturn NULL;\n+\tkey64 = __rte_raw_cksum(key, key_len, 0);\n+\tentry = mlx5_hlist_register(dek_hlist, key64, &dek_ctx);\n \treturn entry == NULL ? NULL :\n \t\t\t container_of(entry, struct mlx5_crypto_dek, entry);\n }\n@@ -76,76 +93,55 @@ mlx5_crypto_dek_match_cb(void *tool_ctx __rte_unused,\n \t\t\t struct mlx5_list_entry *entry, void *cb_ctx)\n {\n \tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n-\tstruct rte_crypto_cipher_xform *cipher_ctx = ctx->cipher;\n+\tstruct rte_crypto_sym_xform *xform = ctx->xform;\n \tstruct mlx5_crypto_dek *dek =\n \t\t\tcontainer_of(entry, typeof(*dek), entry);\n \tuint32_t key_len = dek->size;\n+\tuint16_t xkey_len;\n+\tconst uint8_t *key;\n \n-\tif (key_len != cipher_ctx->key.length)\n+\tif (mlx5_crypto_dek_get_key(xform, &key, &xkey_len))\n+\t\treturn -1;\n+\tif (key_len != xkey_len)\n \t\treturn -1;\n-\treturn memcmp(cipher_ctx->key.data, dek->data, cipher_ctx->key.length);\n+\treturn memcmp(key, dek->data, xkey_len);\n }\n \n static struct mlx5_list_entry *\n mlx5_crypto_dek_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)\n {\n \tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n-\tstruct rte_crypto_cipher_xform *cipher_ctx = ctx->cipher;\n+\tstruct rte_crypto_sym_xform *xform = ctx->xform;\n \tstruct mlx5_crypto_dek *dek = rte_zmalloc(__func__, sizeof(*dek),\n \t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n \tstruct mlx5_devx_dek_attr dek_attr = {\n \t\t.pd = ctx->priv->cdev->pdn,\n-\t\t.key_purpose = MLX5_CRYPTO_KEY_PURPOSE_AES_XTS,\n-\t\t.has_keytag = 1,\n \t};\n-\tbool is_wrapped = ctx->priv->is_wrapped_mode;\n+\tint ret = -1;\n \n \tif (dek == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to allocate dek memory.\");\n \t\treturn NULL;\n \t}\n-\tif (is_wrapped) {\n-\t\tswitch (cipher_ctx->key.length) {\n-\t\tcase 48:\n-\t\t\tdek->size = 48;\n-\t\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n-\t\t\tbreak;\n-\t\tcase 80:\n-\t\t\tdek->size = 80;\n-\t\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tDRV_LOG(ERR, \"Wrapped key size not supported.\");\n-\t\t\treturn NULL;\n-\t\t}\n-\t} else {\n-\t\tswitch (cipher_ctx->key.length) {\n-\t\tcase 32:\n-\t\t\tdek->size = 40;\n-\t\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n-\t\t\tbreak;\n-\t\tcase 64:\n-\t\t\tdek->size = 72;\n-\t\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tDRV_LOG(ERR, \"Key size not supported.\");\n-\t\t\treturn NULL;\n-\t\t}\n-\t\tmemcpy(&dek_attr.key[cipher_ctx->key.length],\n-\t\t\t\t\t\t&ctx->priv->keytag, 8);\n-\t}\n-\tmemcpy(&dek_attr.key, cipher_ctx->key.data, cipher_ctx->key.length);\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)\n+\t\tret = mlx5_crypto_dek_fill_xts_attr(dek, &dek_attr, cb_ctx);\n+\telse if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)\n+\t\tret = mlx5_crypto_dek_fill_gcm_attr(dek, &dek_attr, cb_ctx);\n+\tif (ret)\n+\t\tgoto fail;\n \tdek->obj = mlx5_devx_cmd_create_dek_obj(ctx->priv->cdev->ctx,\n \t\t\t\t\t\t&dek_attr);\n \tif (dek->obj == NULL) {\n-\t\trte_free(dek);\n-\t\treturn NULL;\n+\t\tDRV_LOG(ERR, \"Failed to create dek obj.\");\n+\t\tgoto fail;\n \t}\n-\tmemcpy(&dek->data, cipher_ctx->key.data, cipher_ctx->key.length);\n \treturn &dek->entry;\n+fail:\n+\trte_free(dek);\n+\treturn NULL;\n }\n \n+\n static void\n mlx5_crypto_dek_remove_cb(void *tool_ctx __rte_unused,\n \t\t\t struct mlx5_list_entry *entry)\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\nindex bd78c6d66b..5b315ef42c 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n@@ -27,6 +27,39 @@ static struct rte_cryptodev_capabilities mlx5_crypto_gcm_caps[] = {\n \t}\n };\n \n+int\n+mlx5_crypto_dek_fill_gcm_attr(struct mlx5_crypto_dek *dek,\n+\t\t\t struct mlx5_devx_dek_attr *dek_attr,\n+\t\t\t void *cb_ctx)\n+{\n+\tuint32_t offset = 0;\n+\tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n+\tstruct rte_crypto_aead_xform *aead_ctx = &ctx->xform->aead;\n+\n+\tif (aead_ctx->algo != RTE_CRYPTO_AEAD_AES_GCM) {\n+\t\tDRV_LOG(ERR, \"Only AES-GCM algo supported.\");\n+\t\treturn -EINVAL;\n+\t}\n+\tdek_attr->key_purpose = MLX5_CRYPTO_KEY_PURPOSE_GCM;\n+\tswitch (aead_ctx->key.length) {\n+\tcase 16:\n+\t\toffset = 16;\n+\t\tdek->size = 16;\n+\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n+\t\tbreak;\n+\tcase 32:\n+\t\tdek->size = 32;\n+\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n+\t\tbreak;\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Wrapped key size not supported.\");\n+\t\treturn -EINVAL;\n+\t}\n+\tmemcpy(&dek_attr->key[offset], aead_ctx->key.data, aead_ctx->key.length);\n+\tmemcpy(&dek->data, aead_ctx->key.data, aead_ctx->key.length);\n+\treturn 0;\n+}\n+\n int\n mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv)\n {\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_xts.c b/drivers/crypto/mlx5/mlx5_crypto_xts.c\nindex 964d02e6ed..661da5f589 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_xts.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_xts.c\n@@ -45,6 +45,57 @@ const struct rte_cryptodev_capabilities mlx5_crypto_caps[] = {\n \t},\n };\n \n+int\n+mlx5_crypto_dek_fill_xts_attr(struct mlx5_crypto_dek *dek,\n+\t\t\t struct mlx5_devx_dek_attr *dek_attr,\n+\t\t\t void *cb_ctx)\n+{\n+\tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n+\tstruct rte_crypto_cipher_xform *cipher_ctx = &ctx->xform->cipher;\n+\tbool is_wrapped = ctx->priv->is_wrapped_mode;\n+\n+\tif (cipher_ctx->algo != RTE_CRYPTO_CIPHER_AES_XTS) {\n+\t\tDRV_LOG(ERR, \"Only AES-XTS algo supported.\");\n+\t\treturn -EINVAL;\n+\t}\n+\tdek_attr->key_purpose = MLX5_CRYPTO_KEY_PURPOSE_AES_XTS;\n+\tdek_attr->has_keytag = 1;\n+\tif (is_wrapped) {\n+\t\tswitch (cipher_ctx->key.length) {\n+\t\tcase 48:\n+\t\t\tdek->size = 48;\n+\t\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n+\t\t\tbreak;\n+\t\tcase 80:\n+\t\t\tdek->size = 80;\n+\t\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDRV_LOG(ERR, \"Wrapped key size not supported.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else {\n+\t\tswitch (cipher_ctx->key.length) {\n+\t\tcase 32:\n+\t\t\tdek->size = 40;\n+\t\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n+\t\t\tbreak;\n+\t\tcase 64:\n+\t\t\tdek->size = 72;\n+\t\t\tdek_attr->key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDRV_LOG(ERR, \"Key size not supported.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tmemcpy(&dek_attr->key[cipher_ctx->key.length],\n+\t\t\t\t\t\t&ctx->priv->keytag, 8);\n+\t}\n+\tmemcpy(&dek_attr->key, cipher_ctx->key.data, cipher_ctx->key.length);\n+\tmemcpy(&dek->data, cipher_ctx->key.data, cipher_ctx->key.length);\n+\treturn 0;\n+}\n+\n static int\n mlx5_crypto_xts_sym_session_configure(struct rte_cryptodev *dev,\n \t\t\t\t struct rte_crypto_sym_xform *xform,\n@@ -66,7 +117,7 @@ mlx5_crypto_xts_sym_session_configure(struct rte_cryptodev *dev,\n \t\treturn -ENOTSUP;\n \t}\n \tcipher = &xform->cipher;\n-\tsess_private_data->dek = mlx5_crypto_dek_prepare(priv, cipher);\n+\tsess_private_data->dek = mlx5_crypto_dek_prepare(priv, xform);\n \tif (sess_private_data->dek == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to prepare dek.\");\n \t\treturn -ENOMEM;\n", "prefixes": [ "v4", "4/9" ] }