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GET /api/patches/129061/?format=api
{ "id": 129061, "url": "http://patchwork.dpdk.org/api/patches/129061/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230628162927.92858-3-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230628162927.92858-3-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230628162927.92858-3-ajit.khaparde@broadcom.com", "date": "2023-06-28T16:29:18", "name": "[v4,02/11] net/bnxt: update bnxt hsi structure", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d71dde11ae51db53bc205de090b983eedc8e14b5", "submitter": { "id": 501, "url": "http://patchwork.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patchwork.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230628162927.92858-3-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 28693, "url": "http://patchwork.dpdk.org/api/series/28693/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28693", "date": "2023-06-28T16:29:16", "name": "sync Truflow support with latest release", "version": 4, "mbox": "http://patchwork.dpdk.org/series/28693/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129061/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/129061/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AB78742D82;\n\tWed, 28 Jun 2023 18:31:00 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B78D642D12;\n\tWed, 28 Jun 2023 18:30:48 +0200 (CEST)", "from mail-pl1-f179.google.com (mail-pl1-f179.google.com\n [209.85.214.179])\n by mails.dpdk.org (Postfix) with ESMTP id 29CCF42D0E\n for <dev@dpdk.org>; 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protocol=\"application/pkcs7-signature\";\n micalg=sha-256; boundary=\"00000000000005431605ff331b65\"", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Randy Schacher <stuart.schacher@broadcom.com>\n\nSync hsi structure to latest revision.\nNew version is 1.10.2.138\n\nSigned-off-by: Randy Schacher <stuart.schacher@broadcom.com>\nReviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 5723 +++++++++++++++++++++---\n 1 file changed, 5128 insertions(+), 595 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 380dec4d3e..9afdd056ce 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (c) 2014-2022 Broadcom Inc.\n+ * Copyright (c) 2014-2023 Broadcom Inc.\n * All rights reserved.\n *\n * DO NOT MODIFY!!! This file is automatically generated.\n@@ -442,6 +442,8 @@ struct cmd_nums {\n \t#define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)\n \t#define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda)\n \t#define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb)\n+\t#define HWRM_PORT_CFG UINT32_C(0xdc)\n+\t#define HWRM_PORT_QCFG UINT32_C(0xdd)\n \t#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)\n \t#define HWRM_REG_POWER_QUERY UINT32_C(0xe1)\n \t#define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)\n@@ -480,9 +482,7 @@ struct cmd_nums {\n \t#define HWRM_CFA_FLOW_FREE UINT32_C(0x104)\n \t/* Experimental */\n \t#define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)\n-\t/* Experimental */\n \t#define HWRM_CFA_FLOW_STATS UINT32_C(0x106)\n-\t/* Experimental */\n \t#define HWRM_CFA_FLOW_INFO UINT32_C(0x107)\n \t/* Experimental */\n \t#define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)\n@@ -678,6 +678,17 @@ struct cmd_nums {\n \t#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7)\n \t/* The is the new API to query backing store capabilities. */\n \t#define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8)\n+\t/* To query doorbell pacing NQ id list configuration. */\n+\t#define HWRM_FUNC_DBR_PACING_NQLIST_QUERY UINT32_C(0x1a9)\n+\t/*\n+\t * To notify the firmware that recovery cycle has been\n+\t * completed by host function drivers.\n+\t */\n+\t#define HWRM_FUNC_DBR_RECOVERY_COMPLETED UINT32_C(0x1aa)\n+\t/* Configures SyncE configurations. */\n+\t#define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab)\n+\t/* Queries SyncE configurations. */\n+\t#define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac)\n \t/* Experimental */\n \t#define HWRM_SELFTEST_QLIST UINT32_C(0x200)\n \t/* Experimental */\n@@ -747,6 +758,8 @@ struct cmd_nums {\n \t * to run.\n \t */\n \t#define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217)\n+\t/* Queries the generic stats */\n+\t#define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218)\n \t/* Experimental */\n \t#define HWRM_TF UINT32_C(0x2bc)\n \t/* Experimental */\n@@ -774,6 +787,10 @@ struct cmd_nums {\n \t/* Experimental */\n \t#define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)\n \t/* Experimental */\n+\t#define HWRM_TF_SESSION_HOTUP_STATE_SET UINT32_C(0x2d1)\n+\t/* Experimental */\n+\t#define HWRM_TF_SESSION_HOTUP_STATE_GET UINT32_C(0x2d2)\n+\t/* Experimental */\n \t#define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)\n \t/* Experimental */\n \t#define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)\n@@ -819,6 +836,54 @@ struct cmd_nums {\n \t#define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)\n \t/* Experimental */\n \t#define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)\n+\t/* TruFlow command to check firmware table scope capabilities. */\n+\t#define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380)\n+\t/* TruFlow command to allocate a table scope ID and create the pools. */\n+\t#define HWRM_TFC_TBL_SCOPE_ID_ALLOC UINT32_C(0x381)\n+\t/* TruFlow command to configure the table scope memory. */\n+\t#define HWRM_TFC_TBL_SCOPE_CONFIG UINT32_C(0x382)\n+\t/* TruFlow command to deconfigure a table scope memory. */\n+\t#define HWRM_TFC_TBL_SCOPE_DECONFIG UINT32_C(0x383)\n+\t/* TruFlow command to add a FID to a table scope. */\n+\t#define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384)\n+\t/* TruFlow command to remove a FID from a table scope. */\n+\t#define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385)\n+\t/* TruFlow command to allocate a table scope pool. */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386)\n+\t/* TruFlow command to free a table scope pool. */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387)\n+\t/* Experimental */\n+\t#define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388)\n+\t/* Experimental */\n+\t#define HWRM_TFC_SESSION_FID_ADD UINT32_C(0x389)\n+\t/* Experimental */\n+\t#define HWRM_TFC_SESSION_FID_REM UINT32_C(0x38a)\n+\t/* Experimental */\n+\t#define HWRM_TFC_IDENT_ALLOC UINT32_C(0x38b)\n+\t/* Experimental */\n+\t#define HWRM_TFC_IDENT_FREE UINT32_C(0x38c)\n+\t/* TruFlow command to allocate an index table entry */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC UINT32_C(0x38d)\n+\t/* TruFlow command to allocate and set an index table entry */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_SET UINT32_C(0x38e)\n+\t/* TruFlow command to set an index table entry */\n+\t#define HWRM_TFC_IDX_TBL_SET UINT32_C(0x38f)\n+\t/* TruFlow command to get an index table entry */\n+\t#define HWRM_TFC_IDX_TBL_GET UINT32_C(0x390)\n+\t/* TruFlow command to free an index table entry */\n+\t#define HWRM_TFC_IDX_TBL_FREE UINT32_C(0x391)\n+\t/* TruFlow command to allocate resources for a global id. */\n+\t#define HWRM_TFC_GLOBAL_ID_ALLOC UINT32_C(0x392)\n+\t/* TruFlow command to set TCAM entry. */\n+\t#define HWRM_TFC_TCAM_SET UINT32_C(0x393)\n+\t/* TruFlow command to get TCAM entry. */\n+\t#define HWRM_TFC_TCAM_GET UINT32_C(0x394)\n+\t/* TruFlow command to allocate a TCAM entry. */\n+\t#define HWRM_TFC_TCAM_ALLOC UINT32_C(0x395)\n+\t/* TruFlow command allocate and set TCAM entry. */\n+\t#define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396)\n+\t/* TruFlow command to free a TCAM entry. */\n+\t#define HWRM_TFC_TCAM_FREE UINT32_C(0x397)\n \t/* Experimental */\n \t#define HWRM_SV UINT32_C(0x400)\n \t/* Experimental */\n@@ -1089,8 +1154,8 @@ struct hwrm_err_output {\n #define HWRM_VERSION_MINOR 10\n #define HWRM_VERSION_UPDATE 2\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 83\n-#define HWRM_VERSION_STR \"1.10.2.83\"\n+#define HWRM_VERSION_RSVD 138\n+#define HWRM_VERSION_STR \"1.10.2.138\"\n \n /****************\n * hwrm_ver_get *\n@@ -1345,6 +1410,7 @@ struct hwrm_ver_get_output {\n \t * If set to 1, firmware is capable to support flow aging.\n \t * If set to 0, firmware is not capable to support flow aging.\n \t * By default, this flag should be 0 for older version of core firmware.\n+\t * (deprecated)\n \t */\n \t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \\\n \t\tUINT32_C(0x200)\n@@ -1353,6 +1419,7 @@ struct hwrm_ver_get_output {\n \t * Meter drop counters and EEM counters.\n \t * If set to 0, firmware is not capable to support advanced flow counters.\n \t * By default, this flag should be 0 for older version of core firmware.\n+\t * (deprecated)\n \t */\n \t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \\\n \t\tUINT32_C(0x400)\n@@ -1362,6 +1429,7 @@ struct hwrm_ver_get_output {\n \t * If set to 0, firmware is not capable to support the use of the\n \t * CFA EEM feature.\n \t * By default, this flag should be 0 for older version of core firmware.\n+\t * (deprecated)\n \t */\n \t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \\\n \t\tUINT32_C(0x800)\n@@ -1996,7 +2064,7 @@ struct cfa_bds_event_collect_cmd_data_msg {\n \tuint64_t\thost_address;\n } __rte_packed;\n \n-/* ce_bds_add_data_msg (size:512b/64B) */\n+/* ce_bds_add_data_msg (size:576b/72B) */\n struct ce_bds_add_data_msg {\n \tuint32_t\tversion_algorithm_kid_opcode;\n \t/*\n@@ -2050,26 +2118,14 @@ struct ce_bds_add_data_msg {\n \t\t(UINT32_C(0x1) << 28)\n \t#define CE_BDS_ADD_DATA_MSG__LAST \\\n \t\tCE_BDS_ADD_DATA_MSG__TLS1_3\n-\tuint8_t\tcmd_type_ctx_kind;\n-\t/*\n-\t * Command Type in the TLS header. HW will provide registers that\n-\t * converts the 3b encoded command type to 8b of actual command\n-\t * type in the TLS Header. This field is initialized/updated by\n-\t * this \"KTLS crypto add\" mid-path command.\n-\t */\n-\t#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)\n-\t#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0\n-\t/* Application */\n-\t#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)\n-\t#define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \\\n-\t\tCE_BDS_ADD_DATA_MSG_CMD_TYPE_APP\n+\tuint8_t\tctx_kind;\n \t/* This field selects the context kind for the request. */\n-\t#define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0xf8)\n-\t#define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 3\n+\t#define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f)\n+\t#define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 0\n \t/* Crypto key transmit context */\n-\t#define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 3)\n+\t#define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX UINT32_C(0x11)\n \t/* Crypto key receive context */\n-\t#define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 3)\n+\t#define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX UINT32_C(0x12)\n \t#define CE_BDS_ADD_DATA_MSG_CTX_KIND_LAST \\\n \t\tCE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX\n \tuint8_t\tunused0[3];\n@@ -2083,8 +2139,8 @@ struct ce_bds_add_data_msg {\n \t * is zero padded to 12B and then xor'ed with the 4B of salt to generate\n \t * the 12B of IV. This value is initialized by this mid-path command.\n \t */\n-\tuint32_t\tsalt;\n-\tuint32_t\tunused1;\n+\tuint8_t\tsalt[4];\n+\tuint8_t\tunused1[4];\n \t/*\n \t * This field keeps track of the TCP sequence number that is expected as\n \t * the first byte in the next TCP packet. This field is calculated by HW\n@@ -2111,16 +2167,21 @@ struct ce_bds_add_data_msg {\n \t * the field after that for every record processed as it parses the TCP\n \t * packet.\n \t */\n-\tuint32_t\trecord_seq_num[2];\n+\tuint64_t\trecord_seq_num;\n \t/*\n \t * Key used for encrypting or decrypting TLS records. The Key is\n \t * exchanged during the hand-shake protocol by the client-server and\n \t * provided to HW through this mid-path BD.\n \t */\n-\tuint32_t\tsession_key[8];\n+\tuint8_t\tsession_key[32];\n+\t/*\n+\t * Additional IV that is exchanged as part of sessions setup between\n+\t * the two end points. This field is used for TLS1.3 only.\n+\t */\n+\tuint8_t\taddl_iv[8];\n } __rte_packed;\n \n-/* ce_bds_delete_data_msg (size:64b/8B) */\n+/* ce_bds_delete_data_msg (size:32b/4B) */\n struct ce_bds_delete_data_msg {\n \tuint32_t\tkid_opcode_ctx_kind;\n \t/*\n@@ -2160,7 +2221,6 @@ struct ce_bds_delete_data_msg {\n \t#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24)\n \t#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_LAST \\\n \t\tCE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX\n-\tuint32_t\tunused0;\n } __rte_packed;\n \n /* ce_bds_resync_resp_ack_msg (size:128b/16B) */\n@@ -2213,7 +2273,7 @@ struct ce_bds_resync_resp_ack_msg {\n \t * it has found since sending the resync request, update the context and\n \t * resume decrypting records.\n \t */\n-\tuint32_t\tresync_record_seq_num[2];\n+\tuint64_t\tresync_record_seq_num;\n } __rte_packed;\n \n /* ce_bds_resync_resp_nack_msg (size:64b/8B) */\n@@ -2288,6 +2348,19 @@ struct crypto_presync_bd_cmd {\n \t */\n \t#define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \\\n \t\tUINT32_C(0x1)\n+\t/*\n+\t * When packet with an authentication TAG is lost in the network,\n+\t * During retransmission Device driver will post the entire record for\n+\t * the hardware to recalculate the TAG. Hardware is set to retransmit\n+\t * only portions of the record, it does so by looking at the Header\n+\t * TCP Sequence Number and Start TCP Sequence Number. However, there\n+\t * is a case where the header packet gets dropped in the stack for ex\n+\t * BPF packet filter and it is impossible for the Hardware to\n+\t * determine if this is a case of full replay for only the TAG\n+\t * generation.\n+\t */\n+\t#define CRYPTO_PRESYNC_BD_CMD_FLAGS_FULL_REPLAY_RETRAN \\\n+\t\tUINT32_C(0x2)\n \tuint8_t\tunused0;\n \tuint16_t\tunused1;\n \t/*\n@@ -2331,7 +2404,7 @@ struct crypto_presync_bd_cmd {\n \t * the first TLS header. When subsequent TLS Headers are detected, the\n \t * value is extracted from packet.\n \t */\n-\tuint32_t\texplicit_nonce[2];\n+\tuint8_t\texplicit_nonce[8];\n \t/*\n \t * This is sequence number for the TLS record in a particular session. In\n \t * TLS1.2, record sequence number is part of the Associated Data (AD) in\n@@ -2343,7 +2416,110 @@ struct crypto_presync_bd_cmd {\n \t * delivering more retransmission instruction will also update this\n \t * field.\n \t */\n-\tuint32_t\trecord_seq_num[2];\n+\tuint64_t\trecord_seq_num;\n+} __rte_packed;\n+\n+/* ce_bds_quic_add_data_msg (size:832b/104B) */\n+struct ce_bds_quic_add_data_msg {\n+\tuint32_t\tver_algo_kid_opcode;\n+\t/*\n+\t * This value selects the operation for the mid-path command for the\n+\t * crypto blocks.\n+\t */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_SFT 0\n+\t/*\n+\t * This is the add command. Using this opcode, Host Driver can add\n+\t * information required for QUIC processing. The information is\n+\t * updated in the CFCK context.\n+\t */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_LAST \\\n+\t\tCE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD\n+\t/*\n+\t * This field is the Crypto Context ID. The KID is used to store\n+\t * information used by the associated QUIC offloaded connection.\n+\t */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_KID_MASK \\\n+\t\tUINT32_C(0xfffff0)\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_KID_SFT 4\n+\t/* Algorithm used for encryption and decryption. */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_MASK \\\n+\t\tUINT32_C(0xf000000)\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_SFT 24\n+\t/* AES_GCM_128 Algorithm. */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \\\n+\t\t(UINT32_C(0x1) << 24)\n+\t/* AES_GCM_256 Algorithm. */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \\\n+\t\t(UINT32_C(0x2) << 24)\n+\t/* Chacha20 Algorithm. */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20 \\\n+\t\t(UINT32_C(0x3) << 24)\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_LAST \\\n+\t\tCE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20\n+\t/* Version number of QUIC connection. */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_MASK \\\n+\t\tUINT32_C(0xf0000000)\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_SFT 28\n+\t/* TLS1.2 Version */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_2 \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* TLS1.3 Version */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_3 \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t/* DTLS1.2 Version */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2 \\\n+\t\t(UINT32_C(0x2) << 28)\n+\t/* DTLS1.2 for RoCE Version */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2_ROCE \\\n+\t\t(UINT32_C(0x3) << 28)\n+\t/* QUIC Version */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG__QUIC \\\n+\t\t(UINT32_C(0x4) << 28)\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG__LAST \\\n+\t\tCE_BDS_QUIC_ADD_DATA_MSG__QUIC\n+\tuint32_t\tctx_kind_dcid_width_key_phase;\n+\t/* Key phase. */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_KEY_PHASE UINT32_C(0x1)\n+\t/* Destination connection ID width. */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_MASK UINT32_C(0x3e)\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_SFT 1\n+\t/* This field selects the context kind for the request. */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x7c0)\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_SFT 6\n+\t/* QUIC key transmit context */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_TX \\\n+\t\t(UINT32_C(0x14) << 6)\n+\t/* QUIC key receive context */\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX \\\n+\t\t(UINT32_C(0x15) << 6)\n+\t#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_LAST \\\n+\t\tCE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX\n+\tuint32_t\tunused_0[2];\n+\t/*\n+\t * Least-significant 64 bits (of 96) of additional IV that is\n+\t * exchanged as part of sessions setup between the two end\n+\t * points for QUIC operations.\n+\t */\n+\tuint64_t\tquic_iv_lo;\n+\t/*\n+\t * Most-significant 32 bits (of 96) of additional IV that is\n+\t * exchanged as part of sessions setup between the two end\n+\t * points for QUIC operations.\n+\t */\n+\tuint32_t\tquic_iv_hi;\n+\tuint32_t\tunused_1;\n+\t/*\n+\t * Key used for encrypting or decrypting records. The Key is exchanged\n+\t * as part of sessions setup between the two end points through this\n+\t * mid-path BD.\n+\t */\n+\tuint32_t\tsession_key[8];\n+\t/* Header protection key. */\n+\tuint32_t\thp_key[8];\n+\t/* Packet number associated with the QUIC connection. */\n+\tuint64_t\tpkt_number;\n } __rte_packed;\n \n /* bd_base (size:64b/8B) */\n@@ -3665,7 +3841,7 @@ struct cfa_dma128b_data_msg {\n \n /* ce_cmpls_cmp_data_msg (size:128b/16B) */\n struct ce_cmpls_cmp_data_msg {\n-\tuint16_t\tstatus_subtype_type;\n+\tuint16_t\tclient_subtype_type;\n \t/*\n \t * This field indicates the exact type of the completion. By\n \t * convention, the LSB identifies the length of the record in 16B\n@@ -3678,82 +3854,82 @@ struct ce_cmpls_cmp_data_msg {\n \t#define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)\n \t#define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \\\n \t\tCE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT\n+\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc0)\n+\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 6\n \t/*\n \t * This value indicates the CE sub-type operation that is being\n \t * completed.\n \t */\n-\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)\n-\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0xf00)\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 8\n \t/* Completion Response for a Solicited Command. */\n-\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 8)\n \t/* Error Completion (Unsolicited). */\n-\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 8)\n \t/* Re-Sync Completion (Unsolicited) */\n-\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)\n+\t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 8)\n \t#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \\\n \t\tCE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC\n+\t/*\n+\t * This field represents the Mid-Path client that generated the\n+\t * completion.\n+\t */\n+\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf000)\n+\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 12\n+\t/* TX crypto engine block. */\n+\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_TCE \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t/* RX crypto engine block. */\n+\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE \\\n+\t\t(UINT32_C(0x1) << 12)\n+\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \\\n+\t\tCE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE\n+\tuint16_t\tstatus;\n \t/* This value indicates the status for the command. */\n-\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)\n-\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0xf)\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 0\n \t/* Completed without error. */\n-\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \\\n-\t\t(UINT32_C(0x0) << 10)\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_OK UINT32_C(0x0)\n \t/* CFCK load error. */\n-\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \\\n-\t\t(UINT32_C(0x1) << 10)\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR UINT32_C(0x1)\n \t/* FID check error. */\n-\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \\\n-\t\t(UINT32_C(0x2) << 10)\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR UINT32_C(0x2)\n \t/* Context kind / MP version mismatch error. */\n-\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR \\\n-\t\t(UINT32_C(0x3) << 10)\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR UINT32_C(0x3)\n \t/* Unsupported Destination Connection ID Length. */\n-\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR \\\n-\t\t(UINT32_C(0x4) << 10)\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR UINT32_C(0x4)\n \t/*\n \t * Invalid MP Command [anything other than ADD or DELETE\n \t * triggers this for QUIC].\n \t */\n-\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR \\\n-\t\t(UINT32_C(0x5) << 10)\n+\t#define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR UINT32_C(0x5)\n \t#define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \\\n \t\tCE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR\n-\tuint8_t\tunused0;\n-\tuint8_t\tmp_clients;\n-\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)\n-\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0\n-\t/*\n-\t * This field represents the Mid-Path client that generated the\n-\t * completion.\n-\t */\n-\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)\n-\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4\n-\t/* TX crypto engine block. */\n-\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)\n-\t/* RX crypto engine block. */\n-\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)\n-\t#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \\\n-\t\tCE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE\n+\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xfff0)\n+\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 4\n \t/*\n \t * This is a copy of the opaque field from the mid path BD of this\n \t * command.\n \t */\n \tuint32_t\topaque;\n-\t/* */\n-\tuint32_t\tkid_v;\n+\tuint32_t\tv;\n \t/*\n \t * This value is written by the NIC such that it will be different\n \t * for each pass through the completion queue. The even passes will\n \t * write 1. The odd passes will write 0.\n \t */\n-\t#define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)\n+\t#define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)\n+\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xfffffffe)\n+\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 1\n+\tuint32_t\tkid;\n \t/*\n \t * This field is the Crypto Context ID. The KID is used to store\n \t * information used by the associated kTLS offloaded connection.\n \t */\n-\t#define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)\n-\t#define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1\n-\tuint32_t\tunused2;\n+\t#define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0xfffff)\n+\t#define CE_CMPLS_CMP_DATA_MSG_KID_SFT 0\n+\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED3_MASK UINT32_C(0xfff00000)\n+\t#define CE_CMPLS_CMP_DATA_MSG_UNUSED3_SFT 20\n } __rte_packed;\n \n /* cmpl_base (size:128b/16B) */\n@@ -3783,16 +3959,11 @@ struct cmpl_base {\n \t * Completion of coalesced TX packet. Length = 16B\n \t */\n \t#define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)\n-\t/*\n-\t * TX L2 PTP completion:\n-\t * Completion of PTP TX packet. Length = 32B\n-\t */\n-\t#define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)\n \t/*\n \t * TX L2 Packet Timestamp completion:\n \t * Completion of an L2 Packet Timestamp Packet. Length = 16B\n \t */\n-\t#define CMPL_BASE_TYPE_TX_L2_PTP_TS UINT32_C(0x4)\n+\t#define CMPL_BASE_TYPE_TX_L2_PKT_TS UINT32_C(0x4)\n \t/*\n \t * RX L2 TPA Start V2 Completion:\n \t * Completion of and L2 RX packet. Length = 32B\n@@ -4173,47 +4344,79 @@ struct tx_cmpl_coal {\n \t#define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0\n } __rte_packed;\n \n-/* tx_cmpl_ptp (size:128b/16B) */\n-struct tx_cmpl_ptp {\n-\tuint16_t\tflags_type;\n+/* tx_cmpl_packet_timestamp (size:128b/16B) */\n+struct tx_cmpl_packet_timestamp {\n+\tuint16_t\tts_sub_ns_flags_type;\n \t/*\n-\t * This field indicates the exact type of the completion.\n-\t * By convention, the LSB identifies the length of the\n-\t * record in 16B units. Even values indicate 16B\n-\t * records. Odd values indicate 32B\n-\t * records.\n+\t * This field indicates the exact type of the completion. By\n+\t * convention, the LSB identifies the length of the record in 16B\n+\t * units. Even values indicate 16B records. Odd values indicate\n+\t * 32B records.\n \t */\n-\t#define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)\n-\t#define TX_CMPL_PTP_TYPE_SFT 0\n+\t#define TX_CMPL_PACKET_TIMESTAMP_TYPE_MASK UINT32_C(0x3f)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_TYPE_SFT 0\n \t/*\n-\t * TX L2 PTP completion:\n-\t * Completion of TX packet. Length = 32B\n+\t * TX L2 Packet Timestamp completion:\n+\t * Completion of an L2 Packet Timestamp Packet. Length = 16B\n \t */\n-\t#define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)\n-\t#define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP\n-\t#define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)\n-\t#define TX_CMPL_PTP_FLAGS_SFT 6\n+\t#define TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS UINT32_C(0x4)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_TYPE_LAST \\\n+\t\tTX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS\n+\t#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_MASK UINT32_C(0xfc0)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_SFT 6\n \t/*\n-\t * When this bit is '1', it indicates a packet that has an\n-\t * error of some type. Type of error is indicated in\n-\t * error_flags.\n+\t * When this bit is '1', it indicates a packet that has an error\n+\t * of some type. Type of error is indicated in error_flags.\n \t */\n-\t#define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_ERROR UINT32_C(0x40)\n \t/*\n-\t * When this bit is '1', it indicates that the packet completed\n-\t * was transmitted using the push acceleration data provided\n-\t * by the driver. When this bit is '0', it indicates that the\n-\t * packet had not push acceleration data written or was executed\n-\t * as a normal packet even though push data was provided.\n+\t * This field indicates the TX packet timestamp type that is\n+\t * represented by a TX Packet Timestamp Completion. Note that\n+\t * this field is invalid if the timestamp_invalid_error flag\n+\t * is set.\n \t */\n-\t#define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)\n-\t/* unused1 is 16 b */\n-\tuint16_t\tunused_0;\n+\t#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE UINT32_C(0x80)\n+\t/* The packet timestamp came from PM. */\n+\t#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PM \\\n+\t\t(UINT32_C(0x0) << 7)\n+\t/* The packet timestamp came from PA. */\n+\t#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA \\\n+\t\t(UINT32_C(0x1) << 7)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_LAST \\\n+\t\tTX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA\n+\t/*\n+\t * This flag indicates that the timestamp should have come from PM,\n+\t * but came instead from PA because all PM timestamp resources were\n+\t * in use. This can occur in the following circumstances:\n+\t * 1. The BD specified ts_2cmpl_auto and the packet was a PTP packet\n+\t * but PA could not request a PM timestamp\n+\t * 2. The BD specified ts_2cmpl_pm, but PA could not request a PM\n+\t * timestamp\n+\t */\n+\t#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_FALLBACK UINT32_C(0x100)\n+\t/*\n+\t * For 2-step PTP timestamps, bits[3:0] of this field represent the\n+\t * sub-nanosecond portion of the packet timestamp, returned from PM\n+\t * for 2-step PTP timestamps. For PA timestamps, this field also\n+\t * represents the sub-nanosecond portion of the packet timestamp;\n+\t * however, due to synchronization uncertainties, the accuracy of\n+\t * PA timestamps is limited to approximately +/- 4 ns. Therefore\n+\t * this field is of dubious value for PA timestamps.\n+\t */\n+\t#define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_MASK UINT32_C(0xf000)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_SFT 12\n+\t/*\n+\t * This is bits [47:32] of the nanoseconds portion of the packet\n+\t * timestamp, returned from PM for 2-step PTP timestamps or from\n+\t * PA for PA timestamps. This field is in units of 2^32 ns.\n+\t */\n+\tuint16_t\tts_ns_mid;\n \t/*\n \t * This is a copy of the opaque field from the first TX BD of this\n-\t * transmitted packet. Note that, if the packet was described by a short\n-\t * CSO or short CSO inline BD, then the 16-bit opaque field from the\n-\t * short CSO BD will appear in the bottom 16 bits of this field.\n+\t * transmitted packet. Note that, if the packet was described by a\n+\t * short CSO or short CSO inline BD, then the 16-bit opaque field\n+\t * from the short CSO BD will appear in the bottom 16 bits of this\n+\t * field.\n \t */\n \tuint32_t\topaque;\n \tuint16_t\terrors_v;\n@@ -4222,95 +4425,103 @@ struct tx_cmpl_ptp {\n \t * for each pass through the completion queue. The even passes\n \t * will write 1. The odd passes will write 0.\n \t */\n-\t#define TX_CMPL_PTP_V UINT32_C(0x1)\n-\t#define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)\n-\t#define TX_CMPL_PTP_ERRORS_SFT 1\n+\t#define TX_CMPL_PACKET_TIMESTAMP_V \\\n+\t\tUINT32_C(0x1)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_MASK \\\n+\t\tUINT32_C(0xfffe)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_SFT 1\n \t/*\n-\t * This error indicates that there was some sort of problem\n-\t * with the BDs for the packet.\n+\t * This field was previously used to indicate fatal errors, which\n+\t * now result in aborting and bringing down the ring. This field\n+\t * is deprecated.\n \t */\n-\t#define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)\n-\t#define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1\n-\t/* No error */\n-\t#define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \\\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_MASK \\\n+\t\tUINT32_C(0xe)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_SFT 1\n+\t/* No error. */\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_NO_ERROR \\\n \t\t(UINT32_C(0x0) << 1)\n-\t/*\n-\t * Bad Format:\n-\t * BDs were not formatted correctly.\n-\t */\n-\t#define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \\\n+\t/* Deprecated. */\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT \\\n \t\t(UINT32_C(0x2) << 1)\n-\t#define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \\\n-\t\tTX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_LAST \\\n+\t\tTX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT\n \t/*\n-\t * When this bit is '1', it indicates that the length of\n-\t * the packet was zero. No packet was transmitted.\n+\t * This error is fatal and results in aborting and bringing down the\n+\t * ring, thus is deprecated.\n \t */\n-\t#define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)\n-\t/*\n-\t * When this bit is '1', it indicates that the packet\n-\t * was longer than the programmed limit in TDI. No\n-\t * packet was transmitted.\n-\t */\n-\t#define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_ZERO_LENGTH_PKT \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * When this bit is '1', it indicates that one or more of the\n-\t * BDs associated with this packet generated a PCI error.\n-\t * This probably means the address was not valid.\n+\t * This error is fatal and results in aborting and bringing down the\n+\t * ring, thus is deprecated.\n \t */\n-\t#define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_EXCESSIVE_BD_LENGTH \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * When this bit is '1', it indicates that the packet was longer\n-\t * than indicated by the hint. No packet was transmitted.\n+\t * When this bit is '1', it indicates that one or more of the BDs\n+\t * associated with this packet generated a PCI error when accessing\n+\t * header/payload data from host memory. It most likely indicates\n+\t * that the address was not valid. Note that this bit has no meaning\n+\t * for the timestamp completion and will always be '0'.\n \t */\n-\t#define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_DMA_ERROR \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * When this bit is '1', it indicates that the packet was\n-\t * dropped due to Poison TLP error on one or more of the\n-\t * TLPs in the PXP completion.\n+\t * This error is fatal and results in aborting and bringing down the\n+\t * ring, thus is deprecated.\n \t */\n-\t#define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_HINT_TOO_SHORT \\\n+\t\tUINT32_C(0x80)\n \t/*\n-\t * When this bit is '1', it indicates that the packet was dropped due\n-\t * to a transient internal error in TDC. The packet or LSO can be\n-\t * retried and may transmit successfully on a subsequent attempt.\n+\t * When this bit is '1', it indicates that the packet was dropped\n+\t * due to Poison TLP error on one or more of the TLPs in one or more\n+\t * of the associated PXP completion(s) when accessing header/payload\n+\t * data from host memory. Note that this bit has no meaning for the\n+\t * timestamp completion, and will always be '0'.\n \t */\n-\t#define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_POISON_TLP_ERROR \\\n+\t\tUINT32_C(0x100)\n \t/*\n-\t * When this bit is '1', it was not possible to collect a a timestamp\n-\t * for a PTP completion, in which case the timestamp_hi and\n-\t * timestamp_lo fields are invalid. When this bit is '0' for a PTP\n-\t * completion, the timestamp_hi and timestamp_lo fields are valid.\n-\t * RJRN will copy the value of this bit into the field of the same\n-\t * name in all TX completions, regardless of whether such\n-\t * completions are PTP completions or other TX completions.\n+\t * When this bit is '1', it indicates that the packet was dropped\n+\t * due to a transient internal error in TDC. The packet or LSO can\n+\t * be retried and may transmit successfully on a subsequent attempt.\n+\t * Note that this bit has no meaning for the timestamp completion\n+\t * and will always be '0'.\n \t */\n-\t#define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)\n-\t/* unused2 is 16 b */\n-\tuint16_t\tunused_1;\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_INTERNAL_ERROR \\\n+\t\tUINT32_C(0x200)\n \t/*\n-\t * This is timestamp value (lower 32bits) read from PM for the PTP\n-\t * timestamp enabled packet.\n-\t */\n-\tuint32_t\ttimestamp_lo;\n-} __rte_packed;\n-\n-/* tx_cmpl_ptp_hi (size:128b/16B) */\n-struct tx_cmpl_ptp_hi {\n+\t * When this bit is '1', it was not possible to collect a timestamp\n+\t * for a timestamp completion, in which case the ts_ns and ts_sub_ns\n+\t * fields are invalid. When this bit is '0' in a timestamp\n+\t * completion record, the ts_sub_ns, ts_ns_lo, and ts_ns_mid fields\n+\t * are valid. Note that this bit has meaning only for the timestamp\n+\t * completion. For types other than the timestamp completion, this\n+\t * bit will always be '0'.\n+\t */\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TIMESTAMP_INVALID_ERROR \\\n+\t\tUINT32_C(0x400)\n \t/*\n-\t * This is timestamp value (lower 32bits) read from PM for the PTP\n-\t * timestamp enabled packet.\n+\t * When this bit is '1', it indicates that a Timed Transmit\n+\t * SO-TXTIME packet violated the max_ttx_overtime constraint i.e.,\n+\t * the time the packet was processed for transmission in TWE was\n+\t * later than the time given by (TimedTx_BD.tx_time +\n+\t * max_ttx_overtime) and as result, the packet was dropped.\n+\t * Note that max_ttx_overtime is a global configuration in TWE.\n+\t * Note that this bit has no meaning in a timestamp completion,\n+\t * and will always be '0'.\n \t */\n-\tuint16_t\ttimestamp_hi[3];\n-\tuint16_t\treserved16;\n-\tuint64_t\tv2;\n+\t#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TTX_OVERTIME_ERROR \\\n+\t\tUINT32_C(0x800)\n+\t/* unused2 is 16 b */\n+\tuint16_t\tunused_2;\n \t/*\n-\t * This value is written by the NIC such that it will be different for\n-\t * each pass through the completion queue.\n-\t * The even passes will write 1.\n-\t * The odd passes will write 0.\n+\t * This is bits [31:0] of the nanoseconds portion of the packet\n+\t * timestamp, returned from PM for 2-step PTP timestamp or from\n+\t * PA for PA timestamps. This field is in units of ns.\n \t */\n-\t#define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)\n+\tuint32_t\tts_ns_lo;\n } __rte_packed;\n \n /* rx_pkt_cmpl (size:128b/16B) */\n@@ -9314,9 +9525,31 @@ struct hwrm_async_event_cmpl {\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD \\\n \t\tUINT32_C(0x46)\n+\t/*\n+\t * An event from firmware indicating that the RSS capabilities have\n+\t * changed.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE \\\n+\t\tUINT32_C(0x47)\n+\t/*\n+\t * An event from firmware indicating that list of nq ids used for\n+\t * doorbell pacing DBQ event notification has been updated. The driver\n+\t * needs to take appropriate action and retrieve the new list when this\n+\t * event is received from the firmware.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE \\\n+\t\tUINT32_C(0x48)\n+\t/*\n+\t * An event from firmware indicating that hardware ran into an error\n+\t * while trying to read the host based doorbell copy region. The driver\n+\t * needs to take the appropriate action and maintain the corresponding\n+\t * doorbell copy region.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \\\n+\t\tUINT32_C(0x49)\n \t/* Maximum Registrable event id. */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \\\n-\t\tUINT32_C(0x47)\n+\t\tUINT32_C(0x4a)\n \t/*\n \t * A trace log message. This contains firmware trace logs string\n \t * embedded in the asynchronous message. This is an experimental\n@@ -11828,6 +12061,195 @@ struct hwrm_async_event_cmpl_doorbell_pacing_threshold {\n \tuint32_t\tevent_data1;\n } __rte_packed;\n \n+/* hwrm_async_event_cmpl_rss_change (size:128b/16B) */\n+struct hwrm_async_event_cmpl_rss_change {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_SFT 0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/*\n+\t * This async notification message is used to inform the driver\n+\t * that the RSS capabilities have changed. The driver will need\n+\t * to query hwrm_vnic_qcaps.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE \\\n+\t\tUINT32_C(0x47)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE\n+\t/* Event specific data. */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_V UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+} __rte_packed;\n+\n+/* hwrm_async_event_cmpl_doorbell_pacing_nq_update (size:128b/16B) */\n+struct hwrm_async_event_cmpl_doorbell_pacing_nq_update {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_SFT \\\n+\t\t0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/*\n+\t * An event from firmware indicating that list of nq ids used for\n+\t * doorbell pacing DBQ event notification has been updated. The driver\n+\t * needs to take appropriate action and retrieve the new list when this\n+\t * event is received from the firmware.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE \\\n+\t\tUINT32_C(0x48)\n+\t#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE\n+\t/* Event specific data. */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_V \\\n+\t\tUINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+} __rte_packed;\n+\n+/* hwrm_async_event_cmpl_hw_doorbell_recovery_read_error (size:128b/16B) */\n+struct hwrm_async_event_cmpl_hw_doorbell_recovery_read_error {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_SFT \\\n+\t\t0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/*\n+\t * This async notification message is used to inform the driver\n+\t * that hardware ran into an error while trying to read the host\n+\t * based doorbell copy region. The driver will take the appropriate\n+\t * action to maintain the corresponding functions doorbell copy\n+\t * region in the correct format.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \\\n+\t\tUINT32_C(0x49)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR\n+\t/* Event specific data. */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_V \\\n+\t\tUINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_SFT \\\n+\t\t1\n+\t/* 8-lsb timestamp (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/*\n+\t * Indicates that there is an error while reading the doorbell copy\n+\t * regions.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SFT \\\n+\t\t0\n+\t/*\n+\t * If set to 1, indicates that there is an error while reading the\n+\t * SQ doorbell copy region for this function.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SQ_ERR \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, indicates that there is an error while reading the\n+\t * RQ doorbell copy region for this function.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_RQ_ERR \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, indicates that there is an error while reading the\n+\t * SRQ doorbell copy region for this function.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SRQ_ERR \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, indicates that there is an error while reading the\n+\t * CQ doorbell copy region for this function.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR \\\n+\t\tUINT32_C(0x8)\n+} __rte_packed;\n+\n /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */\n struct hwrm_async_event_cmpl_fw_trace_msg {\n \tuint16_t\ttype;\n@@ -12385,6 +12807,14 @@ struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {\n \t\tUINT32_C(0x4)\n \t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \\\n \t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD\n+\t/*\n+\t * The epoch value to be sent from firmware to the driver to track\n+\t * a doorbell recovery cycle.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK \\\n+\t\tUINT32_C(0xffffff00)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT \\\n+\t\t8\n } __rte_packed;\n \n /* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */\n@@ -12516,8 +12946,8 @@ struct metadata_base_msg {\n \t#define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)\n \t/*\n \t * This setting is used when packets are coming in-order. Depending on\n-\t * the state of the receive context, the meta-data will carry different\n-\t * information.\n+\t * the state of the receive context, the meta-data will carry\n+\t * different information.\n \t */\n \t#define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)\n \t/*\n@@ -12525,12 +12955,21 @@ struct metadata_base_msg {\n \t * record that it is requesting a resync on in the meta data.\n \t */\n \t#define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)\n+\t/* This setting is used for QUIC packets. */\n+\t#define METADATA_BASE_MSG_MD_TYPE_QUIC UINT32_C(0x3)\n+\t/*\n+\t * This setting is used for crypto packets with an unsupported\n+\t * protocol.\n+\t */\n+\t#define METADATA_BASE_MSG_MD_TYPE_ILLEGAL UINT32_C(0x1f)\n \t#define METADATA_BASE_MSG_MD_TYPE_LAST \\\n-\t\tMETADATA_BASE_MSG_MD_TYPE_TLS_RESYNC\n+\t\tMETADATA_BASE_MSG_MD_TYPE_ILLEGAL\n \t/*\n-\t * This field indicates where the next metadata block starts. It is\n-\t * counted in 16B units. A value of zero indicates that there is no\n-\t * metadata.\n+\t * This field indicates where the next metadata block starts, relative\n+\t * to the current metadata block. It is the offset to the next metadata\n+\t * header, counted in 16B units. A value of zero indicates that there is\n+\t * no additional metadata, and that the current metadata block is the\n+\t * last one.\n \t */\n \t#define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)\n \t#define METADATA_BASE_MSG_LINK_SFT 5\n@@ -12544,11 +12983,12 @@ struct tls_metadata_base_msg {\n \t/* This field classifies the data present in the meta-data. */\n \t#define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \\\n \t\tUINT32_C(0x1f)\n-\t#define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0\n+\t#define TLS_METADATA_BASE_MSG_MD_TYPE_SFT \\\n+\t\t0\n \t/*\n-\t * This setting is used when packets are coming in-order. Depending on\n-\t * the state of the receive context, the meta-data will carry different\n-\t * information.\n+\t * This setting is used when packets are coming in-order. Depending\n+\t * on the state of the receive context, the meta-data will carry\n+\t * different information.\n \t */\n \t#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \\\n \t\tUINT32_C(0x1)\n@@ -12567,11 +13007,13 @@ struct tls_metadata_base_msg {\n \t */\n \t#define TLS_METADATA_BASE_MSG_LINK_MASK \\\n \t\tUINT32_C(0x1e0)\n-\t#define TLS_METADATA_BASE_MSG_LINK_SFT 5\n+\t#define TLS_METADATA_BASE_MSG_LINK_SFT \\\n+\t\t5\n \t/* These are flags present in the metadata. */\n \t#define TLS_METADATA_BASE_MSG_FLAGS_MASK \\\n \t\tUINT32_C(0x1fffe00)\n-\t#define TLS_METADATA_BASE_MSG_FLAGS_SFT 9\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_SFT \\\n+\t\t9\n \t/*\n \t * A value of 1 implies that the packet was decrypted by HW. Otherwise\n \t * the packet is passed on as it came in on the wire.\n@@ -12584,7 +13026,8 @@ struct tls_metadata_base_msg {\n \t */\n \t#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \\\n \t\tUINT32_C(0xc00)\n-\t#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT \\\n+\t\t10\n \t/*\n \t * This enumeration states that the ghash is not valid in the\n \t * meta-data.\n@@ -12610,12 +13053,13 @@ struct tls_metadata_base_msg {\n \t/* This field indicates the status of tag authentication. */\n \t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \\\n \t\tUINT32_C(0x3000)\n-\t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT \\\n+\t\t12\n \t/*\n-\t * This enumeration is set when there is no tags present in the\n-\t * packet.\n+\t * This enumeration is set when HW was not able to authenticate a\n+\t * TAG.\n \t */\n-\t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \\\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \\\n \t\t(UINT32_C(0x0) << 12)\n \t/*\n \t * This enumeration states that there is at least one tag in the\n@@ -12638,13 +13082,61 @@ struct tls_metadata_base_msg {\n \t */\n \t#define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \\\n \t\tUINT32_C(0x4000)\n+\t/*\n+\t * A value of 1 indicates that the packet experienced a context load\n+\t * error. In this case, the packet is sent to the host without the\n+\t * header or payload decrypted and the context is not updated.\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_CTX_LOAD_ERR \\\n+\t\tUINT32_C(0x8000)\n+\t/* This field indicates the packet operation state. */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_MASK \\\n+\t\tUINT32_C(0x70000)\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_SFT \\\n+\t\t16\n+\t/* Packet is in order. */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \\\n+\t\t(UINT32_C(0x0) << 16)\n+\t/* Packet is out of order, no header loss. */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \\\n+\t\t(UINT32_C(0x1) << 16)\n+\t/* Packet is header search (out of order with header loss). */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \\\n+\t\t(UINT32_C(0x2) << 16)\n+\t/* Packet is resync (resync record ongoing). */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \\\n+\t\t(UINT32_C(0x3) << 16)\n+\t/*\n+\t * Packet is resync wait (resync record completes, waiting for\n+\t * result).\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \\\n+\t\t(UINT32_C(0x4) << 16)\n+\t/*\n+\t * Packet is resync wait for partial tag (waiting for resync record\n+\t * tag).\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \\\n+\t\t(UINT32_C(0x5) << 16)\n+\t/* Packet is resync success (got resync record success). */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \\\n+\t\t(UINT32_C(0x6) << 16)\n+\t/*\n+\t * Packet is resync success wait (got midpath ACK, waiting for\n+\t * resync record success).\n+\t */\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \\\n+\t\t(UINT32_C(0x7) << 16)\n+\t#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_LAST \\\n+\t\tTLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT\n \t/*\n \t * This value indicates the lower 7-bit of the Crypto Key ID\n \t * associated with this operation.\n \t */\n \t#define TLS_METADATA_BASE_MSG_KID_LO_MASK \\\n \t\tUINT32_C(0xfe000000)\n-\t#define TLS_METADATA_BASE_MSG_KID_LO_SFT 25\n+\t#define TLS_METADATA_BASE_MSG_KID_LO_SFT \\\n+\t\t25\n \tuint16_t\tkid_hi;\n \t/*\n \t * This value indicates the upper 13-bit of the Crypto Key ID\n@@ -12661,11 +13153,12 @@ struct tls_metadata_insync_msg {\n \t/* This field classifies the data present in the meta-data. */\n \t#define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \\\n \t\tUINT32_C(0x1f)\n-\t#define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0\n+\t#define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT \\\n+\t\t0\n \t/*\n \t * This setting is used when packets are coming in-order. Depending on\n-\t * the state of the receive context, the meta-data will carry different\n-\t * information.\n+\t * the state of the receive context, the meta-data will carry\n+\t * different information.\n \t */\n \t#define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \\\n \t\tUINT32_C(0x1)\n@@ -12678,11 +13171,13 @@ struct tls_metadata_insync_msg {\n \t */\n \t#define TLS_METADATA_INSYNC_MSG_LINK_MASK \\\n \t\tUINT32_C(0x1e0)\n-\t#define TLS_METADATA_INSYNC_MSG_LINK_SFT 5\n+\t#define TLS_METADATA_INSYNC_MSG_LINK_SFT \\\n+\t\t5\n \t/* These are flags present in the metadata. */\n \t#define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \\\n \t\tUINT32_C(0x1fffe00)\n-\t#define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_SFT \\\n+\t\t9\n \t/*\n \t * A value of 1 implies that the packet was decrypted by HW. Otherwise\n \t * the packet is passed on as it came in on the wire.\n@@ -12695,7 +13190,8 @@ struct tls_metadata_insync_msg {\n \t */\n \t#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \\\n \t\tUINT32_C(0xc00)\n-\t#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT \\\n+\t\t10\n \t/*\n \t * This enumeration states that the ghash is not valid in the\n \t * meta-data.\n@@ -12721,12 +13217,13 @@ struct tls_metadata_insync_msg {\n \t/* This field indicates the status of tag authentication. */\n \t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \\\n \t\tUINT32_C(0x3000)\n-\t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT \\\n+\t\t12\n \t/*\n-\t * This enumeration is set when there is no tags present in the\n-\t * packet.\n+\t * This enumeration is set when HW was not able to authenticate a\n+\t * TAG.\n \t */\n-\t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \\\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \\\n \t\t(UINT32_C(0x0) << 12)\n \t/*\n \t * This enumeration states that there is at least one tag in the\n@@ -12749,13 +13246,61 @@ struct tls_metadata_insync_msg {\n \t */\n \t#define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \\\n \t\tUINT32_C(0x4000)\n+\t/*\n+\t * A value of 1 indicates that the packet experienced a context load\n+\t * error. In this case, the packet is sent to the host without the\n+\t * header or payload decrypted and the context is not updated.\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_CTX_LOAD_ERR \\\n+\t\tUINT32_C(0x8000)\n+\t/* This field indicates the packet operation state. */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK \\\n+\t\tUINT32_C(0x70000)\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_SFT \\\n+\t\t16\n+\t/* Packet is in order. */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \\\n+\t\t(UINT32_C(0x0) << 16)\n+\t/* Packet is out of order, no header loss. */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \\\n+\t\t(UINT32_C(0x1) << 16)\n+\t/* Packet is header search (out of order with header loss). */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \\\n+\t\t(UINT32_C(0x2) << 16)\n+\t/* Packet is resync (resync record ongoing). */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \\\n+\t\t(UINT32_C(0x3) << 16)\n+\t/*\n+\t * Packet is resync wait (resync record completes, waiting for\n+\t * result).\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \\\n+\t\t(UINT32_C(0x4) << 16)\n+\t/*\n+\t * Packet is resync wait for partial tag (waiting for resync record\n+\t * tag).\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \\\n+\t\t(UINT32_C(0x5) << 16)\n+\t/* Packet is resync success (got resync record success). */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \\\n+\t\t(UINT32_C(0x6) << 16)\n+\t/*\n+\t * Packet is resync success wait (got midpath ACK, waiting for\n+\t * resync record success).\n+\t */\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \\\n+\t\t(UINT32_C(0x7) << 16)\n+\t#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_LAST \\\n+\t\tTLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT\n \t/*\n \t * This value indicates the lower 7-bit of the Crypto Key ID\n \t * associated with this operation.\n \t */\n \t#define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \\\n \t\tUINT32_C(0xfe000000)\n-\t#define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25\n+\t#define TLS_METADATA_INSYNC_MSG_KID_LO_SFT \\\n+\t\t25\n \tuint16_t\tkid_hi;\n \t/*\n \t * This value indicates the upper 13-bit of the Crypto Key ID\n@@ -12764,14 +13309,14 @@ struct tls_metadata_insync_msg {\n \t#define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)\n \t#define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0\n \t/*\n-\t * This field is only valid when md_type is set to tls_insync. This field\n-\t * indicates the offset within the current TCP packet where the TLS header\n-\t * starts. If there are multiple TLS headers in the packet, this provides\n-\t * the offset of the last TLS header.\n+\t * This field is only valid when md_type is set to tls_insync. This\n+\t * field indicates the offset within the current TCP packet where the\n+\t * TLS header starts. If there are multiple TLS headers in the packet,\n+\t * this provides the offset of the last TLS header.\n \t *\n-\t * The field is calculated by subtracting TCP sequence number of the first\n-\t * byte of the TCP payload of the packet from the TCP sequence number of\n-\t * the last TLS header in the packet.\n+\t * The field is calculated by subtracting TCP sequence number of the\n+\t * first byte of the TCP payload of the packet from the TCP sequence\n+\t * number of the last TLS header in the packet.\n \t */\n \tuint16_t\ttls_header_offset;\n \t/*\n@@ -12787,7 +13332,7 @@ struct tls_metadata_insync_msg {\n \t * not decrypt every packet and authenticate the record. Partial GHASH is\n \t * only sent out with packet having the TAG field.\n \t */\n-\tuint64_t\tpartial_ghash;\n+\tuint8_t\tpartial_ghash[8];\n } __rte_packed;\n \n /* tls_metadata_resync_msg (size:256b/32B) */\n@@ -12796,7 +13341,8 @@ struct tls_metadata_resync_msg {\n \t/* This field classifies the data present in the meta-data. */\n \t#define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \\\n \t\tUINT32_C(0x1f)\n-\t#define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0\n+\t#define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT \\\n+\t\t0\n \t/*\n \t * With this setting HW passes the TCP sequence number of the TLS\n \t * record that it is requesting a resync on in the meta data.\n@@ -12812,11 +13358,13 @@ struct tls_metadata_resync_msg {\n \t */\n \t#define TLS_METADATA_RESYNC_MSG_LINK_MASK \\\n \t\tUINT32_C(0x1e0)\n-\t#define TLS_METADATA_RESYNC_MSG_LINK_SFT 5\n+\t#define TLS_METADATA_RESYNC_MSG_LINK_SFT \\\n+\t\t5\n \t/* These are flags present in the metadata. */\n \t#define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \\\n \t\tUINT32_C(0x1fffe00)\n-\t#define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_SFT \\\n+\t\t9\n \t/*\n \t * A value of 1 implies that the packet was decrypted by HW. Otherwise\n \t * the packet is passed on as it came in on the wire.\n@@ -12829,7 +13377,8 @@ struct tls_metadata_resync_msg {\n \t */\n \t#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \\\n \t\tUINT32_C(0xc00)\n-\t#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT \\\n+\t\t10\n \t/*\n \t * This enumeration states that the ghash is not valid in the\n \t * meta-data.\n@@ -12841,28 +13390,77 @@ struct tls_metadata_resync_msg {\n \t/* This field indicates the status of tag authentication. */\n \t#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \\\n \t\tUINT32_C(0x3000)\n-\t#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT \\\n+\t\t12\n \t/*\n-\t * This enumeration is set when there is no tags present in the\n-\t * packet.\n+\t * This enumeration is set when HW was not able to authenticate a\n+\t * TAG.\n \t */\n-\t#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \\\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \\\n \t\t(UINT32_C(0x0) << 12)\n \t#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \\\n-\t\tTLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE\n+\t\tTLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED\n \t/*\n \t * A value of 1 indicates that this packet contains a record that\n \t * starts in the packet and extends beyond the packet.\n \t */\n \t#define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \\\n \t\tUINT32_C(0x4000)\n+\t/*\n+\t * A value of 1 indicates that the packet experienced a context load\n+\t * error. In this case, the packet is sent to the host without the\n+\t * header or payload decrypted and the context is not updated.\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_CTX_LOAD_ERR \\\n+\t\tUINT32_C(0x8000)\n+\t/* This field indicates the packet operation state. */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK \\\n+\t\tUINT32_C(0x70000)\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_SFT \\\n+\t\t16\n+\t/* Packet is in order. */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \\\n+\t\t(UINT32_C(0x0) << 16)\n+\t/* Packet is out of order, no header loss. */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \\\n+\t\t(UINT32_C(0x1) << 16)\n+\t/* Packet is header search (out of order with header loss). */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \\\n+\t\t(UINT32_C(0x2) << 16)\n+\t/* Packet is resync (resync record ongoing). */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \\\n+\t\t(UINT32_C(0x3) << 16)\n+\t/*\n+\t * Packet is resync wait (resync record completes, waiting for\n+\t * result).\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \\\n+\t\t(UINT32_C(0x4) << 16)\n+\t/*\n+\t * Packet is resync wait for partial tag (waiting for resync record\n+\t * tag).\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \\\n+\t\t(UINT32_C(0x5) << 16)\n+\t/* Packet is resync success (got resync record success). */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \\\n+\t\t(UINT32_C(0x6) << 16)\n+\t/*\n+\t * Packet is resync success wait (got midpath ACK, waiting for\n+\t * resync record success).\n+\t */\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \\\n+\t\t(UINT32_C(0x7) << 16)\n+\t#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_LAST \\\n+\t\tTLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT\n \t/*\n \t * This value indicates the lower 7-bit of the Crypto Key ID\n \t * associated with this operation.\n \t */\n \t#define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \\\n \t\tUINT32_C(0xfe000000)\n-\t#define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25\n+\t#define TLS_METADATA_RESYNC_MSG_KID_LO_SFT \\\n+\t\t25\n \tuint16_t\tkid_hi;\n \t/*\n \t * This value indicates the upper 13-bit of the Crypto Key ID\n@@ -13221,7 +13819,7 @@ struct hwrm_func_vf_free_output {\n ********************/\n \n \n-/* hwrm_func_vf_cfg_input (size:448b/56B) */\n+/* hwrm_func_vf_cfg_input (size:512b/64B) */\n struct hwrm_func_vf_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -13384,7 +13982,7 @@ struct hwrm_func_vf_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of TX rings) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \\\n@@ -13393,7 +13991,7 @@ struct hwrm_func_vf_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of RX rings) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \\\n@@ -13402,7 +14000,7 @@ struct hwrm_func_vf_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of CMPL rings) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \\\n@@ -13411,7 +14009,7 @@ struct hwrm_func_vf_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of RSS ctx) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \\\n@@ -13420,7 +14018,7 @@ struct hwrm_func_vf_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of ring groups) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \\\n@@ -13429,7 +14027,7 @@ struct hwrm_func_vf_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of stat ctx) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \\\n@@ -13438,7 +14036,7 @@ struct hwrm_func_vf_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of VNICs) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \\\n@@ -13447,7 +14045,7 @@ struct hwrm_func_vf_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of L2 ctx) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \\\n@@ -13486,9 +14084,10 @@ struct hwrm_func_vf_cfg_input {\n \t/* The number of HW ring groups requested for the VF. */\n \tuint16_t\tnum_hw_ring_grps;\n \t/* Number of Tx Key Contexts requested. */\n-\tuint16_t\tnum_tx_key_ctxs;\n+\tuint32_t\tnum_tx_key_ctxs;\n \t/* Number of Rx Key Contexts requested. */\n-\tuint16_t\tnum_rx_key_ctxs;\n+\tuint32_t\tnum_rx_key_ctxs;\n+\tuint8_t\tunused[4];\n } __rte_packed;\n \n /* hwrm_func_vf_cfg_output (size:128b/16B) */\n@@ -13558,7 +14157,7 @@ struct hwrm_func_qcaps_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_func_qcaps_output (size:768b/96B) */\n+/* hwrm_func_qcaps_output (size:896b/112B) */\n struct hwrm_func_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -14176,6 +14775,74 @@ struct hwrm_func_qcaps_output {\n \t/* When this bit is '1', it indicates that HW and FW support QUIC. */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED \\\n \t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', it indicates that KDNet mode is\n+\t * supported on the port for this function. This bit is\n+\t * never set for a VF.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', it indicates the FW is capable of\n+\t * supporting Enhanced Doorbell Pacing.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', it indicates that FW is capable of\n+\t * supporting software based doorbell drop recovery.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * When this bit is '1', it indicates the FW supports collection\n+\t * and query of the generic statistics.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_GENERIC_STATS_SUPPORTED \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1', it indicates that the HW is capable of\n+\t * supporting UDP GSO on the function.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDP_GSO_SUPPORTED \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', it indicates that SyncE feature is\n+\t * supported.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SYNCE_SUPPORTED \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * When this bit is '1', it indicates the FW is capable of\n+\t * supporting doorbell pacing version 0. As doorbell pacing\n+\t * notification from hardware for Thor2 is completely different\n+\t * from Thor1, this flag is used to differentiate the doorbell\n+\t * pacing notification between Thor1 and Thor2. Thor1 uses\n+\t * dbr_pacing_supported and dbr_pacing_ext_supported flags for\n+\t * doorbell pacing whereas Thor2 uses dbr_pacing_v0_supported flag.\n+\t * These flags will never be set at the same time for Thor2.\n+\t * Based on this flag, host drivers assume doorbell pacing is needed\n+\t * for Thor2.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * When this bit is '1', it indicates that the HW supports\n+\t * two-completion TX packet timestamp feature, a second completion\n+\t * carrying packet TX timestamp in addition to the standard\n+\t * completion returned for packets. Host driver should not use\n+\t * HWRM port timestamp query (HWRM_PORT_TS_QUERY) command for\n+\t * TX timestamp read when two-completion timestamp feature is\n+\t * supported.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * When this bit is '1', it indicates that the hardware based\n+\t * link aggregation group (L2 and RoCE) feature is supported.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED \\\n+\t\tUINT32_C(0x400)\n \tuint16_t\ttunnel_disable_flag;\n \t/*\n \t * When this bit is '1', it indicates that the VXLAN parsing\n@@ -14225,7 +14892,16 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE \\\n \t\tUINT32_C(0x80)\n-\tuint8_t\tunused_1;\n+\tuint8_t\tunused_1[2];\n+\t/*\n+\t * This value uniquely identifies the hardware NIC used by the\n+\t * function. The value returned will be the same for all functions.\n+\t * A value of 00-00-00-00-00-00-00-00 indicates no device serial number\n+\t * is currently configured. This is the same value that is returned by\n+\t * PCIe Capability Device Serial Number.\n+\t */\n+\tuint8_t\tdevice_serial_number[8];\n+\tuint8_t\tunused_2[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -14283,7 +14959,7 @@ struct hwrm_func_qcfg_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_func_qcfg_output (size:896b/112B) */\n+/* hwrm_func_qcfg_output (size:1024b/128B) */\n struct hwrm_func_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -14787,7 +15463,36 @@ struct hwrm_func_qcfg_output {\n \t */\n \t#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \\\n \t\tUINT32_C(0x10)\n-\tuint8_t\tunused_2[3];\n+\t/*\n+\t * Configured doorbell page size for this function.\n+\t * This field is valid for PF only.\n+\t */\n+\tuint8_t\tdb_page_size;\n+\t/* DB page size is 4KB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0)\n+\t/* DB page size is 8KB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1)\n+\t/* DB page size is 16KB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2)\n+\t/* DB page size is 32KB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3)\n+\t/* DB page size is 64KB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4)\n+\t/* DB page size is 128KB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)\n+\t/* DB page size is 256KB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)\n+\t/* DB page size is 512KB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)\n+\t/* DB page size is 1MB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8)\n+\t/* DB page size is 2MB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9)\n+\t/* DB page size is 4MB. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa)\n+\t#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_LAST \\\n+\t\tHWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB\n+\tuint8_t\tunused_2[2];\n \t/*\n \t * Minimum guaranteed bandwidth for the network partition made up\n \t * of the caller physical function and all its child virtual\n@@ -14874,11 +15579,36 @@ struct hwrm_func_qcfg_output {\n \t * value is used if ring MTU is not specified.\n \t */\n \tuint16_t\thost_mtu;\n+\tuint8_t\tunused_3[2];\n+\tuint8_t\tunused_4[2];\n+\t/*\n+\t * KDNet mode for the port for this function. If a VF, KDNet\n+\t * mode is always disabled.\n+\t */\n+\tuint8_t\tport_kdnet_mode;\n+\t/* KDNet mode is not enabled on the port for this function. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)\n+\t/* KDNet mode is enabled on the port for this function. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1)\n+\t#define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_LAST \\\n+\t\tHWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED\n+\t/*\n+\t * If KDNet mode is enabled, the PCI function number of the\n+\t * KDNet partition.\n+\t */\n+\tuint8_t\tkdnet_pcie_function;\n+\t/*\n+\t * Function ID of the KDNET function on this port. If the\n+\t * KDNET partition does not exist and the FW supports this\n+\t * feature, 0xffff will be returned.\n+\t */\n+\tuint16_t\tport_kdnet_fid;\n+\tuint8_t\tunused_5[2];\n \t/* Number of Tx Key Contexts allocated. */\n-\tuint16_t\talloc_tx_key_ctxs;\n+\tuint32_t\talloc_tx_key_ctxs;\n \t/* Number of Rx Key Contexts allocated. */\n-\tuint16_t\talloc_rx_key_ctxs;\n-\tuint8_t\tunused_3[5];\n+\tuint32_t\talloc_rx_key_ctxs;\n+\tuint8_t\tunused_6[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -14894,7 +15624,7 @@ struct hwrm_func_qcfg_output {\n *****************/\n \n \n-/* hwrm_func_cfg_input (size:896b/112B) */\n+/* hwrm_func_cfg_input (size:1024b/128B) */\n struct hwrm_func_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -15002,7 +15732,7 @@ struct hwrm_func_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of TX rings) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \\\n@@ -15011,7 +15741,7 @@ struct hwrm_func_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of RX rings) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \\\n@@ -15020,7 +15750,7 @@ struct hwrm_func_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of CMPL rings) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \\\n@@ -15029,7 +15759,7 @@ struct hwrm_func_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of RSS ctx) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \\\n@@ -15038,7 +15768,7 @@ struct hwrm_func_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of ring groups) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \\\n@@ -15047,7 +15777,7 @@ struct hwrm_func_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of stat ctx) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \\\n@@ -15056,7 +15786,7 @@ struct hwrm_func_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of VNICs) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \\\n@@ -15065,7 +15795,7 @@ struct hwrm_func_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of L2 ctx) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \\\n@@ -15091,7 +15821,7 @@ struct hwrm_func_cfg_input {\n \t * This bit requests that the firmware test to see if all the assets\n \t * requested in this command (i.e. number of NQ rings) are available.\n \t * The firmware will return an error if the requested assets are\n-\t * not available. The firwmare will NOT reserve the assets if they\n+\t * not available. The firmware will NOT reserve the assets if they\n \t * are available.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \\\n@@ -15158,6 +15888,15 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \\\n \t\tUINT32_C(0x40000000)\n+\t/*\n+\t * If this bit is set to 1, the driver is requesting FW to see if\n+\t * all the assets requested in this command (i.e. number of KTLS/\n+\t * QUIC key contexts) are available. The firmware will return an\n+\t * error if the requested assets are not available. The firmware\n+\t * will NOT reserve the assets if they are available.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS_KEY_CTX_ASSETS_TEST \\\n+\t\tUINT32_C(0x80000000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the admin_mtu field to be\n@@ -15803,11 +16542,71 @@ struct hwrm_func_cfg_input {\n \t * ring that is assigned to a function has a valid mtu.\n \t */\n \tuint16_t\thost_mtu;\n+\tuint8_t\tunused_0[4];\n+\tuint32_t\tenables2;\n+\t/*\n+\t * This bit must be '1' for the kdnet_mode field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_KDNET UINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the db_page_size field to be\n+\t * configured. Legacy controller core FW may silently ignore\n+\t * the db_page_size programming request through this command.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2)\n+\t/*\n+\t * KDNet mode for the port for this function. If NPAR is\n+\t * also configured on this port, it takes precedence. KDNet\n+\t * mode is ignored for a VF.\n+\t */\n+\tuint8_t\tport_kdnet_mode;\n+\t/* KDNet mode is not enabled. */\n+\t#define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)\n+\t/* KDNet mode enabled. */\n+\t#define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1)\n+\t#define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_LAST \\\n+\t\tHWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED\n+\t/*\n+\t * This field can be used by the PF driver to configure the doorbell\n+\t * page size. L2 driver can use different pages to ring the doorbell\n+\t * for L2 push operation. The doorbell page size should be configured\n+\t * to match the native CPU page size for proper RoCE and L2 doorbell\n+\t * operations. This value supersedes the older method of configuring\n+\t * the doorbell page size by the RoCE driver using the command queue\n+\t * method. The default is 4K.\n+\t */\n+\tuint8_t\tdb_page_size;\n+\t/* DB page size is 4KB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0)\n+\t/* DB page size is 8KB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1)\n+\t/* DB page size is 16KB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2)\n+\t/* DB page size is 32KB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3)\n+\t/* DB page size is 64KB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4)\n+\t/* DB page size is 128KB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)\n+\t/* DB page size is 256KB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)\n+\t/* DB page size is 512KB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)\n+\t/* DB page size is 1MB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8)\n+\t/* DB page size is 2MB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9)\n+\t/* DB page size is 4MB. */\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa)\n+\t#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_LAST \\\n+\t\tHWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB\n+\tuint8_t\tunused_1[2];\n \t/* Number of Tx Key Contexts requested. */\n-\tuint16_t\tnum_tx_key_ctxs;\n+\tuint32_t\tnum_tx_key_ctxs;\n \t/* Number of Rx Key Contexts requested. */\n-\tuint16_t\tnum_rx_key_ctxs;\n-\tuint8_t\tunused_0[4];\n+\tuint32_t\tnum_rx_key_ctxs;\n+\tuint8_t\tunused_2[4];\n } __rte_packed;\n \n /* hwrm_func_cfg_output (size:128b/16B) */\n@@ -15900,24 +16699,27 @@ struct hwrm_func_qstats_input {\n \t * A privileged PF can query for other function's statistics.\n \t */\n \tuint16_t\tfid;\n-\t/* This flags indicates the type of statistics request. */\n \tuint8_t\tflags;\n-\t/* This value is not used to avoid backward compatibility issues. */\n-\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n \t/*\n-\t * flags should be set to 1 when request is for only RoCE statistics.\n-\t * This will be honored only if the caller_fid is a privileged PF.\n-\t * In all other cases FID and caller_fid should be the same.\n+\t * This bit should be set to 1 when request is for only RoCE\n+\t * statistics. This will be honored only if the caller_fid is\n+\t * a privileged PF. In all other cases FID and caller_fid should\n+\t * be the same.\n \t */\n-\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)\n+\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)\n \t/*\n-\t * flags should be set to 2 when request is for the counter mask,\n+\t * This bit should be set to 1 when request is for the counter mask,\n \t * representing the width of each of the stats counters, rather\n \t * than counters themselves.\n \t */\n-\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)\n-\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \\\n-\t\tHWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK\n+\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)\n+\t/*\n+\t * This bit should be set to 1 when request is for only L2\n+\t * statistics. This will be honored only if the caller_fid is\n+\t * a privileged PF. In all other cases FID and caller_fid should\n+\t * be the same.\n+\t */\n+\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_L2_ONLY UINT32_C(0x4)\n \tuint8_t\tunused_0[5];\n } __rte_packed;\n \n@@ -15992,7 +16794,18 @@ struct hwrm_func_qstats_output {\n \tuint64_t\trx_agg_events;\n \t/* Number of aborted aggregations on the function. */\n \tuint64_t\trx_agg_aborts;\n-\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is the sequence of the statistics of a function being\n+\t * cleared. Firmware starts the sequence from zero. It increments\n+\t * the sequence number every time the statistics of the function\n+\t * are cleared, which can be triggered by a clear statistics request\n+\t * or by freeing all statistics contexts of the function. If a user\n+\t * is interested in knowing if the statistics have been cleared\n+\t * since the last query, it can keep track of this sequence number\n+\t * between queries.\n+\t */\n+\tuint8_t\tclear_seq;\n+\tuint8_t\tunused_0[6];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -16045,24 +16858,20 @@ struct hwrm_func_qstats_ext_input {\n \t * A privileged PF can query for other function's statistics.\n \t */\n \tuint16_t\tfid;\n-\t/* This flags indicates the type of statistics request. */\n \tuint8_t\tflags;\n-\t/* This value is not used to avoid backward compatibility issues. */\n-\t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n \t/*\n-\t * flags should be set to 1 when request is for only RoCE statistics.\n-\t * This will be honored only if the caller_fid is a privileged PF.\n-\t * In all other cases FID and caller_fid should be the same.\n+\t * This bit should be set to 1 when request is for only RoCE\n+\t * statistics. This will be honored only if the caller_fid is\n+\t * a privileged PF. In all other cases FID and caller_fid should\n+\t * be the same.\n \t */\n-\t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)\n+\t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)\n \t/*\n-\t * flags should be set to 2 when request is for the counter mask\n+\t * This bit should be set to 1 when request is for the counter mask\n \t * representing the width of each of the stats counters, rather\n \t * than counters themselves.\n \t */\n-\t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)\n-\t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \\\n-\t\tHWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK\n+\t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)\n \tuint8_t\tunused_0[1];\n \tuint32_t\tenables;\n \t/*\n@@ -16418,6 +17227,14 @@ struct hwrm_func_drv_rgtr_input {\n \t */\n \t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \\\n \t\tUINT32_C(0x200)\n+\t/*\n+\t * When this bit is 1, the function's driver is indicating the\n+\t * support for asymmetric queue configuration, such that queue\n+\t * ids and service profiles on TX side are not the same as the\n+\t * corresponding queue configuration on the RX side\n+\t */\n+\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT \\\n+\t\tUINT32_C(0x400)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the os_type field to be\n@@ -16979,7 +17796,7 @@ struct hwrm_func_resource_qcaps_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_func_resource_qcaps_output (size:512b/64B) */\n+/* hwrm_func_resource_qcaps_output (size:576b/72B) */\n struct hwrm_func_resource_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -17054,15 +17871,16 @@ struct hwrm_func_resource_qcaps_output {\n \t */\n \t#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \\\n \t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[2];\n \t/* Minimum guaranteed number of Tx Key Contexts */\n-\tuint16_t\tmin_tx_key_ctxs;\n+\tuint32_t\tmin_tx_key_ctxs;\n \t/* Maximum non-guaranteed number of Tx Key Contexts */\n-\tuint16_t\tmax_tx_key_ctxs;\n+\tuint32_t\tmax_tx_key_ctxs;\n \t/* Minimum guaranteed number of Rx Key Contexts */\n-\tuint16_t\tmin_rx_key_ctxs;\n+\tuint32_t\tmin_rx_key_ctxs;\n \t/* Maximum non-guaranteed number of Rx Key Contexts */\n-\tuint16_t\tmax_rx_key_ctxs;\n-\tuint8_t\tunused_0[5];\n+\tuint32_t\tmax_rx_key_ctxs;\n+\tuint8_t\tunused_1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -17078,7 +17896,7 @@ struct hwrm_func_resource_qcaps_output {\n *****************************/\n \n \n-/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */\n+/* hwrm_func_vf_resource_cfg_input (size:576b/72B) */\n struct hwrm_func_vf_resource_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -17152,18 +17970,18 @@ struct hwrm_func_vf_resource_cfg_input {\n \t */\n \t#define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \\\n \t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[2];\n \t/* Minimum guaranteed number of Tx Key Contexts */\n-\tuint16_t\tmin_tx_key_ctxs;\n+\tuint32_t\tmin_tx_key_ctxs;\n \t/* Maximum non-guaranteed number of Tx Key Contexts */\n-\tuint16_t\tmax_tx_key_ctxs;\n+\tuint32_t\tmax_tx_key_ctxs;\n \t/* Minimum guaranteed number of Rx Key Contexts */\n-\tuint16_t\tmin_rx_key_ctxs;\n+\tuint32_t\tmin_rx_key_ctxs;\n \t/* Maximum non-guaranteed number of Rx Key Contexts */\n-\tuint16_t\tmax_rx_key_ctxs;\n-\tuint8_t\tunused_0[2];\n+\tuint32_t\tmax_rx_key_ctxs;\n } __rte_packed;\n \n-/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */\n+/* hwrm_func_vf_resource_cfg_output (size:320b/40B) */\n struct hwrm_func_vf_resource_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -17190,10 +18008,10 @@ struct hwrm_func_vf_resource_cfg_output {\n \t/* Reserved number of ring groups */\n \tuint16_t\treserved_hw_ring_grps;\n \t/* Actual number of Tx Key Contexts reserved */\n-\tuint16_t\treserved_tx_key_ctxs;\n+\tuint32_t\treserved_tx_key_ctxs;\n \t/* Actual number of Rx Key Contexts reserved */\n-\tuint16_t\treserved_rx_key_ctxs;\n-\tuint8_t\tunused_0[3];\n+\tuint32_t\treserved_rx_key_ctxs;\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -17479,8 +18297,13 @@ struct hwrm_func_backing_store_qcaps_output {\n \t * function.\n \t */\n \tuint32_t\trkc_max_entries;\n+\t/*\n+\t * Additional number of RoCE QP context entries required for this\n+\t * function to support fast QP destroy feature.\n+\t */\n+\tuint16_t\tfast_qpmd_qp_num_entries;\n \t/* Reserved for future. */\n-\tuint8_t\trsvd1[7];\n+\tuint8_t\trsvd1[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -20638,31 +21461,53 @@ struct hwrm_func_ptp_pin_qcfg_output {\n \t/* Type of function for Pin #2. */\n \tuint8_t\tpin2_usage;\n \t/* No function is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE \\\n+\t\tUINT32_C(0x0)\n \t/* PPS IN is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN \\\n+\t\tUINT32_C(0x1)\n \t/* PPS OUT is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT \\\n+\t\tUINT32_C(0x2)\n \t/* SYNC IN is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN \\\n+\t\tUINT32_C(0x3)\n \t/* SYNC OUT is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT \\\n+\t\tUINT32_C(0x4)\n+\t/* SYNCE primary clock OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT \\\n+\t\tUINT32_C(0x5)\n+\t/* SYNCE secondary clock OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT \\\n+\t\tUINT32_C(0x6)\n \t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \\\n-\t\tHWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT\n+\t\tHWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT\n \t/* Type of function for Pin #3. */\n \tuint8_t\tpin3_usage;\n \t/* No function is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE \\\n+\t\tUINT32_C(0x0)\n \t/* PPS IN is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN \\\n+\t\tUINT32_C(0x1)\n \t/* PPS OUT is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT \\\n+\t\tUINT32_C(0x2)\n \t/* SYNC IN is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN \\\n+\t\tUINT32_C(0x3)\n \t/* SYNC OUT is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT \\\n+\t\tUINT32_C(0x4)\n+\t/* SYNCE primary clock OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT \\\n+\t\tUINT32_C(0x5)\n+\t/* SYNCE secondary OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT \\\n+\t\tUINT32_C(0x6)\n \t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \\\n-\t\tHWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT\n+\t\tHWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT\n \tuint8_t\tunused_0;\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -20813,17 +21658,28 @@ struct hwrm_func_ptp_pin_cfg_input {\n \t/* Configure function for TSIO pin#2. */\n \tuint8_t\tpin2_usage;\n \t/* No function is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE \\\n+\t\tUINT32_C(0x0)\n \t/* PPS IN is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN \\\n+\t\tUINT32_C(0x1)\n \t/* PPS OUT is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT \\\n+\t\tUINT32_C(0x2)\n \t/* SYNC IN is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN \\\n+\t\tUINT32_C(0x3)\n \t/* SYNC OUT is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT \\\n+\t\tUINT32_C(0x4)\n+\t/* SYNCE primary clock OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT \\\n+\t\tUINT32_C(0x5)\n+\t/* SYNCE secondary clock OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT \\\n+\t\tUINT32_C(0x6)\n \t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \\\n-\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT\n+\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT\n \t/* Enable or disable functionality of Pin #3. */\n \tuint8_t\tpin3_state;\n \t/* Disabled */\n@@ -20835,17 +21691,28 @@ struct hwrm_func_ptp_pin_cfg_input {\n \t/* Configure function for TSIO pin#3. */\n \tuint8_t\tpin3_usage;\n \t/* No function is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE \\\n+\t\tUINT32_C(0x0)\n \t/* PPS IN is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN \\\n+\t\tUINT32_C(0x1)\n \t/* PPS OUT is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT \\\n+\t\tUINT32_C(0x2)\n \t/* SYNC IN is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN \\\n+\t\tUINT32_C(0x3)\n \t/* SYNC OUT is configured. */\n-\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT \\\n+\t\tUINT32_C(0x4)\n+\t/* SYNCE primary clock OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT \\\n+\t\tUINT32_C(0x5)\n+\t/* SYNCE secondary clock OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT \\\n+\t\tUINT32_C(0x6)\n \t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \\\n-\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT\n+\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT\n \tuint8_t\tunused_0[4];\n } __rte_packed;\n \n@@ -21130,12 +21997,25 @@ struct hwrm_func_ptp_ts_query_output {\n \tuint16_t\tresp_len;\n \t/* Timestamp value of last PPS event latched. */\n \tuint64_t\tpps_event_ts;\n-\t/* PTM local timestamp value. */\n-\tuint64_t\tptm_res_local_ts;\n-\t/* PTM Master timestamp value. */\n-\tuint64_t\tptm_pmstr_ts;\n-\t/* PTM Master propagation delay */\n-\tuint32_t\tptm_mstr_prop_dly;\n+\t/*\n+\t * PHC timestamp value when PTM responseD request is received\n+\t * at downstream port (t4'). This is a 48 bit timestamp in nanoseconds.\n+\t */\n+\tuint64_t\tptm_local_ts;\n+\t/*\n+\t * PTM System timestamp value corresponding to t4' at\n+\t * root complex (T4'). Together with ptm_local_ts, these\n+\t * two timestamps provide the cross-trigger timestamps.\n+\t * Driver can directly use these values for cross-trigger.\n+\t * This is a 48 bit timestamp in nanoseconds.\n+\t */\n+\tuint64_t\tptm_system_ts;\n+\t/*\n+\t * PTM Link delay. This is the time taken at root complex (RC)\n+\t * between receiving PTM request and sending PTM response to\n+\t * downstream port. This is a 32 bit value in nanoseconds.\n+\t */\n+\tuint32_t\tptm_link_delay;\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -21463,7 +22343,18 @@ struct hwrm_func_key_ctx_alloc_output {\n \tuint16_t\tresp_len;\n \t/* Actual number of Key Contexts allocated. */\n \tuint16_t\tnum_key_ctxs_allocated;\n-\tuint8_t\tunused_0[5];\n+\t/* Control flags. */\n+\tuint8_t\tflags;\n+\t/*\n+\t * When set, it indicates that all key contexts allocated by this\n+\t * command are contiguous. As a result, the driver has to read the\n+\t * start context ID from the first entry of the DMA data buffer\n+\t * and figures out the end context ID by “start context ID +\n+\t * num_key_ctxs_allocated - 1”.\n+\t */\n+\t#define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[4];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -21574,6 +22465,9 @@ struct hwrm_func_backing_store_cfg_v2_input {\n \t * Instance of the backing store type. It is zero-based,\n \t * which means \"0\" indicates the first instance. For backing\n \t * stores with single instance only, leave this field to 0.\n+\t * 1. If the backing store type is MPC TQM ring, use the following\n+\t * instance value to MPC client mapping:\n+\t * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)\n \t */\n \tuint16_t\tinstance;\n \t/* Control flags. */\n@@ -21586,6 +22480,31 @@ struct hwrm_func_backing_store_cfg_v2_input {\n \t */\n \t#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \\\n \t\tUINT32_C(0x1)\n+\t/*\n+\t * When set, the driver indicates that the backing store type\n+\t * to be configured in this command is the last one to do for\n+\t * the associated PF. That means all backing store type\n+\t * configurations are done for the corresponding PF after this\n+\t * command. As a result, the firmware has to do the necessary\n+\t * post configurations.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_CFG_ALL_DONE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When set, the driver indicates extending the size of the specific\n+\t * backing store type instead of configuring the corresponding PBLs.\n+\t * The size specified in the command will be the new size to be\n+\t * configured. The operation is only valid when the specific backing\n+\t * store has been configured before. Otherwise, the firmware will\n+\t * return an error. The driver needs to zero out the “entry_size”,\n+\t * “flags”, “page_dir”, and “page_size_pbl_level” fields, and the\n+\t * firmware will ignore these inputs. Further, the firmware expects\n+\t * the “num_entries” and any valid split entries to be no less than\n+\t * the initial value that has been configured. If not, it will\n+\t * return an error code.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_EXTEND \\\n+\t\tUINT32_C(0x4)\n \t/* Page directory. */\n \tuint64_t\tpage_dir;\n \t/* Number of entries */\n@@ -21957,6 +22876,52 @@ struct hwrm_func_backing_store_qcfg_v2_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/* Common structure to cast QPC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is QPC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */\n+/* qpc_split_entries (size:128b/16B) */\n+struct qpc_split_entries {\n+\t/* Number of L2 QP backing store entries. */\n+\tuint32_t\tqp_num_l2_entries;\n+\t/* Number of QP1 entries. */\n+\tuint32_t\tqp_num_qp1_entries;\n+\tuint32_t\trsvd[2];\n+} __rte_packed;\n+\n+/* Common structure to cast SRQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is SRQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */\n+/* srq_split_entries (size:128b/16B) */\n+struct srq_split_entries {\n+\t/* Number of L2 SRQ backing store entries. */\n+\tuint32_t\tsrq_num_l2_entries;\n+\tuint32_t\trsvd;\n+\tuint32_t\trsvd2[2];\n+} __rte_packed;\n+\n+/* Common structure to cast CQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is CQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */\n+/* cq_split_entries (size:128b/16B) */\n+struct cq_split_entries {\n+\t/* Number of L2 CQ backing store entries. */\n+\tuint32_t\tcq_num_l2_entries;\n+\tuint32_t\trsvd;\n+\tuint32_t\trsvd2[2];\n+} __rte_packed;\n+\n+/* Common structure to cast VNIC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is VNIC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */\n+/* vnic_split_entries (size:128b/16B) */\n+struct vnic_split_entries {\n+\t/* Number of VNIC backing store entries. */\n+\tuint32_t\tvnic_num_vnic_entries;\n+\tuint32_t\trsvd;\n+\tuint32_t\trsvd2[2];\n+} __rte_packed;\n+\n+/* Common structure to cast MRAV split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is MRAV. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */\n+/* mrav_split_entries (size:128b/16B) */\n+struct mrav_split_entries {\n+\t/* Number of AV backing store entries. */\n+\tuint32_t\tmrav_num_av_entries;\n+\tuint32_t\trsvd;\n+\tuint32_t\trsvd2[2];\n+} __rte_packed;\n+\n /************************************\n * hwrm_func_backing_store_qcaps_v2 *\n ************************************/\n@@ -22150,6 +23115,9 @@ struct hwrm_func_backing_store_qcaps_v2_output {\n \t/*\n \t * Bit map of the valid instances associated with the\n \t * backing store type.\n+\t * 1. If the backing store type is MPC TQM ring, use the following\n+\t * bit to MPC client mapping:\n+\t * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)\n \t */\n \tuint32_t\tinstance_bit_map;\n \t/*\n@@ -22506,7 +23474,7 @@ struct hwrm_func_dbr_pacing_qcfg_output {\n \tuint8_t\tunused_3[7];\n \t/*\n \t * Specifies primary function’s NQ ID.\n-\t * A value of 0xFFFF indicates NQ ID is invalid.\n+\t * A value of 0xFFFF FFFF indicates NQ ID is invalid.\n \t */\n \tuint32_t\tprimary_nq_id;\n \t/*\n@@ -22585,13 +23553,13 @@ struct hwrm_func_dbr_pacing_broadcast_event_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***********************\n- * hwrm_func_vlan_qcfg *\n- ***********************/\n+/*************************************\n+ * hwrm_func_dbr_pacing_nqlist_query *\n+ *************************************/\n \n \n-/* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n-struct hwrm_func_vlan_qcfg_input {\n+/* hwrm_func_dbr_pacing_nqlist_query_input (size:128b/16B) */\n+struct hwrm_func_dbr_pacing_nqlist_query_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -22620,18 +23588,10 @@ struct hwrm_func_vlan_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Function ID of the function that is being\n-\t * configured.\n-\t * If set to 0xFF... (All Fs), then the configuration is\n-\t * for the requesting function.\n-\t */\n-\tuint16_t\tfid;\n-\tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_func_vlan_qcfg_output (size:320b/40B) */\n-struct hwrm_func_vlan_qcfg_output {\n+/* hwrm_func_dbr_pacing_nqlist_query_output (size:384b/48B) */\n+struct hwrm_func_dbr_pacing_nqlist_query_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -22640,49 +23600,414 @@ struct hwrm_func_vlan_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint64_t\tunused_0;\n-\t/* S-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tstag_vid;\n-\t/* S-TAG PCP value configured for the function. */\n-\tuint8_t\tstag_pcp;\n-\tuint8_t\tunused_1;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id0;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id1;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id2;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id3;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id4;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id5;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id6;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id7;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id8;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id9;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id10;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id11;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id12;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id13;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id14;\n+\t/* ID of an NQ ring allocated for DBR pacing notifications. */\n+\tuint16_t\tnq_ring_id15;\n+\t/* Number of consecutive NQ ring IDs populated in the response. */\n+\tuint32_t\tnum_nqs;\n+\tuint8_t\tunused_0[3];\n \t/*\n-\t * S-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint16_t\tstag_tpid;\n-\t/* C-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tctag_vid;\n-\t/* C-TAG PCP value configured for the function. */\n-\tuint8_t\tctag_pcp;\n-\tuint8_t\tunused_2;\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/************************************\n+ * hwrm_func_dbr_recovery_completed *\n+ ************************************/\n+\n+\n+/* hwrm_func_dbr_recovery_completed_input (size:192b/24B) */\n+struct hwrm_func_dbr_recovery_completed_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * C-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint16_t\tctag_tpid;\n-\t/* Future use. */\n-\tuint32_t\trsvd2;\n-\t/* Future use. */\n-\tuint32_t\trsvd3;\n-\tuint8_t\tunused_3[3];\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Specifies the epoch value with the one that was specified by the\n+\t * firmware in the error_report_doorbell_drop_threshold async event\n+\t * corresponding to the specific recovery cycle.\n+\t */\n+\tuint32_t\tepoch;\n+\t/* The epoch value. */\n+\t#define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_MASK \\\n+\t\tUINT32_C(0xffffff)\n+\t#define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_SFT 0\n+\tuint8_t\tunused_0[4];\n+} __rte_packed;\n+\n+/* hwrm_func_dbr_recovery_completed_output (size:128b/16B) */\n+struct hwrm_func_dbr_recovery_completed_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**********************\n- * hwrm_func_vlan_cfg *\n- **********************/\n+/***********************\n+ * hwrm_func_synce_cfg *\n+ ***********************/\n \n \n-/* hwrm_func_vlan_cfg_input (size:384b/48B) */\n-struct hwrm_func_vlan_cfg_input {\n+/* hwrm_func_synce_cfg_input (size:192b/24B) */\n+struct hwrm_func_synce_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint8_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the freq_profile field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_FREQ_PROFILE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the primary_clock_state field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_PRIMARY_CLOCK \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the secondary_clock_state field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_SECONDARY_CLOCK \\\n+\t\tUINT32_C(0x4)\n+\t/* Frequency profile for SyncE recovered clock. */\n+\tuint8_t\tfreq_profile;\n+\t/* Invalid frequency profile */\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)\n+\t/* 25MHz SyncE clock profile */\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1)\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_LAST \\\n+\t\tHWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ\n+\t/*\n+\t * Enable or disable primary clock for PF/port, overriding previous\n+\t * primary clock setting.\n+\t */\n+\tuint8_t\tprimary_clock_state;\n+\t/* Disable clock */\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_DISABLE \\\n+\t\tUINT32_C(0x0)\n+\t/* Enable clock */\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_LAST \\\n+\t\tHWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE\n+\t/*\n+\t * Enable or disable secondary clock for PF/port, overriding previous\n+\t * secondary clock setting.\n+\t */\n+\tuint8_t\tsecondary_clock_state;\n+\t/* Clock disabled */\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_DISABLE \\\n+\t\tUINT32_C(0x0)\n+\t/* Clock enabled */\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_LAST \\\n+\t\tHWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE\n+\tuint8_t\tunused_0[4];\n+} __rte_packed;\n+\n+/* hwrm_func_synce_cfg_output (size:128b/16B) */\n+struct hwrm_func_synce_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/************************\n+ * hwrm_func_synce_qcfg *\n+ ************************/\n+\n+\n+/* hwrm_func_synce_qcfg_input (size:192b/24B) */\n+struct hwrm_func_synce_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint8_t\tunused_0[8];\n+} __rte_packed;\n+\n+/* hwrm_func_synce_qcfg_output (size:128b/16B) */\n+struct hwrm_func_synce_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Frequency profile for SyncE recovered clock. */\n+\tuint8_t\tfreq_profile;\n+\t/* Invalid frequency profile */\n+\t#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)\n+\t/* 25MHz SyncE clock profile */\n+\t#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1)\n+\t#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_LAST \\\n+\t\tHWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ\n+\t/* SyncE recovered clock state */\n+\tuint8_t\tstate;\n+\t/*\n+\t * When this bit is '1', primary clock is enabled for this PF/port.\n+\t * When this bit is '0', primary clock is disabled for this PF/port.\n+\t */\n+\t#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_PRIMARY_CLOCK_ENABLED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', secondary clock is enabled for this\n+\t * PF/port.\n+\t * When this bit is '0', secondary clock is disabled for this\n+\t * PF/port.\n+\t */\n+\t#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_SECONDARY_CLOCK_ENABLED \\\n+\t\tUINT32_C(0x2)\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/***********************\n+ * hwrm_func_vlan_qcfg *\n+ ***********************/\n+\n+\n+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n+struct hwrm_func_vlan_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Function ID of the function that is being\n+\t * configured.\n+\t * If set to 0xFF... (All Fs), then the configuration is\n+\t * for the requesting function.\n+\t */\n+\tuint16_t\tfid;\n+\tuint8_t\tunused_0[6];\n+} __rte_packed;\n+\n+/* hwrm_func_vlan_qcfg_output (size:320b/40B) */\n+struct hwrm_func_vlan_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint64_t\tunused_0;\n+\t/* S-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tstag_vid;\n+\t/* S-TAG PCP value configured for the function. */\n+\tuint8_t\tstag_pcp;\n+\tuint8_t\tunused_1;\n+\t/*\n+\t * S-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tstag_tpid;\n+\t/* C-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tctag_vid;\n+\t/* C-TAG PCP value configured for the function. */\n+\tuint8_t\tctag_pcp;\n+\tuint8_t\tunused_2;\n+\t/*\n+\t * C-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tctag_tpid;\n+\t/* Future use. */\n+\tuint32_t\trsvd2;\n+\t/* Future use. */\n+\tuint32_t\trsvd3;\n+\tuint8_t\tunused_3[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**********************\n+ * hwrm_func_vlan_cfg *\n+ **********************/\n+\n+\n+/* hwrm_func_vlan_cfg_input (size:384b/48B) */\n+struct hwrm_func_vlan_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24576,7 +25901,7 @@ struct hwrm_port_phy_qcfg_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_port_phy_qcfg_output (size:768b/96B) */\n+/* hwrm_port_phy_qcfg_output (size:832b/104B) */\n struct hwrm_port_phy_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -25601,6 +26926,14 @@ struct hwrm_port_phy_qcfg_output {\n \t/* 200Gb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \\\n \t\tUINT32_C(0x4)\n+\t/*\n+\t * This field is used to indicate the reasons for link down.\n+\t * This field is set to 0, if the link down reason is unknown.\n+\t */\n+\tuint8_t\tlink_down_reason;\n+\t/* Remote fault */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF UINT32_C(0x1)\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -26934,16 +28267,12 @@ struct hwrm_port_qstats_input {\n \t/* Port ID of port that is being queried. */\n \tuint16_t\tport_id;\n \tuint8_t\tflags;\n-\t/* This value is not used to avoid backward compatibility issues. */\n-\t#define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n \t/*\n \t * This bit is set to 1 when request is for a counter mask,\n \t * representing the width of each of the stats counters, rather\n \t * than counters themselves.\n \t */\n-\t#define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n-\t#define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \\\n-\t\tHWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK\n+\t#define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n \tuint8_t\tunused_0[5];\n \t/*\n \t * This is the host address where\n@@ -27646,16 +28975,12 @@ struct hwrm_port_qstats_ext_input {\n \t */\n \tuint16_t\trx_stat_size;\n \tuint8_t\tflags;\n-\t/* This value is not used to avoid backward compatibility issues. */\n-\t#define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n \t/*\n \t * This bit is set to 1 when request is for the counter mask,\n \t * representing width of each of the stats counters, rather than\n \t * counters themselves.\n \t */\n-\t#define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n-\t#define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \\\n-\t\tHWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK\n+\t#define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n \tuint8_t\tunused_0;\n \t/*\n \t * This is the host address where\n@@ -27903,16 +29228,12 @@ struct hwrm_port_ecn_qstats_input {\n \t */\n \tuint16_t\tecn_stat_buf_size;\n \tuint8_t\tflags;\n-\t/* This value is not used to avoid backward compatibility issues. */\n-\t#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n \t/*\n \t * This bit is set to 1 when request is for a counter mask,\n \t * representing the width of each of the stats counters, rather\n \t * than counters themselves.\n \t */\n-\t#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n-\t#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \\\n-\t\tHWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK\n+\t#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This is the host address where\n@@ -28398,6 +29719,12 @@ struct hwrm_port_phy_qcaps_output {\n \t */\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \\\n \t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, then this field indicates that\n+\t * bank based addressing is supported in firmware.\n+\t */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n \t/*\n \t * Number of internal ports for this device. This field allows the FW\n \t * to advertise how many internal ports are present. Manufacturing\n@@ -29720,6 +31047,14 @@ struct hwrm_port_prbs_test_input {\n \t#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)\n \t/* PRBS58 */\n \t#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)\n+\t/* PRBS49 */\n+\t#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS49 UINT32_C(0x7)\n+\t/* PRBS10 */\n+\t#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS10 UINT32_C(0x8)\n+\t/* PRBS20 */\n+\t#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS20 UINT32_C(0x9)\n+\t/* PRBS13 */\n+\t#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS13 UINT32_C(0xa)\n \t/* Invalid */\n \t#define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)\n \t#define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \\\n@@ -29749,6 +31084,15 @@ struct hwrm_port_prbs_test_input {\n \t */\n \t#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \\\n \t\tUINT32_C(0x4)\n+\t/* If set to 1, FEC stat t-code 0-7 registers are enabled. */\n+\t#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T0_T7 \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * If set to 1, FEC stat t-code 8-15 registers are enabled.\n+\t * If fec_stat_t0_t7 is set, fec_stat_t8_t15 field will be ignored.\n+\t */\n+\t#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T8_T15 \\\n+\t\tUINT32_C(0x10)\n \t/* Duration in seconds to run the PRBS test. */\n \tuint16_t\ttimeout;\n \t/*\n@@ -29777,7 +31121,15 @@ struct hwrm_port_prbs_test_output {\n \tuint16_t\tresp_len;\n \t/* Total length of stored data. */\n \tuint16_t\ttotal_data_len;\n-\tuint16_t\tunused_0;\n+\t/* This field is used in Output records to indicate the output format */\n+\tuint8_t\tber_format;\n+\t/* BER_FORMAT_PRBS */\n+\t#define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_PRBS UINT32_C(0x0)\n+\t/* BER_FORMAT_FEC */\n+\t#define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC UINT32_C(0x1)\n+\t#define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_LAST \\\n+\t\tHWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC\n+\tuint8_t\tunused_0;\n \tuint8_t\tunused_1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -30800,6 +32152,160 @@ struct hwrm_port_ep_tx_qcfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/*****************\n+ * hwrm_port_cfg *\n+ *****************/\n+\n+\n+/* hwrm_port_cfg_input (size:256b/32B) */\n+struct hwrm_port_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the tx_rate_limit field to\n+\t * be configured.\n+\t */\n+\t#define HWRM_PORT_CFG_INPUT_ENABLES_TX_RATE_LIMIT UINT32_C(0x1)\n+\t/* Port ID of port that is to be configured. */\n+\tuint16_t\tport_id;\n+\tuint16_t\tunused_0;\n+\t/*\n+\t * Requested setting of TX rate limit in Mbps.\n+\t * tx_rate_limit = 0 will cancel the rate limit if any.\n+\t * This field is valid only when tx_rate_limit bit in 'enables'\n+\t * field is '1'.\n+\t */\n+\tuint32_t\ttx_rate_limit;\n+} __rte_packed;\n+\n+/* hwrm_port_cfg_output (size:128b/16B) */\n+struct hwrm_port_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/******************\n+ * hwrm_port_qcfg *\n+ ******************/\n+\n+\n+/* hwrm_port_qcfg_input (size:192b/24B) */\n+struct hwrm_port_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Port ID of port that is to be queried. */\n+\tuint16_t\tport_id;\n+\tuint8_t\tunused_0[6];\n+} __rte_packed;\n+\n+/* hwrm_port_qcfg_output (size:192b/24B) */\n+struct hwrm_port_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tsupported;\n+\t/*\n+\t * If set to '1', then this bit indicates that TX rate limit\n+\t * could be configured via hwrm_port_cfg command.\n+\t */\n+\t#define HWRM_PORT_QCFG_OUTPUT_SUPPORTED_TX_RATE_LIMIT UINT32_C(0x1)\n+\tuint32_t\tenabled;\n+\t/*\n+\t * If set to '1', then this bit indicates that TX rate limit\n+\t * is enabled and could be found in tx_rate_limit field.\n+\t */\n+\t#define HWRM_PORT_QCFG_OUTPUT_ENABLED_TX_RATE_LIMIT UINT32_C(0x1)\n+\t/*\n+\t * Current setting of TX rate limit in Mbps.\n+\t * This field is valid only when tx_rate_limit bit in 'enabled'\n+\t * field is '1'.\n+\t */\n+\tuint32_t\ttx_rate_limit;\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /***********************\n * hwrm_queue_qportcfg *\n ***********************/\n@@ -35688,29 +37194,19 @@ struct hwrm_vnic_update_input {\n \t\tHWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP\n \t/*\n \t * The metadata format type used in all the RX packet completions\n-\t * going through this VNIC.\n+\t * going through this VNIC. This value is product specific. Refer to\n+\t * the L2 HSI completion ring structures for the detailed\n+\t * descriptions. For Thor and Thor2, it corresponds to “meta_format”\n+\t * in “rx_pkt_cmpl_hi” and “rx_pkt_v3_cmpl_hi”, respectively.\n \t */\n \tuint8_t\tmetadata_format_type;\n-\t/* No metadata information. */\n-\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \\\n-\t\tUINT32_C(0x0)\n-\t/*\n-\t * Action record pointer (table_scope[4:0], act_rec_ptr[25:0],\n-\t * vtag[19:0]).\n-\t */\n-\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \\\n-\t\tUINT32_C(0x1)\n-\t/* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */\n-\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \\\n-\t\tUINT32_C(0x2)\n-\t/* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */\n-\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \\\n-\t\tUINT32_C(0x3)\n-\t/* Header offsets (hdr_offsets[31:0], vtag[19:0]) */\n-\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \\\n-\t\tUINT32_C(0x4)\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)\n \t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \\\n-\t\tHWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS\n+\t\tHWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4\n \t/*\n \t * The maximum receive unit of the vnic.\n \t * Each vnic is associated with a function.\n@@ -35911,6 +37407,12 @@ struct hwrm_vnic_cfg_input {\n \t */\n \t#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \\\n \t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1' it enables ring selection using the incoming\n+\t * spif and lcos for the packet.\n+\t */\n+\t#define HWRM_VNIC_CFG_INPUT_FLAGS_PORTCOS_MAPPING_MODE \\\n+\t\tUINT32_C(0x80)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the dflt_ring_grp field to be\n@@ -36259,6 +37761,9 @@ struct hwrm_vnic_qcfg_output {\n \t */\n \t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \\\n \t\tUINT32_C(0x80)\n+\t/* When this bit is '1' it indicates port cos_mapping_mode enabled. */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE \\\n+\t\tUINT32_C(0x100)\n \t/*\n \t * When returned with a valid CoS Queue id, the CoS Queue/VNIC association\n \t * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS\n@@ -36315,7 +37820,30 @@ struct hwrm_vnic_qcfg_output {\n \t#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2)\n \t#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST \\\n \t\tHWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED\n-\tuint8_t\tunused_1[3];\n+\t/*\n+\t * This field conveys the metadata format type that has been\n+\t * configured. This value is product specific. Refer to the L2 HSI\n+\t * completion ring structures for the detailed descriptions. For Thor\n+\t * and Thor2, it corresponds to “meta_format” in “rx_pkt_cmpl_hi” and\n+\t * “rx_pkt_v3_cmpl_hi”, respectively.\n+\t */\n+\tuint8_t\tmetadata_format_type;\n+\t#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)\n+\t#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)\n+\t#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)\n+\t#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)\n+\t#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)\n+\t#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_LAST \\\n+\t\tHWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4\n+\t/* This field conveys the VNIC operation state. */\n+\tuint8_t\tvnic_state;\n+\t/* Normal operation state. */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_NORMAL UINT32_C(0x0)\n+\t/* Drop all packets. */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP UINT32_C(0x1)\n+\t#define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_LAST \\\n+\t\tHWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP\n+\tuint8_t\tunused_1;\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -36557,6 +38085,53 @@ struct hwrm_vnic_qcaps_output {\n \t */\n \t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP \\\n \t\tUINT32_C(0x100000)\n+\t/*\n+\t * When this bit is '1' HW supports hash calculation\n+\t * based on IPv4 IPSEC AH SPI field.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP \\\n+\t\tUINT32_C(0x200000)\n+\t/*\n+\t * When this bit is '1' HW supports hash calculation\n+\t * based on IPv4 IPSEC ESP SPI field.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP \\\n+\t\tUINT32_C(0x400000)\n+\t/*\n+\t * When this bit is '1' HW supports hash calculation\n+\t * based on IPv6 IPSEC AH SPI field.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP \\\n+\t\tUINT32_C(0x800000)\n+\t/*\n+\t * When this bit is '1' HW supports hash calculation\n+\t * based on IPv6 IPSEC ESP SPI field.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP \\\n+\t\tUINT32_C(0x1000000)\n+\t/*\n+\t * When outermost_rss_cap is '1' and this bit is '1', the outermost\n+\t * RSS hash mode may be set on a PF or trusted VF.\n+\t * When outermost_rss_cap is '1' and this bit is '0', the outermost\n+\t * RSS hash mode may be set on a PF.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP \\\n+\t\tUINT32_C(0x2000000)\n+\t/*\n+\t * When this bit is '1' it indicates HW is capable of enabling ring\n+\t * selection using the incoming spif and lcos for the packet.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE \\\n+\t\tUINT32_C(0x4000000)\n+\t/*\n+\t * When this bit is '1', it indicates controller enabled\n+\t * RSS profile TCAM mode.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED \\\n+\t\tUINT32_C(0x8000000)\n+\t/* When this bit is '1' FW supports VNIC hash mode. */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP \\\n+\t\tUINT32_C(0x10000000)\n \t/*\n \t * This field advertises the maximum concurrent TPA aggregations\n \t * supported by the VNIC on new devices that support TPA v2 or v3.\n@@ -36869,6 +38444,38 @@ struct hwrm_vnic_rss_cfg_input {\n \t */\n \t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL \\\n \t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed over\n+\t * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC\n+\t * AH/IPv4 packets. Host drivers should set this bit based on\n+\t * rss_ipsec_ah_spi_ipv4_cap.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed over\n+\t * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC\n+\t * ESP/IPv4 packets. Host drivers should set this bit based on\n+\t * rss_ipsec_esp_spi_ipv4_cap.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed over\n+\t * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC\n+\t * AH/IPv6 packets. Host drivers should set this bit based on\n+\t * rss_ipsec_ah_spi_ipv6_cap.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed over\n+\t * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC\n+\t * ESP/IPv6 packets. Host drivers should set this bit based on\n+\t * rss_ipsec_esp_spi_ipv6_cap.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 \\\n+\t\tUINT32_C(0x400)\n \t/* VNIC ID of VNIC associated with RSS table being configured. */\n \tuint16_t\tvnic_id;\n \t/*\n@@ -36876,11 +38483,25 @@ struct hwrm_vnic_rss_cfg_input {\n \t * Valid values range from 0 to 7.\n \t */\n \tuint8_t\tring_table_pair_index;\n-\t/* Flags to specify different RSS hash modes. */\n+\t/*\n+\t * Flags to specify different RSS hash modes. Global RSS hash mode is\n+\t * indicated when vnic_id and rss_ctx_idx fields are set to value of\n+\t * 0xffff. Only PF can initiate global RSS hash mode setting changes.\n+\t * VNIC RSS hash mode is indicated with valid vnic_id and rss_ctx_idx,\n+\t * if FW is VNIC_RSS_HASH_MODE capable. FW configures the mode based\n+\t * on first come first serve order. Global RSS hash mode and VNIC RSS\n+\t * hash modes are mutually exclusive. FW returns invalid error\n+\t * if FW receives conflicting requests. To change the current hash\n+\t * mode, the mode associated drivers need to be unloaded and apply\n+\t * the new configuration.\n+\t */\n \tuint8_t\thash_mode_flags;\n \t/*\n-\t * When this bit is '1', it indicates using current RSS\n-\t * hash mode setting configured in the device.\n+\t * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable,\n+\t * innermost_4 and innermost_2 hash modes are used to configure\n+\t * the tuple mode. When this bit is '1' and FW is not\n+\t * VNIC_RSS_HASH_MODE capable, It indicates using current RSS hash\n+\t * mode setting configured in the device otherwise.\n \t */\n \t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \\\n \t\tUINT32_C(0x1)\n@@ -37063,9 +38684,17 @@ struct hwrm_vnic_rss_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Index to the rss indirection table. */\n+\t/*\n+\t * Index to the rss indirection table. This field is used as a lookup\n+\t * for chips before Thor - i.e. Cumulus and Whitney.\n+\t */\n \tuint16_t\trss_ctx_idx;\n-\tuint8_t\tunused_0[6];\n+\t/*\n+\t * VNIC ID of VNIC associated with RSS table being queried. This field\n+\t * is used as a lookup for Thor and later chips.\n+\t */\n+\tuint16_t\tvnic_id;\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */\n@@ -37084,45 +38713,104 @@ struct hwrm_vnic_rss_qcfg_output {\n \t * over source and destination IPv4 addresses of IPv4\n \t * packets.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 \\\n+\t\tUINT32_C(0x1)\n \t/*\n \t * When this bit is '1', the RSS hash shall be computed\n \t * over source/destination IPv4 addresses and\n \t * source/destination ports of TCP/IPv4 packets.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 \\\n+\t\tUINT32_C(0x2)\n \t/*\n \t * When this bit is '1', the RSS hash shall be computed\n \t * over source/destination IPv4 addresses and\n \t * source/destination ports of UDP/IPv4 packets.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 \\\n+\t\tUINT32_C(0x4)\n \t/*\n \t * When this bit is '1', the RSS hash shall be computed\n \t * over source and destination IPv6 addresses of IPv6\n \t * packets.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 \\\n+\t\tUINT32_C(0x8)\n \t/*\n \t * When this bit is '1', the RSS hash shall be computed\n \t * over source/destination IPv6 addresses and\n \t * source/destination ports of TCP/IPv6 packets.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 \\\n+\t\tUINT32_C(0x10)\n \t/*\n \t * When this bit is '1', the RSS hash shall be computed\n \t * over source/destination IPv6 addresses and\n \t * source/destination ports of UDP/IPv6 packets.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source, destination IPv6 addresses and flow label of IPv6\n+\t * packets. Hash type ipv6 and ipv6_flow_label are mutually\n+\t * exclusive. HW does not include the flow_label in hash\n+\t * calculation for the packets that are matching tcp_ipv6 and\n+\t * udp_ipv6 hash types. This bit will be '0' if\n+\t * rss_ipv6_flow_label_cap is '0'.\n+\t */\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6_FLOW_LABEL \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed over\n+\t * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC\n+\t * AH/IPv4 packets. This bit will be '0' if rss_ipsec_ah_spi_ipv4_cap\n+\t * is '0'.\n+\t */\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV4 \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed over\n+\t * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC\n+\t * ESP/IPv4 packets. This bit will be '0' if\n+\t * rss_ipsec_esp_spi_ipv4_cap is '0'.\n+\t */\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV4 \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed over\n+\t * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC\n+\t * AH/IPv6 packets. This bit will be '0' if\n+\t * rss_ipsec_ah_spi_ipv6_cap is '0'.\n+\t */\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV6 \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed over\n+\t * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC\n+\t * ESP/IPv6 packets. This bit will be '0' if\n+\t * rss_ipsec_esp_spi_ipv6_cap is '0'.\n+\t */\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV6 \\\n+\t\tUINT32_C(0x400)\n \tuint8_t\tunused_0[4];\n \t/* This is the value of rss hash key */\n \tuint32_t\thash_key[10];\n-\t/* Flags to specify different RSS hash modes. */\n+\t/*\n+\t * Flags to specify different RSS hash modes. Setting rss_ctx_idx to\n+\t * the value of 0xffff implies a global RSS configuration query.\n+\t * hash_mode_flags are only valid for global RSS configuration query.\n+\t * Only the PF can initiate a global RSS configuration query.\n+\t * The query request fails if any VNIC is configured with hash mode\n+\t * and rss_ctx_idx is 0xffff.\n+\t */\n \tuint8_t\thash_mode_flags;\n \t/*\n-\t * When this bit is '1', it indicates using current RSS\n-\t * hash mode setting configured in the device.\n+\t * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable,\n+\t * it indicates VNIC's configured RSS hash mode.\n+\t * When this bit is '1' and FW is not VNIC_RSS_HASH_MODE capable,\n+\t * It indicates using current RSS hash mode setting configured in the\n+\t * device.\n \t */\n \t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \\\n \t\tUINT32_C(0x1)\n@@ -37832,6 +39520,27 @@ struct hwrm_ring_alloc_input {\n \t */\n \t#define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION \\\n \t\tUINT32_C(0x2)\n+\t/*\n+\t * Used with enhanced Doorbell Pacing feature, when set to '1'\n+\t * this flag indicates that the NQ id that's allocated should be\n+\t * used for DBR pacing notifications.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_FLAGS_NQ_DBR_PACING \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * Host driver should set this flag bit to '1' to enable\n+\t * two-completion TX packet timestamp feature. By enabling this\n+\t * per QP flag and enabling stamp bit in TX BD lflags, host drivers\n+\t * expect two completions, one for regular TX completion and the\n+\t * other completion with timestamp. For a QP with both completion\n+\t * coalescing and timestamp completion features enabled, completion\n+\t * coalescing takes place on regular TX completions. The timestamp\n+\t * completions are not coalesced and a separate timestamp completion\n+\t * is generated for each packet with stamp bit set in the TX BD\n+\t * lflags.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE \\\n+\t\tUINT32_C(0x8)\n \t/*\n \t * This value is a pointer to the page table for the\n \t * Ring.\n@@ -38026,7 +39735,7 @@ struct hwrm_ring_alloc_input {\n \t * completion rings are allowed.\n \t */\n \tuint8_t\tint_mode;\n-\t/* Legacy INTA */\n+\t/* Legacy INTA (deprecated) */\n \t#define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)\n \t/* Reserved */\n \t#define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)\n@@ -40371,6 +42080,9 @@ struct hwrm_cfa_l2_filter_alloc_input {\n \t */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -41239,6 +42951,9 @@ struct hwrm_cfa_tunnel_filter_alloc_input {\n \t */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -41507,6 +43222,9 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {\n \t */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -41629,6 +43347,9 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {\n \t */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -41743,6 +43464,9 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {\n \t */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -41978,8 +43702,11 @@ struct hwrm_cfa_encap_record_alloc_input {\n \t */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \\\n-\t\tHWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6\n+\t\tHWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE\n \tuint8_t\tunused_0[3];\n \t/* This value is encap data used for the given encap type. */\n \tuint32_t\tencap_data[20];\n@@ -42309,6 +44036,9 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t * Applies to UDP and TCP traffic.\n \t * 6 - TCP\n \t * 17 - UDP\n+\t * 1 - ICMP\n+\t * 58 - ICMPV6\n+\t * 255 - RSVD\n \t */\n \tuint8_t\tip_protocol;\n \t/* invalid */\n@@ -42320,8 +44050,17 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t/* UDP */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \\\n \t\tUINT32_C(0x11)\n+\t/* ICMP */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMP \\\n+\t\tUINT32_C(0x1)\n+\t/* ICMPV6 */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMPV6 \\\n+\t\tUINT32_C(0x3a)\n+\t/* RSVD */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD \\\n+\t\tUINT32_C(0xff)\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \\\n-\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP\n+\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD\n \t/*\n \t * If set, this value shall represent the\n \t * Logical VNIC ID of the destination VNIC for the RX\n@@ -42388,6 +44127,9 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -42979,6 +44721,9 @@ struct hwrm_cfa_em_flow_alloc_input {\n \t */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -44444,6 +46189,9 @@ struct hwrm_cfa_decap_filter_alloc_input {\n \t */\n \t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -44929,6 +46677,9 @@ struct hwrm_cfa_flow_alloc_input {\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -45182,8 +46933,11 @@ struct hwrm_cfa_flow_action_data {\n \t * (IPV6oVXLANGPE)\n \t */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \\\n-\t\tHWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6\n+\t\tHWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE\n \tuint8_t\tunused[7];\n \t/* This value is encap data for the associated encap type. */\n \tuint32_t\tencap_data[20];\n@@ -45238,6 +46992,9 @@ struct hwrm_cfa_flow_tunnel_hdr_data {\n \t */\n \t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -45377,19 +47134,35 @@ struct hwrm_cfa_flow_info_input {\n \t/* Max flow handle */\n \t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \\\n \t\tUINT32_C(0xfff)\n-\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0\n \t/* CNP flow handle */\n \t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \\\n \t\tUINT32_C(0x1000)\n \t/* RoCEv1 flow handle */\n \t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \\\n \t\tUINT32_C(0x2000)\n+\t/* NIC flow handle */\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_TX \\\n+\t\tUINT32_C(0x3000)\n \t/* RoCEv2 flow handle */\n \t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \\\n \t\tUINT32_C(0x4000)\n \t/* Direction rx = 1 */\n \t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \\\n \t\tUINT32_C(0x8000)\n+\t/* CNP flow handle */\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT_RX \\\n+\t\tUINT32_C(0x9000)\n+\t/* RoCEv1 flow handle */\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT_RX \\\n+\t\tUINT32_C(0xa000)\n+\t/* NIC flow handle */\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_RX \\\n+\t\tUINT32_C(0xb000)\n+\t/* RoCEv2 flow handle */\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX \\\n+\t\tUINT32_C(0xc000)\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_LAST \\\n+\t\tHWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX\n \tuint8_t\tunused_0[6];\n \t/* This value identifies a set of CFA data structures used for a flow. */\n \tuint64_t\text_flow_handle;\n@@ -45629,27 +47402,67 @@ struct hwrm_cfa_flow_stats_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Flow handle. */\n+\t/* Number of valid flows in this command. */\n \tuint16_t\tnum_flows;\n-\t/* Flow handle. */\n+\t/*\n+\t * Flow handle.\n+\t * For a listing of applicable flow_handle_0 values, see enumeration\n+\t * in hwrm_cfa_flow_info_input.\n+\t */\n \tuint16_t\tflow_handle_0;\n-\t/* Flow handle. */\n+\t/*\n+\t * Flow handle.\n+\t * For a listing of applicable flow_handle_1 values, see enumeration\n+\t * in hwrm_cfa_flow_info_input.\n+\t */\n \tuint16_t\tflow_handle_1;\n-\t/* Flow handle. */\n+\t/*\n+\t * Flow handle.\n+\t * For a listing of applicable flow_handle_2 values, see enumeration\n+\t * in hwrm_cfa_flow_info_input.\n+\t */\n \tuint16_t\tflow_handle_2;\n-\t/* Flow handle. */\n+\t/*\n+\t * Flow handle.\n+\t * For a listing of applicable flow_handle_3 values, see enumeration\n+\t * in hwrm_cfa_flow_info_input.\n+\t */\n \tuint16_t\tflow_handle_3;\n-\t/* Flow handle. */\n+\t/*\n+\t * Flow handle.\n+\t * For a listing of applicable flow_handle_4 values, see enumeration\n+\t * in hwrm_cfa_flow_info_input.\n+\t */\n \tuint16_t\tflow_handle_4;\n-\t/* Flow handle. */\n+\t/*\n+\t * Flow handle.\n+\t * For a listing of applicable flow_handle_5 values, see enumeration\n+\t * in hwrm_cfa_flow_info_input.\n+\t */\n \tuint16_t\tflow_handle_5;\n-\t/* Flow handle. */\n+\t/*\n+\t * Flow handle.\n+\t * For a listing of applicable flow_handle_6 values, see enumeration\n+\t * in hwrm_cfa_flow_info_input.\n+\t */\n \tuint16_t\tflow_handle_6;\n-\t/* Flow handle. */\n+\t/*\n+\t * Flow handle.\n+\t * For a listing of applicable flow_handle_7 values, see enumeration\n+\t * in hwrm_cfa_flow_info_input.\n+\t */\n \tuint16_t\tflow_handle_7;\n-\t/* Flow handle. */\n+\t/*\n+\t * Flow handle.\n+\t * For a listing of applicable flow_handle_8 values, see enumeration\n+\t * in hwrm_cfa_flow_info_input.\n+\t */\n \tuint16_t\tflow_handle_8;\n-\t/* Flow handle. */\n+\t/*\n+\t * Flow handle.\n+\t * For a listing of applicable flow_handle_9 values, see enumeration\n+\t * in hwrm_cfa_flow_info_input.\n+\t */\n \tuint16_t\tflow_handle_9;\n \tuint8_t\tunused_0[2];\n \t/* Flow ID of a flow. */\n@@ -45724,7 +47537,16 @@ struct hwrm_cfa_flow_stats_output {\n \tuint64_t\tbyte_8;\n \t/* byte_9 is 64 b */\n \tuint64_t\tbyte_9;\n-\tuint8_t\tunused_0[7];\n+\t/*\n+\t * If a flow has been hit, the bit representing the flow will be 1.\n+\t * Likewise, if a flow has not, the bit representing the flow\n+\t * will be 0. Mapping will match flow numbers where bitX is for flowX\n+\t * (ex: bit 0 is flow0). This only applies for NIC flows. Upon\n+\t * reading of the flow, the bit will be cleared for the flow and only\n+\t * set again when traffic is received by the flow.\n+\t */\n+\tuint16_t\tflow_hits;\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -46498,27 +48320,36 @@ struct hwrm_cfa_pair_alloc_input {\n \t * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).\n \t */\n \tuint16_t\tpair_mode;\n-\t/* Pair between VF on local host with PF or VF on specified host. */\n+\t/*\n+\t * Pair between VF on local host with PF or VF on specified host.\n+\t * (deprecated)\n+\t */\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \\\n \t\tUINT32_C(0x0)\n-\t/* Pair between REP on local host with PF or VF on specified host. */\n+\t/*\n+\t * Pair between REP on local host with PF or VF on specified host.\n+\t * (deprecated)\n+\t */\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \\\n \t\tUINT32_C(0x1)\n-\t/* Pair between REP on local host with REP on specified host. */\n+\t/*\n+\t * Pair between REP on local host with REP on specified host.\n+\t * (deprecated)\n+\t */\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \\\n \t\tUINT32_C(0x2)\n-\t/* Pair for the proxy interface. */\n+\t/* Pair for the proxy interface. (deprecated) */\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \\\n \t\tUINT32_C(0x3)\n-\t/* Pair for the PF interface. */\n+\t/* Pair for the PF interface. (deprecated) */\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \\\n \t\tUINT32_C(0x4)\n-\t/* Modify existing rep2fn pair and move pair to new PF. */\n+\t/* Modify existing rep2fn pair and move pair to new PF. (deprecated) */\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \\\n \t\tUINT32_C(0x5)\n \t/*\n \t * Modify existing rep2fn pairs paired with same PF and move pairs\n-\t * to new PF.\n+\t * to new PF. (deprecated)\n \t */\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \\\n \t\tUINT32_C(0x6)\n@@ -46672,21 +48503,30 @@ struct hwrm_cfa_pair_free_input {\n \t * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).\n \t */\n \tuint16_t\tpair_mode;\n-\t/* Pair between VF on local host with PF or VF on specified host. */\n+\t/*\n+\t * Pair between VF on local host with PF or VF on specified host.\n+\t * (deprecated)\n+\t */\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)\n-\t/* Pair between REP on local host with PF or VF on specified host. */\n+\t/*\n+\t * Pair between REP on local host with PF or VF on specified host.\n+\t * (deprecated)\n+\t */\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)\n-\t/* Pair between REP on local host with REP on specified host. */\n+\t/*\n+\t * Pair between REP on local host with REP on specified host.\n+\t * (deprecated)\n+\t */\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)\n-\t/* Pair for the proxy interface. */\n+\t/* Pair for the proxy interface. (deprecated) */\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)\n-\t/* Pair for the PF interface. */\n+\t/* Pair for the PF interface. (deprecated) */\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)\n-\t/* Modify existing rep2fn pair and move pair to new PF. */\n+\t/* Modify existing rep2fn pair and move pair to new PF. (deprecated) */\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)\n \t/*\n \t * Modify existing rep2fn pairs paired with same PF and move pairs\n-\t * to new PF.\n+\t * to new PF. (deprecated)\n \t */\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)\n \t/*\n@@ -46808,15 +48648,24 @@ struct hwrm_cfa_pair_info_output {\n \tuint16_t\ttx_cfa_action_b;\n \t/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */\n \tuint8_t\tpair_mode;\n-\t/* Pair between VF on local host with PF or VF on specified host. */\n+\t/*\n+\t * Pair between VF on local host with PF or VF on specified host.\n+\t * (deprecated)\n+\t */\n \t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)\n-\t/* Pair between REP on local host with PF or VF on specified host. */\n+\t/*\n+\t * Pair between REP on local host with PF or VF on specified host.\n+\t * (deprecated)\n+\t */\n \t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)\n-\t/* Pair between REP on local host with REP on specified host. */\n+\t/*\n+\t * Pair between REP on local host with REP on specified host.\n+\t * (deprecated)\n+\t */\n \t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)\n-\t/* Pair for the proxy interface. */\n+\t/* Pair for the proxy interface. (deprecated) */\n \t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)\n-\t/* Pair for the PF interface. */\n+\t/* Pair for the PF interface. (deprecated) */\n \t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)\n \t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \\\n \t\tHWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR\n@@ -47084,6 +48933,9 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {\n \t */\n \t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0x2000)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE \\\n+\t\tUINT32_C(0x4000)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -48272,7 +50124,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t * Value of 1 to indicate firmware support flow batch delete\n \t * operation through HWRM_CFA_FLOW_FLUSH command.\n \t * Value of 0 to indicate that the firmware does not support flow\n-\t * batch delete operation.\n+\t * batch delete operation. (deprecated)\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \\\n \t\tUINT32_C(0x4)\n@@ -48280,7 +50132,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t * Value of 1 to indicate that the firmware support flow reset all\n \t * operation through HWRM_CFA_FLOW_FLUSH command.\n \t * Value of 0 indicates firmware does not support flow reset all\n-\t * operation.\n+\t * operation. (deprecated)\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \\\n \t\tUINT32_C(0x8)\n@@ -48295,12 +50147,14 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t/*\n \t * Value of 1 to indicate that firmware supports TX EEM flows.\n \t * Value of 0 indicates firmware does not support TX EEM flows.\n+\t * (deprecated)\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \\\n \t\tUINT32_C(0x20)\n \t/*\n \t * Value of 1 to indicate that firmware supports RX EEM flows.\n \t * Value of 0 indicates firmware does not support RX EEM flows.\n+\t * (deprecated)\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \\\n \t\tUINT32_C(0x40)\n@@ -48309,6 +50163,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t * allocation of an on-chip flow counter which can be used for EEM\n \t * flows. Value of 0 indicates firmware does not support the dynamic\n \t * allocation of an on-chip flow counter.\n+\t * (deprecated)\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \\\n \t\tUINT32_C(0x80)\n@@ -48390,6 +50245,19 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \\\n \t\tUINT32_C(0x40000)\n+\t/*\n+\t * If set to 1, firmware is capable returning stats for nic flows\n+\t * in cfa_flow_stats command where flow_handle value 0xF000.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED \\\n+\t\tUINT32_C(0x80000)\n+\t/*\n+\t * If set to 1, firmware is capable of supporting these additional\n+\t * ip_protoccols: ICMP, ICMPV6, RSVD for ntuple rules. By default,\n+\t * this flag should be 0 for older version of firmware.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED \\\n+\t\tUINT32_C(0x100000)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -50172,7 +52040,7 @@ struct hwrm_tf_tbl_type_get_input {\n \tuint32_t\tindex;\n } __rte_packed;\n \n-/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */\n+/* hwrm_tf_tbl_type_get_output (size:2240b/280B) */\n struct hwrm_tf_tbl_type_get_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -50189,7 +52057,7 @@ struct hwrm_tf_tbl_type_get_output {\n \t/* unused */\n \tuint16_t\tunused0;\n \t/* Response data. */\n-\tuint8_t\tdata[128];\n+\tuint8_t\tdata[256];\n \t/* unused */\n \tuint8_t\tunused1[7];\n \t/*\n@@ -50250,6 +52118,8 @@ struct hwrm_tf_tbl_type_set_input {\n \t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX\n+\t/* Indicate table data is being sent via DMA. */\n+\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA UINT32_C(0x2)\n \t/* unused. */\n \tuint8_t\tunused0[2];\n \t/*\n@@ -52298,133 +54168,2494 @@ struct hwrm_tf_if_tbl_set_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n+\t/*\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Index of the type to set. */\n+\tuint32_t\tindex;\n+\t/* Size of the data to set. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint8_t\tunused1[6];\n+\t/* Data to be set. */\n+\tuint8_t\tdata[88];\n+} __rte_packed;\n+\n+/* hwrm_tf_if_tbl_set_output (size:128b/16B) */\n+struct hwrm_tf_if_tbl_set_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*****************************\n+ * hwrm_tf_tbl_type_bulk_get *\n+ *****************************/\n+\n+\n+/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */\n+struct hwrm_tf_tbl_type_bulk_get_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * When set use the special access register access to clear\n+\t * the table entries on read.\n+\t */\n+\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \\\n+\t\tUINT32_C(0x2)\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n+\t/*\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Starting index of the type to retrieve. */\n+\tuint32_t\tstart_index;\n+\t/* Number of entries to retrieve. */\n+\tuint32_t\tnum_entries;\n+\t/* Number of entries to retrieve. */\n+\tuint32_t\tunused1;\n+\t/* Host memory where data will be stored. */\n+\tuint64_t\thost_addr;\n+} __rte_packed;\n+\n+/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */\n+struct hwrm_tf_tbl_type_bulk_get_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Response code. */\n+\tuint32_t\tresp_code;\n+\t/* Response size. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint8_t\tunused0;\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/***********************************\n+ * hwrm_tf_session_hotup_state_set *\n+ ***********************************/\n+\n+\n+/* hwrm_tf_session_hotup_state_set_input (size:192b/24B) */\n+struct hwrm_tf_session_hotup_state_set_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Shared session state. */\n+\tuint16_t\tstate;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX\n+} __rte_packed;\n+\n+/* hwrm_tf_session_hotup_state_set_output (size:128b/16B) */\n+struct hwrm_tf_session_hotup_state_set_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/***********************************\n+ * hwrm_tf_session_hotup_state_get *\n+ ***********************************/\n+\n+\n+/* hwrm_tf_session_hotup_state_get_input (size:192b/24B) */\n+struct hwrm_tf_session_hotup_state_get_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n+} __rte_packed;\n+\n+/* hwrm_tf_session_hotup_state_get_output (size:128b/16B) */\n+struct hwrm_tf_session_hotup_state_get_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Shared session HA state. */\n+\tuint16_t\tstate;\n+\t/* Shared session HA reference count. */\n+\tuint16_t\tref_cnt;\n+\t/* unused. */\n+\tuint8_t\tunused0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/****************************\n+ * hwrm_tfc_tbl_scope_qcaps *\n+ ****************************/\n+\n+\n+/*\n+ * TruFlow command to check if firmware is capable of\n+ * supporting table scopes.\n+ */\n+/* hwrm_tfc_tbl_scope_qcaps_input (size:128b/16B) */\n+struct hwrm_tfc_tbl_scope_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+} __rte_packed;\n+\n+/* hwrm_tfc_tbl_scope_qcaps_output (size:192b/24B) */\n+struct hwrm_tfc_tbl_scope_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * The maximum number of lookup records that a table scope can support.\n+\t * This field is only valid if tbl_scope_capable is not zero.\n+\t */\n+\tuint32_t\tmax_lkup_rec_cnt;\n+\t/*\n+\t * The maximum number of action records that a table scope can support.\n+\t * This field is only valid if tbl_scope_capable is not zero.\n+\t */\n+\tuint32_t\tmax_act_rec_cnt;\n+\t/* Not zero if firmware capable of table scopes. */\n+\tuint8_t\ttbl_scope_capable;\n+\t/*\n+\t * log2 of the number of lookup static buckets that a table scope can\n+\t * support. This field is only valid if tbl_scope_capable is not zero.\n+\t */\n+\tuint8_t\tmax_lkup_static_buckets_exp;\n+\t/* unused. */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*******************************\n+ * hwrm_tfc_tbl_scope_id_alloc *\n+ *******************************/\n+\n+\n+/*\n+ * TruFlow command to allocate a table scope ID and create the pools.\n+ *\n+ * There is no corresponding free command since a table scope\n+ * ID will automatically be freed once the last FID is removed.\n+ * That is, when the hwrm_tfc_tbl_scope_fid_rem command returns\n+ * a fid_cnt of 0 that also means that the table scope ID has\n+ * been freed.\n+ */\n+/* hwrm_tfc_tbl_scope_id_alloc_input (size:192b/24B) */\n+struct hwrm_tfc_tbl_scope_id_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* The maximum number of pools for this table scope. */\n+\tuint16_t\tmax_pools;\n+\t/* Non-zero if this table scope is shared. */\n+\tuint8_t\tshared;\n+\t/*\n+\t * The size of the lookup pools per direction expressed as\n+\t * log2(max_records/max_pools). That is, size=2^exp.\n+\t *\n+\t * Array is indexed by enum cfa_dir.\n+\t */\n+\tuint8_t\tlkup_pool_sz_exp[2];\n+\t/*\n+\t * The size of the action pools per direction expressed as\n+\t * log2(max_records/max_pools). That is, size=2^exp.\n+\t *\n+\t * Array is indexed by enum cfa_dir.\n+\t */\n+\tuint8_t\tact_pool_sz_exp[2];\n+\t/* unused. */\n+\tuint8_t\tunused0;\n+} __rte_packed;\n+\n+/* hwrm_tfc_tbl_scope_id_alloc_output (size:128b/16B) */\n+struct hwrm_tfc_tbl_scope_id_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The table scope ID that was allocated. */\n+\tuint8_t\ttsid;\n+\t/*\n+\t * Non-zero if this is the first FID associated with this table scope\n+\t * ID.\n+\t */\n+\tuint8_t\tfirst;\n+\t/* unused. */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*****************************\n+ * hwrm_tfc_tbl_scope_config *\n+ *****************************/\n+\n+\n+/* TruFlow command to configure the table scope memory. */\n+/* hwrm_tfc_tbl_scope_config_input (size:704b/88B) */\n+struct hwrm_tfc_tbl_scope_config_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * The base addresses for lookup memory.\n+\t * Array is indexed by enum cfa_dir.\n+\t */\n+\tuint64_t\tlkup_base_addr[2];\n+\t/*\n+\t * The base addresses for action memory.\n+\t * Array is indexed by enum cfa_dir.\n+\t */\n+\tuint64_t\tact_base_addr[2];\n+\t/*\n+\t * The number of minimum sized lkup records per direction.\n+\t * In this usage, records are the minimum lookup memory\n+\t * allocation unit in a table scope. This value is the total\n+\t * memory required for buckets and entries.\n+\t *\n+\t * Array is indexed by enum cfa_dir.\n+\t */\n+\tuint32_t\tlkup_rec_cnt[2];\n+\t/*\n+\t * The number of minimum sized action records per direction.\n+\t * Similar to the lkup_rec_cnt, records are the minimum\n+\t * action memory allocation unit in a table scope.\n+\t *\n+\t * Array is indexed by enum cfa_dir.\n+\t */\n+\tuint32_t\tact_rec_cnt[2];\n+\t/*\n+\t * The number of static lookup buckets in the table scope.\n+\t * Array is indexed by enum cfa_dir.\n+\t */\n+\tuint32_t\tlkup_static_bucket_cnt[2];\n+\t/* The page size of the table scope. */\n+\tuint32_t\tpbl_page_sz;\n+\t/*\n+\t * The PBL level for lookup memory.\n+\t * Array is indexed by enum cfa_dir.\n+\t */\n+\tuint8_t\tlkup_pbl_level[2];\n+\t/*\n+\t * The PBL level for action memory.\n+\t * Array is indexed by enum cfa_dir.\n+\t */\n+\tuint8_t\tact_pbl_level[2];\n+\t/* The table scope ID. */\n+\tuint8_t\ttsid;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+} __rte_packed;\n+\n+/* hwrm_tfc_tbl_scope_config_output (size:128b/16B) */\n+struct hwrm_tfc_tbl_scope_config_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*******************************\n+ * hwrm_tfc_tbl_scope_deconfig *\n+ *******************************/\n+\n+\n+/* TruFlow command to deconfigure the table scope memory. */\n+/* hwrm_tfc_tbl_scope_deconfig_input (size:192b/24B) */\n+struct hwrm_tfc_tbl_scope_deconfig_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* The table scope ID. */\n+\tuint8_t\ttsid;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+} __rte_packed;\n+\n+/* hwrm_tfc_tbl_scope_deconfig_output (size:128b/16B) */\n+struct hwrm_tfc_tbl_scope_deconfig_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/******************************\n+ * hwrm_tfc_tbl_scope_fid_add *\n+ ******************************/\n+\n+\n+/* TruFlow command to add a FID to a table scope. */\n+/* hwrm_tfc_tbl_scope_fid_add_input (size:192b/24B) */\n+struct hwrm_tfc_tbl_scope_fid_add_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* The table scope ID. */\n+\tuint8_t\ttsid;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+} __rte_packed;\n+\n+/* hwrm_tfc_tbl_scope_fid_add_output (size:128b/16B) */\n+struct hwrm_tfc_tbl_scope_fid_add_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The number of FIDs currently in the table scope ID. */\n+\tuint8_t\tfid_cnt;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/******************************\n+ * hwrm_tfc_tbl_scope_fid_rem *\n+ ******************************/\n+\n+\n+/* TruFlow command to remove a FID from a table scope. */\n+/* hwrm_tfc_tbl_scope_fid_rem_input (size:192b/24B) */\n+struct hwrm_tfc_tbl_scope_fid_rem_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* The table scope ID. */\n+\tuint8_t\ttsid;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+} __rte_packed;\n+\n+/* hwrm_tfc_tbl_scope_fid_rem_output (size:128b/16B) */\n+struct hwrm_tfc_tbl_scope_fid_rem_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The number of FIDs remaining in the table scope ID. */\n+\tuint16_t\tfid_cnt;\n+\t/* unused. */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*********************************\n+ * hwrm_tfc_tbl_scope_pool_alloc *\n+ *********************************/\n+\n+\n+/* hwrm_tfc_tbl_scope_pool_alloc_input (size:192b/24B) */\n+struct hwrm_tfc_tbl_scope_pool_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Table Scope ID */\n+\tuint8_t\ttsid;\n+\t/* Control flags. Direction and type. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX\n+\t/* Indicates the table type. */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE \\\n+\t\tUINT32_C(0x2)\n+\t/* Lookup table */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LOOKUP \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/* Action table */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LAST \\\n+\t\tHWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION\n+\t/* Unused */\n+\tuint8_t\tunused[6];\n+} __rte_packed;\n+\n+/* hwrm_tfc_tbl_scope_pool_alloc_output (size:128b/16B) */\n+struct hwrm_tfc_tbl_scope_pool_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Pool ID */\n+\tuint16_t\tpool_id;\n+\t/* Pool size exponent. An exponent of 0 indicates a failure. */\n+\tuint8_t\tpool_sz_exp;\n+\t/* unused. */\n+\tuint8_t\tunused1[4];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/********************************\n+ * hwrm_tfc_tbl_scope_pool_free *\n+ ********************************/\n+\n+\n+/* hwrm_tfc_tbl_scope_pool_free_input (size:192b/24B) */\n+struct hwrm_tfc_tbl_scope_pool_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Table Scope ID */\n+\tuint8_t\ttsid;\n+\t/* Control flags. Direction and type. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX\n+\t/* Indicates the table type. */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE \\\n+\t\tUINT32_C(0x2)\n+\t/* Lookup table */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LOOKUP \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/* Action table */\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t#define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LAST \\\n+\t\tHWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION\n+\t/* Pool ID */\n+\tuint16_t\tpool_id;\n+\t/* Unused */\n+\tuint8_t\tunused[4];\n+} __rte_packed;\n+\n+/* hwrm_tfc_tbl_scope_pool_free_output (size:128b/16B) */\n+struct hwrm_tfc_tbl_scope_pool_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*****************************\n+ * hwrm_tfc_session_id_alloc *\n+ *****************************/\n+\n+\n+/*\n+ * Allocate a TFC session. Requests the firmware to allocate a TFC\n+ * session identifier and associate a forwarding function with the\n+ * session. Though there's not an explicit matching free for a session\n+ * id alloc, dis-associating the last fid from a session id (fid_cnt goes\n+ * to 0), will result in this session id being freed automatically.\n+ */\n+/* hwrm_tfc_session_id_alloc_input (size:128b/16B) */\n+struct hwrm_tfc_session_id_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+} __rte_packed;\n+\n+/* hwrm_tfc_session_id_alloc_output (size:128b/16B) */\n+struct hwrm_tfc_session_id_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Unused field */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/****************************\n+ * hwrm_tfc_session_fid_add *\n+ ****************************/\n+\n+\n+/*\n+ * Associate a TFC session id with a forwarding function. The target_fid\n+ * will be associated with the passed in sid.\n+ */\n+/* hwrm_tfc_session_fid_add_input (size:192b/24B) */\n+struct hwrm_tfc_session_fid_add_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Unused field */\n+\tuint8_t\tunused0[6];\n+} __rte_packed;\n+\n+/* hwrm_tfc_session_fid_add_output (size:128b/16B) */\n+struct hwrm_tfc_session_fid_add_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The number of FIDs that share this session. */\n+\tuint16_t\tfid_cnt;\n+\t/* Unused field */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/****************************\n+ * hwrm_tfc_session_fid_rem *\n+ ****************************/\n+\n+\n+/*\n+ * Dis-associate a TFC session from the target_fid.\n+ * Though there's not an explicit matching free for a\n+ * session id alloc, dis-associating the last fid from a session id\n+ * (fid_cnt goes to 0), will result in this session id being freed\n+ * automatically.\n+ */\n+/* hwrm_tfc_session_fid_rem_input (size:192b/24B) */\n+struct hwrm_tfc_session_fid_rem_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Unused field */\n+\tuint8_t\tunused0[6];\n+} __rte_packed;\n+\n+/* hwrm_tfc_session_fid_rem_output (size:128b/16B) */\n+struct hwrm_tfc_session_fid_rem_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The number of FIDs that share this session. */\n+\tuint16_t\tfid_cnt;\n+\t/* Unused field */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/************************\n+ * hwrm_tfc_ident_alloc *\n+ ************************/\n+\n+\n+/*\n+ * Allocate a TFC identifier. Requests the firmware to\n+ * allocate a TFC identifier. The session id and track_type are passed\n+ * in. The tracking_id is either the sid or target_fid depends on the\n+ * track_type. The resource subtype is passed in, an id corresponding\n+ * to all these is allocated and returned in the HWRM response.\n+ */\n+/* hwrm_tfc_ident_alloc_input (size:192b/24B) */\n+struct hwrm_tfc_ident_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware. Will be used to track this identifier.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Control flags. Direction. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * CFA resource subtype. For definitions, please see\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/* Describes the type of tracking tag to be used */\n+\tuint8_t\ttrack_type;\n+\t/* Invalid track type */\n+\t#define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \\\n+\t\tUINT32_C(0x0)\n+\t/* Tracked by session id */\n+\t#define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \\\n+\t\tUINT32_C(0x1)\n+\t/* Tracked by function id */\n+\t#define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_LAST \\\n+\t\tHWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID\n+\t/* Unused field */\n+\tuint8_t\tunused0[3];\n+} __rte_packed;\n+\n+/* hwrm_tfc_ident_alloc_output (size:128b/16B) */\n+struct hwrm_tfc_ident_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Resource identifier allocated by the firmware using\n+\t * parameters above.\n+\t */\n+\tuint16_t\tident_id;\n+\t/* Unused field */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/***********************\n+ * hwrm_tfc_ident_free *\n+ ***********************/\n+\n+\n+/*\n+ * Requests the firmware to free a TFC resource identifier.\n+ * A resource subtype and session id are passed in.\n+ * An identifier (previously allocated) corresponding to all these is\n+ * freed, only after various sanity checks are completed.\n+ */\n+/* hwrm_tfc_ident_free_input (size:192b/24B) */\n+struct hwrm_tfc_ident_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware. Will be used to validate this request.\n+\t */\n+\tuint16_t\tsid;\n+\t/*\n+\t * CFA resource subtype. For definitions, please see\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/* Control flags. Direction. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX\n+\t/* The resource identifier to be freed */\n+\tuint16_t\tident_id;\n+\t/* Reserved */\n+\tuint8_t\tunused0[2];\n+} __rte_packed;\n+\n+/* hwrm_tfc_ident_free_output (size:128b/16B) */\n+struct hwrm_tfc_ident_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Reserved */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**************************\n+ * hwrm_tfc_idx_tbl_alloc *\n+ **************************/\n+\n+\n+/* hwrm_tfc_idx_tbl_alloc_input (size:192b/24B) */\n+struct hwrm_tfc_idx_tbl_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Unique session id for the session created by the\n+\t * firmware. Will be used to track this index table entry\n+\t * only if track type is track_type_sid.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Control flags. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * CFA resource subtype. For definitions, please see\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/* Describes the type of tracking id to be used */\n+\tuint8_t\ttrack_type;\n+\t/* Invalid track type */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \\\n+\t\tUINT32_C(0x0)\n+\t/* Tracked by session id */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \\\n+\t\tUINT32_C(0x1)\n+\t/* Tracked by function id */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_LAST \\\n+\t\tHWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID\n+\t/* Reserved */\n+\tuint8_t\tunused0[3];\n+} __rte_packed;\n+\n+/* hwrm_tfc_idx_tbl_alloc_output (size:128b/16B) */\n+struct hwrm_tfc_idx_tbl_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Index table entry allocated by the firmware using the\n+\t * parameters above.\n+\t */\n+\tuint16_t\tidx_tbl_id;\n+\t/* Reserved */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/******************************\n+ * hwrm_tfc_idx_tbl_alloc_set *\n+ ******************************/\n+\n+\n+/* hwrm_tfc_idx_tbl_alloc_set_input (size:1088b/136B) */\n+struct hwrm_tfc_idx_tbl_alloc_set_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Unique session id for the session created by the\n+\t * firmware. Will be used to track this index table entry\n+\t * only if track type is track_type_sid.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Control flags. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Indicate device data is being sent via DMA, the device\n+\t * data packing does not change.\n+\t */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2)\n+\t/*\n+\t * CFA resource subtype. For definitions, please see\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/* Describes the type of tracking id to be used */\n+\tuint8_t\ttrack_type;\n+\t/* Invalid track type */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \\\n+\t\tUINT32_C(0x0)\n+\t/* Tracked by session id */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID \\\n+\t\tUINT32_C(0x1)\n+\t/* Tracked by function id */\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_LAST \\\n+\t\tHWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID\n+\t/* Reserved */\n+\tuint8_t\tunused0;\n+\t/* The size of the index table entry in bytes. */\n+\tuint16_t\tdata_size;\n+\t/* The location of the dma buffer */\n+\tuint64_t\tdma_addr;\n+\t/*\n+\t * Index table data located at offset 0. If dma bit is set,\n+\t * then this field contains the DMA buffer pointer.\n+\t */\n+\tuint8_t\tdev_data[104];\n+} __rte_packed;\n+\n+/* hwrm_tfc_idx_tbl_alloc_set_output (size:128b/16B) */\n+struct hwrm_tfc_idx_tbl_alloc_set_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Index table entry allocated by the firmware using the\n+\t * parameters above.\n+\t */\n+\tuint16_t\tidx_tbl_id;\n+\t/* Reserved */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/************************\n+ * hwrm_tfc_idx_tbl_set *\n+ ************************/\n+\n+\n+/* hwrm_tfc_idx_tbl_set_input (size:1088b/136B) */\n+struct hwrm_tfc_idx_tbl_set_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Indicate device data is being sent via DMA, the device\n+\t * data packing does not change.\n+\t */\n+\t#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DMA UINT32_C(0x2)\n+\t/*\n+\t * CFA resource subtype. For definitions, please see\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/*\n+\t * Session id associated with the firmware. Will be used\n+\t * for validation if the track type matches.\n+\t */\n+\tuint16_t\tsid;\n+\t/*\n+\t * Index table index returned during alloc by the\n+\t * firmware.\n+\t */\n+\tuint16_t\tidx_tbl_id;\n+\t/* The size of the index table entry in bytes. */\n+\tuint16_t\tdata_size;\n+\t/* The location of the dma buffer */\n+\tuint64_t\tdma_addr;\n+\t/*\n+\t * Index table data located at offset 0. If dma bit is set,\n+\t * then this field contains the DMA buffer pointer.\n+\t */\n+\tuint8_t\tdev_data[104];\n+} __rte_packed;\n+\n+/* hwrm_tfc_idx_tbl_set_output (size:128b/16B) */\n+struct hwrm_tfc_idx_tbl_set_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/************************\n+ * hwrm_tfc_idx_tbl_get *\n+ ************************/\n+\n+\n+/* hwrm_tfc_idx_tbl_get_input (size:256b/32B) */\n+struct hwrm_tfc_idx_tbl_get_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * When set use the special access register access to clear\n+\t * the table entry on read.\n+\t */\n+\t#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_CLEAR_ON_READ \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * CFA resource subtype. For definitions, please see\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/*\n+\t * Session id associated with the firmware. Will be used\n+\t * for validation if the track type matches.\n+\t */\n+\tuint16_t\tsid;\n+\t/*\n+\t * Index table index returned during alloc by the\n+\t * firmware.\n+\t */\n+\tuint16_t\tidx_tbl_id;\n+\t/* The size of the index table entry buffer in bytes. */\n+\tuint16_t\tbuffer_size;\n+\t/* The location of the response dma buffer */\n+\tuint64_t\tdma_addr;\n+} __rte_packed;\n+\n+/* hwrm_tfc_idx_tbl_get_output (size:128b/16B) */\n+struct hwrm_tfc_idx_tbl_get_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The size of the index table buffer returned in device size bytes. */\n+\tuint16_t\tdata_size;\n+\t/* unused */\n+\tuint8_t\tunused1[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*************************\n+ * hwrm_tfc_idx_tbl_free *\n+ *************************/\n+\n+\n+/* hwrm_tfc_idx_tbl_free_input (size:192b/24B) */\n+struct hwrm_tfc_idx_tbl_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * CFA resource subtype. For definitions, please see\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/*\n+\t * Session id associated with the firmware. Will be used\n+\t * for validation if the track type matches.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Index table id to be freed by the firmware. */\n+\tuint16_t\tidx_tbl_id;\n+\t/* Reserved */\n+\tuint8_t\tunused0[2];\n+} __rte_packed;\n+\n+/* hwrm_tfc_idx_tbl_free_output (size:128b/16B) */\n+struct hwrm_tfc_idx_tbl_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Reserved */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/* TruFlow resources request for a global id. */\n+/* tfc_global_id_hwrm_req (size:64b/8B) */\n+struct tfc_global_id_hwrm_req {\n+\t/* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */\n+\tuint16_t\trtype;\n+\t/* Indicates the flow direction in type of cfa_dir. */\n+\tuint16_t\tdir;\n+\t/* Subtype of the resource type. */\n+\tuint16_t\tsubtype;\n+\t/* Number of the type of resources. */\n+\tuint16_t\tcnt;\n+} __rte_packed;\n+\n+/* The reserved resources for the global id. */\n+/* tfc_global_id_hwrm_rsp (size:64b/8B) */\n+struct tfc_global_id_hwrm_rsp {\n+\t/* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */\n+\tuint16_t\trtype;\n+\t/* Indicates the flow direction in type of cfa_dir. */\n+\tuint16_t\tdir;\n+\t/* Subtype of the resource type. */\n+\tuint16_t\tsubtype;\n+\t/* The global id that the resources reserved for. */\n+\tuint16_t\tid;\n+} __rte_packed;\n+\n+/****************************\n+ * hwrm_tfc_global_id_alloc *\n+ ****************************/\n+\n+\n+/* hwrm_tfc_global_id_alloc_input (size:320b/40B) */\n+struct hwrm_tfc_global_id_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint16_t\tsid;\n+\t/* Global domain id. */\n+\tuint16_t\tglobal_id;\n+\t/*\n+\t * Defines the array size of the provided req_addr and\n+\t * resv_addr array buffers. Should be set to the number of\n+\t * request entries.\n+\t */\n+\tuint16_t\treq_cnt;\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n+\t/*\n+\t * This is the DMA address for the request input data array\n+\t * buffer. Array is of tfc_global_id_hwrm_req type. Size of the\n+\t * array buffer is provided by the 'req_cnt' field in this\n+\t * message.\n+\t */\n+\tuint64_t\treq_addr;\n+\t/*\n+\t * This is the DMA address for the resc output data array\n+\t * buffer. Array is of tfc_global_id_hwrm_rsp type. Size of the array\n+\t * buffer is provided by the 'req_cnt' field in this\n+\t * message.\n+\t */\n+\tuint64_t\tresc_addr;\n+} __rte_packed;\n+\n+/* hwrm_tfc_global_id_alloc_output (size:128b/16B) */\n+struct hwrm_tfc_global_id_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Size of the returned hwrm_tfc_global_id_req data array. The value\n+\t * cannot exceed the req_cnt defined by the input msg. The data\n+\t * array is returned using the resv_addr specified DMA\n+\t * address also provided by the input msg.\n+\t */\n+\tuint16_t\trsp_cnt;\n+\t/* Non-zero if this is the first allocation for the global ID. */\n+\tuint8_t\tfirst;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*********************\n+ * hwrm_tfc_tcam_set *\n+ *********************/\n+\n+\n+/* hwrm_tfc_tcam_set_input (size:1088b/136B) */\n+struct hwrm_tfc_tcam_set_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Session id associated with the firmware. Will be used\n+\t * for validation if the track type matches.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Logical TCAM ID. */\n+\tuint16_t\ttcam_id;\n+\t/* Number of bytes in the TCAM key. */\n+\tuint16_t\tkey_size;\n+\t/* Number of bytes in the TCAM result. */\n+\tuint16_t\tresult_size;\n+\t/* Control flags. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX\n+\t/* Indicate device data is being sent via DMA. */\n+\t#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)\n+\t/*\n+\t * Subtype of TCAM resource. See\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n+\t/* The location of the response dma buffer */\n+\tuint64_t\tdma_addr;\n+\t/*\n+\t * TCAM key located at offset 0, mask located at mask_offset\n+\t * and result at result_offset for the device.\n+\t */\n+\tuint8_t\tdev_data[96];\n+} __rte_packed;\n+\n+/* hwrm_tfc_tcam_set_output (size:128b/16B) */\n+struct hwrm_tfc_tcam_set_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*********************\n+ * hwrm_tfc_tcam_get *\n+ *********************/\n+\n+\n+/* hwrm_tfc_tcam_get_input (size:192b/24B) */\n+struct hwrm_tfc_tcam_get_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Subtype of TCAM resource See\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/*\n+\t * Session id associated with the firmware. Will be used\n+\t * for validation if the track type matches.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Logical TCAM ID. */\n+\tuint16_t\ttcam_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n+} __rte_packed;\n+\n+/* hwrm_tfc_tcam_get_output (size:2368b/296B) */\n+struct hwrm_tfc_tcam_get_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Number of bytes in the TCAM key. */\n+\tuint16_t\tkey_size;\n+\t/* Number of bytes in the TCAM result. */\n+\tuint16_t\tresult_size;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n+\t/*\n+\t * TCAM key located at offset 0, mask located at key_size\n+\t * and result at 2 * key_size for the device.\n+\t */\n+\tuint8_t\tdev_data[272];\n+\t/* unused. */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written. When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/***********************\n+ * hwrm_tfc_tcam_alloc *\n+ ***********************/\n+\n+\n+/* hwrm_tfc_tcam_alloc_input (size:256b/32B) */\n+struct hwrm_tfc_tcam_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Subtype of TCAM resource. See\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/*\n+\t * Unique session id for the session created by the\n+\t * firmware. Will be used to track this index table entry\n+\t * only if track type is track_type_sid.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Number of bytes in the TCAM key. */\n+\tuint16_t\tkey_size;\n+\t/* Entry priority. */\n+\tuint16_t\tpriority;\n+\t/* Describes the type of tracking id to be used */\n+\tuint8_t\ttrack_type;\n+\t/* Invalid track type */\n+\t#define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \\\n+\t\tUINT32_C(0x0)\n+\t/* Tracked by session id */\n+\t#define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \\\n+\t\tUINT32_C(0x1)\n+\t/* Tracked by function id */\n+\t#define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_LAST \\\n+\t\tHWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID\n+\t/* Unused. */\n+\tuint8_t\tunused0[7];\n+} __rte_packed;\n+\n+/* hwrm_tfc_tcam_alloc_output (size:128b/16B) */\n+struct hwrm_tfc_tcam_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Index table entry allocated by the firmware using the\n+\t * parameters above.\n+\t */\n+\tuint16_t\tidx;\n+\t/* Reserved */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/***************************\n+ * hwrm_tfc_tcam_alloc_set *\n+ ***************************/\n+\n+\n+/* hwrm_tfc_tcam_alloc_set_input (size:1088b/136B) */\n+struct hwrm_tfc_tcam_alloc_set_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint8_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n+\t#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX\n+\t/* Indicate device data is being sent via DMA. */\n+\t#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2)\n+\t/*\n+\t * Subtype of TCAM resource. See\n+\t * cfa_v3/include/cfa_resources.h.\n+\t */\n+\tuint8_t\tsubtype;\n+\t/*\n+\t * Unique session id for the session created by the\n+\t * firmware. Will be used to track this index table entry\n+\t * only if track type is track_type_sid.\n+\t */\n+\tuint16_t\tsid;\n+\t/* Number of bytes in the TCAM key. */\n+\tuint16_t\tkey_size;\n+\t/* The size of the TCAM table entry in bytes. */\n+\tuint16_t\tresult_size;\n+\t/* Entry priority. */\n+\tuint16_t\tpriority;\n+\t/* Describes the type of tracking id to be used */\n+\tuint8_t\ttrack_type;\n+\t/* Invalid track type */\n+\t#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \\\n+\t\tUINT32_C(0x0)\n+\t/* Tracked by session id */\n+\t#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID \\\n+\t\tUINT32_C(0x1)\n+\t/* Tracked by function id */\n+\t#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_LAST \\\n+\t\tHWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID\n+\t/* Unused */\n+\tuint8_t\tunused[5];\n+\t/* The location of the response dma buffer */\n+\tuint64_t\tdma_addr;\n+\t/*\n+\t * Index table data located at offset 0. If dma bit is set,\n+\t * then this field contains the DMA buffer pointer.\n+\t */\n+\tuint8_t\tdev_data[96];\n+} __rte_packed;\n+\n+/* hwrm_tfc_tcam_alloc_set_output (size:128b/16B) */\n+struct hwrm_tfc_tcam_alloc_set_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Logical TCAM ID. */\n+\tuint16_t\ttcam_id;\n+\t/* Reserved */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**********************\n+ * hwrm_tfc_tcam_free *\n+ **********************/\n+\n+\n+/* hwrm_tfc_tcam_free_input (size:192b/24B) */\n+struct hwrm_tfc_tcam_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n \t/* Control flags. */\n-\tuint16_t\tflags;\n+\tuint8_t\tflags;\n \t/* Indicates the flow direction. */\n-\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t#define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t#define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n \t/* If this bit is set to 1, then it indicates tx flow. */\n-\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n-\t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX\n-\t/* unused. */\n-\tuint8_t\tunused0[2];\n-\t/*\n-\t * Type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n-\t */\n-\tuint32_t\ttype;\n-\t/* Index of the type to set. */\n-\tuint32_t\tindex;\n-\t/* Size of the data to set. */\n-\tuint16_t\tsize;\n-\t/* unused */\n-\tuint8_t\tunused1[6];\n-\t/* Data to be set. */\n-\tuint8_t\tdata[88];\n-} __rte_packed;\n-\n-/* hwrm_tf_if_tbl_set_output (size:128b/16B) */\n-struct hwrm_tf_if_tbl_set_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* unused. */\n-\tuint8_t\tunused0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field\n-\t * is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __rte_packed;\n-\n-/*****************************\n- * hwrm_tf_tbl_type_bulk_get *\n- *****************************/\n-\n-\n-/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */\n-struct hwrm_tf_tbl_type_bulk_get_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\t#define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * Subtype of TCAM resource. See\n+\t * cfa_v3/include/cfa_resources.h.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint8_t\tsubtype;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Session id associated with the firmware. Will be used\n+\t * for validation if the track type matches.\n \t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n-\t * * 0xFFFD - Reserved for user-space HWRM interface\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n-\tuint32_t\tfw_session_id;\n-\t/* Control flags. */\n-\tuint16_t\tflags;\n-\t/* Indicates the flow direction. */\n-\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \\\n-\t\tUINT32_C(0x1)\n-\t/* If this bit set to 0, then it indicates rx flow. */\n-\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \\\n-\t\tUINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates tx flow. */\n-\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \\\n-\t\tUINT32_C(0x1)\n-\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \\\n-\t\tHWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX\n-\t/*\n-\t * When set use the special access register access to clear\n-\t * the table entries on read.\n-\t */\n-\t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \\\n-\t\tUINT32_C(0x2)\n-\t/* unused. */\n+\tuint16_t\tsid;\n+\t/* Logical TCAM ID. */\n+\tuint16_t\ttcam_id;\n+\t/* Reserved */\n \tuint8_t\tunused0[2];\n-\t/*\n-\t * Type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n-\t */\n-\tuint32_t\ttype;\n-\t/* Starting index of the type to retrieve. */\n-\tuint32_t\tstart_index;\n-\t/* Number of entries to retrieve. */\n-\tuint32_t\tnum_entries;\n-\t/* Number of entries to retrieve. */\n-\tuint32_t\tunused1;\n-\t/* Host memory where data will be stored. */\n-\tuint64_t\thost_addr;\n } __rte_packed;\n \n-/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */\n-struct hwrm_tf_tbl_type_bulk_get_output {\n+/* hwrm_tfc_tcam_free_output (size:128b/16B) */\n+struct hwrm_tfc_tcam_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -52433,12 +56664,8 @@ struct hwrm_tf_tbl_type_bulk_get_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Response code. */\n-\tuint32_t\tresp_code;\n-\t/* Response size. */\n-\tuint16_t\tsize;\n-\t/* unused */\n-\tuint8_t\tunused0;\n+\t/* Reserved */\n+\tuint8_t\tunused0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -52505,8 +56732,20 @@ struct hwrm_tunnel_dst_port_query_input {\n \t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n \t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Custom GRE uses UPAR to parse customized GRE packets */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE \\\n+\t\tUINT32_C(0xd)\n+\t/* Enhanced Common Packet Radio Interface (eCPRI) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI \\\n+\t\tUINT32_C(0xe)\n+\t/* IPv6 Segment Routing (SRv6) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 \\\n+\t\tUINT32_C(0xf)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n+\t\tHWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE\n \tuint8_t\tunused_0[7];\n } __rte_packed;\n \n@@ -52538,7 +56777,38 @@ struct hwrm_tunnel_dst_port_query_output {\n \t * configured.\n \t */\n \tuint16_t\ttunnel_dst_port_val;\n-\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field represents the UPAR usage status.\n+\t * Available UPARs on wh+ are UPAR0 and UPAR1\n+\t * Available UPARs on Thor are UPAR0 to UPAR3\n+\t * Available UPARs on Thor2 are UPAR0 to UPAR7\n+\t */\n+\tuint8_t\tupar_in_use;\n+\t/* This bit will be '1' when UPAR0 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR0 \\\n+\t\tUINT32_C(0x1)\n+\t/* This bit will be '1' when UPAR1 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR1 \\\n+\t\tUINT32_C(0x2)\n+\t/* This bit will be '1' when UPAR2 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR2 \\\n+\t\tUINT32_C(0x4)\n+\t/* This bit will be '1' when UPAR3 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR3 \\\n+\t\tUINT32_C(0x8)\n+\t/* This bit will be '1' when UPAR4 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR4 \\\n+\t\tUINT32_C(0x10)\n+\t/* This bit will be '1' when UPAR5 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR5 \\\n+\t\tUINT32_C(0x20)\n+\t/* This bit will be '1' when UPAR6 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6 \\\n+\t\tUINT32_C(0x40)\n+\t/* This bit will be '1' when UPAR7 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 \\\n+\t\tUINT32_C(0x80)\n+\tuint8_t\tunused_0[2];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -52604,8 +56874,20 @@ struct hwrm_tunnel_dst_port_alloc_input {\n \t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n \t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE \\\n+\t\tUINT32_C(0xd)\n+\t/* Enhanced Common Packet Radio Interface (eCPRI) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI \\\n+\t\tUINT32_C(0xe)\n+\t/* IPv6 Segment Routing (SRv6) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 \\\n+\t\tUINT32_C(0xf)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n+\t\tHWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE\n \tuint8_t\tunused_0;\n \t/*\n \t * This field represents the value of L4 destination port used\n@@ -52636,7 +56918,51 @@ struct hwrm_tunnel_dst_port_alloc_output {\n \t * types that has l4 destination port parameters.\n \t */\n \tuint16_t\ttunnel_dst_port_id;\n-\tuint8_t\tunused_0[5];\n+\t/* Error information */\n+\tuint8_t\terror_info;\n+\t/* No error */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_SUCCESS \\\n+\t\tUINT32_C(0x0)\n+\t/* Tunnel port is already allocated */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED \\\n+\t\tUINT32_C(0x1)\n+\t/* Out of resources error */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_LAST \\\n+\t\tHWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE\n+\t/*\n+\t * This field represents the UPAR usage status.\n+\t * Available UPARs on wh+ are UPAR0 and UPAR1\n+\t * Available UPARs on Thor are UPAR0 to UPAR3\n+\t * Available UPARs on Thor2 are UPAR0 to UPAR7\n+\t */\n+\tuint8_t\tupar_in_use;\n+\t/* This bit will be '1' when UPAR0 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR0 \\\n+\t\tUINT32_C(0x1)\n+\t/* This bit will be '1' when UPAR1 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR1 \\\n+\t\tUINT32_C(0x2)\n+\t/* This bit will be '1' when UPAR2 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR2 \\\n+\t\tUINT32_C(0x4)\n+\t/* This bit will be '1' when UPAR3 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR3 \\\n+\t\tUINT32_C(0x8)\n+\t/* This bit will be '1' when UPAR4 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR4 \\\n+\t\tUINT32_C(0x10)\n+\t/* This bit will be '1' when UPAR5 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR5 \\\n+\t\tUINT32_C(0x20)\n+\t/* This bit will be '1' when UPAR6 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR6 \\\n+\t\tUINT32_C(0x40)\n+\t/* This bit will be '1' when UPAR7 is IN_USE */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR7 \\\n+\t\tUINT32_C(0x80)\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -52702,8 +57028,20 @@ struct hwrm_tunnel_dst_port_free_input {\n \t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n \t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n+\t/* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE \\\n+\t\tUINT32_C(0xd)\n+\t/* Enhanced Common Packet Radio Interface (eCPRI) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI \\\n+\t\tUINT32_C(0xe)\n+\t/* IPv6 Segment Routing (SRv6) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 \\\n+\t\tUINT32_C(0xf)\n+\t/* Generic Protocol Extension for VXLAN (VXLAN-GPE) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \\\n+\t\tUINT32_C(0x10)\n \t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n+\t\tHWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE\n \tuint8_t\tunused_0;\n \t/*\n \t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n@@ -52723,7 +57061,20 @@ struct hwrm_tunnel_dst_port_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_1[7];\n+\t/* Error information */\n+\tuint8_t\terror_info;\n+\t/* No error */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_SUCCESS \\\n+\t\tUINT32_C(0x0)\n+\t/* Not owner error */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_OWNER \\\n+\t\tUINT32_C(0x1)\n+\t/* Not allocated error */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_LAST \\\n+\t\tHWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED\n+\tuint8_t\tunused_1[6];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -53534,6 +57885,185 @@ struct pcie_ctx_hw_stats {\n \tuint64_t\tpcie_recovery_histogram;\n } __rte_packed;\n \n+/****************************\n+ * hwrm_stat_generic_qstats *\n+ ****************************/\n+\n+\n+/* hwrm_stat_generic_qstats_input (size:256b/32B) */\n+struct hwrm_stat_generic_qstats_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * The size of the generic statistics buffer passed in the\n+\t * generic_stat_host_addr in bytes.\n+\t * Firmware will not exceed this size when it DMAs the\n+\t * statistics structure to the host. The actual DMA size\n+\t * will be returned in the response.\n+\t */\n+\tuint16_t\tgeneric_stat_size;\n+\tuint8_t\tflags;\n+\t/*\n+\t * The bit should be set to 1 when request is for the counter mask\n+\t * representing the width of each of the stats counters, rather\n+\t * than counters themselves.\n+\t */\n+\t#define HWRM_STAT_GENERIC_QSTATS_INPUT_FLAGS_COUNTER_MASK \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This is the host address where\n+\t * generic statistics will be stored\n+\t */\n+\tuint64_t\tgeneric_stat_host_addr;\n+} __rte_packed;\n+\n+/* hwrm_stat_generic_qstats_output (size:128b/16B) */\n+struct hwrm_stat_generic_qstats_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The size of Generic Statistics block in bytes. */\n+\tuint16_t\tgeneric_stat_size;\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/* Generic Statistic Format */\n+/* generic_sw_hw_stats (size:1408b/176B) */\n+struct generic_sw_hw_stats {\n+\t/*\n+\t * This is the number of TLP bytes that have been transmitted for\n+\t * the caller PF.\n+\t */\n+\tuint64_t\tpcie_statistics_tx_tlp;\n+\t/*\n+\t * This is the number of TLP bytes that have been received\n+\t * for the caller PF.\n+\t */\n+\tuint64_t\tpcie_statistics_rx_tlp;\n+\t/* Posted Header Flow Control credits available for the caller PF. */\n+\tuint64_t\tpcie_credit_fc_hdr_posted;\n+\t/* Non-posted Header Flow Control credits available for the caller PF. */\n+\tuint64_t\tpcie_credit_fc_hdr_nonposted;\n+\t/* Completion Header Flow Control credits available for the caller PF. */\n+\tuint64_t\tpcie_credit_fc_hdr_cmpl;\n+\t/* Posted Data Flow Control credits available for the caller PF. */\n+\tuint64_t\tpcie_credit_fc_data_posted;\n+\t/* Non-Posted Data Flow Control credits available for the caller PF. */\n+\tuint64_t\tpcie_credit_fc_data_nonposted;\n+\t/* Completion Data Flow Control credits available for the caller PF. */\n+\tuint64_t\tpcie_credit_fc_data_cmpl;\n+\t/*\n+\t * Available Non-posted credit for target flow control reads or\n+\t * config for the caller PF.\n+\t */\n+\tuint64_t\tpcie_credit_fc_tgt_nonposted;\n+\t/*\n+\t * Available posted data credit for target flow control writes\n+\t * for the caller PF.\n+\t */\n+\tuint64_t\tpcie_credit_fc_tgt_data_posted;\n+\t/*\n+\t * Available posted header credit for target flow control writes\n+\t * for the caller PF.\n+\t */\n+\tuint64_t\tpcie_credit_fc_tgt_hdr_posted;\n+\t/* Available completion flow control header credits for the caller PF. */\n+\tuint64_t\tpcie_credit_fc_cmpl_hdr_posted;\n+\t/* Available completion flow control data credits. */\n+\tuint64_t\tpcie_credit_fc_cmpl_data_posted;\n+\t/*\n+\t * Displays Time information of the longest completon time from any of\n+\t * the 4 tags for the caller PF. The unit of time recorded is in\n+\t * microseconds.\n+\t */\n+\tuint64_t\tpcie_cmpl_longest;\n+\t/*\n+\t * Displays Time information of the shortest completon time from any of\n+\t * the 4 tags for the caller PF. The unit of time recorded is in\n+\t * microseconds.\n+\t */\n+\tuint64_t\tpcie_cmpl_shortest;\n+\t/*\n+\t * This field contains the total number of CFCQ 'misses' observed for\n+\t * all the PF's.\n+\t */\n+\tuint64_t\tcache_miss_count_cfcq;\n+\t/*\n+\t * This field contains the total number of CFCS 'misses' observed for\n+\t * all the PF's.\n+\t */\n+\tuint64_t\tcache_miss_count_cfcs;\n+\t/*\n+\t * This field contains the total number of CFCC 'misses' observed for\n+\t * all the PF's.\n+\t */\n+\tuint64_t\tcache_miss_count_cfcc;\n+\t/*\n+\t * This field contains the total number of CFCM 'misses' observed\n+\t * for all the PF's.\n+\t */\n+\tuint64_t\tcache_miss_count_cfcm;\n+\t/*\n+\t * Total number of Doorbell messages dropped from the DB FIFO.\n+\t * This counter is only applicable for devices that support\n+\t * the hardware based doorbell drop recovery feature.\n+\t */\n+\tuint64_t\thw_db_recov_dbs_dropped;\n+\t/*\n+\t * Total number of doorbell drops serviced.\n+\t * This counter is only applicable for devices that support\n+\t * the hardware based doorbell drop recovery feature.\n+\t */\n+\tuint64_t\thw_db_recov_drops_serviced;\n+\t/*\n+\t * Total number of dropped doorbells recovered.\n+\t * This counter is only applicable for devices that support\n+\t * the hardware based doorbell drop recovery feature.\n+\t */\n+\tuint64_t\thw_db_recov_dbs_recovered;\n+} __rte_packed;\n+\n /**********************\n * hwrm_exec_fwd_resp *\n **********************/\n@@ -55174,8 +59704,11 @@ struct hwrm_nvm_install_update_cmd_err {\n \t/* Firmware update failed due to Anti-rollback. */\n \t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \\\n \t\tUINT32_C(0x3)\n+\t/* Firmware update does not support voltage regulators on the device. */\n+\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT \\\n+\t\tUINT32_C(0x4)\n \t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK\n+\t\tHWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT\n \tuint8_t\tunused_0[7];\n } __rte_packed;\n \n", "prefixes": [ "v4", "02/11" ] }