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GET /api/patches/129199/?format=api
{ "id": 129199, "url": "http://patchwork.dpdk.org/api/patches/129199/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230702045758.23244-4-igozlan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230702045758.23244-4-igozlan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230702045758.23244-4-igozlan@nvidia.com", "date": "2023-07-02T04:57:57", "name": "[v2,4/5] net/mlx5: support symmetric RSS hash function", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "2485a92b2884ded648d52f263426e913d5ca250c", "submitter": { "id": 3118, "url": "http://patchwork.dpdk.org/api/people/3118/?format=api", "name": "Itamar Gozlan", "email": "igozlan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230702045758.23244-4-igozlan@nvidia.com/mbox/", "series": [ { "id": 28775, "url": "http://patchwork.dpdk.org/api/series/28775/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28775", "date": "2023-07-02T04:57:54", "name": "[v2,1/5] net/mlx5: support indirect list METER_MARK action", "version": 2, "mbox": "http://patchwork.dpdk.org/series/28775/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129199/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/129199/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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<xuemingl@nvidia.com>", "Subject": "[v2 4/5] net/mlx5: support symmetric RSS hash function", "Date": "Sun, 2 Jul 2023 07:57:57 +0300", "Message-ID": "<20230702045758.23244-4-igozlan@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20230702045758.23244-1-igozlan@nvidia.com>", "References": "<20230629072125.20369-5-igozlan@nvidia.com>\n <20230702045758.23244-1-igozlan@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT088:EE_|IA0PR12MB7776:EE_", "X-MS-Office365-Filtering-Correlation-Id": "55d398fc-1a71-4041-edaa-08db7ab8fb3c", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n wQeRmeqeSv0f7ozy5P2+2B1cMTgqjoO2HD7rUV86PAbZTbFQaaZLxNA/XPq+QUFbTZ1jvjs2KUEkoTyQVgBSUa/HKI65iN8ndlZN6H96GFeesIHtjX7QAKpqoboC15vvbb21NvQSZs/sbT5uaOMNMXXnc3e0V9HRoZguvf2Un3fUKB262R4uURTFWd5+juUHC1V+YpxI270mLZXF/hCGiO94D2Caygprxj6TxqThfUzgV2mpPW0L60YsXBDmdcqVs80cyUYHWQk6fDCqYMTkdq5eBBIHXxkNSWkyxEVNsbKWdUvq5ZG4AAta9+zMGcXtqPtHFft2zzZDNNiikV6uDmAJrGGy+k2eRexyTTNDQSNqqJyJ9HfVjwnNqJgleW7hRpHCE1NG64Oc8XtGP7JHb6pprLoLGfxvHg6v8MiSqvJd3tXQOFPEiXqaQhFNb69Svzw84jCznclsdPQ+kjbEgCFyImxfV8QWZimnPgcH1RDuzdiRuyNPtv1obdh8N7cuFZnBOY8LFA6ggbLvE9jf5aiphJ0Sqo4W8MxlpFBbahOWB0CJ0cL1Kcu2wlIvM6YZUisKf+Vt8I4PFplt84xZwRohiv5UqCbyMXI+Jej7VQgfYfhywKj0J/Gcc0pLRptKzgqqXnNRkmjA19pexUQF6UQosYpW3q4j9W/xYZM2hAqi97Kq1k3mKW0routIZzVzil2LB2JlyFvu8lOesHXECWlQONRrA/AokA1xVJHzA9UMRRIXuke0ou5VFQas5cZAk5KT1e1gAUh6j91lNdBWLvLhvv+YlH24wPjffTMKBqM=", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(39860400002)(396003)(346002)(376002)(136003)(451199021)(36840700001)(40470700004)(46966006)(55016003)(336012)(426003)(83380400001)(40460700003)(47076005)(30864003)(2616005)(2906002)(7636003)(356005)(82740400003)(36860700001)(40480700001)(36756003)(8936002)(8676002)(82310400005)(110136005)(5660300002)(86362001)(107886003)(54906003)(41300700001)(6636002)(4326008)(70206006)(70586007)(6666004)(316002)(7696005)(478600001)(6286002)(186003)(1076003)(26005)(21314003)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Jul 2023 04:58:30.9140 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 55d398fc-1a71-4041-edaa-08db7ab8fb3c", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT088.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA0PR12MB7776", "X-Mailman-Approved-At": "Mon, 03 Jul 2023 11:21:13 +0200", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Xueming Li <xuemingl@nvidia.com>\n\nThis patch supports symmetric hash function that creating same\nhash result for bi-direction traffic which having reverse\nsource and destination IP and L4 port.\n\nSince the hash algorithom is different than spec(XOR), leave a\nwarning in validation.\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 3 +++\n drivers/net/mlx5/mlx5_devx.c | 11 ++++++++---\n drivers/net/mlx5/mlx5_flow.c | 10 ++++++++--\n drivers/net/mlx5/mlx5_flow.h | 5 +++++\n drivers/net/mlx5/mlx5_flow_dv.c | 13 ++++++++++++-\n drivers/net/mlx5/mlx5_flow_hw.c | 7 +++++++\n drivers/net/mlx5/mlx5_rx.h | 2 +-\n drivers/net/mlx5/mlx5_rxq.c | 8 +++++---\n 8 files changed, 49 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex b5b809633c..4fc67c4f36 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1579,6 +1579,7 @@ struct mlx5_mtr_config {\n \n /* RSS description. */\n struct mlx5_flow_rss_desc {\n+\tbool symmetric_hash_function; /**< Symmetric hash function */\n \tuint32_t level;\n \tuint32_t queue_num; /**< Number of entries in @p queue. */\n \tuint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */\n@@ -1647,6 +1648,7 @@ struct mlx5_hrxq {\n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \tvoid *action; /* DV QP action pointer. */\n #endif\n+\tbool symmetric_hash_function; /* Symmetric hash function */\n \tuint32_t hws_flags; /* Hw steering flags. */\n \tuint64_t hash_fields; /* Verbs Hash fields. */\n \tuint32_t rss_key_len; /* Hash key length in bytes. */\n@@ -1718,6 +1720,7 @@ struct mlx5_obj_ops {\n \tint (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \t\t\t const uint8_t *rss_key,\n \t\t\t uint64_t hash_fields,\n+\t\t\t bool symmetric_hash_function,\n \t\t\t const struct mlx5_ind_table_obj *ind_tbl);\n \tvoid (*hrxq_destroy)(struct mlx5_hrxq *hrxq);\n \tint (*drop_action_create)(struct rte_eth_dev *dev);\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 5082a7e178..d286cfe864 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -803,7 +803,8 @@ static void\n mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,\n \t\t uint64_t hash_fields,\n \t\t const struct mlx5_ind_table_obj *ind_tbl,\n-\t\t int tunnel, struct mlx5_devx_tir_attr *tir_attr)\n+\t\t int tunnel, bool symmetric_hash_function,\n+\t\t struct mlx5_devx_tir_attr *tir_attr)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tbool is_hairpin;\n@@ -834,6 +835,7 @@ mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,\n \ttir_attr->disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;\n \ttir_attr->rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;\n \ttir_attr->tunneled_offload_en = !!tunnel;\n+\ttir_attr->rx_hash_symmetric = symmetric_hash_function;\n \t/* If needed, translate hash_fields bitmap to PRM format. */\n \tif (hash_fields) {\n \t\tstruct mlx5_rx_hash_field_select *rx_hash_field_select =\n@@ -902,7 +904,8 @@ mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \tint err;\n \n \tmlx5_devx_tir_attr_set(dev, hrxq->rss_key, hrxq->hash_fields,\n-\t\t\t hrxq->ind_table, tunnel, &tir_attr);\n+\t\t\t hrxq->ind_table, tunnel, hrxq->symmetric_hash_function,\n+\t\t\t &tir_attr);\n \thrxq->tir = mlx5_devx_cmd_create_tir(priv->sh->cdev->ctx, &tir_attr);\n \tif (!hrxq->tir) {\n \t\tDRV_LOG(ERR, \"Port %u cannot create DevX TIR.\",\n@@ -969,13 +972,13 @@ static int\n mlx5_devx_hrxq_modify(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \t\t const uint8_t *rss_key,\n \t\t uint64_t hash_fields,\n+\t\t bool symmetric_hash_function,\n \t\t const struct mlx5_ind_table_obj *ind_tbl)\n {\n \tstruct mlx5_devx_modify_tir_attr modify_tir = {0};\n \n \t/*\n \t * untested for modification fields:\n-\t * - rx_hash_symmetric not set in hrxq_new(),\n \t * - rx_hash_fn set hard-coded in hrxq_new(),\n \t * - lro_xxx not set after rxq setup\n \t */\n@@ -983,11 +986,13 @@ mlx5_devx_hrxq_modify(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \t\tmodify_tir.modify_bitmask |=\n \t\t\tMLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE;\n \tif (hash_fields != hrxq->hash_fields ||\n+\t\t\tsymmetric_hash_function != hrxq->symmetric_hash_function ||\n \t\t\tmemcmp(hrxq->rss_key, rss_key, MLX5_RSS_HASH_KEY_LEN))\n \t\tmodify_tir.modify_bitmask |=\n \t\t\tMLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH;\n \tmlx5_devx_tir_attr_set(dev, rss_key, hash_fields, ind_tbl,\n \t\t\t 0, /* N/A - tunnel modification unsupported */\n+\t\t\t symmetric_hash_function,\n \t\t\t &modify_tir.tir);\n \tmodify_tir.tirn = hrxq->tir->id;\n \tif (mlx5_devx_cmd_modify_tir(hrxq->tir, &modify_tir)) {\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 45f2210ae7..572763decf 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -2204,8 +2204,11 @@ mlx5_validate_action_rss(struct rte_eth_dev *dev,\n \tconst char *message;\n \tuint32_t queue_idx;\n \n-\tif (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT &&\n-\t rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ)\n+\tif (rss->func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {\n+\t\tDRV_LOG(WARNING, \"port %u symmetric RSS supported with SORT\",\n+\t\t\tdev->data->port_id);\n+\t} else if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT &&\n+\t\t rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION_CONF,\n \t\t\t\t\t &rss->func,\n@@ -5720,6 +5723,8 @@ get_meter_sub_policy(struct rte_eth_dev *dev,\n \t\t\t\t\t\titems, rss_actions, error))\n \t\t\t\t\tgoto exit;\n \t\t\t\trss_desc_v[i] = wks->rss_desc;\n+\t\t\t\trss_desc_v[i].symmetric_hash_function =\n+\t\t\t\t\t\tdev_flow.symmetri_hash_function;\n \t\t\t\trss_desc_v[i].key_len = MLX5_RSS_HASH_KEY_LEN;\n \t\t\t\trss_desc_v[i].hash_fields =\n \t\t\t\t\t\tdev_flow.hash_fields;\n@@ -7424,6 +7429,7 @@ flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type,\n \t\trss = flow_get_rss_action(dev, p_actions_rx);\n \tif (rss) {\n \t\tMLX5_ASSERT(rss->queue_num <= RTE_ETH_RSS_RETA_SIZE_512);\n+\t\trss_desc->symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func);\n \t\t/*\n \t\t * The following information is required by\n \t\t * mlx5_flow_hashfields_adjust() in advance.\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex e273bd958d..e39afc47ad 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1003,6 +1003,7 @@ struct mlx5_flow {\n \tbool external; /**< true if the flow is created external to PMD. */\n \tuint8_t ingress:1; /**< 1 if the flow is ingress. */\n \tuint8_t skip_scale:2;\n+\tuint8_t symmetri_hash_function:1;\n \t/**\n \t * Each Bit be set to 1 if Skip the scale the flow group with factor.\n \t * If bit0 be set to 1, then skip the scale the original flow group;\n@@ -1353,6 +1354,7 @@ struct mlx5_action_construct_data {\n \t\t\tuint32_t mask[MLX5_ACT_MAX_MOD_FIELDS];\n \t\t} modify_header;\n \t\tstruct {\n+\t\t\tbool symmetric_hash_function; /* Symmetric RSS hash */\n \t\t\tuint64_t types; /* RSS hash types. */\n \t\t\tuint32_t level; /* RSS level. */\n \t\t\tuint32_t idx; /* Shared action index. */\n@@ -1575,6 +1577,9 @@ struct rte_flow_template_table {\n \t\t\t\tMLX5_RSS_HASH_ESP_SPI)\n #define MLX5_RSS_HASH_NONE 0ULL\n \n+#define MLX5_RSS_IS_SYMM(func) \\\n+\t\t((func) == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)\n+\n \n /* extract next protocol type from Ethernet & VLAN headers */\n #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \\\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex bae74fd383..ca2143c7cd 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -12875,6 +12875,7 @@ flow_dv_hrxq_prepare(struct rte_eth_dev *dev,\n \tstruct mlx5_hrxq *hrxq;\n \n \tMLX5_ASSERT(rss_desc->queue_num);\n+\trss_desc->symmetric_hash_function = dev_flow->symmetri_hash_function;\n \trss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;\n \trss_desc->hash_fields = dev_flow->hash_fields;\n \trss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);\n@@ -13419,6 +13420,8 @@ flow_dv_translate_action_sample(struct rte_eth_dev *dev,\n \t\t\tconst uint8_t *rss_key;\n \n \t\t\trss = sub_actions->conf;\n+\t\t\trss_desc->symmetric_hash_function =\n+\t\t\t\tMLX5_RSS_IS_SYMM(rss->func);\n \t\t\tmemcpy(rss_desc->queue, rss->queue,\n \t\t\t rss->queue_num * sizeof(uint16_t));\n \t\t\trss_desc->queue_num = rss->queue_num;\n@@ -15466,6 +15469,8 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RSS:\n \t\t\trss = actions->conf;\n+\t\t\trss_desc->symmetric_hash_function =\n+\t\t\t\tMLX5_RSS_IS_SYMM(rss->func);\n \t\t\tmemcpy(rss_desc->queue, rss->queue,\n \t\t\t rss->queue_num * sizeof(uint16_t));\n \t\t\trss_desc->queue_num = rss->queue_num;\n@@ -15948,10 +15953,12 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\t\t error);\n \tif (ret)\n \t\treturn -rte_errno;\n-\tif (action_flags & MLX5_FLOW_ACTION_RSS)\n+\tif (action_flags & MLX5_FLOW_ACTION_RSS) {\n+\t\tdev_flow->symmetri_hash_function = rss_desc->symmetric_hash_function;\n \t\tflow_dv_hashfields_set(dev_flow->handle->layers,\n \t\t\t\t rss_desc,\n \t\t\t\t &dev_flow->hash_fields);\n+\t}\n \t/* If has RSS action in the sample action, the Sample/Mirror resource\n \t * should be registered after the hash filed be update.\n \t */\n@@ -17029,6 +17036,8 @@ __flow_dv_action_rss_setup(struct rte_eth_dev *dev,\n \t\t\t\t\t \"cannot setup indirection table\");\n \tmemcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);\n \trss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;\n+\trss_desc.symmetric_hash_function =\n+\t\tMLX5_RSS_IS_SYMM(shared_rss->origin.func);\n \trss_desc.const_q = shared_rss->origin.queue;\n \trss_desc.queue_num = shared_rss->origin.queue_num;\n \t/* Set non-zero value to indicate a shared RSS. */\n@@ -20153,6 +20162,8 @@ flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,\n \tif (!(r1->level <= 1 && r2->level <= 1) &&\n \t !(r1->level > 1 && r2->level > 1))\n \t\treturn 1;\n+\tif (r1->func != r2->func)\n+\t\treturn 1;\n \tif (r1->types != r2->types &&\n \t !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&\n \t (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 5e5ebbe620..3d2d240f43 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -431,6 +431,7 @@ flow_hw_tir_action_register(struct rte_eth_dev *dev,\n \t\t MLX5_RSS_HASH_KEY_LEN);\n \t\trss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;\n \t\trss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;\n+\t\trss_desc.symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func);\n \t\tflow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);\n \t\tflow_dv_action_rss_l34_hash_adjust(rss->types,\n \t\t\t\t\t\t &rss_desc.hash_fields);\n@@ -716,6 +717,8 @@ __flow_hw_act_data_shared_rss_append(struct mlx5_priv *priv,\n \tact_data->shared_rss.types = !rss->origin.types ? RTE_ETH_RSS_IP :\n \t\t\t\t rss->origin.types;\n \tact_data->shared_rss.idx = idx;\n+\tact_data->shared_rss.symmetric_hash_function =\n+\t\tMLX5_RSS_IS_SYMM(rss->origin.func);\n \tLIST_INSERT_HEAD(&acts->act_list, act_data, next);\n \treturn 0;\n }\n@@ -2217,6 +2220,7 @@ flow_hw_shared_action_get(struct rte_eth_dev *dev,\n \tcase MLX5_RTE_FLOW_ACTION_TYPE_RSS:\n \t\trss_desc.level = act_data->shared_rss.level;\n \t\trss_desc.types = act_data->shared_rss.types;\n+\t\trss_desc.symmetric_hash_function = act_data->shared_rss.symmetric_hash_function;\n \t\tflow_dv_hashfields_set(item_flags, &rss_desc, &hash_fields);\n \t\thrxq_idx = flow_dv_action_rss_hrxq_lookup\n \t\t\t(dev, act_data->shared_rss.idx, hash_fields);\n@@ -2304,6 +2308,9 @@ flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,\n \t\tact_data.shared_rss.types = !shared_rss->origin.types ?\n \t\t\t\t\t RTE_ETH_RSS_IP :\n \t\t\t\t\t shared_rss->origin.types;\n+\t\tact_data.shared_rss.symmetric_hash_function =\n+\t\t\tMLX5_RSS_IS_SYMM(shared_rss->origin.func);\n+\n \t\titem_flags = table->its[it_idx]->item_flags;\n \t\tif (flow_hw_shared_action_get\n \t\t\t\t(dev, &act_data, item_flags, rule_act))\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex ff48194b9f..bc60dcaeb1 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -282,7 +282,7 @@ uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);\n void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev);\n int mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hxrq_idx,\n \t\t const uint8_t *rss_key, uint32_t rss_key_len,\n-\t\t uint64_t hash_fields,\n+\t\t uint64_t hash_fields, bool symmetric_hash_function,\n \t\t const uint16_t *queues, uint32_t queues_n);\n \n /* mlx5_rx.c */\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 6e99c4dde4..77936d463a 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -2759,6 +2759,7 @@ mlx5_hrxq_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,\n \tstruct mlx5_hrxq *hrxq = container_of(entry, typeof(*hrxq), entry);\n \n \treturn (hrxq->rss_key_len != rss_desc->key_len ||\n+\t hrxq->symmetric_hash_function != rss_desc->symmetric_hash_function ||\n \t memcmp(hrxq->rss_key, rss_desc->key, rss_desc->key_len) ||\n \t hrxq->hws_flags != rss_desc->hws_flags ||\n \t hrxq->hash_fields != rss_desc->hash_fields ||\n@@ -2792,7 +2793,7 @@ mlx5_hrxq_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,\n int\n mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hrxq_idx,\n \t\t const uint8_t *rss_key, uint32_t rss_key_len,\n-\t\t uint64_t hash_fields,\n+\t\t uint64_t hash_fields, bool symmetric_hash_function,\n \t\t const uint16_t *queues, uint32_t queues_n)\n {\n \tint err;\n@@ -2837,8 +2838,8 @@ mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hrxq_idx,\n \t\treturn -rte_errno;\n \t}\n \tMLX5_ASSERT(priv->obj_ops.hrxq_modify);\n-\tret = priv->obj_ops.hrxq_modify(dev, hrxq, rss_key,\n-\t\t\t\t\thash_fields, ind_tbl);\n+\tret = priv->obj_ops.hrxq_modify(dev, hrxq, rss_key, hash_fields,\n+\t\t\t\t\tsymmetric_hash_function, ind_tbl);\n \tif (ret) {\n \t\trte_errno = errno;\n \t\tgoto error;\n@@ -2938,6 +2939,7 @@ __mlx5_hrxq_create(struct rte_eth_dev *dev,\n \thrxq->rss_key_len = rss_key_len;\n \thrxq->hash_fields = rss_desc->hash_fields;\n \thrxq->hws_flags = rss_desc->hws_flags;\n+\thrxq->symmetric_hash_function = rss_desc->symmetric_hash_function;\n \tmemcpy(hrxq->rss_key, rss_key, rss_key_len);\n \tret = priv->obj_ops.hrxq_new(dev, hrxq, rss_desc->tunnel);\n \tif (ret < 0)\n", "prefixes": [ "v2", "4/5" ] }