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GET /api/patches/129899/?format=api
{ "id": 129899, "url": "http://patchwork.dpdk.org/api/patches/129899/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230803081301.3502865-9-caowenbo@mucse.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230803081301.3502865-9-caowenbo@mucse.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230803081301.3502865-9-caowenbo@mucse.com", "date": "2023-08-03T08:13:01", "name": "[v4,8/8] net/rnp handle device interrupts", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e5cc50351cb19257128ec82266f7d3d1903a3ea3", "submitter": { "id": 2142, "url": "http://patchwork.dpdk.org/api/people/2142/?format=api", "name": "11", "email": "caowenbo@mucse.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230803081301.3502865-9-caowenbo@mucse.com/mbox/", "series": [ { "id": 29103, "url": "http://patchwork.dpdk.org/api/series/29103/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29103", "date": "2023-08-03T08:12:53", "name": "drivers/net Add Support mucse N10 Pmd Driver", "version": 4, "mbox": "http://patchwork.dpdk.org/series/29103/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129899/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/129899/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 06CA142FC4;\n\tThu, 3 Aug 2023 10:14:27 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A8A0D43261;\n\tThu, 3 Aug 2023 10:14:08 +0200 (CEST)", "from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24])\n by mails.dpdk.org (Postfix) with ESMTP id 4B30343261\n for <dev@dpdk.org>; Thu, 3 Aug 2023 10:14:05 +0200 (CEST)", "from steven.localdomain ( [183.81.182.182])\n by bizesmtp.qq.com (ESMTP) with\n id ; Thu, 03 Aug 2023 16:13:49 +0800 (CST)" ], "X-QQ-mid": "bizesmtp79t1691050433tneayd8i", "X-QQ-SSF": "01400000000000D0F000000A0000000", "X-QQ-FEAT": "RFp2QSjOiS68uXzIVrxxrdyGdMPY+Y//cPCciAPrZycC7N4LaLV1TiBHX84ah\n +ZL6bq7OTHpCF5eUKE7s/HHWTaooA7QHu1NIncCPNj2zMI89S/nQGI1P71XTjTanT883u9s\n B6koeqr8COWBlNMeQ+G9k4LAsmmiRiNYGBYr/QfJAP6uBXoOfKr07sLzaFVselaq85KUT4j\n 2W7Nb6k/+G9eBGHpK4ftsHk6hIxzUlpAiCxjHi5ZpdlRtaGr50LzcsOOOzFv0LuSPCF+CQ2\n BpODyuj8k83rlWUamNpmACL92RaQTle93WYbIN3iMaVjkwFEC/C3g1qsnCkEZb4mlb03d5J\n wCHqARbao+cyA8fgkXmd8+UAAQ2RvjsefzDjSFbEVi69KxO62EpNtQY0ROQvQfmoFSQa89k\n /eNP6kx6IcucJNJI7uekSA==", "X-QQ-GoodBg": "2", "X-BIZMAIL-ID": "6161802308177165681", "From": "Wenbo Cao <caowenbo@mucse.com>", "To": "stephen@networkplumber.org,\n\tWenbo Cao <caowenbo@mucse.com>", "Cc": "dev@dpdk.org, ferruh.yigit@amd.com, andrew.rybchenko@oktetlabs.ru,\n yaojun@mucse.com", "Subject": "[PATCH v4 8/8] net/rnp handle device interrupts", "Date": "Thu, 3 Aug 2023 08:13:01 +0000", "Message-Id": "<20230803081301.3502865-9-caowenbo@mucse.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230803081301.3502865-1-caowenbo@mucse.com>", "References": "<20230803081301.3502865-1-caowenbo@mucse.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:mucse.com:qybglogicsvrgz:qybglogicsvrgz5a-0", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Handle device lsc interrupt event\n\nSigned-off-by: Wenbo Cao <caowenbo@mucse.com>\n---\n drivers/net/rnp/base/rnp_hw.h | 5 +\n drivers/net/rnp/base/rnp_mac_regs.h | 279 ++++++++++++++++++++++++++++\n drivers/net/rnp/rnp.h | 8 +\n drivers/net/rnp/rnp_ethdev.c | 17 ++\n drivers/net/rnp/rnp_mbx.h | 3 +-\n drivers/net/rnp/rnp_mbx_fw.c | 233 +++++++++++++++++++++++\n drivers/net/rnp/rnp_mbx_fw.h | 38 +++-\n 7 files changed, 580 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/rnp/base/rnp_mac_regs.h", "diff": "diff --git a/drivers/net/rnp/base/rnp_hw.h b/drivers/net/rnp/base/rnp_hw.h\nindex 395b9d5c71..5c50484c6c 100644\n--- a/drivers/net/rnp/base/rnp_hw.h\n+++ b/drivers/net/rnp/base/rnp_hw.h\n@@ -10,6 +10,7 @@\n #include \"rnp_osdep.h\"\n #include \"rnp_dma_regs.h\"\n #include \"rnp_eth_regs.h\"\n+#include \"rnp_mac_regs.h\"\n #include \"rnp_cfg.h\"\n \n static inline unsigned int rnp_rd_reg(volatile void *addr)\n@@ -48,6 +49,10 @@ static inline void rnp_wr_reg(volatile void *reg, int val)\n \trnp_eth_wr(hw, RNP_RAL_BASE_ADDR(hw_idx), val)\n #define RNP_MACADDR_UPDATE_HI(hw, hw_idx, val) \\\n \trnp_eth_wr(hw, RNP_RAH_BASE_ADDR(hw_idx), val)\n+#define rnp_mac_rd(hw, id, off) \\\n+\trnp_rd_reg((char *)(hw)->mac_base[id] + (off))\n+#define rnp_mac_wr(hw, id, off, val) \\\n+\trnp_wr_reg((char *)(hw)->mac_base[id] + (off), val)\n struct rnp_hw;\n /* Mbx Operate info */\n enum MBX_ID {\ndiff --git a/drivers/net/rnp/base/rnp_mac_regs.h b/drivers/net/rnp/base/rnp_mac_regs.h\nnew file mode 100644\nindex 0000000000..f9466b3841\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_mac_regs.h\n@@ -0,0 +1,279 @@\n+#ifndef __RNP_MAC_REGS_H__\n+#define __RNP_MAC_REGS_H__\n+\n+#include \"rnp_osdep.h\"\n+#define RNP_MAC_TX_CFG\t\t(0x0)\n+\n+/* Transmitter Enable */\n+#define RNP_MAC_TE\t\t\tBIT(0)\n+/* Jabber Disable */\n+#define RNP_MAC_JD\t\t\tBIT(16)\n+#define RNP_SPEED_SEL_1G\t\t(BIT(30) | BIT(29) | BIT(28))\n+#define RNP_SPEED_SEL_10G\t\tBIT(30)\n+#define RNP_SPEED_SEL_40G\t\t(0)\n+#define RNP_MAC_RX_CFG\t\t\t(0x4)\n+/* Receiver Enable */\n+#define RNP_MAC_RE\t\t\tBIT(0)\n+/* Automatic Pad or CRC Stripping */\n+#define RNP_MAC_ACS\t\t\tBIT(1)\n+/* CRC stripping for Type packets */\n+#define RNP_MAC_CST\t\t\tBIT(2)\n+/* Disable CRC Check */\n+#define RNP_MAC_DCRCC\t\t\tBIT(3)\n+/* Enable Max Frame Size Limit */\n+#define RNP_MAC_GPSLCE\t\t\tBIT(6)\n+/* Watchdog Disable */\n+#define RNP_MAC_WD\t\t\tBIT(7)\n+/* Jumbo Packet Support En */\n+#define RNP_MAC_JE\t\t\tBIT(8)\n+/* Loopback Mode */\n+#define RNP_MAC_LM\t\t\tBIT(10)\n+/* Giant Packet Size Limit */\n+#define RNP_MAC_GPSL_MASK\t\tGENMASK(29, 16)\n+#define RNP_MAC_MAX_GPSL\t\t(1518)\n+#define RNP_MAC_CPSL_SHIFT\t\t(16)\n+\n+#define RNP_MAC_PKT_FLT_CTRL\t\t(0x8)\n+\n+/* Receive All */\n+#define RNP_MAC_RA\t\t\tBIT(31)\n+/* Pass Control Packets */\n+#define RNP_MAC_PCF\t\t\tGENMASK(7, 6)\n+#define RNP_MAC_PCF_OFFSET\t\t(6)\n+/* Mac Filter ALL Ctrl Frame */\n+#define RNP_MAC_PCF_FAC\t\t\t(0)\n+/* Mac Forward ALL Ctrl Frame Except Pause */\n+#define RNP_MAC_PCF_NO_PAUSE\t\t(1)\n+/* Mac Forward All Ctrl Pkt */\n+#define RNP_MAC_PCF_PA\t\t\t(2)\n+/* Mac Forward Ctrl Frame Match Unicast */\n+#define RNP_MAC_PCF_PUN\t\t\t(3)\n+/* Promiscuous Mode */\n+#define RNP_MAC_PROMISC_EN\t\tBIT(0)\n+/* Hash Unicast */\n+#define RNP_MAC_HUC\t\t\tBIT(1)\n+/* Hash Multicast */\n+#define RNP_MAC_HMC\t\t\tBIT(2)\n+/* Pass All Multicast */\n+#define RNP_MAC_PM\t\t\tBIT(4)\n+/* Disable Broadcast Packets */\n+#define RNP_MAC_DBF\t\t\tBIT(5)\n+/* Hash or Perfect Filter */\n+#define RNP_MAC_HPF\t\t\tBIT(10)\n+#define RNP_MAC_VTFE\t\t\tBIT(16)\n+/* Interrupt Status */\n+#define RNP_MAC_INT_STATUS\t\t_MAC_(0xb0)\n+#define RNP_MAC_LS_MASK\t\t\tGENMASK(25, 24)\n+#define RNP_MAC_LS_UP\t\t\t(0)\n+#define RNP_MAC_LS_LOCAL_FAULT\t\tBIT(25)\n+#define RNP_MAC_LS_REMOTE_FAULT\t\t(BIT(25) | BIT(24))\n+/* Unicast Mac Hash Table */\n+#define RNP_MAC_UC_HASH_TB(n)\t\t_MAC_(0x10 + ((n) * 0x4))\n+\n+\n+#define RNP_MAC_LPI_CTRL\t\t(0xd0)\n+\n+/* PHY Link Status Disable */\n+#define RNP_MAC_PLSDIS\t\t\tBIT(18)\n+/* PHY Link Status */\n+#define RNP_MAC_PLS\t\t\tBIT(17)\n+\n+/* MAC VLAN CTRL Strip REG */\n+#define RNP_MAC_VLAN_TAG\t\t(0x50)\n+\n+/* En Inner VLAN Strip Action */\n+#define RNP_MAC_EIVLS\t\t\tGENMASK(29, 28)\n+/* Inner VLAN Strip Action Shift */\n+#define RNP_MAC_IV_EIVLS_SHIFT\t\t(28)\n+/* Inner Vlan Don't Strip*/\n+#define RNP_MAC_IV_STRIP_NONE\t\t(0x0)\n+/* Inner Vlan Strip When Filter Match Success */\n+#define RNP_MAC_IV_STRIP_PASS\t\t(0x1)\n+/* Inner Vlan STRIP When Filter Match FAIL */\n+#define RNP_MAC_IV_STRIP_FAIL\t\t(0x2)\n+/* Inner Vlan STRIP Always */\n+#define RNP_MAC_IV_STRIP_ALL\t\t(0X3)\n+/* VLAN Strip Mode Ctrl Shift */\n+#define RNP_VLAN_TAG_CTRL_EVLS_SHIFT\t(21)\n+/* En Double Vlan Processing */\n+#define RNP_MAC_VLAN_EDVLP\t\tBIT(26)\n+/* VLAN Tag Hash Table Match Enable */\n+#define RNP_MAC_VLAN_VTHM\t\tBIT(25)\n+/* Enable VLAN Tag in Rx status */\n+#define RNP_MAC_VLAN_EVLRXS\t\tBIT(24)\n+/* Disable VLAN Type Check */\n+#define RNP_MAC_VLAN_DOVLTC\t\tBIT(20)\n+/* Enable S-VLAN */\n+#define RNP_MAC_VLAN_ESVL\t\tBIT(18)\n+/* Enable 12-Bit VLAN Tag Comparison Filter */\n+#define RNP_MAC_VLAN_ETV\t\tBIT(16)\n+#define RNP_MAC_VLAN_HASH_EN\t\tGENMASK(15, 0)\n+#define RNP_MAC_VLAN_VID\t\tGENMASK(15, 0)\n+/* VLAN Don't Strip */\n+#define RNP_MAC_VLAN_STRIP_NONE\t\t(0x0 << RNP_VLAN_TAG_CTRL_EVLS_SHIFT)\n+/* VLAN Filter Success Then STRIP */\n+#define RNP_MAC_VLAN_STRIP_PASS\t\t(0x1 << RNP_VLAN_TAG_CTRL_EVLS_SHIFT)\n+/* VLAN Filter Failed Then STRIP */\n+#define RNP_MAC_VLAN_STRIP_FAIL\t\t(0x2 << RNP_VLAN_TAG_CTRL_EVLS_SHIFT)\n+/* All Vlan Will Strip */\n+#define RNP_MAC_VLAN_STRIP_ALL\t\t(0x3 << RNP_VLAN_TAG_CTRL_EVLS_SHIFT)\n+\n+#define RNP_MAC_VLAN_HASH_TB\t\t(0x58)\n+#define RNP_MAC_VLAN_HASH_MASK\t\tGENMASK(15, 0)\n+\n+/* MAC VLAN CTRL INSERT REG */\n+#define RNP_MAC_VLAN_INCL\t\t(0x60)\n+#define RNP_MAC_INVLAN_INCL\t\t(0x64)\n+\n+/* VLAN Tag Input */\n+/* VLAN_Tag Insert From Description */\n+#define RNP_MAC_VLAN_VLTI\t\tBIT(20)\n+/* C-VLAN or S-VLAN */\n+#define RNP_MAC_VLAN_CSVL\t\tBIT(19)\n+#define RNP_MAC_VLAN_INSERT_CVLAN\t(0 << 19)\n+#define RNP_MAC_VLAN_INSERT_SVLAN\t(1 << 19)\n+/* VLAN Tag Control in Transmit Packets */\n+#define RNP_MAC_VLAN_VLC\t\tGENMASK(17, 16)\n+/* VLAN Tag Control Offset Bit */\n+#define RNP_MAC_VLAN_VLC_SHIFT\t\t(16)\n+/* Don't Anything ON TX VLAN*/\n+#define RNP_MAC_VLAN_VLC_NONE\t\t(0x0 << RNP_MAC_VLAN_VLC_SHIFT)\n+/* MAC Delete VLAN */\n+#define RNP_MAC_VLAN_VLC_DEL\t\t(0x1 << RNP_MAC_VLAN_VLC_SHIFT)\n+/* MAC Add VLAN */\n+#define RNP_MAC_VLAN_VLC_ADD\t\t(0x2 << RNP_MAC_VLAN_VLC_SHIFT)\n+/* MAC Replace VLAN */\n+#define RNP_MAC_VLAN_VLC_REPLACE\t(0x3 << RNP_MAC_VLAN_VLC_SHIFT)\n+/* VLAN Tag for Transmit Packets For Insert/Remove */\n+#define RNP_MAC_VLAN_VLT\t\tGENMASK(15, 0)\n+/* TX Peer TC Flow Ctrl */\n+\n+#define RNP_MAC_Q0_TX_FC(n)\t\t(0x70 + ((n) * 0x4))\n+\n+/* Edit Pause Time */\n+#define RNP_MAC_FC_PT\t\t\tGENMASK(31, 16)\n+#define RNP_MAC_FC_PT_OFFSET\t\t(16)\n+/* Disable Zero-Quanta Pause */\n+#define RNP_MAC_FC_DZPQ\t\t\tBIT(7)\n+/* Pause Low Threshold */\n+#define RNP_MAC_FC_PLT\t\t\tGENMASK(6, 4)\n+#define RNP_MAC_FC_PLT_OFFSET\t\t(4)\n+#define RNP_MAC_FC_PLT_4_SLOT\t\t(0)\n+#define RNP_MAC_FC_PLT_28_SLOT\t\t(1)\n+#define RNP_MAC_FC_PLT_36_SLOT\t\t(2)\n+#define RNP_MAC_FC_PLT_144_SLOT\t\t(3)\n+#define RNP_MAC_FC_PLT_256_SLOT\t\t(4)\n+/* Transmit Flow Control Enable */\n+#define RNP_MAC_FC_TEE\t\t\tBIT(1)\n+/* Transmit Flow Control Busy Immediately */\n+#define RNP_MAC_FC_FCB\t\t\tBIT(0)\n+/* Mac RX Flow Ctrl*/\n+\n+#define RNP_MAC_RX_FC\t\t\t(0x90)\n+\n+/* Rx Priority Based Flow Control Enable */\n+#define RNP_MAC_RX_FC_PFCE\t\tBIT(8)\n+/* Unicast Pause Packet Detect */\n+#define RNP_MAC_RX_FC_UP\t\tBIT(1)\n+/* Receive Flow Control Enable */\n+#define RNP_MAC_RX_FC_RFE\t\tBIT(0)\n+\n+/* Rx Mac Address Base */\n+#define RNP_MAC_ADDR_DEF_HI\t\t_MAC_(0x0300)\n+\n+#define RNP_MAC_AE\t\t\tBIT(31)\n+#define RNP_MAC_ADDR_LO(n)\t\t_MAC_((0x0304) + ((n) * 0x8))\n+#define RNP_MAC_ADDR_HI(n)\t\t_MAC_((0x0300) + ((n) * 0x8))\n+\n+/* Mac Manage Counts */\n+#define RNP_MMC_CTRL\t\t\t_MAC_(0x0800)\n+#define RNP_MMC_RSTONRD\t\t\tBIT(2)\n+/* Tx Good And Bad Bytes Base */\n+#define RNP_MMC_TX_GBOCTGB\t\t_MAC_(0x0814)\n+/* Tx Good And Bad Frame Num Base */\n+#define RNP_MMC_TX_GBFRMB\t\t_MAC_(0x081c)\n+/* Tx Good Broadcast Frame Num Base */\n+#define RNP_MMC_TX_BCASTB\t\t_MAC_(0x0824)\n+/* Tx Good Multicast Frame Num Base */\n+#define RNP_MMC_TX_MCASTB\t\t_MAC_(0x082c)\n+/* Tx 64Bytes Frame Num */\n+#define RNP_MMC_TX_64_BYTESB\t\t_MAC_(0x0834)\n+#define RNP_MMC_TX_65TO127_BYTESB\t_MAC_(0x083c)\n+#define RNP_MMC_TX_128TO255_BYTEB\t_MAC_(0x0844)\n+#define RNP_MMC_TX_256TO511_BYTEB\t_MAC_(0x084c)\n+#define RNP_MMC_TX_512TO1023_BYTEB\t_MAC_(0x0854)\n+#define RNP_MMC_TX_1024TOMAX_BYTEB\t_MAC_(0x085c)\n+/* Tx Good And Bad Unicast Frame Num Base */\n+#define RNP_MMC_TX_GBUCASTB\t\t_MAC_(0x0864)\n+/* Tx Good And Bad Multicast Frame Num Base */\n+#define RNP_MMC_TX_GBMCASTB\t\t_MAC_(0x086c)\n+/* Tx Good And Bad Broadcast Frame NUM Base */\n+#define RNP_MMC_TX_GBBCASTB\t\t_MAC_(0x0874)\n+/* Tx Frame Underflow Error */\n+#define RNP_MMC_TX_UNDRFLWB\t\t_MAC_(0x087c)\n+/* Tx Good Frame Bytes Base */\n+#define RNP_MMC_TX_GBYTESB\t\t_MAC_(0x0884)\n+/* Tx Good Frame Num Base*/\n+#define RNP_MMC_TX_GBRMB\t\t_MAC_(0x088c)\n+/* Tx Good Pause Frame Num Base */\n+#define RNP_MMC_TX_PAUSEB\t\t_MAC_(0x0894)\n+/* Tx Good Vlan Frame Num Base */\n+#define RNP_MMC_TX_VLANB\t\t_MAC_(0x089c)\n+\n+/* Rx Good And Bad Frames Num Base */\n+#define RNP_MMC_RX_GBFRMB\t\t_MAC_(0x0900)\n+/* Rx Good And Bad Frames Bytes Base */\n+#define RNP_MMC_RX_GBOCTGB\t\t_MAC_(0x0908)\n+/* Rx Good Framse Bytes Base */\n+#define RNP_MMC_RX_GOCTGB\t\t_MAC_(0x0910)\n+/* Rx Good Broadcast Frames Num Base */\n+#define RNP_MMC_RX_BCASTGB\t\t_MAC_(0x0918)\n+/* Rx Good Multicast Frames Num Base */\n+#define RNP_MMC_RX_MCASTGB\t\t_MAC_(0x0920)\n+/* Rx Crc Error Frames Num Base */\n+#define RNP_MMC_RX_CRCERB\t\t_MAC_(0x0928)\n+/* Rx Less Than 64Byes with Crc Err Base*/\n+#define RNP_MMC_RX_RUNTERB\t\t_MAC_(0x0930)\n+/* Receive Jumbo Frame Error */\n+#define RNP_MMC_RX_JABBER_ERR\t\t_MAC_(0x0934)\n+/* Shorter Than 64Bytes without Any Errora Base */\n+#define RNP_MMC_RX_USIZEGB\t\t_MAC_(0x0938)\n+/* Len Oversize Than Support */\n+#define RNP_MMC_RX_OSIZEGB\t\t_MAC_(0x093c)\n+/* Rx 64Byes Frame Num Base */\n+#define RNP_MMC_RX_64_BYTESB\t\t_MAC_(0x0940)\n+/* Rx 65Bytes To 127Bytes Frame Num Base */\n+#define RNP_MMC_RX_65TO127_BYTESB\t_MAC_(0x0948)\n+/* Rx 128Bytes To 255Bytes Frame Num Base */\n+#define RNP_MMC_RX_128TO255_BYTESB\t_MAC_(0x0950)\n+/* Rx 256Bytes To 511Bytes Frame Num Base */\n+#define RNP_MMC_RX_256TO511_BYTESB\t_MAC_(0x0958)\n+/* Rx 512Bytes To 1023Bytes Frame Num Base */\n+#define RNP_MMC_RX_512TO1203_BYTESB\t_MAC_(0x0960)\n+/* Rx Len Bigger Than 1024Bytes Base */\n+#define RNP_MMC_RX_1024TOMAX_BYTESB\t_MAC_(0x0968)\n+/* Rx Unicast Frame Good Num Base */\n+#define RNP_MMC_RX_UCASTGB\t\t_MAC_(0x0970)\n+/* Rx Length Error Of Frame Part */\n+#define RNP_MMC_RX_LENERRB\t\t_MAC_(0x0978)\n+/* Rx received with a Length field not equal to the valid frame size */\n+#define RNP_MMC_RX_OUTOF_RANGE\t\t_MAC_(0x0980)\n+/* Rx Pause Frame Good Num Base */\n+#define RNP_MMC_RX_PAUSEB\t\t_MAC_(0x0988)\n+/* Rx Vlan Frame Good Num Base */\n+#define RNP_MMC_RX_VLANGB\t\t_MAC_(0x0998)\n+/* Rx With A Watchdog Timeout Err Frame Base */\n+#define RNP_MMC_RX_WDOGERRB\t\t_MAC_(0x09a0)\n+\n+/* 1588 */\n+#define RNP_MAC_TS_CTRL _MAC_(0X0d00)\n+#define RNP_MAC_SUB_SECOND_INCREMENT _MAC_(0x0d04)\n+#define RNP_MAC_SYS_TIME_SEC_CFG _MAC_(0x0d08)\n+#define RNP_MAC_SYS_TIME_NANOSEC_CFG _MAC_(0x0d0c)\n+#define RNP_MAC_SYS_TIME_SEC_UPDATE _MAC_(0x0d10)\n+#define RNP_MAC_SYS_TIME_NANOSEC_UPDATE _MAC_(0x0d14)\n+#define RNP_MAC_TS_ADDEND _MAC_(0x0d18)\n+#define RNP_MAC_TS_STATS _MAC_(0x0d20)\n+#define RNP_MAC_INTERRUPT_ENABLE _MAC_(0x00b4)\n+\n+#endif /* __RNP_MAC_REGS_H__ */\ndiff --git a/drivers/net/rnp/rnp.h b/drivers/net/rnp/rnp.h\nindex 933cdc6007..61adb20909 100644\n--- a/drivers/net/rnp/rnp.h\n+++ b/drivers/net/rnp/rnp.h\n@@ -111,6 +111,8 @@ struct rnp_eth_port {\n \tuint8_t tx_func_sec; /* force set io tx func */\n \tstruct rte_eth_dev *eth_dev;\n \tstruct rnp_port_attr attr;\n+\tuint64_t state;\n+\trte_spinlock_t rx_mac_lock; /* Lock For Mac_cfg resource write */\n \t/* Recvice Mac Address Record Table */\n \tuint8_t mac_use_tb[RNP_MAX_MAC_ADDRS];\n \tuint8_t use_num_mac;\n@@ -131,6 +133,12 @@ enum {\n \tRNP_IO_FUNC_USE_COMMON,\n };\n \n+enum rnp_port_state {\n+\tRNP_PORT_STATE_PAUSE = 0,\n+\tRNP_PORT_STATE_FINISH,\n+\tRNP_PORT_STATE_SETTING,\n+};\n+\n struct rnp_eth_adapter {\n \tenum rnp_work_mode mode;\n \tenum rnp_resource_share_m s_mode; /* Port Resource Share Policy */\ndiff --git a/drivers/net/rnp/rnp_ethdev.c b/drivers/net/rnp/rnp_ethdev.c\nindex 5313dae5a2..ddbe84180d 100644\n--- a/drivers/net/rnp/rnp_ethdev.c\n+++ b/drivers/net/rnp/rnp_ethdev.c\n@@ -601,10 +601,23 @@ static int rnp_post_handle(struct rnp_eth_adapter *adapter)\n \treturn 0;\n }\n \n+static void rnp_dev_interrupt_handler(void *param)\n+{\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n+\tstruct rnp_eth_adapter *adapter = RNP_DEV_TO_ADAPTER(dev);\n+\n+\trte_intr_disable(intr_handle);\n+\trnp_fw_msg_handler(adapter);\n+\trte_intr_enable(intr_handle);\n+}\n+\n static int\n rnp_eth_dev_init(struct rte_eth_dev *dev)\n {\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n \tstruct rnp_eth_port *port = RNP_DEV_TO_PORT(dev);\n \tstruct rnp_eth_adapter *adapter = NULL;\n \tchar name[RTE_ETH_NAME_MAX_LEN] = \" \";\n@@ -680,6 +693,10 @@ rnp_eth_dev_init(struct rte_eth_dev *dev)\n \t\trnp_mac_rx_disable(eth_dev);\n \t\trnp_mac_tx_disable(eth_dev);\n \t}\n+\trte_intr_disable(intr_handle);\n+\t/* Enable Link Update Event Interrupt */\n+\trte_intr_callback_register(intr_handle,\n+\t\t\trnp_dev_interrupt_handler, dev);\n \tret = rnp_post_handle(adapter);\n \tif (ret)\n \t\tgoto eth_alloc_error;\ndiff --git a/drivers/net/rnp/rnp_mbx.h b/drivers/net/rnp/rnp_mbx.h\nindex 87949c1726..d6b78e32a7 100644\n--- a/drivers/net/rnp/rnp_mbx.h\n+++ b/drivers/net/rnp/rnp_mbx.h\n@@ -13,7 +13,8 @@\n \n /* Mbx Ctrl state */\n #define RNP_VFMAILBOX_SIZE\t(14) /* 16 32 bit words - 64 bytes */\n-#define TSRN10_VFMBX_SIZE\t(RNP_VFMAILBOX_SIZE)\n+#define RNP_FW_MAILBOX_SIZE\tRNP_VFMAILBOX_SIZE\n+#define RNP_VFMBX_SIZE\t\t(RNP_VFMAILBOX_SIZE)\n #define RNP_VT_MSGTYPE_ACK\t(0x80000000)\n \n #define RNP_VT_MSGTYPE_NACK\t(0x40000000)\ndiff --git a/drivers/net/rnp/rnp_mbx_fw.c b/drivers/net/rnp/rnp_mbx_fw.c\nindex d98dd2dcd2..6e8315445d 100644\n--- a/drivers/net/rnp/rnp_mbx_fw.c\n+++ b/drivers/net/rnp/rnp_mbx_fw.c\n@@ -546,3 +546,236 @@ int rnp_hw_set_fw_force_speed_1g(struct rte_eth_dev *dev, int enable)\n {\n \treturn rnp_mbx_set_dump(dev, 0x01150000 | (enable & 1));\n }\n+\n+static inline int\n+rnp_mbx_fw_reply_handler(struct rnp_eth_adapter *adapter __rte_unused,\n+\t\t\t struct mbx_fw_cmd_reply *reply)\n+{\n+\tstruct mbx_req_cookie *cookie;\n+\t/* dbg_here; */\n+\tcookie = reply->cookie;\n+\tif (!cookie || cookie->magic != COOKIE_MAGIC) {\n+\t\tRNP_PMD_LOG(ERR,\n+\t\t\t\t\"[%s] invalid cookie:%p opcode: \"\n+\t\t\t\t\"0x%x v0:0x%x\\n\",\n+\t\t\t\t__func__,\n+\t\t\t\tcookie,\n+\t\t\t\treply->opcode,\n+\t\t\t\t*((int *)reply));\n+\t\treturn -EIO;\n+\t}\n+\n+\tif (cookie->priv_len > 0)\n+\t\tmemcpy(cookie->priv, reply->data, cookie->priv_len);\n+\n+\tcookie->done = 1;\n+\n+\tif (reply->flags & FLAGS_ERR)\n+\t\tcookie->errcode = reply->error_code;\n+\telse\n+\t\tcookie->errcode = 0;\n+\n+\treturn 0;\n+}\n+\n+void rnp_link_stat_mark(struct rnp_hw *hw, int nr_lane, int up)\n+{\n+\tu32 v;\n+\n+\trte_spinlock_lock(&hw->fw_lock);\n+\tv = rnp_rd_reg(hw->link_sync);\n+\tv &= ~(0xffff0000);\n+\tv |= 0xa5a40000;\n+\tif (up)\n+\t\tv |= BIT(nr_lane);\n+\telse\n+\t\tv &= ~BIT(nr_lane);\n+\trnp_wr_reg(hw->link_sync, v);\n+\n+\trte_spinlock_unlock(&hw->fw_lock);\n+}\n+\n+void rnp_link_report(struct rte_eth_dev *dev, bool link_en)\n+{\n+\tstruct rnp_eth_port *port = RNP_DEV_TO_PORT(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct rte_eth_link link;\n+\n+\tlink.link_duplex = link_en ? port->attr.phy_meta.link_duplex :\n+\t\tRTE_ETH_LINK_FULL_DUPLEX;\n+\tlink.link_status = link_en ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;\n+\tlink.link_speed = link_en ? port->attr.speed :\n+\t\tRTE_ETH_SPEED_NUM_UNKNOWN;\n+\tRNP_PMD_LOG(INFO,\n+\t\t\t\"\\nPF[%d]link changed: changed_lane:0x%x, \"\n+\t\t\t\"status:0x%x\\n\",\n+\t\t\thw->pf_vf_num & RNP_PF_NB_MASK ? 1 : 0,\n+\t\t\tport->attr.nr_port,\n+\t\t\tlink_en);\n+\tlink.link_autoneg = port->attr.phy_meta.link_autoneg\n+\t\t? RTE_ETH_LINK_SPEED_AUTONEG\n+\t\t: RTE_ETH_LINK_SPEED_FIXED;\n+\t/* Report Link Info To Upper Firmwork */\n+\trte_eth_linkstatus_set(dev, &link);\n+\t/* Notice Event Process Link Status Change */\n+\trte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);\n+\t/* Notce Firmware LSC Event SW Received */\n+\trnp_link_stat_mark(hw, port->attr.nr_port, link_en);\n+}\n+\n+static void rnp_dev_alarm_link_handler(void *param)\n+{\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n+\tstruct rnp_eth_port *port = RNP_DEV_TO_PORT(dev);\n+\tuint32_t status;\n+\n+\tstatus = port->attr.link_ready;\n+\trnp_link_report(dev, status);\n+}\n+\n+static void rnp_link_event(struct rnp_eth_adapter *adapter,\n+\t\t\t struct mbx_fw_cmd_req *req)\n+{\n+\tstruct rnp_hw *hw = &adapter->hw;\n+\tstruct rnp_eth_port *port;\n+\tbool link_change = false;\n+\tuint32_t lane_bit;\n+\tuint32_t sync_bit;\n+\tuint32_t link_en;\n+\tuint32_t ctrl;\n+\tint i;\n+\n+\tfor (i = 0; i < adapter->num_ports; i++) {\n+\t\tport = adapter->ports[i];\n+\t\tif (port == NULL)\n+\t\t\tcontinue;\n+\t\tlink_change = false;\n+\t\tlane_bit = port->attr.nr_port;\n+\t\tif (__atomic_load_n(&port->state, __ATOMIC_RELAXED)\n+\t\t\t\t!= RNP_PORT_STATE_FINISH)\n+\t\t\tcontinue;\n+\t\tif (!(BIT(lane_bit) & req->link_stat.changed_lanes))\n+\t\t\tcontinue;\n+\t\tlink_en = BIT(lane_bit) & req->link_stat.lane_status;\n+\t\tsync_bit = BIT(lane_bit) & rnp_rd_reg(hw->link_sync);\n+\n+\t\tif (link_en) {\n+\t\t\t/* Port Link Change To Up */\n+\t\t\tif (!port->attr.link_ready) {\n+\t\t\t\tlink_change = true;\n+\t\t\t\tport->attr.link_ready = true;\n+\t\t\t}\n+\t\t\tif (req->link_stat.port_st_magic == SPEED_VALID_MAGIC) {\n+\t\t\t\tport->attr.speed = req->link_stat.st[lane_bit].speed;\n+\t\t\t\tport->attr.phy_meta.link_duplex =\n+\t\t\t\t\treq->link_stat.st[lane_bit].duplex;\n+\t\t\t\tport->attr.phy_meta.link_autoneg =\n+\t\t\t\t\treq->link_stat.st[lane_bit].autoneg;\n+\t\t\t\tRNP_PMD_INIT_LOG(INFO,\n+\t\t\t\t\t\t\"phy_id %d speed %d duplex \"\n+\t\t\t\t\t\t\"%d issgmii %d PortID %d\\n\",\n+\t\t\t\t\t\treq->link_stat.st[lane_bit].phy_addr,\n+\t\t\t\t\t\treq->link_stat.st[lane_bit].speed,\n+\t\t\t\t\t\treq->link_stat.st[lane_bit].duplex,\n+\t\t\t\t\t\treq->link_stat.st[lane_bit].is_sgmii,\n+\t\t\t\t\t\tport->attr.rte_pid);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* Port Link to Down */\n+\t\t\tif (port->attr.link_ready) {\n+\t\t\t\tlink_change = true;\n+\t\t\t\tport->attr.link_ready = false;\n+\t\t\t}\n+\t\t}\n+\t\tif (link_change || sync_bit != link_en) {\n+\t\t\t/* WorkAround For Hardware When Link Down\n+\t\t\t * Eth Module Tx-side Can't Drop In some condition\n+\t\t\t * So back The Packet To Rx Side To Drop Packet\n+\t\t\t */\n+\t\t\t/* To Protect Conflict Hw Resource */\n+\t\t\trte_spinlock_lock(&port->rx_mac_lock);\n+\t\t\tctrl = rnp_mac_rd(hw, lane_bit, RNP_MAC_RX_CFG);\n+\t\t\tif (port->attr.link_ready) {\n+\t\t\t\tctrl &= ~RNP_MAC_LM;\n+\t\t\t\trnp_eth_wr(hw,\n+\t\t\t\t\tRNP_RX_FIFO_FULL_THRETH(lane_bit),\n+\t\t\t\t\tRNP_RX_DEFAULT_VAL);\n+\t\t\t} else {\n+\t\t\t\trnp_eth_wr(hw,\n+\t\t\t\t\tRNP_RX_FIFO_FULL_THRETH(lane_bit),\n+\t\t\t\t\tRNP_RX_WORKAROUND_VAL);\n+\t\t\t\tctrl |= RNP_MAC_LM;\n+\t\t\t}\n+\t\t\trnp_mac_wr(hw, lane_bit, RNP_MAC_RX_CFG, ctrl);\n+\t\t\trte_spinlock_unlock(&port->rx_mac_lock);\n+\t\t\trte_eal_alarm_set(RNP_ALARM_INTERVAL,\n+\t\t\t\t\trnp_dev_alarm_link_handler,\n+\t\t\t\t\t(void *)port->eth_dev);\n+\t\t}\n+\t}\n+}\n+\n+static inline int\n+rnp_mbx_fw_req_handler(struct rnp_eth_adapter *adapter,\n+\t\t struct mbx_fw_cmd_req *req)\n+{\n+\tswitch (req->opcode) {\n+\tcase LINK_STATUS_EVENT:\n+\t\trnp_link_event(adapter, req);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline int rnp_rcv_msg_from_fw(struct rnp_eth_adapter *adapter)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(adapter->eth_dev);\n+\tstruct rnp_hw *hw = &adapter->hw;\n+\tu32 msgbuf[RNP_FW_MAILBOX_SIZE];\n+\tuint16_t check_state;\n+\tint retval;\n+\n+\tretval = ops->read(hw, msgbuf, RNP_FW_MAILBOX_SIZE, MBX_FW);\n+\tif (retval) {\n+\t\tPMD_DRV_LOG(ERR, \"Error receiving message from FW\\n\");\n+\t\treturn retval;\n+\t}\n+#define RNP_MBX_SYNC_MASK GENMASK(15, 0)\n+\n+\tcheck_state = msgbuf[0] & RNP_MBX_SYNC_MASK;\n+\t/* this is a message we already processed, do nothing */\n+\tif (check_state & FLAGS_DD)\n+\t\treturn rnp_mbx_fw_reply_handler(adapter,\n+\t\t\t\t(struct mbx_fw_cmd_reply *)msgbuf);\n+\telse\n+\t\treturn rnp_mbx_fw_req_handler(adapter,\n+\t\t\t\t(struct mbx_fw_cmd_req *)msgbuf);\n+\n+\treturn 0;\n+}\n+\n+static void rnp_rcv_ack_from_fw(struct rnp_eth_adapter *adapter)\n+{\n+\tstruct rnp_hw *hw __rte_unused = &adapter->hw;\n+\tu32 msg __rte_unused = RNP_VT_MSGTYPE_NACK;\n+\t/* do-nothing */\n+}\n+\n+int rnp_fw_msg_handler(struct rnp_eth_adapter *adapter)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(adapter->eth_dev);\n+\tstruct rnp_hw *hw = &adapter->hw;\n+\n+\t/* == check cpureq */\n+\tif (!ops->check_for_msg(hw, MBX_FW))\n+\t\trnp_rcv_msg_from_fw(adapter);\n+\n+\t/* process any acks */\n+\tif (!ops->check_for_ack(hw, MBX_FW))\n+\t\trnp_rcv_ack_from_fw(adapter);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/rnp/rnp_mbx_fw.h b/drivers/net/rnp/rnp_mbx_fw.h\nindex 051ffd1bdc..292ad6dfbe 100644\n--- a/drivers/net/rnp/rnp_mbx_fw.h\n+++ b/drivers/net/rnp/rnp_mbx_fw.h\n@@ -32,6 +32,8 @@ enum GENERIC_CMD {\n \tGET_PHY_ABALITY = 0x0601,\n \tGET_MAC_ADDRES = 0x0602,\n \tRESET_PHY = 0x0603,\n+\tGET_LINK_STATUS = 0x0607,\n+\tLINK_STATUS_EVENT = 0x0608,\n \tGET_LANE_STATUS = 0x0610,\n \tSET_EVENT_MASK = 0x0613,\n \t /* fw update */\n@@ -98,6 +100,21 @@ struct phy_abilities {\n \t};\n } __rte_packed __rte_aligned(4);\n \n+struct port_stat {\n+\tu8 phy_addr;\t\t/* Phy MDIO address */\n+\n+\tu8 duplex : 1; /* FIBRE is always 1,Twisted Pair 1 or 0 */\n+\tu8 autoneg : 1; /* autoned state */\n+\tu8 fec : 1;\n+\tu8 an_rev : 1;\n+\tu8 link_traing : 1;\n+\tu8 is_sgmii : 1; /* avild fw >= 0.5.0.17 */\n+\tu16 speed;\t\t/* cur port linked speed */\n+\n+\tu16 pause : 4;\n+\tu16 rev : 12;\n+} __rte_packed;\n+\n #define RNP_SPEED_CAP_UNKNOWN (0)\n #define RNP_SPEED_CAP_10M_FULL BIT(2)\n #define RNP_SPEED_CAP_100M_FULL BIT(3)\n@@ -186,8 +203,14 @@ struct mbx_fw_cmd_reply {\n \t\tstruct phy_abilities phy_abilities;\n \t};\n } __rte_packed __rte_aligned(4);\n-\n-#define MBX_REQ_HDR_LEN 24\n+/* == flags == */\n+#define FLAGS_DD\tBIT(0) /* driver clear 0, FW must set 1 */\n+#define FLAGS_CMP\tBIT(1) /* driver clear 0, FW mucst set */\n+/* driver clear 0, FW must set only if it reporting an error */\n+#define FLAGS_ERR\tBIT(2)\n+\n+#define MBX_REQ_HDR_LEN\t\t(24)\n+#define RNP_ALARM_INTERVAL\t(50000) /* unit us */\n /* driver -> firmware */\n struct mbx_fw_cmd_req {\n \tunsigned short flags; /* 0-1 */\n@@ -240,6 +263,14 @@ struct mbx_fw_cmd_req {\n \t\t\tint flag;\n \t\t\tint nr_lane;\n \t\t} set_dump;\n+\n+\t\tstruct {\n+\t\t\tunsigned short changed_lanes;\n+\t\t\tunsigned short lane_status;\n+\t\t\tunsigned int port_st_magic;\n+#define SPEED_VALID_MAGIC 0xa4a6a8a9\n+\t\t\tstruct port_stat st[4];\n+\t\t} link_stat; /* FW->RC */\n \t};\n } __rte_packed __rte_aligned(4);\n \n@@ -364,4 +395,7 @@ int rnp_mbx_get_lane_stat(struct rte_eth_dev *dev);\n int rnp_fw_update(struct rnp_eth_adapter *adapter);\n int rnp_hw_set_fw_10g_1g_auto_detch(struct rte_eth_dev *dev, int enable);\n int rnp_hw_set_fw_force_speed_1g(struct rte_eth_dev *dev, int enable);\n+void rnp_link_stat_mark(struct rnp_hw *hw, int nr_lane, int up);\n+void rnp_link_report(struct rte_eth_dev *dev, bool link_en);\n+int rnp_fw_msg_handler(struct rnp_eth_adapter *adapter);\n #endif /* __RNP_MBX_FW_H__*/\n", "prefixes": [ "v4", "8/8" ] }