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GET /api/patches/130028/?format=api
{ "id": 130028, "url": "http://patchwork.dpdk.org/api/patches/130028/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230809155134.539287-16-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230809155134.539287-16-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230809155134.539287-16-beilei.xing@intel.com", "date": "2023-08-09T15:51:30", "name": "[15/19] common/idpf: refine inline function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f1fc7790120c550f075922fb630514128e89cad6", "submitter": { "id": 410, "url": "http://patchwork.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230809155134.539287-16-beilei.xing@intel.com/mbox/", "series": [ { "id": 29139, "url": "http://patchwork.dpdk.org/api/series/29139/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29139", "date": "2023-08-09T15:51:15", "name": "net/cpfl: support port representor", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29139/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/130028/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/130028/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 758C343016;\n\tWed, 9 Aug 2023 09:35:02 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7072D432A6;\n\tWed, 9 Aug 2023 09:33:37 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id 23FF34329D\n for <dev@dpdk.org>; Wed, 9 Aug 2023 09:33:34 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Aug 2023 00:33:34 -0700", "from dpdk-beileix-icelake.sh.intel.com ([10.67.116.252])\n by fmsmga005.fm.intel.com with ESMTP; 09 Aug 2023 00:33:32 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1691566415; x=1723102415;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=Ops/0oBhWrtNXLCwVUL42vxNJ00WF+JnE9Cw7zk6gZk=;\n b=E7ilVaQQ5gj4TPhfO+RdFTumOWIuU3XO6YEjO4B+llIqEQFlsmRvfsBU\n 7UNfDrSkqwT9XcOOsTP090AGLoE9MLMYp1J8wc2OJFt21cb/sey0YlcR7\n l8OcH3SsF3e4BLYvf4Bim72FcMg0n3PAW/VjbUdukZ/vvRIgCZ6pksoNV\n VvLieKN2t2bK3iI8Tphwi2+Dk6spDPBtEHGGlLE6PpHpH4F2t+NkVlWzB\n ekItSAnsoEvLvmqhMj3YMMb2tqrqkdNnROr0lFRKDjSLKgQ3Fl77XJhJB\n X2o/g01ejQN7LXaHFg1uoicsR93gPz3cpT9dPWRDauqP4D4u0vUOdgu35 Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10795\"; a=\"356014523\"", "E=Sophos;i=\"6.01,158,1684825200\"; d=\"scan'208\";a=\"356014523\"", "E=McAfee;i=\"6600,9927,10795\"; a=\"1062337456\"", "E=Sophos;i=\"6.01,158,1684825200\"; d=\"scan'208\";a=\"1062337456\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com,\n\tmingxia.liu@intel.com", "Cc": "dev@dpdk.org,\n\tBeilei Xing <beilei.xing@intel.com>", "Subject": "[PATCH 15/19] common/idpf: refine inline function", "Date": "Wed, 9 Aug 2023 15:51:30 +0000", "Message-Id": "<20230809155134.539287-16-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230809155134.539287-1-beilei.xing@intel.com>", "References": "<20230809155134.539287-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nMove some static inline functions to header file.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/common/idpf/idpf_common_rxtx.c | 246 -------------------------\n drivers/common/idpf/idpf_common_rxtx.h | 246 +++++++++++++++++++++++++\n drivers/common/idpf/version.map | 3 +\n 3 files changed, 249 insertions(+), 246 deletions(-)", "diff": "diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c\nindex fc87e3e243..50465e76ea 100644\n--- a/drivers/common/idpf/idpf_common_rxtx.c\n+++ b/drivers/common/idpf/idpf_common_rxtx.c\n@@ -442,188 +442,6 @@ idpf_qc_split_rxq_mbufs_alloc(struct idpf_rx_queue *rxq)\n \treturn 0;\n }\n \n-#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000\n-/* Helper function to convert a 32b nanoseconds timestamp to 64b. */\n-static inline uint64_t\n-idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag,\n-\t\t\t uint32_t in_timestamp)\n-{\n-#ifdef RTE_ARCH_X86_64\n-\tstruct idpf_hw *hw = &ad->hw;\n-\tconst uint64_t mask = 0xFFFFFFFF;\n-\tuint32_t hi, lo, lo2, delta;\n-\tuint64_t ns;\n-\n-\tif (flag != 0) {\n-\t\tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n-\t\tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |\n-\t\t\t PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n-\t\tlo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n-\t\thi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);\n-\t\t/*\n-\t\t * On typical system, the delta between lo and lo2 is ~1000ns,\n-\t\t * so 10000 seems a large-enough but not overly-big guard band.\n-\t\t */\n-\t\tif (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))\n-\t\t\tlo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n-\t\telse\n-\t\t\tlo2 = lo;\n-\n-\t\tif (lo2 < lo) {\n-\t\t\tlo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n-\t\t\thi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);\n-\t\t}\n-\n-\t\tad->time_hw = ((uint64_t)hi << 32) | lo;\n-\t}\n-\n-\tdelta = (in_timestamp - (uint32_t)(ad->time_hw & mask));\n-\tif (delta > (mask / 2)) {\n-\t\tdelta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);\n-\t\tns = ad->time_hw - delta;\n-\t} else {\n-\t\tns = ad->time_hw + delta;\n-\t}\n-\n-\treturn ns;\n-#else /* !RTE_ARCH_X86_64 */\n-\tRTE_SET_USED(ad);\n-\tRTE_SET_USED(flag);\n-\tRTE_SET_USED(in_timestamp);\n-\treturn 0;\n-#endif /* RTE_ARCH_X86_64 */\n-}\n-\n-#define IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S\t\t\t\t\\\n-\t(RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_IPE_S) | \\\n-\t RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_L4E_S) | \\\n-\t RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EIPE_S) | \\\n-\t RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EUDPE_S))\n-\n-static inline uint64_t\n-idpf_splitq_rx_csum_offload(uint8_t err)\n-{\n-\tuint64_t flags = 0;\n-\n-\tif (unlikely((err & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_L3L4P_S)) == 0))\n-\t\treturn flags;\n-\n-\tif (likely((err & IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S) == 0)) {\n-\t\tflags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n-\t\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD);\n-\t\treturn flags;\n-\t}\n-\n-\tif (unlikely((err & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_IPE_S)) != 0))\n-\t\tflags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;\n-\telse\n-\t\tflags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;\n-\n-\tif (unlikely((err & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_L4E_S)) != 0))\n-\t\tflags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;\n-\telse\n-\t\tflags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;\n-\n-\tif (unlikely((err & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EIPE_S)) != 0))\n-\t\tflags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;\n-\n-\tif (unlikely((err & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EUDPE_S)) != 0))\n-\t\tflags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;\n-\telse\n-\t\tflags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD;\n-\n-\treturn flags;\n-}\n-\n-#define IDPF_RX_FLEX_DESC_ADV_HASH1_S 0\n-#define IDPF_RX_FLEX_DESC_ADV_HASH2_S 16\n-#define IDPF_RX_FLEX_DESC_ADV_HASH3_S 24\n-\n-static inline uint64_t\n-idpf_splitq_rx_rss_offload(struct rte_mbuf *mb,\n-\t\t\t volatile struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc)\n-{\n-\tuint8_t status_err0_qw0;\n-\tuint64_t flags = 0;\n-\n-\tstatus_err0_qw0 = rx_desc->status_err0_qw0;\n-\n-\tif ((status_err0_qw0 & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_RSS_VALID_S)) != 0) {\n-\t\tflags |= RTE_MBUF_F_RX_RSS_HASH;\n-\t\tmb->hash.rss = (rte_le_to_cpu_16(rx_desc->hash1) <<\n-\t\t\t\tIDPF_RX_FLEX_DESC_ADV_HASH1_S) |\n-\t\t\t((uint32_t)(rx_desc->ff2_mirrid_hash2.hash2) <<\n-\t\t\t IDPF_RX_FLEX_DESC_ADV_HASH2_S) |\n-\t\t\t((uint32_t)(rx_desc->hash3) <<\n-\t\t\t IDPF_RX_FLEX_DESC_ADV_HASH3_S);\n-\t}\n-\n-\treturn flags;\n-}\n-\n-static void\n-idpf_split_rx_bufq_refill(struct idpf_rx_queue *rx_bufq)\n-{\n-\tvolatile struct virtchnl2_splitq_rx_buf_desc *rx_buf_ring;\n-\tvolatile struct virtchnl2_splitq_rx_buf_desc *rx_buf_desc;\n-\tuint16_t nb_refill = rx_bufq->rx_free_thresh;\n-\tuint16_t nb_desc = rx_bufq->nb_rx_desc;\n-\tuint16_t next_avail = rx_bufq->rx_tail;\n-\tstruct rte_mbuf *nmb[rx_bufq->rx_free_thresh];\n-\tuint64_t dma_addr;\n-\tuint16_t delta;\n-\tint i;\n-\n-\tif (rx_bufq->nb_rx_hold < rx_bufq->rx_free_thresh)\n-\t\treturn;\n-\n-\trx_buf_ring = rx_bufq->rx_ring;\n-\tdelta = nb_desc - next_avail;\n-\tif (unlikely(delta < nb_refill)) {\n-\t\tif (likely(rte_pktmbuf_alloc_bulk(rx_bufq->mp, nmb, delta) == 0)) {\n-\t\t\tfor (i = 0; i < delta; i++) {\n-\t\t\t\trx_buf_desc = &rx_buf_ring[next_avail + i];\n-\t\t\t\trx_bufq->sw_ring[next_avail + i] = nmb[i];\n-\t\t\t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i]));\n-\t\t\t\trx_buf_desc->hdr_addr = 0;\n-\t\t\t\trx_buf_desc->pkt_addr = dma_addr;\n-\t\t\t}\n-\t\t\tnb_refill -= delta;\n-\t\t\tnext_avail = 0;\n-\t\t\trx_bufq->nb_rx_hold -= delta;\n-\t\t} else {\n-\t\t\t__atomic_fetch_add(&rx_bufq->rx_stats.mbuf_alloc_failed,\n-\t\t\t\t\t nb_desc - next_avail, __ATOMIC_RELAXED);\n-\t\t\tRX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u queue_id=%u\",\n-\t\t\t rx_bufq->port_id, rx_bufq->queue_id);\n-\t\t\treturn;\n-\t\t}\n-\t}\n-\n-\tif (nb_desc - next_avail >= nb_refill) {\n-\t\tif (likely(rte_pktmbuf_alloc_bulk(rx_bufq->mp, nmb, nb_refill) == 0)) {\n-\t\t\tfor (i = 0; i < nb_refill; i++) {\n-\t\t\t\trx_buf_desc = &rx_buf_ring[next_avail + i];\n-\t\t\t\trx_bufq->sw_ring[next_avail + i] = nmb[i];\n-\t\t\t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i]));\n-\t\t\t\trx_buf_desc->hdr_addr = 0;\n-\t\t\t\trx_buf_desc->pkt_addr = dma_addr;\n-\t\t\t}\n-\t\t\tnext_avail += nb_refill;\n-\t\t\trx_bufq->nb_rx_hold -= nb_refill;\n-\t\t} else {\n-\t\t\t__atomic_fetch_add(&rx_bufq->rx_stats.mbuf_alloc_failed,\n-\t\t\t\t\t nb_desc - next_avail, __ATOMIC_RELAXED);\n-\t\t\tRX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u queue_id=%u\",\n-\t\t\t rx_bufq->port_id, rx_bufq->queue_id);\n-\t\t}\n-\t}\n-\n-\tIDPF_PCI_REG_WRITE(rx_bufq->qrx_tail, next_avail);\n-\n-\trx_bufq->rx_tail = next_avail;\n-}\n-\n uint16_t\n idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t uint16_t nb_pkts)\n@@ -749,70 +567,6 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \treturn nb_rx;\n }\n \n-static inline void\n-idpf_split_tx_free(struct idpf_tx_queue *cq)\n-{\n-\tvolatile struct idpf_splitq_tx_compl_desc *compl_ring = cq->compl_ring;\n-\tvolatile struct idpf_splitq_tx_compl_desc *txd;\n-\tuint16_t next = cq->tx_tail;\n-\tstruct idpf_tx_entry *txe;\n-\tstruct idpf_tx_queue *txq;\n-\tuint16_t gen, qid, q_head;\n-\tuint16_t nb_desc_clean;\n-\tuint8_t ctype;\n-\n-\ttxd = &compl_ring[next];\n-\tgen = (rte_le_to_cpu_16(txd->qid_comptype_gen) &\n-\t IDPF_TXD_COMPLQ_GEN_M) >> IDPF_TXD_COMPLQ_GEN_S;\n-\tif (gen != cq->expected_gen_id)\n-\t\treturn;\n-\n-\tctype = (rte_le_to_cpu_16(txd->qid_comptype_gen) &\n-\t\t IDPF_TXD_COMPLQ_COMPL_TYPE_M) >> IDPF_TXD_COMPLQ_COMPL_TYPE_S;\n-\tqid = (rte_le_to_cpu_16(txd->qid_comptype_gen) &\n-\t IDPF_TXD_COMPLQ_QID_M) >> IDPF_TXD_COMPLQ_QID_S;\n-\tq_head = rte_le_to_cpu_16(txd->q_head_compl_tag.compl_tag);\n-\ttxq = cq->txqs[qid - cq->tx_start_qid];\n-\n-\tswitch (ctype) {\n-\tcase IDPF_TXD_COMPLT_RE:\n-\t\t/* clean to q_head which indicates be fetched txq desc id + 1.\n-\t\t * TODO: need to refine and remove the if condition.\n-\t\t */\n-\t\tif (unlikely(q_head % 32)) {\n-\t\t\tTX_LOG(ERR, \"unexpected desc (head = %u) completion.\",\n-\t\t\t q_head);\n-\t\t\treturn;\n-\t\t}\n-\t\tif (txq->last_desc_cleaned > q_head)\n-\t\t\tnb_desc_clean = (txq->nb_tx_desc - txq->last_desc_cleaned) +\n-\t\t\t\tq_head;\n-\t\telse\n-\t\t\tnb_desc_clean = q_head - txq->last_desc_cleaned;\n-\t\ttxq->nb_free += nb_desc_clean;\n-\t\ttxq->last_desc_cleaned = q_head;\n-\t\tbreak;\n-\tcase IDPF_TXD_COMPLT_RS:\n-\t\t/* q_head indicates sw_id when ctype is 2 */\n-\t\ttxe = &txq->sw_ring[q_head];\n-\t\tif (txe->mbuf != NULL) {\n-\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n-\t\t\ttxe->mbuf = NULL;\n-\t\t}\n-\t\tbreak;\n-\tdefault:\n-\t\tTX_LOG(ERR, \"unknown completion type.\");\n-\t\treturn;\n-\t}\n-\n-\tif (++next == cq->nb_tx_desc) {\n-\t\tnext = 0;\n-\t\tcq->expected_gen_id ^= 1;\n-\t}\n-\n-\tcq->tx_tail = next;\n-}\n-\n /* Check if the context descriptor is needed for TX offloading */\n static inline uint16_t\n idpf_calc_context_desc(uint64_t flags)\ndiff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h\nindex 6cb83fc0a6..a53335616a 100644\n--- a/drivers/common/idpf/idpf_common_rxtx.h\n+++ b/drivers/common/idpf/idpf_common_rxtx.h\n@@ -229,6 +229,252 @@ struct idpf_txq_ops {\n extern int idpf_timestamp_dynfield_offset;\n extern uint64_t idpf_timestamp_dynflag;\n \n+static inline void\n+idpf_split_tx_free(struct idpf_tx_queue *cq)\n+{\n+\tvolatile struct idpf_splitq_tx_compl_desc *compl_ring = cq->compl_ring;\n+\tvolatile struct idpf_splitq_tx_compl_desc *txd;\n+\tuint16_t next = cq->tx_tail;\n+\tstruct idpf_tx_entry *txe;\n+\tstruct idpf_tx_queue *txq;\n+\tuint16_t gen, qid, q_head;\n+\tuint16_t nb_desc_clean;\n+\tuint8_t ctype;\n+\n+\ttxd = &compl_ring[next];\n+\tgen = (rte_le_to_cpu_16(txd->qid_comptype_gen) &\n+\t IDPF_TXD_COMPLQ_GEN_M) >> IDPF_TXD_COMPLQ_GEN_S;\n+\tif (gen != cq->expected_gen_id)\n+\t\treturn;\n+\n+\tctype = (rte_le_to_cpu_16(txd->qid_comptype_gen) &\n+\t\t IDPF_TXD_COMPLQ_COMPL_TYPE_M) >> IDPF_TXD_COMPLQ_COMPL_TYPE_S;\n+\tqid = (rte_le_to_cpu_16(txd->qid_comptype_gen) &\n+\t IDPF_TXD_COMPLQ_QID_M) >> IDPF_TXD_COMPLQ_QID_S;\n+\tq_head = rte_le_to_cpu_16(txd->q_head_compl_tag.compl_tag);\n+\ttxq = cq->txqs[qid - cq->tx_start_qid];\n+\n+\tswitch (ctype) {\n+\tcase IDPF_TXD_COMPLT_RE:\n+\t\t/* clean to q_head which indicates be fetched txq desc id + 1.\n+\t\t * TODO: need to refine and remove the if condition.\n+\t\t */\n+\t\tif (unlikely(q_head % 32)) {\n+\t\t\tTX_LOG(ERR, \"unexpected desc (head = %u) completion.\",\n+\t\t\t q_head);\n+\t\t\treturn;\n+\t\t}\n+\t\tif (txq->last_desc_cleaned > q_head)\n+\t\t\tnb_desc_clean = (txq->nb_tx_desc - txq->last_desc_cleaned) +\n+\t\t\t\tq_head;\n+\t\telse\n+\t\t\tnb_desc_clean = q_head - txq->last_desc_cleaned;\n+\t\ttxq->nb_free += nb_desc_clean;\n+\t\ttxq->last_desc_cleaned = q_head;\n+\t\tbreak;\n+\tcase IDPF_TXD_COMPLT_RS:\n+\t\t/* q_head indicates sw_id when ctype is 2 */\n+\t\ttxe = &txq->sw_ring[q_head];\n+\t\tif (txe->mbuf != NULL) {\n+\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n+\t\t\ttxe->mbuf = NULL;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tTX_LOG(ERR, \"unknown completion type.\");\n+\t\treturn;\n+\t}\n+\n+\tif (++next == cq->nb_tx_desc) {\n+\t\tnext = 0;\n+\t\tcq->expected_gen_id ^= 1;\n+\t}\n+\n+\tcq->tx_tail = next;\n+}\n+\n+#define IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S\t\t\t\t\\\n+\t(RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_IPE_S) | \\\n+\t RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_L4E_S) | \\\n+\t RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EIPE_S) | \\\n+\t RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EUDPE_S))\n+\n+static inline uint64_t\n+idpf_splitq_rx_csum_offload(uint8_t err)\n+{\n+\tuint64_t flags = 0;\n+\n+\tif (unlikely((err & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_L3L4P_S)) == 0))\n+\t\treturn flags;\n+\n+\tif (likely((err & IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S) == 0)) {\n+\t\tflags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n+\t\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD);\n+\t\treturn flags;\n+\t}\n+\n+\tif (unlikely((err & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_IPE_S)) != 0))\n+\t\tflags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;\n+\telse\n+\t\tflags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;\n+\n+\tif (unlikely((err & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_L4E_S)) != 0))\n+\t\tflags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;\n+\telse\n+\t\tflags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;\n+\n+\tif (unlikely((err & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EIPE_S)) != 0))\n+\t\tflags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;\n+\n+\tif (unlikely((err & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EUDPE_S)) != 0))\n+\t\tflags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;\n+\telse\n+\t\tflags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD;\n+\n+\treturn flags;\n+}\n+\n+#define IDPF_RX_FLEX_DESC_ADV_HASH1_S 0\n+#define IDPF_RX_FLEX_DESC_ADV_HASH2_S 16\n+#define IDPF_RX_FLEX_DESC_ADV_HASH3_S 24\n+\n+static inline uint64_t\n+idpf_splitq_rx_rss_offload(struct rte_mbuf *mb,\n+\t\t\t volatile struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc)\n+{\n+\tuint8_t status_err0_qw0;\n+\tuint64_t flags = 0;\n+\n+\tstatus_err0_qw0 = rx_desc->status_err0_qw0;\n+\n+\tif ((status_err0_qw0 & RTE_BIT32(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_RSS_VALID_S)) != 0) {\n+\t\tflags |= RTE_MBUF_F_RX_RSS_HASH;\n+\t\tmb->hash.rss = (rte_le_to_cpu_16(rx_desc->hash1) <<\n+\t\t\t\tIDPF_RX_FLEX_DESC_ADV_HASH1_S) |\n+\t\t\t((uint32_t)(rx_desc->ff2_mirrid_hash2.hash2) <<\n+\t\t\t IDPF_RX_FLEX_DESC_ADV_HASH2_S) |\n+\t\t\t((uint32_t)(rx_desc->hash3) <<\n+\t\t\t IDPF_RX_FLEX_DESC_ADV_HASH3_S);\n+\t}\n+\n+\treturn flags;\n+}\n+\n+#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000\n+/* Helper function to convert a 32b nanoseconds timestamp to 64b. */\n+static inline uint64_t\n+idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag,\n+\t\t\t uint32_t in_timestamp)\n+{\n+#ifdef RTE_ARCH_X86_64\n+\tstruct idpf_hw *hw = &ad->hw;\n+\tconst uint64_t mask = 0xFFFFFFFF;\n+\tuint32_t hi, lo, lo2, delta;\n+\tuint64_t ns;\n+\n+\tif (flag != 0) {\n+\t\tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n+\t\tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |\n+\t\t\t PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n+\t\tlo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n+\t\thi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);\n+\t\t/*\n+\t\t * On typical system, the delta between lo and lo2 is ~1000ns,\n+\t\t * so 10000 seems a large-enough but not overly-big guard band.\n+\t\t */\n+\t\tif (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))\n+\t\t\tlo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n+\t\telse\n+\t\t\tlo2 = lo;\n+\n+\t\tif (lo2 < lo) {\n+\t\t\tlo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n+\t\t\thi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);\n+\t\t}\n+\n+\t\tad->time_hw = ((uint64_t)hi << 32) | lo;\n+\t}\n+\n+\tdelta = (in_timestamp - (uint32_t)(ad->time_hw & mask));\n+\tif (delta > (mask / 2)) {\n+\t\tdelta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);\n+\t\tns = ad->time_hw - delta;\n+\t} else {\n+\t\tns = ad->time_hw + delta;\n+\t}\n+\n+\treturn ns;\n+#else /* !RTE_ARCH_X86_64 */\n+\tRTE_SET_USED(ad);\n+\tRTE_SET_USED(flag);\n+\tRTE_SET_USED(in_timestamp);\n+\treturn 0;\n+#endif /* RTE_ARCH_X86_64 */\n+}\n+\n+static inline void\n+idpf_split_rx_bufq_refill(struct idpf_rx_queue *rx_bufq)\n+{\n+\tvolatile struct virtchnl2_splitq_rx_buf_desc *rx_buf_ring;\n+\tvolatile struct virtchnl2_splitq_rx_buf_desc *rx_buf_desc;\n+\tuint16_t nb_refill = rx_bufq->rx_free_thresh;\n+\tuint16_t nb_desc = rx_bufq->nb_rx_desc;\n+\tuint16_t next_avail = rx_bufq->rx_tail;\n+\tstruct rte_mbuf *nmb[rx_bufq->rx_free_thresh];\n+\tuint64_t dma_addr;\n+\tuint16_t delta;\n+\tint i;\n+\n+\tif (rx_bufq->nb_rx_hold < rx_bufq->rx_free_thresh)\n+\t\treturn;\n+\n+\trx_buf_ring = rx_bufq->rx_ring;\n+\tdelta = nb_desc - next_avail;\n+\tif (unlikely(delta < nb_refill)) {\n+\t\tif (likely(rte_pktmbuf_alloc_bulk(rx_bufq->mp, nmb, delta) == 0)) {\n+\t\t\tfor (i = 0; i < delta; i++) {\n+\t\t\t\trx_buf_desc = &rx_buf_ring[next_avail + i];\n+\t\t\t\trx_bufq->sw_ring[next_avail + i] = nmb[i];\n+\t\t\t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i]));\n+\t\t\t\trx_buf_desc->hdr_addr = 0;\n+\t\t\t\trx_buf_desc->pkt_addr = dma_addr;\n+\t\t\t}\n+\t\t\tnb_refill -= delta;\n+\t\t\tnext_avail = 0;\n+\t\t\trx_bufq->nb_rx_hold -= delta;\n+\t\t} else {\n+\t\t\t__atomic_fetch_add(&rx_bufq->rx_stats.mbuf_alloc_failed,\n+\t\t\t\t\t nb_desc - next_avail, __ATOMIC_RELAXED);\n+\t\t\tRX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u queue_id=%u\",\n+\t\t\t rx_bufq->port_id, rx_bufq->queue_id);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tif (nb_desc - next_avail >= nb_refill) {\n+\t\tif (likely(rte_pktmbuf_alloc_bulk(rx_bufq->mp, nmb, nb_refill) == 0)) {\n+\t\t\tfor (i = 0; i < nb_refill; i++) {\n+\t\t\t\trx_buf_desc = &rx_buf_ring[next_avail + i];\n+\t\t\t\trx_bufq->sw_ring[next_avail + i] = nmb[i];\n+\t\t\t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i]));\n+\t\t\t\trx_buf_desc->hdr_addr = 0;\n+\t\t\t\trx_buf_desc->pkt_addr = dma_addr;\n+\t\t\t}\n+\t\t\tnext_avail += nb_refill;\n+\t\t\trx_bufq->nb_rx_hold -= nb_refill;\n+\t\t} else {\n+\t\t\t__atomic_fetch_add(&rx_bufq->rx_stats.mbuf_alloc_failed,\n+\t\t\t\t\t nb_desc - next_avail, __ATOMIC_RELAXED);\n+\t\t\tRX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u queue_id=%u\",\n+\t\t\t rx_bufq->port_id, rx_bufq->queue_id);\n+\t\t}\n+\t}\n+\n+\tIDPF_PCI_REG_WRITE(rx_bufq->qrx_tail, next_avail);\n+\n+\trx_bufq->rx_tail = next_avail;\n+}\n+\n __rte_internal\n int idpf_qc_rx_thresh_check(uint16_t nb_desc, uint16_t thresh);\n __rte_internal\ndiff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map\nindex 0729f6b912..8a637b3a0d 100644\n--- a/drivers/common/idpf/version.map\n+++ b/drivers/common/idpf/version.map\n@@ -74,5 +74,8 @@ INTERNAL {\n \tidpf_vport_rss_config;\n \tidpf_vport_stats_update;\n \n+\tidpf_timestamp_dynfield_offset;\n+\tidpf_timestamp_dynflag;\n+\n \tlocal: *;\n };\n", "prefixes": [ "15/19" ] }