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GET /api/patches/131008/?format=api
{ "id": 131008, "url": "http://patchwork.dpdk.org/api/patches/131008/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230901023050.40893-5-caowenbo@mucse.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230901023050.40893-5-caowenbo@mucse.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230901023050.40893-5-caowenbo@mucse.com", "date": "2023-09-01T02:30:46", "name": "[v6,4/8] net/rnp: add mbx basic api feature", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "91175cb7cee06dbb6ad08efab486eb1cc1624621", "submitter": { "id": 2142, "url": "http://patchwork.dpdk.org/api/people/2142/?format=api", "name": "11", "email": "caowenbo@mucse.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230901023050.40893-5-caowenbo@mucse.com/mbox/", "series": [ { "id": 29398, "url": "http://patchwork.dpdk.org/api/series/29398/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29398", "date": "2023-09-01T02:30:42", "name": "drivers/net Add Support mucse N10 Pmd Driver", "version": 6, "mbox": "http://patchwork.dpdk.org/series/29398/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/131008/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/131008/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C79A842219;\n\tFri, 1 Sep 2023 04:31:44 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AE7DB402B4;\n\tFri, 1 Sep 2023 04:31:40 +0200 (CEST)", "from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22])\n by mails.dpdk.org (Postfix) with ESMTP id 0B8E0402A5\n for <dev@dpdk.org>; Fri, 1 Sep 2023 04:31:37 +0200 (CEST)", "from steven.localdomain ( [183.81.182.182])\n by bizesmtp.qq.com (ESMTP) with\n id ; Fri, 01 Sep 2023 10:31:15 +0800 (CST)" ], "X-QQ-mid": "bizesmtp81t1693535479tbvjgnzi", "X-QQ-SSF": "01400000000000D0F000000A0000000", "X-QQ-FEAT": "FwowAM4HOqC/6qeqXqo2yTZ2fMQpF6ApURiVkLxFG1Op2AfiGZIwB18Y+1ywL\n XKZEVEvlsl6KGHQ9BVegF658m4Wii7QEj3pt250c5L83gH6VA1LzedooqO9cTdmODvF3ymc\n XL5mkoShkxyLlxQuM94/PD1inEBLqtrqhpfo5S0GgFyF527nwFkqrc5V38aWjDWgtjB2z8/\n EHqhl1IpD4jQzda5Dbwl66IYxQPJ9gcPrR94Vnv53LHZlN6cJVTTqLa1NxAgi8f1fILD2+Y\n WIYvLSWosKSNlyQga0ags/pnkjjldDi2GEzno8sGjzNy+OxDEHABT/2d92IW5mFGWBLJ3vU\n o6k5ddq80Na47W7MOcYd+dCc2fhaqp1XhGG8z8bRc9TB0SWSgtZeNFkqwlStAxZDtJKpzBC\n eVWlpToP/rSnExYB0NZFFQ==", "X-QQ-GoodBg": "2", "X-BIZMAIL-ID": "12752801599276432701", "From": "Wenbo Cao <caowenbo@mucse.com>", "To": "Wenbo Cao <caowenbo@mucse.com>", "Cc": "dev@dpdk.org, ferruh.yigit@amd.com, thomas@monjalon.net,\n andrew.rybchenko@oktetlabs.ru, yaojun@mucse.com,\n Stephen Hemminger <stephen@networkplumber.org>", "Subject": "[PATCH v6 4/8] net/rnp: add mbx basic api feature", "Date": "Fri, 1 Sep 2023 02:30:46 +0000", "Message-Id": "<20230901023050.40893-5-caowenbo@mucse.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230901023050.40893-1-caowenbo@mucse.com>", "References": "<20230901023050.40893-1-caowenbo@mucse.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:mucse.com:qybglogicsvrgz:qybglogicsvrgz5a-0", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "mbx base code is for communicate with the firmware\n\nSigned-off-by: Wenbo Cao <caowenbo@mucse.com>\nSuggested-by: Stephen Hemminger <stephen@networkplumber.org>\n---\n drivers/net/rnp/base/rnp_api.c | 23 ++\n drivers/net/rnp/base/rnp_api.h | 7 +\n drivers/net/rnp/base/rnp_cfg.h | 7 +\n drivers/net/rnp/base/rnp_dma_regs.h | 73 ++++\n drivers/net/rnp/base/rnp_eth_regs.h | 124 +++++++\n drivers/net/rnp/base/rnp_hw.h | 112 +++++-\n drivers/net/rnp/meson.build | 1 +\n drivers/net/rnp/rnp.h | 35 ++\n drivers/net/rnp/rnp_ethdev.c | 70 +++-\n drivers/net/rnp/rnp_logs.h | 9 +\n drivers/net/rnp/rnp_mbx.c | 522 ++++++++++++++++++++++++++++\n drivers/net/rnp/rnp_mbx.h | 139 ++++++++\n drivers/net/rnp/rnp_mbx_fw.c | 271 +++++++++++++++\n drivers/net/rnp/rnp_mbx_fw.h | 22 ++\n 14 files changed, 1412 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/rnp/base/rnp_api.c\n create mode 100644 drivers/net/rnp/base/rnp_api.h\n create mode 100644 drivers/net/rnp/base/rnp_cfg.h\n create mode 100644 drivers/net/rnp/base/rnp_dma_regs.h\n create mode 100644 drivers/net/rnp/base/rnp_eth_regs.h\n create mode 100644 drivers/net/rnp/rnp_mbx.c\n create mode 100644 drivers/net/rnp/rnp_mbx.h\n create mode 100644 drivers/net/rnp/rnp_mbx_fw.c\n create mode 100644 drivers/net/rnp/rnp_mbx_fw.h", "diff": "diff --git a/drivers/net/rnp/base/rnp_api.c b/drivers/net/rnp/base/rnp_api.c\nnew file mode 100644\nindex 0000000000..550da6217d\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_api.c\n@@ -0,0 +1,23 @@\n+#include \"rnp.h\"\n+#include \"rnp_api.h\"\n+\n+int\n+rnp_init_hw(struct rte_eth_dev *dev)\n+{\n+\tconst struct rnp_mac_api *ops = RNP_DEV_TO_MAC_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\n+\tif (ops->init_hw)\n+\t\treturn ops->init_hw(hw);\n+\treturn -EOPNOTSUPP;\n+}\n+\n+int\n+rnp_reset_hw(struct rte_eth_dev *dev, struct rnp_hw *hw)\n+{\n+\tconst struct rnp_mac_api *ops = RNP_DEV_TO_MAC_OPS(dev);\n+\n+\tif (ops->reset_hw)\n+\t\treturn ops->reset_hw(hw);\n+\treturn -EOPNOTSUPP;\n+}\ndiff --git a/drivers/net/rnp/base/rnp_api.h b/drivers/net/rnp/base/rnp_api.h\nnew file mode 100644\nindex 0000000000..df574dab77\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_api.h\n@@ -0,0 +1,7 @@\n+#ifndef __RNP_API_H__\n+#define __RNP_API_H__\n+int\n+rnp_init_hw(struct rte_eth_dev *dev);\n+int\n+rnp_reset_hw(struct rte_eth_dev *dev, struct rnp_hw *hw);\n+#endif /* __RNP_API_H__ */\ndiff --git a/drivers/net/rnp/base/rnp_cfg.h b/drivers/net/rnp/base/rnp_cfg.h\nnew file mode 100644\nindex 0000000000..90f25268ad\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_cfg.h\n@@ -0,0 +1,7 @@\n+#ifndef __RNP_CFG_H__\n+#define __RNP_CFG_H__\n+#include \"rnp_osdep.h\"\n+\n+#define RNP_NIC_RESET\t\t_NIC_(0x0010)\n+#define RNP_TX_QINQ_WORKAROUND\t_NIC_(0x801c)\n+#endif /* __RNP_CFG_H__ */\ndiff --git a/drivers/net/rnp/base/rnp_dma_regs.h b/drivers/net/rnp/base/rnp_dma_regs.h\nnew file mode 100644\nindex 0000000000..bfe87e534d\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_dma_regs.h\n@@ -0,0 +1,73 @@\n+#ifndef __RNP_REGS_H__\n+#define __RNP_REGS_H__\n+\n+#include \"rnp_osdep.h\"\n+\n+/* mac address offset */\n+#define RNP_DMA_CTRL\t\t\t\t(0x4)\n+#define RNP_VEB_BYPASS_EN\t\t\tBIT(4)\n+#define RNP_DMA_MEM_CFG_LE\t\t\t(0 << 5)\n+#define TSNR10_DMA_MEM_CFG_BE\t\t\t(1 << 5)\n+#define RNP_DMA_SCATTER_MEM_SHIFT\t\t(16)\n+\n+#define RNP_FIRMWARE_SYNC\t\t\t(0xc)\n+#define RNP_FIRMWARE_SYNC_MASK\t\t\tGENMASK(31, 16)\n+#define RNP_FIRMWARE_SYNC_MAGIC\t\t\t(0xa5a40000)\n+#define RNP_DRIVER_REMOVE\t\t\t(0x5a000000)\n+/* 1BIT <-> 16 bytes Dma Addr Size*/\n+#define RNP_DMA_SCATTER_MEM_MASK\t\tGENMASK(31, 16)\n+#define RNP_DMA_TX_MAP_MODE_SHIFT\t\t(12)\n+#define RNP_DMA_TX_MAP_MODE_MASK\t\tGENMASK(15, 12)\n+#define RNP_DMA_RX_MEM_PAD_EN\t\t\tBIT(8)\n+/* === queue register ===== */\n+/* enable */\n+#define RNP_DMA_RXQ_START(qid)\t\t\t_RING_(0x0010 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_READY(qid)\t\t\t_RING_(0x0014 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_START(qid)\t\t\t_RING_(0x0018 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_READY(qid)\t\t\t_RING_(0x001c + 0x100 * (qid))\n+\n+#define RNP_DMA_INT_STAT(qid)\t\t\t_RING_(0x0020 + 0x100 * (qid))\n+#define RNP_DMA_INT_MASK(qid)\t\t\t_RING_(0x0024 + 0x100 * (qid))\n+#define RNP_TX_INT_MASK\t\t\t\tBIT(1)\n+#define RNP_RX_INT_MASK\t\t\t\tBIT(0)\n+#define RNP_DMA_INT_CLER(qid)\t\t\t_RING_(0x0028 + 0x100 * (qid))\n+\n+/* rx-queue */\n+#define RNP_DMA_RXQ_BASE_ADDR_HI(qid)\t\t_RING_(0x0030 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_BASE_ADDR_LO(qid)\t\t_RING_(0x0034 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_LEN(qid)\t\t\t_RING_(0x0038 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_HEAD(qid)\t\t\t_RING_(0x003c + 0x100 * (qid))\n+#define RNP_DMA_RXQ_TAIL(qid)\t\t\t_RING_(0x0040 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_DESC_FETCH_CTRL(qid)\t_RING_(0x0044 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_INT_DELAY_TIMER(qid)\t_RING_(0x0048 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_INT_DELAY_PKTCNT(qidx)\t_RING_(0x004c + 0x100 * (qid))\n+#define RNP_DMA_RXQ_RX_PRI_LVL(qid)\t\t_RING_(0x0050 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_DROP_TIMEOUT_TH(qid)\t_RING_(0x0054 + 0x100 * (qid))\n+/* tx-queue */\n+#define RNP_DMA_TXQ_BASE_ADDR_HI(qid)\t\t_RING_(0x0060 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_BASE_ADDR_LO(qid)\t\t_RING_(0x0064 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_LEN(qid)\t\t\t_RING_(0x0068 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_HEAD(qid)\t\t\t_RING_(0x006c + 0x100 * (qid))\n+#define RNP_DMA_TXQ_TAIL(qid)\t\t\t_RING_(0x0070 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_DESC_FETCH_CTRL(qid)\t_RING_(0x0074 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_INT_DELAY_TIMER(qid)\t_RING_(0x0078 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_INT_DELAY_PKTCNT(qid)\t_RING_(0x007c + 0x100 * (qid))\n+\n+#define RNP_DMA_TXQ_PRI_LVL(qid)\t\t_RING_(0x0080 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_RATE_CTRL_TH(qid)\t\t_RING_(0x0084 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_RATE_CTRL_TM(qid)\t\t_RING_(0x0088 + 0x100 * (qid))\n+\n+/* VEB Table Register */\n+#define RNP_VBE_MAC_LO(port, nr)\t\t_RING_(0x00a0 + (4 * (port)) + \\\n+\t\t\t\t\t\t(0x100 * (nr)))\n+#define RNP_VBE_MAC_HI(port, nr)\t\t_RING_(0x00b0 + (4 * (port)) + \\\n+\t\t\t\t\t\t(0x100 * (nr)))\n+#define RNP_VEB_VID_CFG(port, nr)\t\t_RING_(0x00c0 + (4 * (port)) + \\\n+\t\t\t\t\t\t(0x100 * (nr)))\n+#define RNP_VEB_VF_RING(port, nr)\t\t_RING_(0x00d0 + (4 * (port)) + \\\n+\t\t\t\t\t\t(0x100 * (nr)))\n+#define RNP_MAX_VEB_TB\t\t\t\t(64)\n+#define RNP_VEB_RING_CFG_OFFSET\t\t\t(8)\n+#define RNP_VEB_SWITCH_VF_EN\t\t\tBIT(7)\n+#define MAX_VEB_TABLES_NUM\t\t\t(4)\n+#endif /* RNP_DMA_REGS_H_ */\ndiff --git a/drivers/net/rnp/base/rnp_eth_regs.h b/drivers/net/rnp/base/rnp_eth_regs.h\nnew file mode 100644\nindex 0000000000..88e8e1e552\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_eth_regs.h\n@@ -0,0 +1,124 @@\n+#ifndef _RNP_ETH_REGS_H_\n+#define _RNP_ETH_REGS_H_\n+\n+#include \"rnp_osdep.h\"\n+\n+/* PTP 1588 TM Offload */\n+#define RNP_ETH_PTP_TX_STATUS(n)\t_ETH_(0x0400 + ((n) * 0x14))\n+#define RNP_ETH_PTP_TX_HTIMES(n)\t_ETH_(0x0404 + ((n) * 0x14))\n+#define RNP_ETH_PTP_TX_LTIMES(n)\t_ETH_(0x0408 + ((n) * 0x14))\n+#define RNP_ETH_PTP_TX_TS_ST(n)\t\t_ETH_(0x040c + ((n) * 0x14))\n+#define RNP_ETH_PTP_TX_CLEAR(n)\t\t_ETH_(0x0410 + ((n) * 0x14))\n+\n+#define RNP_ETH_ENGINE_BYPASS\t\t_ETH_(0x8000)\n+#define RNP_EN_TUNNEL_VXLAN_PARSE\t_ETH_(0x8004)\n+#define RNP_ETH_MAC_LOOPBACK\t\t_ETH_(0x8008)\n+#define RNP_ETH_FIFO_CTRL\t\t_ETH_(0x800c)\n+#define RNP_ETH_FOUR_FIFO\t\tBIT(0)\n+#define RNP_ETH_TWO_FIFO\t\tBIT(1)\n+#define RNP_ETH_ONE_FIFO\t\tBIT(2)\n+#define RNP_FIFO_CFG_EN\t\t\t(0x1221)\n+#define RNP_ETH_VXLAN_PORT_CTRL\t\t_ETH_(0x8010)\n+#define RNP_ETH_VXLAN_DEF_PORT\t\t(4789)\n+#define RNP_HOST_FILTER_EN\t\t_ETH_(0x801c)\n+#define RNP_HW_SCTP_CKSUM_CTRL\t\t_ETH_(0x8038)\n+#define RNP_HW_CHECK_ERR_CTRL\t\t_ETH_(0x8060)\n+#define RNP_HW_ERR_HDR_LEN\t\tBIT(0)\n+#define RNP_HW_ERR_PKTLEN\t\tBIT(1)\n+#define RNP_HW_L3_CKSUM_ERR\t\tBIT(2)\n+#define RNP_HW_L4_CKSUM_ERR\t\tBIT(3)\n+#define RNP_HW_SCTP_CKSUM_ERR\t\tBIT(4)\n+#define RNP_HW_INNER_L3_CKSUM_ERR\tBIT(5)\n+#define RNP_HW_INNER_L4_CKSUM_ERR\tBIT(6)\n+#define RNP_HW_CKSUM_ERR_MASK\t\tGENMASK(6, 2)\n+#define RNP_HW_CHECK_ERR_MASK\t\tGENMASK(6, 0)\n+#define RNP_HW_ERR_RX_ALL_MASK\t\tGENMASK(1, 0)\n+\n+#define RNP_REDIR_CTRL\t\t\t_ETH_(0x8030)\n+#define RNP_VLAN_Q_STRIP_CTRL(n)\t_ETH_(0x8040 + 0x4 * ((n) / 32))\n+/* This Just VLAN Master Switch */\n+#define RNP_VLAN_TUNNEL_STRIP_EN\t_ETH_(0x8050)\n+#define RNP_VLAN_TUNNEL_STRIP_MODE\t_ETH_(0x8054)\n+#define RNP_VLAN_TUNNEL_STRIP_OUTER\t(0)\n+#define RNP_VLAN_TUNNEL_STRIP_INNER\t(1)\n+#define RNP_RSS_INNER_CTRL\t\t_ETH_(0x805c)\n+#define RNP_INNER_RSS_EN\t\t(1)\n+\n+#define RNP_ETH_DEFAULT_RX_RING\t\t_ETH_(0x806c)\n+#define RNP_RX_FC_HI_WATER(n)\t\t_ETH_(0x80c0 + ((n) * 0x8))\n+#define RNP_RX_FC_LO_WATER(n)\t\t_ETH_(0x80c4 + ((n) * 0x8))\n+\n+#define RNP_RX_FIFO_FULL_THRETH(n)\t_ETH_(0x8070 + ((n) * 0x8))\n+#define RNP_RX_WORKAROUND_VAL\t\t_ETH_(0x7ff)\n+#define RNP_RX_DEFAULT_VAL\t\t_ETH_(0x270)\n+\n+#define RNP_MIN_FRAME_CTRL\t\t_ETH_(0x80f0)\n+#define RNP_MAX_FRAME_CTRL\t\t_ETH_(0x80f4)\n+\n+#define RNP_RX_FC_ENABLE\t\t_ETH_(0x8520)\n+#define RNP_RING_FC_EN(n)\t\t_ETH_(0x8524 + 0x4 * ((n) / 32))\n+#define RNP_RING_FC_THRESH(n)\t\t_ETH_(0x8a00 + 0x4 * (n))\n+\n+/* Mac Host Filter */\n+#define RNP_MAC_FCTRL\t\t\t_ETH_(0x9110)\n+#define RNP_MAC_FCTRL_MPE\t\tBIT(8)\t/* Multicast Promiscuous En */\n+#define RNP_MAC_FCTRL_UPE\t\tBIT(9)\t/* Unicast Promiscuous En */\n+#define RNP_MAC_FCTRL_BAM\t\tBIT(10) /* Broadcast Accept Mode */\n+#define RNP_MAC_FCTRL_BYPASS\t\t(RNP_MAC_FCTRL_MPE | \\\n+\t\t\t\t\tRNP_MAC_FCTRL_UPE | \\\n+\t\t\t\t\tRNP_MAC_FCTRL_BAM)\n+/* MC UC Mac Hash Filter Ctrl */\n+#define RNP_MAC_MCSTCTRL\t\t_ETH_(0x9114)\n+#define RNP_MAC_HASH_MASK\t\tGENMASK(11, 0)\n+#define RNP_MAC_MULTICASE_TBL_EN\tBIT(2)\n+#define RNP_MAC_UNICASE_TBL_EN\t\tBIT(3)\n+#define RNP_UC_HASH_TB(n)\t\t_ETH_(0xA800 + ((n) * 0x4))\n+#define RNP_MC_HASH_TB(n)\t\t_ETH_(0xAC00 + ((n) * 0x4))\n+\n+#define RNP_VLAN_FILTER_CTRL\t\t_ETH_(0x9118)\n+#define RNP_L2TYPE_FILTER_CTRL\t\t(RNP_VLAN_FILTER_CTRL)\n+#define RNP_L2TYPE_FILTER_EN\t\tBIT(31)\n+#define RNP_VLAN_FILTER_EN\t\tBIT(30)\n+\n+#define RNP_FC_PAUSE_FWD_ACT\t\t_ETH_(0x9280)\n+#define RNP_FC_PAUSE_DROP\t\tBIT(31)\n+#define RNP_FC_PAUSE_PASS\t\t(0)\n+#define RNP_FC_PAUSE_TYPE\t\t_ETH_(0x9284)\n+#define RNP_FC_PAUSE_POLICY_EN\t\tBIT(31)\n+#define RNP_PAUSE_TYPE\t\t\t_ETH_(0x8808)\n+\n+#define RNP_INPUT_USE_CTRL\t\t_ETH_(0x91d0)\n+#define RNP_INPUT_VALID_MASK\t\t(0xf)\n+#define RNP_INPUT_POLICY(n)\t\t_ETH_(0x91e0 + ((n) * 0x4))\n+/* RSS */\n+#define RNP_RSS_MRQC_ADDR\t\t_ETH_(0x92a0)\n+#define RNP_SRIOV_CTRL\t\t\tRNP_RSS_MRQC_ADDR\n+#define RNP_SRIOV_ENABLE\t\tBIT(3)\n+\n+#define RNP_RSS_REDIR_TB(mac, idx)\t_ETH_(0xe000 + \\\n+\t\t((mac) * 0x200) + ((idx) * 0x4))\n+#define RNP_RSS_KEY_TABLE(idx)\t\t_ETH_(0x92d0 + ((idx) * 0x4))\n+/*=======================================================================\n+ *HOST_MAC_ADDRESS_FILTER\n+ *=======================================================================\n+ */\n+#define RNP_RAL_BASE_ADDR(vf_id)\t_ETH_(0xA000 + 0x04 * (vf_id))\n+#define RNP_RAH_BASE_ADDR(vf_id)\t_ETH_(0xA400 + 0x04 * (vf_id))\n+#define RNP_MAC_FILTER_EN\t\tBIT(31)\n+\n+/* ETH Statistic */\n+#define RNP_ETH_RXTRANS_DROP(p_id)\t_ETH_((0x8904) + ((p_id) * (0x40)))\n+#define RNP_ETH_RXTRANS_CAT_ERR(p_id)\t_ETH_((0x8928) + ((p_id) * (0x40)))\n+#define RNP_ETH_TXTM_DROP\t\t_ETH_(0X0470)\n+\n+#define RNP_VFTA_BASE_ADDR\t\t_ETH_(0xB000)\n+#define RNP_VFTA_HASH_TABLE(id)\t\t(RNP_VFTA_BASE_ADDR + 0x4 * (id))\n+#define RNP_ETYPE_BASE_ADDR\t\t_ETH_(0xB300)\n+#define RNP_MPSAR_BASE_ADDR(vf_id)\t_ETH_(0xB400 + 0x04 * (vf_id))\n+#define RNP_PFVLVF_BASE_ADDR\t\t_ETH_(0xB600)\n+#define RNP_PFVLVFB_BASE_ADDR\t\t_ETH_(0xB700)\n+#define RNP_TUNNEL_PFVLVF_BASE_ADDR\t_ETH_(0xB800)\n+#define RNP_TUNNEL_PFVLVFB_BASE_ADDR\t_ETH_(0xB900)\n+\n+#define RNP_TC_PORT_MAP_TB(port)\t_ETH_(0xe840 + 0x04 * (port))\n+#endif /* RNP_ETH_REGS_H_ */\ndiff --git a/drivers/net/rnp/base/rnp_hw.h b/drivers/net/rnp/base/rnp_hw.h\nindex d80d23f4b4..1db966cf21 100644\n--- a/drivers/net/rnp/base/rnp_hw.h\n+++ b/drivers/net/rnp/base/rnp_hw.h\n@@ -4,16 +4,126 @@\n #ifndef __RNP_HW_H__\n #define __RNP_HW_H__\n \n+#include <rte_io.h>\n+#include <ethdev_driver.h>\n+\n+#include \"rnp_osdep.h\"\n+\n+static inline unsigned int rnp_rd_reg(volatile void *addr)\n+{\n+\tunsigned int v = rte_read32(addr);\n+\n+\treturn v;\n+}\n+\n+static inline void rnp_wr_reg(volatile void *reg, int val)\n+{\n+\trte_write32_relaxed((val), (reg));\n+}\n+\n+#define mbx_rd32(_hw, _off)\t\t\\\n+\trnp_rd_reg((uint8_t *)((_hw)->iobar4) + (_off))\n+#define mbx_wr32(_hw, _off, _val)\t\\\n+\trnp_wr_reg((uint8_t *)((_hw)->iobar4) + (_off), (_val))\n+#define rnp_io_rd(_base, _off)\t\t\\\n+\trnp_rd_reg((uint8_t *)(_base) + (_off))\n+#define rnp_io_wr(_base, _off, _val)\t\\\n+\trnp_wr_reg((uint8_t *)(_base) + (_off), (_val))\n+\n+struct rnp_hw;\n+/* Mbx Operate info */\n+enum MBX_ID {\n+\tMBX_PF = 0,\n+\tMBX_VF,\n+\tMBX_CM3CPU,\n+\tMBX_FW = MBX_CM3CPU,\n+\tMBX_VFCNT\n+};\n+struct rnp_mbx_api {\n+\tvoid (*init_mbx)(struct rnp_hw *hw);\n+\tint32_t (*read)(struct rnp_hw *hw,\n+\t\t\tuint32_t *msg,\n+\t\t\tuint16_t size,\n+\t\t\tenum MBX_ID);\n+\tint32_t (*write)(struct rnp_hw *hw,\n+\t\t\tuint32_t *msg,\n+\t\t\tuint16_t size,\n+\t\t\tenum MBX_ID);\n+\tint32_t (*read_posted)(struct rte_eth_dev *dev,\n+\t\t\tuint32_t *msg,\n+\t\t\tuint16_t size,\n+\t\t\tenum MBX_ID);\n+\tint32_t (*write_posted)(struct rte_eth_dev *dev,\n+\t\t\tuint32_t *msg,\n+\t\t\tuint16_t size,\n+\t\t\tenum MBX_ID);\n+\tint32_t (*check_for_msg)(struct rnp_hw *hw, enum MBX_ID);\n+\tint32_t (*check_for_ack)(struct rnp_hw *hw, enum MBX_ID);\n+\tint32_t (*check_for_rst)(struct rnp_hw *hw, enum MBX_ID);\n+};\n+\n+struct rnp_mbx_stats {\n+\tu32 msgs_tx;\n+\tu32 msgs_rx;\n+\n+\tu32 acks;\n+\tu32 reqs;\n+\tu32 rsts;\n+};\n+\n+struct rnp_mbx_info {\n+\tstruct rnp_mbx_api ops;\n+\tuint32_t usec_delay; /* retry interval delay time */\n+\tuint32_t timeout; /* retry ops timeout limit */\n+\tuint16_t size; /* data buffer size*/\n+\tuint16_t vf_num; /* Virtual Function num */\n+\tuint16_t pf_num; /* Physical Function num */\n+\tuint16_t sriov_st; /* Sriov state */\n+\tbool irq_enabled;\n+\tunion {\n+\t\tstruct {\n+\t\t\tunsigned short pf_req;\n+\t\t\tunsigned short pf_ack;\n+\t\t};\n+\t\tstruct {\n+\t\t\tunsigned short cpu_req;\n+\t\t\tunsigned short cpu_ack;\n+\t\t};\n+\t};\n+\tunsigned short vf_req[64];\n+\tunsigned short vf_ack[64];\n+\n+\tstruct rnp_mbx_stats stats;\n+\n+\trte_atomic16_t state;\n+} __rte_cache_aligned;\n+\n struct rnp_eth_adapter;\n+#define RNP_MAX_HW_PORT_PERR_PF (4)\n struct rnp_hw {\n \tstruct rnp_eth_adapter *back;\n \tvoid *iobar0;\n \tuint32_t iobar0_len;\n \tvoid *iobar4;\n \tuint32_t iobar4_len;\n+\tvoid *link_sync;\n+\tvoid *dma_base;\n+\tvoid *eth_base;\n+\tvoid *veb_base;\n+\tvoid *mac_base[RNP_MAX_HW_PORT_PERR_PF];\n+\tvoid *msix_base;\n+\t/* === dma == */\n+\tvoid *dma_axi_en;\n+\tvoid *dma_axi_st;\n \n \tuint16_t device_id;\n \tuint16_t vendor_id;\n-} __rte_cache_aligned;\n+\tuint16_t function;\n+\tuint16_t pf_vf_num;\n+\tuint16_t max_vfs;\n+\tvoid *cookie_pool;\n+\tchar cookie_p_name[RTE_MEMZONE_NAMESIZE];\n \n+\tstruct rnp_mbx_info mbx;\n+} __rte_cache_aligned;\n #endif /* __RNP_H__*/\ndiff --git a/drivers/net/rnp/meson.build b/drivers/net/rnp/meson.build\nindex f85d597e68..60bba486fc 100644\n--- a/drivers/net/rnp/meson.build\n+++ b/drivers/net/rnp/meson.build\n@@ -8,5 +8,6 @@ endif\n \n sources = files(\n \t\t'rnp_ethdev.c',\n+\t\t'rnp_mbx.c',\n )\n includes += include_directories('base')\ndiff --git a/drivers/net/rnp/rnp.h b/drivers/net/rnp/rnp.h\nindex cab1b8e85d..6e12885877 100644\n--- a/drivers/net/rnp/rnp.h\n+++ b/drivers/net/rnp/rnp.h\n@@ -3,6 +3,7 @@\n */\n #ifndef __RNP_H__\n #define __RNP_H__\n+#include <rte_log.h>\n \n #include \"base/rnp_hw.h\"\n \n@@ -14,14 +15,17 @@\n \n struct rnp_eth_port {\n \tstruct rnp_eth_adapter *adapt;\n+\tstruct rnp_hw *hw;\n \tstruct rte_eth_dev *eth_dev;\n } __rte_cache_aligned;\n \n struct rnp_share_ops {\n+\tconst struct rnp_mbx_api *mbx_api;\n } __rte_cache_aligned;\n \n struct rnp_eth_adapter {\n \tstruct rnp_hw hw;\n+\tuint16_t max_vfs;\n \tstruct rte_pci_device *pdev;\n \tstruct rte_eth_dev *eth_dev; /* primary eth_dev */\n \tstruct rnp_eth_port *ports[RNP_MAX_PORT_OF_PF];\n@@ -34,5 +38,36 @@ struct rnp_eth_adapter {\n \t(((struct rnp_eth_port *)((eth_dev)->data->dev_private)))\n #define RNP_DEV_TO_ADAPTER(eth_dev) \\\n \t((struct rnp_eth_adapter *)(RNP_DEV_TO_PORT(eth_dev)->adapt))\n+#define RNP_DEV_TO_HW(eth_dev) \\\n+\t(&((struct rnp_eth_adapter *)(RNP_DEV_TO_PORT((eth_dev))->adapt))->hw)\n+#define RNP_DEV_PP_PRIV_TO_MBX_OPS(dev) \\\n+\t(((struct rnp_share_ops *)(dev)->process_private)->mbx_api)\n+#define RNP_DEV_TO_MBX_OPS(dev)\tRNP_DEV_PP_PRIV_TO_MBX_OPS(dev)\n \n+static inline void rnp_reg_offset_init(struct rnp_hw *hw)\n+{\n+\tuint16_t i;\n+\n+\tif (hw->device_id == RNP_DEV_ID_N10G && hw->mbx.pf_num) {\n+\t\thw->iobar4 = (void *)((uint8_t *)hw->iobar4 + 0x100000);\n+\t\thw->msix_base = (void *)((uint8_t *)hw->iobar4 + 0xa4000);\n+\t\thw->msix_base = (void *)((uint8_t *)hw->msix_base + 0x200);\n+\t} else {\n+\t\thw->msix_base = (void *)((uint8_t *)hw->iobar4 + 0xa4000);\n+\t}\n+\t/* === dma status/config====== */\n+\thw->link_sync = (void *)((uint8_t *)hw->iobar4 + 0x000c);\n+\thw->dma_axi_en = (void *)((uint8_t *)hw->iobar4 + 0x0010);\n+\thw->dma_axi_st = (void *)((uint8_t *)hw->iobar4 + 0x0014);\n+\n+\tif (hw->mbx.pf_num)\n+\t\thw->msix_base = (void *)((uint8_t *)0x200);\n+\t/* === queue registers === */\n+\thw->dma_base = (void *)((uint8_t *)hw->iobar4 + 0x08000);\n+\thw->veb_base = (void *)((uint8_t *)hw->iobar4 + 0x0);\n+\thw->eth_base = (void *)((uint8_t *)hw->iobar4 + 0x10000);\n+\t/* mac */\n+\tfor (i = 0; i < RNP_MAX_HW_PORT_PERR_PF; i++)\n+\t\thw->mac_base[i] = (void *)((uint8_t *)hw->iobar4 + 0x60000 + 0x10000 * i);\n+}\n #endif /* __RNP_H__ */\ndiff --git a/drivers/net/rnp/rnp_ethdev.c b/drivers/net/rnp/rnp_ethdev.c\nindex ae737643a7..a2dc27548a 100644\n--- a/drivers/net/rnp/rnp_ethdev.c\n+++ b/drivers/net/rnp/rnp_ethdev.c\n@@ -8,6 +8,7 @@\n #include <ethdev_driver.h>\n \n #include \"rnp.h\"\n+#include \"rnp_mbx.h\"\n #include \"rnp_logs.h\"\n \n static int\n@@ -89,6 +90,58 @@ rnp_alloc_eth_port(struct rte_pci_device *primary_pci, char *name)\n \treturn NULL;\n }\n \n+static void rnp_get_nic_attr(struct rnp_eth_adapter *adapter)\n+{\n+\tRTE_SET_USED(adapter);\n+}\n+\n+static int\n+rnp_process_resource_init(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rnp_share_ops *share_priv;\n+\n+\t/* allocate process_private memory this must can't\n+\t * belone to the dpdk mem resource manager\n+\t * such as from rte_malloc or rte_dma_zone..\n+\t */\n+\t/* use the process_prive point to resolve secondary process\n+\t * use point-func. This point is per process will be safe to cover.\n+\t * This will cause secondary process core-dump because of IPC\n+\t * Secondary will call primary process point func virt-address\n+\t * secondary process don't alloc user/pmd to alloc or free\n+\t * the memory of dpdk-mem resource it will cause hugepage\n+\t * mem exception\n+\t * be careful for secondary Process to use the share-mem of\n+\t * point correlation\n+\t */\n+\tshare_priv = calloc(1, sizeof(*share_priv));\n+\tif (!share_priv) {\n+\t\tPMD_DRV_LOG(ERR, \"calloc share_priv failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tmemset(share_priv, 0, sizeof(*share_priv));\n+\teth_dev->process_private = share_priv;\n+\n+\treturn 0;\n+}\n+\n+static void\n+rnp_common_ops_init(struct rnp_eth_adapter *adapter)\n+{\n+\tstruct rnp_share_ops *share_priv;\n+\n+\tshare_priv = adapter->share_priv;\n+\tshare_priv->mbx_api = &rnp_mbx_pf_ops;\n+}\n+\n+static int\n+rnp_special_ops_init(struct rte_eth_dev *eth_dev)\n+{\n+\tRTE_SET_USED(eth_dev);\n+\n+\treturn 0;\n+}\n+\n static int\n rnp_eth_dev_init(struct rte_eth_dev *dev)\n {\n@@ -124,6 +177,20 @@ rnp_eth_dev_init(struct rte_eth_dev *dev)\n \thw->device_id = pci_dev->id.device_id;\n \thw->vendor_id = pci_dev->id.vendor_id;\n \thw->device_id = pci_dev->id.device_id;\n+\tadapter->max_vfs = pci_dev->max_vfs;\n+\tret = rnp_process_resource_init(dev);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"share prive resource init failed\");\n+\t\treturn ret;\n+\t}\n+\tadapter->share_priv = dev->process_private;\n+\trnp_common_ops_init(adapter);\n+\trnp_get_nic_attr(adapter);\n+\t/* We need Use Device Id To Change The Resource Mode */\n+\trnp_special_ops_init(dev);\n+\tport->adapt = adapter;\n+\tport->hw = hw;\n+\trnp_init_mbx_ops_pf(hw);\n \tfor (p_id = 0; p_id < adapter->num_ports; p_id++) {\n \t\t/* port 0 resource has been allocated When Probe */\n \t\tif (!p_id) {\n@@ -158,11 +225,10 @@ rnp_eth_dev_init(struct rte_eth_dev *dev)\n \t\t\tcontinue;\n \t\tif (port->eth_dev) {\n \t\t\trnp_dev_close(port->eth_dev);\n-\t\t\trte_eth_dev_release_port(port->eth_dev);\n \t\t\tif (port->eth_dev->process_private)\n \t\t\t\tfree(port->eth_dev->process_private);\n+\t\t\trte_eth_dev_release_port(port->eth_dev);\n \t\t}\n-\t\trte_free(port);\n \t}\n \trte_free(adapter);\n \ndiff --git a/drivers/net/rnp/rnp_logs.h b/drivers/net/rnp/rnp_logs.h\nindex 1b3ee33745..f1648aabb5 100644\n--- a/drivers/net/rnp/rnp_logs.h\n+++ b/drivers/net/rnp/rnp_logs.h\n@@ -13,6 +13,15 @@ extern int rnp_drv_logtype;\n #define RNP_PMD_DRV_LOG(level, fmt, args...) \\\n \trte_log(RTE_LOG_##level, rnp_drv_logtype, \\\n \t\t\"%s() \" fmt, __func__, ##args)\n+#define PMD_DRV_LOG_RAW(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, rnp_drv_logtype, \"%s(): \" fmt, \\\n+\t\t\t__func__, ## args)\n+#define PMD_DRV_LOG(level, fmt, args...) \\\n+\tPMD_DRV_LOG_RAW(level, fmt \"\\n\", ## args)\n+\n+#define RNP_PMD_LOG(level, fmt, args...) \\\n+\trte_log(RTE_LOG_##level, rnp_drv_logtype, \\\n+\t\t\t\"rnp_net: (%d) \" fmt, __LINE__, ##args)\n #ifdef RTE_LIBRTE_RNP_DEBUG_RX\n extern int rnp_rx_logtype;\n #define RNP_PMD_RX_LOG(level, fmt, args...) \\\ndiff --git a/drivers/net/rnp/rnp_mbx.c b/drivers/net/rnp/rnp_mbx.c\nnew file mode 100644\nindex 0000000000..29aedc554b\n--- /dev/null\n+++ b/drivers/net/rnp/rnp_mbx.c\n@@ -0,0 +1,522 @@\n+#include <rte_cycles.h>\n+#include <rte_log.h>\n+\n+#include \"rnp.h\"\n+#include \"rnp_hw.h\"\n+#include \"rnp_mbx.h\"\n+#include \"rnp_mbx_fw.h\"\n+#include \"rnp_logs.h\"\n+\n+#define RNP_MAX_VF_FUNCTIONS\t(64)\n+/* == VEC == */\n+#define VF2PF_MBOX_VEC(VF)\t(0xa5100 + 4 * (VF))\n+#define CPU2PF_MBOX_VEC\t\t(0xa5300)\n+\n+/* == PF <--> VF mailbox ==== */\n+#define SHARE_MEM_BYTES\t\t(64) /* 64bytes */\n+/* for PF1 rtl will remap 6000 to 0xb000 */\n+#define PF_VF_SHM(vf)\t\t((0xa6000) + (64 * (vf)))\n+#define PF2VF_COUNTER(vf)\t(PF_VF_SHM(vf) + 0)\n+#define VF2PF_COUNTER(vf)\t(PF_VF_SHM(vf) + 4)\n+#define PF_VF_SHM_DATA(vf)\t(PF_VF_SHM(vf) + 8)\n+#define PF2VF_MBOX_CTRL(vf)\t((0xa7100) + (4 * (vf)))\n+#define PF_VF_MBOX_MASK_LO\t((0xa7200))\n+#define PF_VF_MBOX_MASK_HI\t((0xa7300))\n+\n+/* === CPU <--> PF === */\n+#define CPU_PF_SHM\t\t(0xaa000)\n+#define CPU2PF_COUNTER\t\t(CPU_PF_SHM + 0)\n+#define PF2CPU_COUNTER\t\t(CPU_PF_SHM + 4)\n+#define CPU_PF_SHM_DATA\t\t(CPU_PF_SHM + 8)\n+#define PF2CPU_MBOX_CTRL\t(0xaa100)\n+#define CPU_PF_MBOX_MASK\t(0xaa300)\n+\n+/* === CPU <--> VF === */\n+#define CPU_VF_SHM(vf)\t\t(0xa8000 + (64 * (vf)))\n+#define CPU2VF_COUNTER(vf)\t(CPU_VF_SHM(vf) + 0)\n+#define VF2CPU_COUNTER(vf)\t(CPU_VF_SHM(vf) + 4)\n+#define CPU_VF_SHM_DATA(vf)\t(CPU_VF_SHM(vf) + 8)\n+#define VF2CPU_MBOX_CTRL(vf)\t(0xa9000 + 64 * (vf))\n+#define CPU_VF_MBOX_MASK_LO(vf) (0xa9200 + 64 * (vf))\n+#define CPU_VF_MBOX_MASK_HI(vf) (0xa9300 + 64 * (vf))\n+\n+#define MBOX_CTRL_REQ\t\t(1 << 0) /* WO */\n+/* VF:WR, PF:RO */\n+#define MBOX_CTRL_PF_HOLD_SHM\t(1 << 3) /* VF:RO, PF:WR */\n+\n+#define MBOX_IRQ_EN\t\t(0)\n+#define MBOX_IRQ_DISABLE\t(1)\n+\n+/****************************PF MBX OPS************************************/\n+static inline u16 rnp_mbx_get_req(struct rnp_hw *hw, int reg)\n+{\n+\trte_mb();\n+\treturn mbx_rd32(hw, reg) & 0xffff;\n+}\n+\n+static inline u16 rnp_mbx_get_ack(struct rnp_hw *hw, int reg)\n+{\n+\trte_mb();\n+\treturn (mbx_rd32(hw, reg) >> 16) & 0xffff;\n+}\n+\n+static inline void rnp_mbx_inc_pf_req(struct rnp_hw *hw, enum MBX_ID mbx_id)\n+{\n+\tint reg = (mbx_id == MBX_CM3CPU) ?\n+\t\tPF2CPU_COUNTER : PF2VF_COUNTER(mbx_id);\n+\tu32 v = mbx_rd32(hw, reg);\n+\tu16 req;\n+\n+\treq = (v & 0xffff);\n+\treq++;\n+\tv &= ~(0x0000ffff);\n+\tv |= req;\n+\n+\trte_mb();\n+\tmbx_wr32(hw, reg, v);\n+\n+\t/* update stats */\n+\t/* hw->mbx.stats.msgs_tx++; */\n+}\n+\n+static inline void rnp_mbx_inc_pf_ack(struct rnp_hw *hw, enum MBX_ID mbx_id)\n+{\n+\tint reg = (mbx_id == MBX_CM3CPU) ?\n+\t\tPF2CPU_COUNTER : PF2VF_COUNTER(mbx_id);\n+\tu32 v = mbx_rd32(hw, reg);\n+\tu16 ack;\n+\n+\tack = (v >> 16) & 0xffff;\n+\tack++;\n+\tv &= ~(0xffff0000);\n+\tv |= (ack << 16);\n+\n+\trte_mb();\n+\tmbx_wr32(hw, reg, v);\n+\n+\t/* update stats */\n+\t/* hw->mbx.stats.msgs_rx++; */\n+}\n+\n+/**\n+ * rnp_poll_for_msg - Wait for message notification\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: id of mailbox to write\n+ *\n+ * returns SUCCESS if it successfully received a message notification\n+ **/\n+static int32_t rnp_poll_for_msg(struct rte_eth_dev *dev, enum MBX_ID mbx_id)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct rnp_mbx_info *mbx = &hw->mbx;\n+\tint countdown = mbx->timeout;\n+\n+\tif (!countdown || !ops->check_for_msg)\n+\t\tgoto out;\n+\n+\twhile (countdown && ops->check_for_msg(hw, mbx_id)) {\n+\t\tcountdown--;\n+\t\tif (!countdown)\n+\t\t\tbreak;\n+\t\trte_delay_us_block(mbx->usec_delay);\n+\t}\n+\n+out:\n+\treturn countdown ? 0 : -ETIMEDOUT;\n+}\n+\n+/**\n+ * rnp_poll_for_ack - Wait for message acknowledgment\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: id of mailbox to write\n+ *\n+ * returns SUCCESS if it successfully received a message acknowledgment\n+ **/\n+static int32_t rnp_poll_for_ack(struct rte_eth_dev *dev, enum MBX_ID mbx_id)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct rnp_mbx_info *mbx = &hw->mbx;\n+\tint countdown = mbx->timeout;\n+\n+\tif (!countdown || !ops->check_for_ack)\n+\t\tgoto out;\n+\n+\twhile (countdown && ops->check_for_ack(hw, mbx_id)) {\n+\t\tcountdown--;\n+\t\tif (!countdown)\n+\t\t\tbreak;\n+\t\trte_delay_us_block(mbx->usec_delay);\n+\t}\n+\n+out:\n+\treturn countdown ? 0 : -ETIMEDOUT;\n+}\n+\n+/**\n+ * rnp_read_posted_mbx - Wait for message notification and receive message\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @mbx_id: id of mailbox to write\n+ *\n+ * returns SUCCESS if it successfully received a message notification and\n+ * copied it into the receive buffer.\n+ **/\n+static int32_t\n+rnp_read_posted_mbx_pf(struct rte_eth_dev *dev, u32 *msg, u16 size,\n+\t\t enum MBX_ID mbx_id)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct rnp_mbx_info *mbx = &hw->mbx;\n+\tint countdown = mbx->timeout;\n+\tint32_t ret_val = -ETIMEDOUT;\n+\n+\tif (!ops->read || !countdown)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tret_val = rnp_poll_for_msg(dev, mbx_id);\n+\n+\t/* if ack received read message, otherwise we timed out */\n+\tif (!ret_val)\n+\t\treturn ops->read(hw, msg, size, mbx_id);\n+\treturn ret_val;\n+}\n+\n+/**\n+ * rnp_write_posted_mbx - Write a message to the mailbox, wait for ack\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @mbx_id: id of mailbox to write\n+ *\n+ * returns SUCCESS if it successfully copied message into the buffer and\n+ * received an ack to that message within delay * timeout period\n+ **/\n+static int32_t\n+rnp_write_posted_mbx_pf(struct rte_eth_dev *dev, u32 *msg, u16 size,\n+\t\t\tenum MBX_ID mbx_id)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct rnp_mbx_info *mbx = &hw->mbx;\n+\tint32_t ret_val = -ETIMEDOUT;\n+\n+\t/* exit if either we can't write or there isn't a defined timeout */\n+\tif (!ops->write || !mbx->timeout)\n+\t\tgoto out;\n+\n+\t/* send msg and hold buffer lock */\n+\tif (ops->write)\n+\t\tret_val = ops->write(hw, msg, size, mbx_id);\n+\n+\t/* if msg sent wait until we receive an ack */\n+\tif (!ret_val)\n+\t\tret_val = rnp_poll_for_ack(dev, mbx_id);\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ * rnp_check_for_msg_pf - checks to see if the VF has sent mail\n+ * @hw: pointer to the HW structure\n+ * @vf_number: the VF index\n+ *\n+ * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n+ **/\n+static int32_t rnp_check_for_msg_pf(struct rnp_hw *hw, enum MBX_ID mbx_id)\n+{\n+\tint32_t ret_val = -ETIMEDOUT;\n+\n+\tif (mbx_id == MBX_CM3CPU) {\n+\t\tif (rnp_mbx_get_req(hw, CPU2PF_COUNTER) != hw->mbx.cpu_req) {\n+\t\t\tret_val = 0;\n+\t\t\t/* hw->mbx.stats.reqs++; */\n+\t\t}\n+\t} else {\n+\t\tif (rnp_mbx_get_req(hw, VF2PF_COUNTER(mbx_id)) !=\n+\t\t\t\thw->mbx.vf_req[mbx_id]) {\n+\t\t\tret_val = 0;\n+\t\t\t/* hw->mbx.stats.reqs++; */\n+\t\t}\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * rnp_check_for_ack_pf - checks to see if the VF has ACKed\n+ * @hw: pointer to the HW structure\n+ * @vf_number: the VF index\n+ *\n+ * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n+ **/\n+static int32_t rnp_check_for_ack_pf(struct rnp_hw *hw, enum MBX_ID mbx_id)\n+{\n+\tint32_t ret_val = -ETIMEDOUT;\n+\n+\tif (mbx_id == MBX_CM3CPU) {\n+\t\tif (rnp_mbx_get_ack(hw, CPU2PF_COUNTER) != hw->mbx.cpu_ack) {\n+\t\t\tret_val = 0;\n+\t\t\t/* hw->mbx.stats.acks++; */\n+\t\t}\n+\t} else {\n+\t\tif (rnp_mbx_get_ack(hw, VF2PF_COUNTER(mbx_id)) != hw->mbx.vf_ack[mbx_id]) {\n+\t\t\tret_val = 0;\n+\t\t\t/* hw->mbx.stats.acks++; */\n+\t\t}\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * rnp_obtain_mbx_lock_pf - obtain mailbox lock\n+ * @hw: pointer to the HW structure\n+ * @mbx_id: the VF index or CPU\n+ *\n+ * return SUCCESS if we obtained the mailbox lock\n+ **/\n+static int32_t rnp_obtain_mbx_lock_pf(struct rnp_hw *hw, enum MBX_ID mbx_id)\n+{\n+\tint32_t ret_val = -ETIMEDOUT;\n+\tint try_cnt = 5000; /* 500ms */\n+\tu32 CTRL_REG = (mbx_id == MBX_CM3CPU) ?\n+\t\tPF2CPU_MBOX_CTRL : PF2VF_MBOX_CTRL(mbx_id);\n+\n+\twhile (try_cnt-- > 0) {\n+\t\t/* Take ownership of the buffer */\n+\t\tmbx_wr32(hw, CTRL_REG, MBOX_CTRL_PF_HOLD_SHM);\n+\n+\t\t/* reserve mailbox for cm3 use */\n+\t\tif (mbx_rd32(hw, CTRL_REG) & MBOX_CTRL_PF_HOLD_SHM)\n+\t\t\treturn 0;\n+\t\trte_delay_us_block(100);\n+\t}\n+\n+\tRNP_PMD_LOG(WARNING, \"%s: failed to get:%d lock\\n\",\n+\t\t\t__func__, mbx_id);\n+\treturn ret_val;\n+}\n+\n+/**\n+ * rnp_write_mbx_pf - Places a message in the mailbox\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @mbx_id: the VF index\n+ *\n+ * returns SUCCESS if it successfully copied message into the buffer\n+ **/\n+static int32_t rnp_write_mbx_pf(struct rnp_hw *hw, u32 *msg,\n+\t\t\t\tu16 size, enum MBX_ID mbx_id)\n+{\n+\tu32 DATA_REG = (mbx_id == MBX_CM3CPU) ?\n+\t\tCPU_PF_SHM_DATA : PF_VF_SHM_DATA(mbx_id);\n+\tu32 CTRL_REG = (mbx_id == MBX_CM3CPU) ?\n+\t\tPF2CPU_MBOX_CTRL : PF2VF_MBOX_CTRL(mbx_id);\n+\tint32_t ret_val = 0;\n+\tu32 stat __rte_unused;\n+\tu16 i;\n+\n+\tif (size > RNP_VFMAILBOX_SIZE) {\n+\t\tRNP_PMD_LOG(ERR, \"%s: size:%d should <%d\\n\", __func__,\n+\t\t\t\tsize, RNP_VFMAILBOX_SIZE);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* lock the mailbox to prevent pf/vf/cpu race condition */\n+\tret_val = rnp_obtain_mbx_lock_pf(hw, mbx_id);\n+\tif (ret_val) {\n+\t\tRNP_PMD_LOG(WARNING, \"PF[%d] Can't Get Mbx-Lock Try Again\\n\",\n+\t\t\t\thw->function);\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* copy the caller specified message to the mailbox memory buffer */\n+\tfor (i = 0; i < size; i++) {\n+#ifdef MBX_WR_DEBUG\n+\t\tmbx_pwr32(hw, DATA_REG + i * 4, msg[i]);\n+#else\n+\t\tmbx_wr32(hw, DATA_REG + i * 4, msg[i]);\n+#endif\n+\t}\n+\n+\t/* flush msg and acks as we are overwriting the message buffer */\n+\tif (mbx_id == MBX_CM3CPU)\n+\t\thw->mbx.cpu_ack = rnp_mbx_get_ack(hw, CPU2PF_COUNTER);\n+\telse\n+\t\thw->mbx.vf_ack[mbx_id] = rnp_mbx_get_ack(hw, VF2PF_COUNTER(mbx_id));\n+\n+\trnp_mbx_inc_pf_req(hw, mbx_id);\n+\trte_mb();\n+\n+\trte_delay_us(300);\n+\n+\t/* Interrupt VF/CM3 to tell it a message\n+\t * has been sent and release buffer\n+\t */\n+\tmbx_wr32(hw, CTRL_REG, MBOX_CTRL_REQ);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * rnp_read_mbx_pf - Read a message from the mailbox\n+ * @hw: pointer to the HW structure\n+ * @msg: The message buffer\n+ * @size: Length of buffer\n+ * @vf_number: the VF index\n+ *\n+ * This function copies a message from the mailbox buffer to the caller's\n+ * memory buffer. The presumption is that the caller knows that there was\n+ * a message due to a VF/CPU request so no polling for message is needed.\n+ **/\n+static int32_t rnp_read_mbx_pf(struct rnp_hw *hw, u32 *msg,\n+\t\t\t u16 size, enum MBX_ID mbx_id)\n+{\n+\tu32 BUF_REG = (mbx_id == MBX_CM3CPU) ?\n+\t\tCPU_PF_SHM_DATA : PF_VF_SHM_DATA(mbx_id);\n+\tu32 CTRL_REG = (mbx_id == MBX_CM3CPU) ?\n+\t\tPF2CPU_MBOX_CTRL : PF2VF_MBOX_CTRL(mbx_id);\n+\tint32_t ret_val = -EIO;\n+\tu32 stat __rte_unused, i;\n+\tif (size > RNP_VFMAILBOX_SIZE) {\n+\t\tRNP_PMD_LOG(ERR, \"%s: size:%d should <%d\\n\", __func__,\n+\t\t\t\tsize, RNP_VFMAILBOX_SIZE);\n+\t\treturn -EINVAL;\n+\t}\n+\t/* lock the mailbox to prevent pf/vf race condition */\n+\tret_val = rnp_obtain_mbx_lock_pf(hw, mbx_id);\n+\tif (ret_val)\n+\t\tgoto out_no_read;\n+\n+\t/* copy the message from the mailbox memory buffer */\n+\tfor (i = 0; i < size; i++) {\n+#ifdef MBX_RD_DEBUG\n+\t\tmsg[i] = mbx_prd32(hw, BUF_REG + 4 * i);\n+#else\n+\t\tmsg[i] = mbx_rd32(hw, BUF_REG + 4 * i);\n+#endif\n+\t}\n+\tmbx_wr32(hw, BUF_REG, 0);\n+\n+\t/* update req. used by rnpvf_check_for_msg_vf */\n+\tif (mbx_id == MBX_CM3CPU)\n+\t\thw->mbx.cpu_req = rnp_mbx_get_req(hw, CPU2PF_COUNTER);\n+\telse\n+\t\thw->mbx.vf_req[mbx_id] = rnp_mbx_get_req(hw, VF2PF_COUNTER(mbx_id));\n+\n+\t/* this ack maybe too earier? */\n+\t/* Acknowledge receipt and release mailbox, then we're done */\n+\trnp_mbx_inc_pf_ack(hw, mbx_id);\n+\n+\trte_mb();\n+\n+\t/* free ownership of the buffer */\n+\tmbx_wr32(hw, CTRL_REG, 0);\n+\n+out_no_read:\n+\n+\treturn ret_val;\n+}\n+\n+static void rnp_mbx_reset_pf(struct rnp_hw *hw)\n+{\n+\tint v;\n+\n+\t/* reset pf->cm3 status */\n+\tv = mbx_rd32(hw, CPU2PF_COUNTER);\n+\thw->mbx.cpu_req = v & 0xffff;\n+\thw->mbx.cpu_ack = (v >> 16) & 0xffff;\n+\t/* release pf->cm3 buffer lock */\n+\tmbx_wr32(hw, PF2CPU_MBOX_CTRL, 0);\n+\n+\trte_mb();\n+\t/* enable irq to fw */\n+\tmbx_wr32(hw, CPU_PF_MBOX_MASK, 0);\n+}\n+\n+static int get_pfvfnum(struct rnp_hw *hw)\n+{\n+\tuint32_t addr_mask;\n+\tuint32_t offset;\n+\tuint32_t val;\n+#define RNP_PF_NUM_REG (0x75f000)\n+#define RNP_PFVF_SHIFT (4)\n+#define RNP_PF_SHIFT (6)\n+#define RNP_PF_BIT_MASK BIT(6)\n+\taddr_mask = hw->iobar0_len - 1;\n+\toffset = RNP_PF_NUM_REG & addr_mask;\n+\tval = rnp_io_rd(hw->iobar0, offset);\n+\n+\treturn val >> RNP_PFVF_SHIFT;\n+}\n+\n+const struct rnp_mbx_api rnp_mbx_pf_ops = {\n+\t.read = rnp_read_mbx_pf,\n+\t.write = rnp_write_mbx_pf,\n+\t.read_posted = rnp_read_posted_mbx_pf,\n+\t.write_posted = rnp_write_posted_mbx_pf,\n+\t.check_for_msg = rnp_check_for_msg_pf,\n+\t.check_for_ack = rnp_check_for_ack_pf,\n+};\n+\n+void *rnp_memzone_reserve(const char *name, unsigned int size)\n+{\n+#define NO_FLAGS 0\n+\tconst struct rte_memzone *mz = NULL;\n+\n+\tif (name) {\n+\t\tif (size) {\n+\t\t\tmz = rte_memzone_reserve(name, size,\n+\t\t\t\t\trte_socket_id(), NO_FLAGS);\n+\t\t\tif (mz)\n+\t\t\t\tmemset(mz->addr, 0, size);\n+\t\t} else {\n+\t\t\tmz = rte_memzone_lookup(name);\n+\t\t}\n+\t\treturn mz ? mz->addr : NULL;\n+\t}\n+\treturn NULL;\n+}\n+\n+void rnp_init_mbx_ops_pf(struct rnp_hw *hw)\n+{\n+\tstruct rnp_eth_adapter *adapter = hw->back;\n+\tstruct rnp_mbx_info *mbx = &hw->mbx;\n+\tstruct mbx_req_cookie *cookie;\n+\tuint32_t vf_isolat_off;\n+\n+\tmbx->size = RNP_VFMAILBOX_SIZE;\n+\tmbx->usec_delay = RNP_MBX_DELAY_US;\n+\tmbx->timeout = (RNP_MBX_TIMEOUT_SECONDS * 1000 * 1000) /\n+\t\tmbx->usec_delay;\n+\tif (hw->device_id == RNP_DEV_ID_N10G) {\n+\t\tvf_isolat_off = RNP_VF_ISOLATE_CTRL &\n+\t\t\t(hw->iobar0_len - 1);\n+\t\trnp_io_wr(hw->iobar0, vf_isolat_off, 0);\n+\t}\n+\tmbx->sriov_st = 0;\n+\thw->pf_vf_num = get_pfvfnum(hw);\n+\tmbx->vf_num = UINT16_MAX;\n+\tmbx->pf_num = (hw->pf_vf_num & RNP_PF_BIT_MASK) >> RNP_PF_SHIFT;\n+\thw->function = mbx->pf_num;\n+\t/* Retrieving and storing the HW base address of device */\n+\trnp_reg_offset_init(hw);\n+\tsnprintf(hw->cookie_p_name, RTE_MEMZONE_NAMESIZE, \"mbx_req_cookie%d_%d\",\n+\t\t\thw->function, adapter->eth_dev->data->port_id);\n+\thw->cookie_pool = rnp_memzone_reserve(hw->cookie_p_name,\n+\t\t\tsizeof(struct mbx_req_cookie));\n+\n+\tcookie = (struct mbx_req_cookie *)hw->cookie_pool;\n+\tif (cookie) {\n+\t\tcookie->timeout_ms = 1000;\n+\t\tcookie->magic = COOKIE_MAGIC;\n+\t\tcookie->priv_len = RNP_MAX_SHARE_MEM;\n+\t}\n+\n+\trnp_mbx_reset_pf(hw);\n+}\ndiff --git a/drivers/net/rnp/rnp_mbx.h b/drivers/net/rnp/rnp_mbx.h\nnew file mode 100644\nindex 0000000000..87949c1726\n--- /dev/null\n+++ b/drivers/net/rnp/rnp_mbx.h\n@@ -0,0 +1,139 @@\n+#ifndef __TSRN10_MBX_H__\n+#define __TSRN10_MBX_H__\n+\n+#define VF_NUM_MASK_TEMP\t(0xff0)\n+#define VF_NUM_OFF\t\t(4)\n+#define RNP_VF_NUM\t\t(0x75f000)\n+#define RNP_VF_NB_MASK\t\t(0x3f)\n+#define RNP_PF_NB_MASK\t\t(0x40)\n+#define RNP_VF_ISOLATE_CTRL\t(0x7982fc)\n+#define RNP_IS_SRIOV\t\tBIT(7)\n+#define RNP_SRIOV_ST_SHIFT\t(24)\n+#define RNP_VF_DEFAULT_PORT\t(0)\n+\n+/* Mbx Ctrl state */\n+#define RNP_VFMAILBOX_SIZE\t(14) /* 16 32 bit words - 64 bytes */\n+#define TSRN10_VFMBX_SIZE\t(RNP_VFMAILBOX_SIZE)\n+#define RNP_VT_MSGTYPE_ACK\t(0x80000000)\n+\n+#define RNP_VT_MSGTYPE_NACK\t(0x40000000)\n+/* Messages below or'd with * this are the NACK */\n+#define RNP_VT_MSGTYPE_CTS\t(0x20000000)\n+/* Indicates that VF is still\n+ *clear to send requests\n+ */\n+#define RNP_VT_MSGINFO_SHIFT\t(16)\n+\n+#define RNP_VT_MSGINFO_MASK\t(0xFF << RNP_VT_MSGINFO_SHIFT)\n+/* The mailbox memory size is 64 bytes accessed by 32-bit registers */\n+#define RNP_VLVF_VIEN\t\t(0x80000000) /* filter is valid */\n+#define RNP_VLVF_ENTRIES\t(64)\n+#define RNP_VLVF_VLANID_MASK\t(0x00000FFF)\n+/* Every VF own 64 bytes mem for communitate accessed by 32-bit */\n+\n+#define RNP_VF_RESET\t\t(0x01) /* VF requests reset */\n+#define RNP_VF_SET_MAC_ADDR\t(0x02) /* VF requests PF to set MAC addr */\n+#define RNP_VF_SET_MULTICAST\t(0x03) /* VF requests PF to set MC addr */\n+#define RNP_VF_SET_VLAN\t\t(0x04) /* VF requests PF to set VLAN */\n+\n+#define RNP_VF_SET_LPE\t\t(0x05) /* VF requests PF to set VMOLR.LPE */\n+#define RNP_VF_SET_MACVLAN\t(0x06) /* VF requests PF for unicast filter */\n+#define RNP_VF_GET_MACVLAN\t(0x07) /* VF requests mac */\n+#define RNP_VF_API_NEGOTIATE\t(0x08) /* negotiate API version */\n+#define RNP_VF_GET_QUEUES\t(0x09) /* get queue configuration */\n+#define RNP_VF_GET_LINK\t\t(0x10) /* get link status */\n+\n+#define RNP_VF_SET_VLAN_STRIP\t(0x0a) /* VF Requests PF to set VLAN STRIP */\n+#define RNP_VF_REG_RD\t\t(0x0b) /* VF Read Reg */\n+#define RNP_VF_GET_MAX_MTU\t(0x0c) /* VF Get Max Mtu */\n+#define RNP_VF_SET_MTU\t\t(0x0d) /* VF Set Mtu */\n+#define RNP_VF_GET_FW\t\t(0x0e) /* VF Get Firmware Version */\n+\n+#define RNP_PF_VFNUM_MASK\tGENMASK(26, 21)\n+\n+#define RNP_PF_SET_FCS\t\t(0x10) /* PF set fcs status */\n+#define RNP_PF_SET_PAUSE\t(0x11) /* PF set pause status */\n+#define RNP_PF_SET_FT_PADDING\t(0x12) /* PF set ft padding status */\n+#define RNP_PF_SET_VLAN_FILTER\t(0x13) /* PF set ntuple status */\n+#define RNP_PF_SET_VLAN\t\t(0x14)\n+#define RNP_PF_SET_LINK\t\t(0x15)\n+#define RNP_PF_SET_SPEED_40G\tBIT(8)\n+#define RNP_PF_SET_SPEED_10G\tBIT(7)\n+#define RNP_PF_SET_SPEED_1G\tBIT(5)\n+#define RNP_PF_SET_SPEED_100M\tBIT(3)\n+\n+#define RNP_PF_SET_MTU\t\t(0x16)\n+#define RNP_PF_SET_RESET\t(0x17)\n+#define RNP_PF_LINK_UP\t\tBIT(31)\n+#define RNP_PF_SPEED_MASK\tGENMASK(15, 0)\n+\n+/* Define mailbox register bits */\n+#define RNP_PF_REMOVE\t\t(0x0f)\n+\n+/* Mailbox API ID VF Request */\n+/* length of permanent address message returned from PF */\n+#define RNP_VF_PERMADDR_MSG_LEN (11)\n+#define RNP_VF_TX_QUEUES\t(1) /* number of Tx queues supported */\n+#define RNP_VF_RX_QUEUES\t(2) /* number of Rx queues supported */\n+#define RNP_VF_TRANS_VLAN\t(3) /* Indication of port vlan */\n+#define RNP_VF_DEF_QUEUE\t(4) /* Default queue offset */\n+/* word in permanent address message with the current multicast type */\n+#define RNP_VF_VLAN_WORD\t(5)\n+#define RNP_VF_PHY_TYPE_WORD\t(6)\n+#define RNP_VF_FW_VERSION_WORD\t(7)\n+#define RNP_VF_LINK_STATUS_WORD\t(8)\n+#define RNP_VF_AXI_MHZ\t\t(9)\n+#define RNP_VF_RNP_VF_FEATURE\t(10)\n+#define RNP_VF_RNP_VF_FILTER_EN\tBIT(0)\n+\n+#define RNP_LINK_SPEED_UNKNOWN 0\n+#define RNP_LINK_SPEED_10_FULL BIT(2)\n+#define RNP_LINK_SPEED_100_FULL BIT(3)\n+#define RNP_LINK_SPEED_1GB_FULL BIT(4)\n+#define RNP_LINK_SPEED_10GB_FULL BIT(5)\n+#define RNP_LINK_SPEED_40GB_FULL BIT(6)\n+#define RNP_LINK_SPEED_25GB_FULL BIT(7)\n+#define RNP_LINK_SPEED_50GB_FULL BIT(8)\n+#define RNP_LINK_SPEED_100GB_FULL BIT(9)\n+#define RNP_LINK_SPEED_10_HALF BIT(10)\n+#define RNP_LINK_SPEED_100_HALF BIT(11)\n+#define RNP_LINK_SPEED_1GB_HALF BIT(12)\n+\n+/* Mailbox API ID PF Request */\n+#define RNP_VF_MC_TYPE_WORD\t\t(3)\n+#define RNP_VF_DMA_VERSION_WORD\t\t(4)\n+/* Get Queue write-back reference value */\n+#define RNP_PF_CONTROL_PRING_MSG\t(0x0100) /* PF control message */\n+\n+#define TSRN10_MBX_VECTOR_ID (0)\n+#define TSRN10_PF2VF_MBX_VEC_CTR(n) (0xa5000 + 0x4 * (n))\n+\n+#define RNP_VF_INIT_TIMEOUT\t\t(200) /* Number of retries to clear RSTI */\n+#define RNP_VF_MBX_INIT_TIMEOUT\t\t(2000) /* number of retries on mailbox */\n+\n+#define MBOX_CTRL_REQ\t\t\t(1 << 0) /* WO */\n+#define MBOX_CTRL_VF_HOLD_SHM\t\t(1 << 2) /* VF:WR, PF:RO */\n+#define VF_NUM_MASK 0x3f\n+#define VFNUM(num)\t\t\t((num) & VF_NUM_MASK)\n+\n+#define PF_VF_SHM(vf)\t\\\n+\t((0xa6000) + (64 * (vf))) /* for PF1 rtl will remap 6000 to 0xb000 */\n+#define PF2VF_COUNTER(vf)\t\t(PF_VF_SHM(vf) + 0)\n+#define VF2PF_COUNTER(vf)\t\t(PF_VF_SHM(vf) + 4)\n+#define PF_VF_SHM_DATA(vf)\t\t(PF_VF_SHM(vf) + 8)\n+#define VF2PF_MBOX_CTRL(vf)\t\t((0xa7000) + (4 * (vf)))\n+\n+/* Error Codes */\n+#define RNP_ERR_INVALID_MAC_ADDR\t(-1)\n+#define RNP_ERR_MBX\t\t\t(-100)\n+\n+#define RNP_MBX_DELAY_US\t\t(100) /* Delay us for Retry */\n+/* Max Retry Time */\n+#define RNP_MBX_TIMEOUT_SECONDS\t(2) /* Max Retry Time 2s */\n+#define RNP_ARRAY_OPCODE_OFFSET\t(0)\n+#define RNP_ARRAY_CTRL_OFFSET\t(1)\n+\n+void rnp_init_mbx_ops_pf(struct rnp_hw *hw);\n+extern const struct rnp_mbx_api rnp_mbx_pf_ops;\n+void *rnp_memzone_reserve(const char *name, unsigned int size);\n+#endif\ndiff --git a/drivers/net/rnp/rnp_mbx_fw.c b/drivers/net/rnp/rnp_mbx_fw.c\nnew file mode 100644\nindex 0000000000..6fe008351b\n--- /dev/null\n+++ b/drivers/net/rnp/rnp_mbx_fw.c\n@@ -0,0 +1,271 @@\n+#include <stdio.h>\n+\n+#include <rte_version.h>\n+#include <ethdev_pci.h>\n+#include <rte_malloc.h>\n+#include <rte_alarm.h>\n+\n+#include \"rnp.h\"\n+#include \"rnp_mbx.h\"\n+#include \"rnp_mbx_fw.h\"\n+#include \"rnp_logs.h\"\n+\n+static int\n+rnp_fw_send_cmd_wait(struct rte_eth_dev *dev, struct mbx_fw_cmd_req *req,\n+\t\t struct mbx_fw_cmd_reply *reply)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tint err;\n+\n+\trte_spinlock_lock(&hw->fw_lock);\n+\n+\terr = ops->write_posted(dev, (u32 *)req,\n+\t\t\t(req->datalen + MBX_REQ_HDR_LEN) / 4, MBX_FW);\n+\tif (err) {\n+\t\tRNP_PMD_LOG(ERR, \"%s: write_posted failed! err:0x%x\\n\",\n+\t\t\t\t__func__, err);\n+\t\trte_spinlock_unlock(&hw->fw_lock);\n+\t\treturn err;\n+\t}\n+\n+\terr = ops->read_posted(dev, (u32 *)reply, sizeof(*reply) / 4, MBX_FW);\n+\trte_spinlock_unlock(&hw->fw_lock);\n+\tif (err) {\n+\t\tRNP_PMD_LOG(ERR,\n+\t\t\t\t\"%s: read_posted failed! err:0x%x. \"\n+\t\t\t\t\"req-op:0x%x\\n\",\n+\t\t\t\t__func__,\n+\t\t\t\terr,\n+\t\t\t\treq->opcode);\n+\t\tgoto err_quit;\n+\t}\n+\n+\tif (reply->error_code) {\n+\t\tRNP_PMD_LOG(ERR,\n+\t\t\t\t\"%s: reply err:0x%x. req-op:0x%x\\n\",\n+\t\t\t\t__func__,\n+\t\t\t\treply->error_code,\n+\t\t\t\treq->opcode);\n+\t\terr = -reply->error_code;\n+\t\tgoto err_quit;\n+\t}\n+\n+\treturn 0;\n+err_quit:\n+\tRNP_PMD_LOG(ERR,\n+\t\t\t\"%s:PF[%d]: req:%08x_%08x_%08x_%08x \"\n+\t\t\t\"reply:%08x_%08x_%08x_%08x\\n\",\n+\t\t\t__func__,\n+\t\t\thw->function,\n+\t\t\t((int *)req)[0],\n+\t\t\t((int *)req)[1],\n+\t\t\t((int *)req)[2],\n+\t\t\t((int *)req)[3],\n+\t\t\t((int *)reply)[0],\n+\t\t\t((int *)reply)[1],\n+\t\t\t((int *)reply)[2],\n+\t\t\t((int *)reply)[3]);\n+\n+\treturn err;\n+}\n+\n+static int rnp_mbx_fw_post_req(struct rte_eth_dev *dev,\n+\t\t\t struct mbx_fw_cmd_req *req,\n+\t\t\t struct mbx_req_cookie *cookie)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tint err = 0;\n+\tint timeout_cnt;\n+#define WAIT_MS 10\n+\n+\tcookie->done = 0;\n+\n+\trte_spinlock_lock(&hw->fw_lock);\n+\n+\t/* down_interruptible(&pf_cpu_lock); */\n+\terr = ops->write(hw, (u32 *)req,\n+\t\t\t(req->datalen + MBX_REQ_HDR_LEN) / 4, MBX_FW);\n+\tif (err) {\n+\t\tRNP_PMD_LOG(ERR, \"rnp_write_mbx failed!\\n\");\n+\t\tgoto quit;\n+\t}\n+\n+\ttimeout_cnt = cookie->timeout_ms / WAIT_MS;\n+\twhile (timeout_cnt > 0) {\n+\t\trte_delay_ms(WAIT_MS);\n+\t\ttimeout_cnt--;\n+\t\tif (cookie->done)\n+\t\t\tbreak;\n+\t}\n+\n+quit:\n+\trte_spinlock_unlock(&hw->fw_lock);\n+\treturn err;\n+}\n+\n+static int rnp_fw_get_capablity(struct rte_eth_dev *dev,\n+\t\t\t\tstruct phy_abilities *abil)\n+{\n+\tstruct mbx_fw_cmd_reply reply;\n+\tstruct mbx_fw_cmd_req req;\n+\tint err;\n+\n+\tmemset(&req, 0, sizeof(req));\n+\tmemset(&reply, 0, sizeof(reply));\n+\n+\tbuild_phy_abalities_req(&req, &req);\n+\n+\terr = rnp_fw_send_cmd_wait(dev, &req, &reply);\n+\tif (err)\n+\t\treturn err;\n+\n+\tmemcpy(abil, &reply.phy_abilities, sizeof(*abil));\n+\n+\treturn 0;\n+}\n+\n+#define RNP_MBX_API_MAX_RETRY (10)\n+int rnp_mbx_get_capability(struct rte_eth_dev *dev,\n+\t\t\t int *lane_mask,\n+\t\t\t int *nic_mode)\n+{\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct phy_abilities ablity;\n+\tuint16_t temp_lmask;\n+\tuint16_t lane_bit = 0;\n+\tuint16_t retry = 0;\n+\tint lane_cnt = 0;\n+\tuint8_t lane_idx;\n+\tint err = -EIO;\n+\tuint8_t idx;\n+\n+\tmemset(&ablity, 0, sizeof(ablity));\n+\n+\t/* enable CM3CPU to PF MBX IRQ */\n+\tdo {\n+\t\terr = rnp_fw_get_capablity(dev, &ablity);\n+\t\tif (retry > RNP_MBX_API_MAX_RETRY)\n+\t\t\tbreak;\n+\t\tretry++;\n+\t} while (err);\n+\tif (!err) {\n+\t\thw->lane_mask = ablity.lane_mask;\n+\t\thw->nic_mode = ablity.nic_mode;\n+\t\thw->pfvfnum = ablity.pfnum;\n+\t\thw->fw_version = ablity.fw_version;\n+\t\thw->axi_mhz = ablity.axi_mhz;\n+\t\thw->fw_uid = ablity.fw_uid;\n+\t\tif (ablity.phy_type == PHY_TYPE_SGMII) {\n+\t\t\thw->is_sgmii = 1;\n+\t\t\thw->sgmii_phy_id = ablity.phy_id;\n+\t\t}\n+\n+\t\tif (ablity.ext_ablity != 0xffffffff && ablity.e.valid) {\n+\t\t\thw->ncsi_en = (ablity.e.ncsi_en == 1);\n+\t\t\thw->ncsi_rar_entries = 1;\n+\t\t}\n+\n+\t\tif (hw->nic_mode == RNP_SINGLE_10G &&\n+\t\t\t\thw->fw_version >= 0x00050201 &&\n+\t\t\t\tablity.speed == RTE_ETH_SPEED_NUM_10G) {\n+\t\t\thw->force_speed_stat = FORCE_SPEED_STAT_DISABLED;\n+\t\t\thw->force_10g_1g_speed_ablity = 1;\n+\t\t}\n+\n+\t\tif (lane_mask)\n+\t\t\t*lane_mask = hw->lane_mask;\n+\t\tif (nic_mode)\n+\t\t\t*nic_mode = hw->nic_mode;\n+\n+\t\tlane_cnt = __builtin_popcount(hw->lane_mask);\n+\t\ttemp_lmask = hw->lane_mask;\n+\t\tfor (idx = 0; idx < lane_cnt; idx++) {\n+\t\t\thw->phy_port_ids[idx] = ablity.port_ids[idx];\n+\t\t\tlane_bit = ffs(temp_lmask) - 1;\n+\t\t\tlane_idx = ablity.port_ids[idx] % lane_cnt;\n+\t\t\thw->lane_of_port[lane_idx] = lane_bit;\n+\t\t\ttemp_lmask &= ~BIT(lane_bit);\n+\t\t}\n+\t\thw->max_port_num = lane_cnt;\n+\t}\n+\n+\tRNP_PMD_LOG(INFO,\n+\t\t\t\"%s: nic-mode:%d lane_cnt:%d lane_mask:0x%x \"\n+\t\t\t\"pfvfnum:0x%x, fw_version:0x%08x, ports:%d-%d-%d-%d ncsi:en:%d\\n\",\n+\t\t\t__func__,\n+\t\t\thw->nic_mode,\n+\t\t\tlane_cnt,\n+\t\t\thw->lane_mask,\n+\t\t\thw->pfvfnum,\n+\t\t\tablity.fw_version,\n+\t\t\tablity.port_ids[0],\n+\t\t\tablity.port_ids[1],\n+\t\t\tablity.port_ids[2],\n+\t\t\tablity.port_ids[3],\n+\t\t\thw->ncsi_en);\n+\n+\tif (lane_cnt <= 0 || lane_cnt > 4)\n+\t\treturn -EIO;\n+\n+\treturn err;\n+}\n+\n+int rnp_mbx_link_event_enable(struct rte_eth_dev *dev, int enable)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct mbx_fw_cmd_reply reply;\n+\tstruct mbx_fw_cmd_req req;\n+\tint err, v;\n+\n+\tmemset(&req, 0, sizeof(req));\n+\tmemset(&reply, 0, sizeof(reply));\n+\n+\trte_spinlock_lock(&hw->fw_lock);\n+\tif (enable) {\n+\t\tv = rnp_rd_reg(hw->link_sync);\n+\t\tv &= ~RNP_FIRMWARE_SYNC_MASK;\n+\t\tv |= RNP_FIRMWARE_SYNC_MAGIC;\n+\t\trnp_wr_reg(hw->link_sync, v);\n+\t} else {\n+\t\trnp_wr_reg(hw->link_sync, 0);\n+\t}\n+\trte_spinlock_unlock(&hw->fw_lock);\n+\n+\tbuild_link_set_event_mask(&req, BIT(EVT_LINK_UP),\n+\t\t\t(enable & 1) << EVT_LINK_UP, &req);\n+\n+\trte_spinlock_lock(&hw->fw_lock);\n+\terr = ops->write_posted(dev, (u32 *)&req,\n+\t\t\t(req.datalen + MBX_REQ_HDR_LEN) / 4, MBX_FW);\n+\trte_spinlock_unlock(&hw->fw_lock);\n+\n+\trte_delay_ms(200);\n+\n+\treturn err;\n+}\n+\n+int rnp_mbx_fw_reset_phy(struct rte_eth_dev *dev)\n+{\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct mbx_fw_cmd_reply reply;\n+\tstruct mbx_req_cookie *cookie;\n+\tstruct mbx_fw_cmd_req req;\n+\n+\tmemset(&req, 0, sizeof(req));\n+\tmemset(&reply, 0, sizeof(reply));\n+\n+\tif (hw->mbx.irq_enabled) {\n+\t\tcookie = rnp_memzone_reserve(hw->cookie_p_name, 0);\n+\t\tif (!cookie)\n+\t\t\treturn -ENOMEM;\n+\t\tmemset(cookie->priv, 0, cookie->priv_len);\n+\t\tbuild_reset_phy_req(&req, cookie);\n+\t\treturn rnp_mbx_fw_post_req(dev, &req, cookie);\n+\t}\n+\tbuild_reset_phy_req(&req, &req);\n+\n+\treturn rnp_fw_send_cmd_wait(dev, &req, &reply);\n+}\ndiff --git a/drivers/net/rnp/rnp_mbx_fw.h b/drivers/net/rnp/rnp_mbx_fw.h\nnew file mode 100644\nindex 0000000000..439090b5a3\n--- /dev/null\n+++ b/drivers/net/rnp/rnp_mbx_fw.h\n@@ -0,0 +1,22 @@\n+#ifndef __RNP_MBX_FW_H__\n+#define __RNP_MBX_FW_H__\n+\n+struct mbx_fw_cmd_reply;\n+typedef void (*cookie_cb)(struct mbx_fw_cmd_reply *reply, void *priv);\n+#define RNP_MAX_SHARE_MEM (8 * 8)\n+struct mbx_req_cookie {\n+\tint magic;\n+#define COOKIE_MAGIC 0xCE\n+\tcookie_cb cb;\n+\tint timeout_ms;\n+\tint errcode;\n+\n+\t/* wait_queue_head_t wait; */\n+\tvolatile int done;\n+\tint priv_len;\n+\tchar priv[RNP_MAX_SHARE_MEM];\n+};\n+struct mbx_fw_cmd_reply {\n+} __rte_cache_aligned;\n+\n+#endif /* __RNP_MBX_FW_H__*/\n", "prefixes": [ "v6", "4/8" ] }